rtwreg.h revision 1.26
1/* $NetBSD: rtwreg.h,v 1.26 2008/09/08 23:36:54 gmcgarry Exp $ */ 2/*- 3 * Copyright (c) 2004, 2005 David Young. All rights reserved. 4 * 5 * Programmed for NetBSD by David Young. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of David Young may not be used to endorse or promote 16 * products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 22 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 23 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 25 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 27 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 30 * OF SUCH DAMAGE. 31 */ 32 33#include <lib/libkern/libkern.h> 34 35/* RTL8180L Host Control and Status Registers */ 36 37#define RTW_IDR0 0x00 /* ID Register: MAC addr, 6 bytes. 38 * Auto-loaded from EEPROM. Read by byte, 39 * by word, or by double word, but write 40 * only by double word. 41 */ 42#define RTW_IDR1 0x04 43 44#define RTW_MAR0 0x08 /* Multicast filter, 64b. */ 45#define RTW_MAR1 0x0c 46 47#define RTW_TSFTRL 0x18 /* Timing Synchronization Function Timer 48 * Register, low word, 32b, read-only. 49 */ 50#define RTW_TSFTRH 0x1c /* High word, 32b, read-only. */ 51#define RTW_TLPDA 0x20 /* Transmit Low Priority Descriptors Start 52 * Address, 32b, 256-byte alignment. 53 */ 54#define RTW_TNPDA 0x24 /* Transmit Normal Priority Descriptors Start 55 * Address, 32b, 256-byte alignment. 56 */ 57#define RTW_THPDA 0x28 /* Transmit High Priority Descriptors Start 58 * Address, 32b, 256-byte alignment. 59 */ 60 61#define RTW_BRSR 0x2c /* Basic Rate Set Register, 16b */ 62#define RTW_BRSR_BPLCP __BIT(8)/* 1: use short PLCP header for CTS/ACK packet, 63 * 0: use long PLCP header 64 */ 65#define RTW_BRSR_MBR8180_MASK __BITS(1,0) /* Maximum Basic Service Rate */ 66#define RTW_BRSR_MBR8180_1MBPS __SHIFTIN(0, RTW_BRSR_MBR8180_MASK) 67#define RTW_BRSR_MBR8180_2MBPS __SHIFTIN(1, RTW_BRSR_MBR8180_MASK) 68#define RTW_BRSR_MBR8180_5MBPS __SHIFTIN(2, RTW_BRSR_MBR8180_MASK) 69#define RTW_BRSR_MBR8180_11MBPS __SHIFTIN(3, RTW_BRSR_MBR8180_MASK) 70 71/* 8181 and 8180 docs conflict! */ 72#define RTW_BRSR_MBR8181_1MBPS __BIT(0) 73#define RTW_BRSR_MBR8181_2MBPS __BIT(1) 74#define RTW_BRSR_MBR8181_5MBPS __BIT(2) 75#define RTW_BRSR_MBR8181_11MBPS __BIT(3) 76 77#define RTW_BSSID 0x2e 78/* BSSID, 6 bytes */ 79#define RTW_BSSID16 0x2e /* first two bytes */ 80#define RTW_BSSID32 (0x2e + 4) /* remaining four bytes */ 81#define RTW_BSSID0 RTW_BSSID16 /* BSSID[0], 8b */ 82#define RTW_BSSID1 (RTW_BSSID0 + 1) /* BSSID[1], 8b */ 83#define RTW_BSSID2 (RTW_BSSID1 + 1) /* BSSID[2], 8b */ 84#define RTW_BSSID3 (RTW_BSSID2 + 1) /* BSSID[3], 8b */ 85#define RTW_BSSID4 (RTW_BSSID3 + 1) /* BSSID[4], 8b */ 86#define RTW_BSSID5 (RTW_BSSID4 + 1) /* BSSID[5], 8b */ 87 88#define RTW_CR 0x37 /* Command Register, 8b */ 89#define RTW_CR_RST __BIT(4)/* Reset: host sets to 1 to disable 90 * transmitter & receiver, reinitialize FIFO. 91 * RTL8180L sets to 0 to signal completion. 92 */ 93#define RTW_CR_RE __BIT(3)/* Receiver Enable: host enables receiver 94 * by writing 1. RTL8180L indicates receiver 95 * is active with 1. After power-up, host 96 * must wait for reset before writing. 97 */ 98#define RTW_CR_TE __BIT(2)/* Transmitter Enable: host enables transmitter 99 * by writing 1. RTL8180L indicates transmitter 100 * is active with 1. After power-up, host 101 * must wait for reset before writing. 102 */ 103#define RTW_CR_MULRW __BIT(0)/* PCI Multiple Read/Write enable: 1 enables, 104 * 0 disables. XXX RTL8180, only? 105 */ 106 107#define RTW_IMR 0x3c /* Interrupt Mask Register, 16b */ 108#define RTW_ISR 0x3e /* Interrupt status register, 16b */ 109 110#define RTW_INTR_TXFOVW __BIT(15) /* Tx FIFO underflow */ 111#define RTW_INTR_TIMEOUT __BIT(14) /* Time Out: 1 indicates 112 * RTW_TSFTR[0:31] = RTW_TINT 113 */ 114/* Beacon Time Out: time for host to prepare beacon: 115 * RTW_TSFTR % (RTW_BCNITV_BCNITV * TU) = 116 * (RTW_BCNITV_BCNITV * TU - RTW_BINTRITV) 117 */ 118#define RTW_INTR_BCNINT __BIT(13) 119/* ATIM Time Out: ATIM interval will pass, 120 * RTW_TSFTR % (RTW_BCNITV_BCNITV * TU) = 121 * (RTW_ATIMWND_ATIMWND * TU - RTW_ATIMTRITV) 122 */ 123#define RTW_INTR_ATIMINT __BIT(12) 124/* Tx Beacon Descriptor Error: beacon transmission aborted because frame Rx'd */ 125#define RTW_INTR_TBDER __BIT(11) 126#define RTW_INTR_TBDOK __BIT(10) /* Tx Beacon Descriptor OK */ 127#define RTW_INTR_THPDER __BIT(9)/* Tx High Priority Descriptor Error: 128 * reached short/long retry limit 129 */ 130#define RTW_INTR_THPDOK __BIT(8)/* Tx High Priority Descriptor OK */ 131#define RTW_INTR_TNPDER __BIT(7)/* Tx Normal Priority Descriptor Error: 132 * reached short/long retry limit 133 */ 134#define RTW_INTR_TNPDOK __BIT(6)/* Tx Normal Priority Descriptor OK */ 135#define RTW_INTR_RXFOVW __BIT(5)/* Rx FIFO Overflow: either RDU (see below) 136 * or PCI bus too slow/busy 137 */ 138#define RTW_INTR_RDU __BIT(4)/* Rx Descriptor Unavailable */ 139#define RTW_INTR_TLPDER __BIT(3)/* Tx Normal Priority Descriptor Error 140 * reached short/long retry limit 141 */ 142#define RTW_INTR_TLPDOK __BIT(2)/* Tx Normal Priority Descriptor OK */ 143#define RTW_INTR_RER __BIT(1)/* Rx Error: CRC32 or ICV error */ 144#define RTW_INTR_ROK __BIT(0)/* Rx OK */ 145 146/* Convenient interrupt conjunctions. */ 147#define RTW_INTR_RX (RTW_INTR_RER|RTW_INTR_ROK|RTW_INTR_RDU|RTW_INTR_RXFOVW) 148#define RTW_INTR_TX (RTW_INTR_TLPDER|RTW_INTR_TLPDOK|RTW_INTR_THPDER|\ 149 RTW_INTR_THPDOK|RTW_INTR_TNPDER|RTW_INTR_TNPDOK|\ 150 RTW_INTR_TBDER|RTW_INTR_TBDOK) 151#define RTW_INTR_BEACON (RTW_INTR_BCNINT|RTW_INTR_TBDER|RTW_INTR_TBDOK) 152#define RTW_INTR_IOERROR (RTW_INTR_TXFOVW) 153 154#define RTW_TCR 0x40 /* Transmit Configuration Register, 32b */ 155#define RTW_TCR_CWMIN __BIT(31)/* 1: CWmin = 8, 0: CWmin = 32. */ 156#define RTW_TCR_SWSEQ __BIT(30)/* 1: host assigns 802.11 sequence number, 157 * 0: hardware assigns sequence number 158 */ 159/* Hardware version ID, read-only */ 160#define RTW_TCR_HWVERID_MASK __BITS(29, 25) 161#define RTW_TCR_HWVERID_D __SHIFTIN(26, RTW_TCR_HWVERID_MASK) 162#define RTW_TCR_HWVERID_F __SHIFTIN(27, RTW_TCR_HWVERID_MASK) 163#define RTW_TCR_HWVERID_RTL8180 RTW_TCR_HWVERID_F 164 165/* Set ACK/CTS Timeout (EIFS). 166 * 1: ACK rate = max(RTW_BRSR_MBR, Rx rate) (XXX not min? typo in datasheet?) 167 * 0: ACK rate = 1Mbps 168 */ 169#define RTW_TCR_SAT __BIT(24) 170/* Max DMA Burst Size per Tx DMA Burst */ 171#define RTW_TCR_MXDMA_MASK __BITS(23,21) 172#define RTW_TCR_MXDMA_16 __SHIFTIN(0, RTW_TCR_MXDMA_MASK) 173#define RTW_TCR_MXDMA_32 __SHIFTIN(1, RTW_TCR_MXDMA_MASK) 174#define RTW_TCR_MXDMA_64 __SHIFTIN(2, RTW_TCR_MXDMA_MASK) 175#define RTW_TCR_MXDMA_128 __SHIFTIN(3, RTW_TCR_MXDMA_MASK) 176#define RTW_TCR_MXDMA_256 __SHIFTIN(4, RTW_TCR_MXDMA_MASK) 177#define RTW_TCR_MXDMA_512 __SHIFTIN(5, RTW_TCR_MXDMA_MASK) 178#define RTW_TCR_MXDMA_1024 __SHIFTIN(6, RTW_TCR_MXDMA_MASK) 179#define RTW_TCR_MXDMA_2048 __SHIFTIN(7, RTW_TCR_MXDMA_MASK) 180 181/* disable 802.11 random backoff */ 182#define RTW_TCR_DISCW __BIT(20) 183 184/* host lets RTL8180 append ICV to WEP packets */ 185#define RTW_TCR_ICV __BIT(19) 186 187/* Loopback Test: disables TXI/TXQ outputs. */ 188#define RTW_TCR_LBK_MASK __BITS(18,17) 189#define RTW_TCR_LBK_NORMAL __SHIFTIN(0, RTW_TCR_LBK_MASK) /* normal ops */ 190#define RTW_TCR_LBK_MAC __SHIFTIN(1, RTW_TCR_LBK_MASK) /* MAC loopback */ 191#define RTW_TCR_LBK_BBP __SHIFTIN(2, RTW_TCR_LBK_MASK) /* baseband loop. */ 192#define RTW_TCR_LBK_CONT __SHIFTIN(3, RTW_TCR_LBK_MASK) /* continuous Tx */ 193 194#define RTW_TCR_CRC __BIT(16) /* 0: RTL8180 appends CRC32 195 * 1: host appends CRC32 196 * 197 * (I *think* this is right. 198 * The docs have a mysterious 199 * description in the 200 * passive voice.) 201 */ 202#define RTW_TCR_SRL_MASK __BITS(15,8) /* Short Retry Limit */ 203#define RTW_TCR_LRL_MASK __BITS(7,0) /* Long Retry Limit */ 204 205#define RTW_RCR 0x44 /* Receive Configuration Register, 32b */ 206/* only do Early Rx on packets longer than 1536 bytes */ 207#define RTW_RCR_ONLYERLPKT __BIT(31) 208/* enable carrier sense method 2 */ 209#define RTW_RCR_ENCS2 __BIT(30) 210/* enable carrier sense method 1 */ 211#define RTW_RCR_ENCS1 __BIT(29) 212#define RTW_RCR_ENMARP __BIT(28) /* enable MAC auto-reset PHY */ 213/* Check BSSID/ToDS/FromDS: set "Link On" when received BSSID 214 * matches RTW_BSSID and received ToDS/FromDS are appropriate 215 * according to RTW_MSR_NETYPE. 216 */ 217#define RTW_RCR_CBSSID __BIT(23) 218 /* accept packets w/ PWRMGMT bit set */ 219#define RTW_RCR_APWRMGT __BIT(22) 220/* when RTW_MSR_NETYPE == RTW_MSR_NETYPE_INFRA_OK, accept 221 * broadcast/multicast packets whose 3rd address matches RTL8180's MAC. 222 */ 223#define RTW_RCR_ADD3 __BIT(21) 224#define RTW_RCR_AMF __BIT(20) /* accept management frames */ 225#define RTW_RCR_ACF __BIT(19) /* accept control frames */ 226#define RTW_RCR_ADF __BIT(18) /* accept data frames */ 227/* Rx FIFO Threshold: RTL8180 begins PCI transfer when this many data 228 * bytes are received 229 */ 230#define RTW_RCR_RXFTH_MASK __BITS(15,13) 231#define RTW_RCR_RXFTH_64 __SHIFTIN(2, RTW_RCR_RXFTH_MASK) 232#define RTW_RCR_RXFTH_128 __SHIFTIN(3, RTW_RCR_RXFTH_MASK) 233#define RTW_RCR_RXFTH_256 __SHIFTIN(4, RTW_RCR_RXFTH_MASK) 234#define RTW_RCR_RXFTH_512 __SHIFTIN(5, RTW_RCR_RXFTH_MASK) 235#define RTW_RCR_RXFTH_1024 __SHIFTIN(6, RTW_RCR_RXFTH_MASK) 236#define RTW_RCR_RXFTH_WHOLE __SHIFTIN(7, RTW_RCR_RXFTH_MASK) 237 238#define RTW_RCR_AICV __BIT(12)/* accept frames w/ ICV errors */ 239 240/* Max DMA Burst Size per Rx DMA Burst */ 241#define RTW_RCR_MXDMA_MASK __BITS(10,8) 242#define RTW_RCR_MXDMA_16 __SHIFTIN(0, RTW_RCR_MXDMA_MASK) 243#define RTW_RCR_MXDMA_32 __SHIFTIN(1, RTW_RCR_MXDMA_MASK) 244#define RTW_RCR_MXDMA_64 __SHIFTIN(2, RTW_RCR_MXDMA_MASK) 245#define RTW_RCR_MXDMA_128 __SHIFTIN(3, RTW_RCR_MXDMA_MASK) 246#define RTW_RCR_MXDMA_256 __SHIFTIN(4, RTW_RCR_MXDMA_MASK) 247#define RTW_RCR_MXDMA_512 __SHIFTIN(5, RTW_RCR_MXDMA_MASK) 248#define RTW_RCR_MXDMA_1024 __SHIFTIN(6, RTW_RCR_MXDMA_MASK) 249#define RTW_RCR_MXDMA_UNLIMITED __SHIFTIN(7, RTW_RCR_MXDMA_MASK) 250 251/* EEPROM type, read-only. 1: EEPROM is 93c56, 0: 93c46 */ 252#define RTW_RCR_9356SEL __BIT(6) 253 254#define RTW_RCR_ACRC32 __BIT(5)/* accept frames w/ CRC32 errors */ 255#define RTW_RCR_AB __BIT(3)/* accept broadcast frames */ 256#define RTW_RCR_AM __BIT(2)/* accept multicast frames */ 257/* accept physical match frames. XXX means PLCP header ok? */ 258#define RTW_RCR_APM __BIT(1) 259#define RTW_RCR_AAP __BIT(0)/* accept frames w/ destination */ 260 261/* Additional bits to set in monitor mode. */ 262#define RTW_RCR_MONITOR ( \ 263 RTW_RCR_AAP | \ 264 RTW_RCR_ACF | \ 265 RTW_RCR_ACRC32 | \ 266 RTW_RCR_AICV | \ 267 0) 268 269/* The packet filter bits. */ 270#define RTW_RCR_PKTFILTER_MASK (\ 271 RTW_RCR_AAP | \ 272 RTW_RCR_AB | \ 273 RTW_RCR_ACF | \ 274 RTW_RCR_ACRC32 | \ 275 RTW_RCR_ADD3 | \ 276 RTW_RCR_ADF | \ 277 RTW_RCR_AICV | \ 278 RTW_RCR_AM | \ 279 RTW_RCR_AMF | \ 280 RTW_RCR_APM | \ 281 RTW_RCR_APWRMGT | \ 282 0) 283 284/* Receive power-management frames and mgmt/ctrl/data frames. */ 285#define RTW_RCR_PKTFILTER_DEFAULT ( \ 286 RTW_RCR_ACF | \ 287 RTW_RCR_ADF | \ 288 RTW_RCR_AMF | \ 289 RTW_RCR_APM | \ 290 RTW_RCR_APWRMGT | \ 291 0) 292 293#define RTW_TINT 0x48 /* Timer Interrupt Register, 32b */ 294#define RTW_TBDA 0x4c /* Transmit Beacon Descriptor Start Address, 295 * 32b, 256-byte alignment 296 */ 297#define RTW_9346CR 0x50 /* 93c46/93c56 Command Register, 8b */ 298#define RTW_9346CR_EEM_MASK __BITS(7,6) /* Operating Mode */ 299#define RTW_9346CR_EEM_NORMAL __SHIFTIN(0, RTW_9346CR_EEM_MASK) 300/* Load the EEPROM. Reset registers to defaults. 301 * Takes ~2ms. RTL8180 indicates completion with RTW_9346CR_EEM_NORMAL. 302 * XXX RTL8180 only? 303 */ 304#define RTW_9346CR_EEM_AUTOLOAD __SHIFTIN(1, RTW_9346CR_EEM_MASK) 305/* Disable network & bus-master operations and enable 306 * _EECS, _EESK, _EEDI, _EEDO. 307 * XXX RTL8180 only? 308 */ 309#define RTW_9346CR_EEM_PROGRAM __SHIFTIN(2, RTW_9346CR_EEM_MASK) 310/* Enable RTW_CONFIG[0123] registers. */ 311#define RTW_9346CR_EEM_CONFIG __SHIFTIN(3, RTW_9346CR_EEM_MASK) 312/* EEPROM pin status/control in _EEM_CONFIG, _EEM_AUTOLOAD modes. 313 * XXX RTL8180 only? 314 */ 315#define RTW_9346CR_EECS __BIT(3) 316#define RTW_9346CR_EESK __BIT(2) 317#define RTW_9346CR_EEDI __BIT(1) 318#define RTW_9346CR_EEDO __BIT(0) /* read-only */ 319 320#define RTW_CONFIG0 0x51 /* Configuration Register 0, 8b */ 321#define RTW_CONFIG0_WEP40 __BIT(7)/* implements 40-bit WEP, 322 * XXX RTL8180 only? 323 */ 324#define RTW_CONFIG0_WEP104 __BIT(6)/* implements 104-bit WEP, 325 * from EEPROM, read-only 326 * XXX RTL8180 only? 327 */ 328#define RTW_CONFIG0_LEDGPOEN __BIT(4)/* 1: RTW_PSR_LEDGPO[01] control 329 * LED[01] pins. 330 * 0: LED behavior defined by 331 * RTW_CONFIG1_LEDS10_MASK 332 * XXX RTL8180 only? 333 */ 334/* auxiliary power is present, read-only */ 335#define RTW_CONFIG0_AUXPWR __BIT(3) 336/* Geographic Location, read-only */ 337#define RTW_CONFIG0_GL_MASK __BITS(1,0) 338/* _RTW_CONFIG0_GL_* is what the datasheet says, but RTW_CONFIG0_GL_* 339 * work. 340 */ 341#define _RTW_CONFIG0_GL_USA __SHIFTIN(3, RTW_CONFIG0_GL_MASK) 342#define RTW_CONFIG0_GL_EUROPE __SHIFTIN(2, RTW_CONFIG0_GL_MASK) 343#define RTW_CONFIG0_GL_JAPAN __SHIFTIN(1, RTW_CONFIG0_GL_MASK) 344#define RTW_CONFIG0_GL_USA __SHIFTIN(0, RTW_CONFIG0_GL_MASK) 345/* RTL8181 datasheet says RTW_CONFIG0_GL_JAPAN = 0. */ 346 347#define RTW_CONFIG1 0x52 /* Configuration Register 1, 8b */ 348 349/* LED configuration. From EEPROM. Read/write. 350 * 351 * Setting LED0 LED1 352 * ------- ---- ---- 353 * RTW_CONFIG1_LEDS_ACT_INFRA Activity Infrastructure 354 * RTW_CONFIG1_LEDS_ACT_LINK Activity Link 355 * RTW_CONFIG1_LEDS_TX_RX Tx Rx 356 * RTW_CONFIG1_LEDS_LINKACT_INFRA Link/Activity Infrastructure 357 */ 358#define RTW_CONFIG1_LEDS_MASK __BITS(7,6) 359#define RTW_CONFIG1_LEDS_ACT_INFRA __SHIFTIN(0, RTW_CONFIG1_LEDS_MASK) 360#define RTW_CONFIG1_LEDS_ACT_LINK __SHIFTIN(1, RTW_CONFIG1_LEDS_MASK) 361#define RTW_CONFIG1_LEDS_TX_RX __SHIFTIN(2, RTW_CONFIG1_LEDS_MASK) 362#define RTW_CONFIG1_LEDS_LINKACT_INFRA __SHIFTIN(3, RTW_CONFIG1_LEDS_MASK) 363 364/* LWAKE Output Signal. Only applicable to Cardbus. Pulse width is 150ms. 365 * 366 * RTW_CONFIG1_LWACT 367 * 0 1 368 * RTW_CONFIG4_LWPTN 0 active high active low 369 * 1 positive pulse negative pulse 370 */ 371#define RTW_CONFIG1_LWACT __BIT(4) 372 373#define RTW_CONFIG1_MEMMAP __BIT(3)/* using PCI memory space, read-only */ 374#define RTW_CONFIG1_IOMAP __BIT(2)/* using PCI I/O space, read-only */ 375#define RTW_CONFIG1_VPD __BIT(1)/* if set, VPD from offsets 376 * 0x40-0x7f in EEPROM are at 377 * registers 0x60-0x67 of PCI 378 * Configuration Space (XXX huh?) 379 */ 380#define RTW_CONFIG1_PMEN __BIT(0)/* Power Management Enable: TBD */ 381 382#define RTW_CONFIG2 0x53 /* Configuration Register 2, 8b */ 383#define RTW_CONFIG2_LCK __BIT(7)/* clocks are locked, read-only: 384 * Tx frequency & symbol clocks 385 * are derived from the same OSC 386 */ 387#define RTW_CONFIG2_ANT __BIT(6) /* diversity enabled, read-only */ 388#define RTW_CONFIG2_DPS __BIT(3) /* Descriptor Polling State: enable 389 * test mode. 390 */ 391#define RTW_CONFIG2_PAPESIGN __BIT(2) /* TBD, from EEPROM */ 392#define RTW_CONFIG2_PAPETIME_MASK __BITS(1,0) /* TBD, from EEPROM */ 393 394#define RTW_ANAPARM 0x54 /* Analog parameter, 32b */ 395#define RTW_ANAPARM_RFPOW0_MASK __BITS(30,28) /* undocumented bits 396 * which appear to 397 * control the power 398 * state of the RF 399 * components 400 */ 401#define RTW_ANAPARM_RFPOW_MASK \ 402 (RTW_ANAPARM_RFPOW0_MASK|RTW_ANAPARM_RFPOW1_MASK) 403 404#define RTW_ANAPARM_TXDACOFF __BIT(27) /* 1: disable Tx DAC, 405 * 0: enable 406 */ 407#define RTW_ANAPARM_RFPOW1_MASK __BITS(26,20) /* undocumented bits 408 * which appear to 409 * control the power 410 * state of the RF 411 * components 412 */ 413 414/* 415 * Maxim On/Sleep/Off control 416 */ 417#define RTW_ANAPARM_RFPOW_MAXIM_ON __SHIFTIN(0x8, RTW_ANAPARM_RFPOW1_MASK) 418 419/* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ 420#define RTW_ANAPARM_RFPOW_MAXIM_SLEEP __SHIFTIN(0x378, RTW_ANAPARM_RFPOW1_MASK) 421 422/* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ 423#define RTW_ANAPARM_RFPOW_MAXIM_OFF __SHIFTIN(0x379, RTW_ANAPARM_RFPOW1_MASK) 424 425/* 426 * RFMD On/Sleep/Off control 427 */ 428#define RTW_ANAPARM_RFPOW_RFMD_ON __SHIFTIN(0x408, RTW_ANAPARM_RFPOW1_MASK) 429 430/* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ 431#define RTW_ANAPARM_RFPOW_RFMD_SLEEP __SHIFTIN(0x378, RTW_ANAPARM_RFPOW1_MASK) 432 433/* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ 434#define RTW_ANAPARM_RFPOW_RFMD_OFF __SHIFTIN(0x379, RTW_ANAPARM_RFPOW1_MASK) 435 436/* 437 * Philips On/Sleep/Off control 438 */ 439#define RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON \ 440 __SHIFTIN(0x328, RTW_ANAPARM_RFPOW1_MASK) 441#define RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON \ 442 __SHIFTIN(0x008, RTW_ANAPARM_RFPOW1_MASK) 443 444/* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ 445#define RTW_ANAPARM_RFPOW_PHILIPS_SLEEP\ 446 __SHIFTIN(0x378, RTW_ANAPARM_RFPOW1_MASK) 447 448/* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ 449#define RTW_ANAPARM_RFPOW_PHILIPS_OFF\ 450 __SHIFTIN(0x379, RTW_ANAPARM_RFPOW1_MASK) 451 452#define RTW_ANAPARM_RFPOW_PHILIPS_ON __SHIFTIN(0x328, RTW_ANAPARM_RFPOW1_MASK) 453 454#define RTW_ANAPARM_CARDSP_MASK __BITS(19,0) /* undocumented 455 * card-specific 456 * bits from the 457 * EEPROM. 458 */ 459 460#define RTW_MSR 0x58 /* Media Status Register, 8b */ 461/* Network Type and Link Status */ 462#define RTW_MSR_NETYPE_MASK __BITS(3,2) 463/* AP, XXX RTL8181 only? */ 464#define RTW_MSR_NETYPE_AP_OK __SHIFTIN(3, RTW_MSR_NETYPE_MASK) 465/* infrastructure link ok */ 466#define RTW_MSR_NETYPE_INFRA_OK __SHIFTIN(2, RTW_MSR_NETYPE_MASK) 467/* ad-hoc link ok */ 468#define RTW_MSR_NETYPE_ADHOC_OK __SHIFTIN(1, RTW_MSR_NETYPE_MASK) 469/* no link */ 470#define RTW_MSR_NETYPE_NOLINK __SHIFTIN(0, RTW_MSR_NETYPE_MASK) 471 472#define RTW_CONFIG3 0x59 /* Configuration Register 3, 8b */ 473#define RTW_CONFIG3_GNTSEL __BIT(7) /* Grant Select, read-only */ 474#define RTW_CONFIG3_PARMEN __BIT(6) /* Set RTW_CONFIG3_PARMEN and 475 * RTW_9346CR_EEM_CONFIG to 476 * allow RTW_ANAPARM writes. 477 */ 478#define RTW_CONFIG3_MAGIC __BIT(5)/* Valid when RTW_CONFIG1_PMEN is 479 * set. If set, RTL8180 wakes up 480 * OS when Magic Packet is Rx'd. 481 */ 482#define RTW_CONFIG3_CARDBEN __BIT(3)/* Cardbus-related registers 483 * and functions are enabled, 484 * read-only. XXX RTL8180 only. 485 */ 486#define RTW_CONFIG3_CLKRUNEN __BIT(2)/* CLKRUN enabled, read-only. 487 * XXX RTL8180 only. 488 */ 489#define RTW_CONFIG3_FUNCREGEN __BIT(1)/* Function Registers Enabled, 490 * read-only. XXX RTL8180 only. 491 */ 492#define RTW_CONFIG3_FBTBEN __BIT(0)/* Fast back-to-back enabled, 493 * read-only. 494 */ 495#define RTW_CONFIG4 0x5A /* Configuration Register 4, 8b */ 496#define RTW_CONFIG4_VCOPDN __BIT(7)/* VCO Power Down 497 * 0: normal operation 498 * (power-on default) 499 * 1: power-down VCO, RF front-end, 500 * and most RTL8180 components. 501 */ 502#define RTW_CONFIG4_PWROFF __BIT(6)/* Power Off 503 * 0: normal operation 504 * (power-on default) 505 * 1: power-down RF front-end, 506 * and most RTL8180 components, 507 * but leave VCO on. 508 * 509 * XXX RFMD front-end only? 510 */ 511#define RTW_CONFIG4_PWRMGT __BIT(5)/* Power Management 512 * 0: normal operation 513 * (power-on default) 514 * 1: set Tx packet's PWRMGMT bit. 515 */ 516#define RTW_CONFIG4_LWPME __BIT(4)/* LANWAKE vs. PMEB: Cardbus-only 517 * 0: LWAKE & PMEB asserted 518 * simultaneously 519 * 1: LWAKE asserted only if 520 * both PMEB is asserted and 521 * ISOLATEB is low. 522 * XXX RTL8180 only. 523 */ 524#define RTW_CONFIG4_LWPTN __BIT(2)/* see RTW_CONFIG1_LWACT 525 * XXX RTL8180 only. 526 */ 527/* Radio Front-End Programming Method */ 528#define RTW_CONFIG4_RFTYPE_MASK __BITS(1,0) 529#define RTW_CONFIG4_RFTYPE_INTERSIL __SHIFTIN(1, RTW_CONFIG4_RFTYPE_MASK) 530#define RTW_CONFIG4_RFTYPE_RFMD __SHIFTIN(2, RTW_CONFIG4_RFTYPE_MASK) 531#define RTW_CONFIG4_RFTYPE_PHILIPS __SHIFTIN(3, RTW_CONFIG4_RFTYPE_MASK) 532 533#define RTW_TESTR 0x5B /* TEST mode register, 8b */ 534 535#define RTW_PSR 0x5e /* Page Select Register, 8b */ 536#define RTW_PSR_GPO __BIT(7)/* Control/status of pin 52. */ 537#define RTW_PSR_GPI __BIT(6)/* Status of pin 64. */ 538#define RTW_PSR_LEDGPO1 __BIT(5)/* Status/control of LED1 pin if 539 * RTW_CONFIG0_LEDGPOEN is set. 540 */ 541#define RTW_PSR_LEDGPO0 __BIT(4)/* Status/control of LED0 pin if 542 * RTW_CONFIG0_LEDGPOEN is set. 543 */ 544#define RTW_PSR_UWF __BIT(1)/* Enable Unicast Wakeup Frame */ 545#define RTW_PSR_PSEN __BIT(0)/* 1: page 1, 0: page 0 */ 546 547#define RTW_SCR 0x5f /* Security Configuration Register, 8b */ 548#define RTW_SCR_KM_MASK __BITS(5,4) /* Key Mode */ 549#define RTW_SCR_KM_WEP104 __SHIFTIN(1, RTW_SCR_KM_MASK) 550#define RTW_SCR_KM_WEP40 __SHIFTIN(0, RTW_SCR_KM_MASK) 551#define RTW_SCR_TXSECON __BIT(1)/* Enable Tx WEP. Invalid if 552 * neither RTW_CONFIG0_WEP40 nor 553 * RTW_CONFIG0_WEP104 is set. 554 */ 555#define RTW_SCR_RXSECON __BIT(0)/* Enable Rx WEP. Invalid if 556 * neither RTW_CONFIG0_WEP40 nor 557 * RTW_CONFIG0_WEP104 is set. 558 */ 559 560#define RTW_BCNITV 0x70 /* Beacon Interval Register, 16b */ 561#define RTW_BCNITV_BCNITV_MASK __BITS(9,0) /* TU between TBTT, written 562 * by host. 563 */ 564#define RTW_ATIMWND 0x72 /* ATIM Window Register, 16b */ 565#define RTW_ATIMWND_ATIMWND __BITS(9,0) /* ATIM Window length in TU, 566 * written by host. 567 */ 568 569#define RTW_BINTRITV 0x74 /* Beacon Interrupt Interval Register, 16b */ 570#define RTW_BINTRITV_BINTRITV __BITS(9,0) /* RTL8180 wakes host with 571 * RTW_INTR_BCNINT at BINTRITV 572 * microseconds before TBTT 573 */ 574#define RTW_ATIMTRITV 0x76 /* ATIM Interrupt Interval Register, 16b */ 575#define RTW_ATIMTRITV_ATIMTRITV __BITS(9,0) /* RTL8180 wakes host with 576 * RTW_INTR_ATIMINT at ATIMTRITV 577 * microseconds before end of 578 * ATIM Window 579 */ 580 581#define RTW_PHYDELAY 0x78 /* PHY Delay Register, 8b */ 582#define RTW_PHYDELAY_REVC_MAGIC __BIT(3) /* Rev. C magic from reference 583 * driver 584 */ 585#define RTW_PHYDELAY_PHYDELAY __BITS(2,0) /* microsecond Tx delay between 586 * MAC and RF front-end 587 */ 588#define RTW_CRCOUNT 0x79 /* Carrier Sense Counter, 8b */ 589#define RTW_CRCOUNT_MAGIC 0x4c 590 591#define RTW_CRC16ERR 0x7a /* CRC16 error count, 16b, XXX RTL8181 only? */ 592 593#define RTW_BB 0x7c /* Baseband interface, 32b */ 594/* used for writing RTL8180's integrated baseband processor */ 595#define RTW_BB_RD_MASK __BITS(23,16) /* data to read */ 596#define RTW_BB_WR_MASK __BITS(15,8) /* data to write */ 597#define RTW_BB_WREN __BIT(7) /* write enable */ 598#define RTW_BB_ADDR_MASK __BITS(6,0) /* address */ 599 600#define RTW_PHYADDR 0x7c /* Address register for PHY interface, 8b */ 601#define RTW_PHYDATAW 0x7d /* Write data to PHY, 8b, write-only */ 602#define RTW_PHYDATAR 0x7e /* Read data from PHY, 8b (?), read-only */ 603 604#define RTW_PHYCFG 0x80 /* PHY Configuration Register, 32b */ 605#define RTW_PHYCFG_MAC_POLL __BIT(31) /* if !RTW_PHYCFG_HST, 606 * host sets. MAC clears 607 * after banging bits. 608 */ 609#define RTW_PHYCFG_HST __BIT(30) /* 1: host bangs bits 610 * 0: MAC bangs bits 611 */ 612#define RTW_PHYCFG_MAC_RFTYPE_MASK __BITS(29,28) 613#define RTW_PHYCFG_MAC_RFTYPE_INTERSIL __SHIFTIN(0, RTW_PHYCFG_MAC_RFTYPE_MASK) 614#define RTW_PHYCFG_MAC_RFTYPE_RFMD __SHIFTIN(1, RTW_PHYCFG_MAC_RFTYPE_MASK) 615#define RTW_PHYCFG_MAC_RFTYPE_GCT RTW_PHYCFG_MAC_RFTYPE_RFMD 616#define RTW_PHYCFG_MAC_RFTYPE_PHILIPS __SHIFTIN(3, RTW_PHYCFG_MAC_RFTYPE_MASK) 617#define RTW_PHYCFG_MAC_PHILIPS_ADDR_MASK __BITS(27,24) 618#define RTW_PHYCFG_MAC_PHILIPS_DATA_MASK __BITS(23,0) 619#define RTW_PHYCFG_MAC_MAXIM_LODATA_MASK __BITS(27,24) 620#define RTW_PHYCFG_MAC_MAXIM_ADDR_MASK __BITS(11,8) 621#define RTW_PHYCFG_MAC_MAXIM_HIDATA_MASK __BITS(7,0) 622#define RTW_PHYCFG_HST_EN __BIT(2) 623#define RTW_PHYCFG_HST_CLK __BIT(1) 624#define RTW_PHYCFG_HST_DATA __BIT(0) 625 626#define RTW_MAXIM_HIDATA_MASK __BITS(11,4) 627#define RTW_MAXIM_LODATA_MASK __BITS(3,0) 628 629/** 630 ** 0x84 - 0xD3, page 1, selected when RTW_PSR[PSEN] == 1. 631 **/ 632 633#define RTW_WAKEUP0L 0x84 /* Power Management Wakeup Frame */ 634#define RTW_WAKEUP0H 0x88 /* 32b */ 635 636#define RTW_WAKEUP1L 0x8c 637#define RTW_WAKEUP1H 0x90 638 639#define RTW_WAKEUP2LL 0x94 640#define RTW_WAKEUP2LH 0x98 641 642#define RTW_WAKEUP2HL 0x9c 643#define RTW_WAKEUP2HH 0xa0 644 645#define RTW_WAKEUP3LL 0xa4 646#define RTW_WAKEUP3LH 0xa8 647 648#define RTW_WAKEUP3HL 0xac 649#define RTW_WAKEUP3HH 0xb0 650 651#define RTW_WAKEUP4LL 0xb4 652#define RTW_WAKEUP4LH 0xb8 653 654#define RTW_WAKEUP4HL 0xbc 655#define RTW_WAKEUP4HH 0xc0 656 657#define RTW_CRC0 0xc4 /* CRC of wakeup frame 0, 16b */ 658#define RTW_CRC1 0xc6 /* CRC of wakeup frame 1, 16b */ 659#define RTW_CRC2 0xc8 /* CRC of wakeup frame 2, 16b */ 660#define RTW_CRC3 0xca /* CRC of wakeup frame 3, 16b */ 661#define RTW_CRC4 0xcc /* CRC of wakeup frame 4, 16b */ 662 663/** 664 ** 0x84 - 0xD3, page 0, selected when RTW_PSR[PSEN] == 0. 665 **/ 666 667/* Default Key Registers, each 128b 668 * 669 * If RTW_SCR_KM_WEP104, 104 lsb are the key. 670 * If RTW_SCR_KM_WEP40, 40 lsb are the key. 671 */ 672#define RTW_DK0 0x90 /* Default Key 0 Register, 128b */ 673#define RTW_DK1 0xa0 /* Default Key 1 Register, 128b */ 674#define RTW_DK2 0xb0 /* Default Key 2 Register, 128b */ 675#define RTW_DK3 0xc0 /* Default Key 3 Register, 128b */ 676 677#define RTW_CONFIG5 0xd8 /* Configuration Register 5, 8b */ 678#define RTW_CONFIG5_TXFIFOOK __BIT(7)/* Tx FIFO self-test pass, read-only */ 679#define RTW_CONFIG5_RXFIFOOK __BIT(6)/* Rx FIFO self-test pass, read-only */ 680#define RTW_CONFIG5_CALON __BIT(5)/* 1: start calibration cycle 681 * and raise AGCRESET pin. 682 * 0: lower AGCRESET pin 683 */ 684#define RTW_CONFIG5_EACPI __BIT(2)/* Enable ACPI Wake up, default 0 */ 685#define RTW_CONFIG5_LANWAKE __BIT(1)/* Enable LAN Wake signal, 686 * from EEPROM 687 */ 688#define RTW_CONFIG5_PMESTS __BIT(0)/* 1: both software & PCI Reset 689 * reset PME_Status 690 * 0: only software resets PME_Status 691 * 692 * From EEPROM. 693 */ 694 695#define RTW_TPPOLL 0xd9 /* Transmit Priority Polling Register, 8b, 696 * write-only. 697 */ 698#define RTW_TPPOLL_BQ __BIT(7)/* RTL8180 clears to notify host of a beacon 699 * Tx. Host writes have no effect. 700 */ 701#define RTW_TPPOLL_HPQ __BIT(6)/* Host writes 1 to notify RTL8180 of 702 * high-priority Tx packets, RTL8180 clears 703 * to after high-priority Tx is complete. 704 */ 705#define RTW_TPPOLL_NPQ __BIT(5)/* If RTW_CONFIG2_DPS is set, 706 * host writes 1 to notify RTL8180 of 707 * normal-priority Tx packets, RTL8180 clears 708 * after normal-priority Tx is complete. 709 * 710 * If RTW_CONFIG2_DPS is clear, host writes 711 * have no effect. RTL8180 clears after 712 * normal-priority Tx is complete. 713 */ 714#define RTW_TPPOLL_LPQ __BIT(4)/* Host writes 1 to notify RTL8180 of 715 * low-priority Tx packets, RTL8180 clears 716 * after low-priority Tx is complete. 717 */ 718#define RTW_TPPOLL_SBQ __BIT(3)/* Host writes 1 to tell RTL8180 to 719 * stop beacon DMA. This bit is invalid 720 * when RTW_CONFIG2_DPS is set. 721 */ 722#define RTW_TPPOLL_SHPQ __BIT(2)/* Host writes 1 to tell RTL8180 to 723 * stop high-priority DMA. 724 */ 725#define RTW_TPPOLL_SNPQ __BIT(1)/* Host writes 1 to tell RTL8180 to 726 * stop normal-priority DMA. This bit is invalid 727 * when RTW_CONFIG2_DPS is set. 728 */ 729#define RTW_TPPOLL_SLPQ __BIT(0)/* Host writes 1 to tell RTL8180 to 730 * stop low-priority DMA. 731 */ 732 733/* Start all queues. */ 734#define RTW_TPPOLL_ALL (RTW_TPPOLL_BQ | RTW_TPPOLL_HPQ | \ 735 RTW_TPPOLL_NPQ | RTW_TPPOLL_LPQ) 736/* Check all queues' activity. */ 737#define RTW_TPPOLL_ACTIVE RTW_TPPOLL_ALL 738/* Stop all queues. */ 739#define RTW_TPPOLL_SALL (RTW_TPPOLL_SBQ | RTW_TPPOLL_SHPQ | \ 740 RTW_TPPOLL_SNPQ | RTW_TPPOLL_SLPQ) 741 742#define RTW_CWR 0xdc /* Contention Window Register, 16b, read-only */ 743/* Contention Window: indicates number of contention windows before Tx 744 */ 745#define RTW_CWR_CW __BITS(9,0) 746 747/* Retry Count Register, 16b, read-only */ 748#define RTW_RETRYCTR 0xde 749/* Retry Count: indicates number of retries after Tx */ 750#define RTW_RETRYCTR_RETRYCT __BITS(7,0) 751 752#define RTW_RDSAR 0xe4 /* Receive descriptor Start Address Register, 753 * 32b, 256-byte alignment. 754 */ 755/* Function Event Register, 32b, Cardbus only. Only valid when 756 * both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN are set. 757 */ 758#define RTW_FER 0xf0 759#define RTW_FER_INTR __BIT(15) /* set when RTW_FFER_INTR is set */ 760#define RTW_FER_GWAKE __BIT(4) /* General Wakeup */ 761/* Function Event Mask Register, 32b, Cardbus only. Only valid when 762 * both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN are set. 763 */ 764#define RTW_FEMR 0xf4 765#define RTW_FEMR_INTR __BIT(15) /* set when RTW_FFER_INTR is set */ 766#define RTW_FEMR_WKUP __BIT(14) /* Wakeup Mask */ 767#define RTW_FEMR_GWAKE __BIT(4) /* General Wakeup */ 768/* Function Present State Register, 32b, read-only, Cardbus only. 769 * Only valid when both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN 770 * are set. 771 */ 772#define RTW_FPSR 0xf8 773#define RTW_FPSR_INTR __BIT(15) /* TBD */ 774#define RTW_FPSR_GWAKE __BIT(4) /* General Wakeup: TBD */ 775/* Function Force Event Register, 32b, write-only, Cardbus only. 776 * Only valid when both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN 777 * are set. 778 */ 779#define RTW_FFER 0xfc 780#define RTW_FFER_INTR __BIT(15) /* TBD */ 781#define RTW_FFER_GWAKE __BIT(4) /* General Wakeup: TBD */ 782 783/* Serial EEPROM offsets */ 784#define RTW_SR_ID 0x00 /* 16b */ 785#define RTW_SR_VID 0x02 /* 16b */ 786#define RTW_SR_DID 0x04 /* 16b */ 787#define RTW_SR_SVID 0x06 /* 16b */ 788#define RTW_SR_SMID 0x08 /* 16b */ 789#define RTW_SR_MNGNT 0x0a 790#define RTW_SR_MXLAT 0x0b 791#define RTW_SR_RFCHIPID 0x0c 792#define RTW_SR_CONFIG3 0x0d 793#define RTW_SR_MAC 0x0e /* 6 bytes */ 794#define RTW_SR_CONFIG0 0x14 795#define RTW_SR_CONFIG1 0x15 796#define RTW_SR_PMC 0x16 /* Power Management Capabilities, 16b */ 797#define RTW_SR_CONFIG2 0x18 798#define RTW_SR_CONFIG4 0x19 799#define RTW_SR_ANAPARM 0x1a /* Analog Parameters, 32b */ 800#define RTW_SR_TESTR 0x1e 801#define RTW_SR_CONFIG5 0x1f 802#define RTW_SR_TXPOWER1 0x20 803#define RTW_SR_TXPOWER2 0x21 804#define RTW_SR_TXPOWER3 0x22 805#define RTW_SR_TXPOWER4 0x23 806#define RTW_SR_TXPOWER5 0x24 807#define RTW_SR_TXPOWER6 0x25 808#define RTW_SR_TXPOWER7 0x26 809#define RTW_SR_TXPOWER8 0x27 810#define RTW_SR_TXPOWER9 0x28 811#define RTW_SR_TXPOWER10 0x29 812#define RTW_SR_TXPOWER11 0x2a 813#define RTW_SR_TXPOWER12 0x2b 814#define RTW_SR_TXPOWER13 0x2c 815#define RTW_SR_TXPOWER14 0x2d 816#define RTW_SR_CHANNELPLAN 0x2e /* bitmap of channels to scan */ 817#define RTW_SR_ENERGYDETTHR 0x2f /* energy-detect threshold */ 818#define RTW_SR_ENERGYDETTHR_DEFAULT 0x0c /* use this if old SROM */ 819#define RTW_SR_CISPOINTER 0x30 /* 16b */ 820#define RTW_SR_RFPARM 0x32 /* RF-specific parameter */ 821#define RTW_SR_RFPARM_DIGPHY __BIT(0) /* 1: digital PHY */ 822#define RTW_SR_RFPARM_DFLANTB __BIT(1) /* 1: antenna B is default */ 823#define RTW_SR_RFPARM_CS_MASK __BITS(2,3) /* carrier-sense type */ 824#define RTW_SR_VERSION 0x3c /* EEPROM content version, 16b */ 825#define RTW_SR_CRC 0x3e /* EEPROM content CRC, 16b */ 826#define RTW_SR_VPD 0x40 /* Vital Product Data, 64 bytes */ 827#define RTW_SR_CIS 0x80 /* CIS Data, 93c56 only, 128 bytes*/ 828 829/* 830 * RTL8180 Transmit/Receive Descriptors 831 */ 832 833/* the first descriptor in each ring must be on a 256-byte boundary */ 834#define RTW_DESC_ALIGNMENT 256 835 836/* Tx descriptor */ 837struct rtw_txdesc { 838 volatile uint32_t td_ctl0; 839 volatile uint32_t td_ctl1; 840 volatile uint32_t td_buf; 841 volatile uint32_t td_len; 842 volatile uint32_t td_next; 843 volatile uint32_t td_rsvd[3]; 844} __packed __aligned(4); 845 846#define td_stat td_ctl0 847 848#define RTW_TXCTL0_OWN __BIT(31) /* 1: ready to Tx */ 849#define RTW_TXCTL0_RSVD0 __BIT(30) /* reserved */ 850#define RTW_TXCTL0_FS __BIT(29) /* first segment */ 851#define RTW_TXCTL0_LS __BIT(28) /* last segment */ 852 853#define RTW_TXCTL0_RATE_MASK __BITS(27,24) /* Tx rate */ 854#define RTW_TXCTL0_RATE_1MBPS __SHIFTIN(0, RTW_TXCTL0_RATE_MASK) 855#define RTW_TXCTL0_RATE_2MBPS __SHIFTIN(1, RTW_TXCTL0_RATE_MASK) 856#define RTW_TXCTL0_RATE_5MBPS __SHIFTIN(2, RTW_TXCTL0_RATE_MASK) 857#define RTW_TXCTL0_RATE_11MBPS __SHIFTIN(3, RTW_TXCTL0_RATE_MASK) 858 859#define RTW_TXCTL0_RTSEN __BIT(23) /* RTS Enable */ 860 861#define RTW_TXCTL0_RTSRATE_MASK __BITS(22,19) /* Tx rate */ 862#define RTW_TXCTL0_RTSRATE_1MBPS __SHIFTIN(0, RTW_TXCTL0_RTSRATE_MASK) 863#define RTW_TXCTL0_RTSRATE_2MBPS __SHIFTIN(1, RTW_TXCTL0_RTSRATE_MASK) 864#define RTW_TXCTL0_RTSRATE_5MBPS __SHIFTIN(2, RTW_TXCTL0_RTSRATE_MASK) 865#define RTW_TXCTL0_RTSRATE_11MBPS __SHIFTIN(3, RTW_TXCTL0_RTSRATE_MASK) 866 867#define RTW_TXCTL0_BEACON __BIT(18) /* packet is a beacon */ 868#define RTW_TXCTL0_MOREFRAG __BIT(17) /* another fragment 869 * follows 870 */ 871/* add short PLCP preamble and header */ 872#define RTW_TXCTL0_SPLCP __BIT(16) 873#define RTW_TXCTL0_KEYID_MASK __BITS(15,14) /* default key id */ 874#define RTW_TXCTL0_RSVD1_MASK __BITS(13,12) /* reserved */ 875#define RTW_TXCTL0_TPKTSIZE_MASK __BITS(11,0) /* Tx packet size 876 * in bytes 877 */ 878 879#define RTW_TXSTAT_OWN RTW_TXCTL0_OWN 880#define RTW_TXSTAT_RSVD0 RTW_TXCTL0_RSVD0 881#define RTW_TXSTAT_FS RTW_TXCTL0_FS 882#define RTW_TXSTAT_LS RTW_TXCTL0_LS 883#define RTW_TXSTAT_RSVD1_MASK __BITS(27,16) 884#define RTW_TXSTAT_TOK __BIT(15) 885#define RTW_TXSTAT_RTSRETRY_MASK __BITS(14,8) /* RTS retry count */ 886#define RTW_TXSTAT_DRC_MASK __BITS(7,0) /* Data retry count */ 887 888#define RTW_TXCTL1_LENGEXT __BIT(31) /* supplements _LENGTH 889 * in packets sent 5.5Mb/s or 890 * faster 891 */ 892#define RTW_TXCTL1_LENGTH_MASK __BITS(30,16) /* PLCP length (microseconds) */ 893#define RTW_TXCTL1_RTSDUR_MASK __BITS(15,0) /* RTS Duration 894 * (microseconds) 895 */ 896 897#define RTW_TXLEN_LENGTH_MASK __BITS(11,0) /* Tx buffer length in bytes */ 898 899/* Rx descriptor */ 900struct rtw_rxdesc { 901 volatile uint32_t rd_ctl; 902 volatile uint32_t rd_rsvd0; 903 volatile uint32_t rd_buf; 904 volatile uint32_t rd_rsvd1; 905} __packed __aligned(4); 906 907#define rd_stat rd_ctl 908#define rd_rssi rd_rsvd0 909#define rd_tsftl rd_buf /* valid only when RTW_RXSTAT_LS is set */ 910#define rd_tsfth rd_rsvd1 /* valid only when RTW_RXSTAT_LS is set */ 911 912#define RTW_RXCTL_OWN __BIT(31) /* 1: owned by NIC */ 913#define RTW_RXCTL_EOR __BIT(30) /* end of ring */ 914#define RTW_RXCTL_FS __BIT(29) /* first segment */ 915#define RTW_RXCTL_LS __BIT(28) /* last segment */ 916#define RTW_RXCTL_RSVD0_MASK __BITS(29,12) /* reserved */ 917#define RTW_RXCTL_LENGTH_MASK __BITS(11,0) /* Rx buffer length */ 918 919#define RTW_RXSTAT_OWN RTW_RXCTL_OWN 920#define RTW_RXSTAT_EOR RTW_RXCTL_EOR 921#define RTW_RXSTAT_FS RTW_RXCTL_FS /* first segment */ 922#define RTW_RXSTAT_LS RTW_RXCTL_LS /* last segment */ 923#define RTW_RXSTAT_DMAFAIL __BIT(27) /* DMA failure on this pkt */ 924#define RTW_RXSTAT_BOVF __BIT(26) /* buffer overflow XXX means 925 * FIFO exhausted? 926 */ 927#define RTW_RXSTAT_SPLCP __BIT(25) /* Rx'd with short preamble 928 * and PLCP header 929 */ 930#define RTW_RXSTAT_RSVD1 __BIT(24) /* reserved */ 931#define RTW_RXSTAT_RATE_MASK __BITS(23,20) /* Rx rate */ 932#define RTW_RXSTAT_RATE_1MBPS __SHIFTIN(0, RTW_RXSTAT_RATE_MASK) 933#define RTW_RXSTAT_RATE_2MBPS __SHIFTIN(1, RTW_RXSTAT_RATE_MASK) 934#define RTW_RXSTAT_RATE_5MBPS __SHIFTIN(2, RTW_RXSTAT_RATE_MASK) 935#define RTW_RXSTAT_RATE_11MBPS __SHIFTIN(3, RTW_RXSTAT_RATE_MASK) 936#define RTW_RXSTAT_MIC __BIT(19) /* XXX from reference driver */ 937#define RTW_RXSTAT_MAR __BIT(18) /* is multicast */ 938#define RTW_RXSTAT_PAR __BIT(17) /* matches RTL8180's MAC */ 939#define RTW_RXSTAT_BAR __BIT(16) /* is broadcast */ 940#define RTW_RXSTAT_RES __BIT(15) /* error summary. valid when 941 * RTW_RXSTAT_LS set. indicates 942 * that either RTW_RXSTAT_CRC32 943 * or RTW_RXSTAT_ICV is set. 944 */ 945#define RTW_RXSTAT_PWRMGT __BIT(14) /* 802.11 PWRMGMT bit is set */ 946#define RTW_RXSTAT_CRC16 __BIT(14) /* XXX CRC16 error, from 947 * reference driver 948 */ 949#define RTW_RXSTAT_CRC32 __BIT(13) /* CRC32 error */ 950#define RTW_RXSTAT_ICV __BIT(12) /* ICV error */ 951#define RTW_RXSTAT_LENGTH_MASK __BITS(11,0) /* frame length, including 952 * CRC32 953 */ 954 955/* Convenient status conjunction. */ 956#define RTW_RXSTAT_ONESEG (RTW_RXSTAT_FS|RTW_RXSTAT_LS) 957/* Convenient status disjunctions. */ 958#define RTW_RXSTAT_IOERROR (RTW_RXSTAT_DMAFAIL|RTW_RXSTAT_BOVF) 959#define RTW_RXSTAT_DEBUG (RTW_RXSTAT_SPLCP|RTW_RXSTAT_MAR|\ 960 RTW_RXSTAT_PAR|RTW_RXSTAT_BAR|\ 961 RTW_RXSTAT_PWRMGT|RTW_RXSTAT_CRC32|\ 962 RTW_RXSTAT_ICV) 963 964 965#define RTW_RXRSSI_VLAN __BITS(31,16) /* XXX from reference driver */ 966/* for Philips RF front-ends */ 967#define RTW_RXRSSI_RSSI __BITS(15,8) /* RF energy at the PHY */ 968/* for RF front-ends by Intersil, Maxim, RFMD */ 969#define RTW_RXRSSI_IMR_RSSI __BITS(15,9) /* RF energy at the PHY */ 970#define RTW_RXRSSI_IMR_LNA __BIT(8) /* 1: LNA activated */ 971#define RTW_RXRSSI_SQ __BITS(7,0) /* Barker code-lock quality */ 972 973#define RTW_READ8(regs, ofs) \ 974 bus_space_read_1((regs)->r_bt, (regs)->r_bh, (ofs)) 975 976#define RTW_READ16(regs, ofs) \ 977 bus_space_read_2((regs)->r_bt, (regs)->r_bh, (ofs)) 978 979#define RTW_READ(regs, ofs) \ 980 bus_space_read_4((regs)->r_bt, (regs)->r_bh, (ofs)) 981 982#define RTW_WRITE8(regs, ofs, val) \ 983 bus_space_write_1((regs)->r_bt, (regs)->r_bh, (ofs), (val)) 984 985#define RTW_WRITE16(regs, ofs, val) \ 986 bus_space_write_2((regs)->r_bt, (regs)->r_bh, (ofs), (val)) 987 988#define RTW_WRITE(regs, ofs, val) \ 989 bus_space_write_4((regs)->r_bt, (regs)->r_bh, (ofs), (val)) 990 991#define RTW_ISSET(regs, reg, mask) \ 992 (RTW_READ((regs), (reg)) & (mask)) 993 994#define RTW_CLR(regs, reg, mask) \ 995 RTW_WRITE((regs), (reg), RTW_READ((regs), (reg)) & ~(mask)) 996 997/* bus_space(9) lied? */ 998#ifndef BUS_SPACE_BARRIER_SYNC 999#define BUS_SPACE_BARRIER_SYNC (BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 1000#endif 1001 1002#ifndef BUS_SPACE_BARRIER_READ_BEFORE_READ 1003#define BUS_SPACE_BARRIER_READ_BEFORE_READ BUS_SPACE_BARRIER_READ 1004#endif 1005 1006#ifndef BUS_SPACE_BARRIER_READ_BEFORE_WRITE 1007#define BUS_SPACE_BARRIER_READ_BEFORE_WRITE BUS_SPACE_BARRIER_READ 1008#endif 1009 1010#ifndef BUS_SPACE_BARRIER_WRITE_BEFORE_READ 1011#define BUS_SPACE_BARRIER_WRITE_BEFORE_READ BUS_SPACE_BARRIER_WRITE 1012#endif 1013 1014#ifndef BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE 1015#define BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE BUS_SPACE_BARRIER_WRITE 1016#endif 1017 1018/* 1019 * Bus barrier 1020 * 1021 * Complete outstanding read and/or write ops on [reg0, reg1] 1022 * ([reg1, reg0]) before starting new ops on the same region. See 1023 * acceptable bus_space_barrier(9) for the flag definitions. 1024 */ 1025#define RTW_BARRIER(regs, reg0, reg1, flags) \ 1026 bus_space_barrier((regs)->r_bh, (regs)->r_bt, \ 1027 MIN(reg0, reg1), MAX(reg0, reg1) - MIN(reg0, reg1) + 4, flags) 1028 1029/* 1030 * Barrier convenience macros. 1031 */ 1032/* sync */ 1033#define RTW_SYNC(regs, reg0, reg1) \ 1034 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_SYNC) 1035 1036/* write-before-write */ 1037#define RTW_WBW(regs, reg0, reg1) \ 1038 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE) 1039 1040/* write-before-read */ 1041#define RTW_WBR(regs, reg0, reg1) \ 1042 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_READ) 1043 1044/* read-before-read */ 1045#define RTW_RBR(regs, reg0, reg1) \ 1046 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_READ) 1047 1048/* read-before-write */ 1049#define RTW_RBW(regs, reg0, reg1) \ 1050 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_WRITE) 1051 1052#define RTW_WBRW(regs, reg0, reg1) \ 1053 RTW_BARRIER(regs, reg0, reg1, \ 1054 BUS_SPACE_BARRIER_WRITE_BEFORE_READ | \ 1055 BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE) 1056 1057/* 1058 * Registers for RTL8180L's built-in baseband modem. 1059 */ 1060#define RTW_BBP_SYS1 0x00 1061#define RTW_BBP_TXAGC 0x03 /* guess: transmit auto gain control */ 1062#define RTW_BBP_LNADET 0x04 /* guess: low-noise amplifier activation 1063 * threshold 1064 */ 1065#define RTW_BBP_IFAGCINI 0x05 /* guess: intermediate frequency (IF) 1066 * auto-gain control (AGC) initial value 1067 */ 1068#define RTW_BBP_IFAGCLIMIT 0x06 /* guess: IF AGC maximum value */ 1069#define RTW_BBP_IFAGCDET 0x07 /* guess: activation threshold for 1070 * IF AGC loop 1071 */ 1072 1073#define RTW_BBP_ANTATTEN 0x10 /* guess: antenna & attenuation */ 1074#define RTW_BBP_ANTATTEN_GCT_MAGIC 0xa3 1075#define RTW_BBP_ANTATTEN_PHILIPS_MAGIC 0x91 1076#define RTW_BBP_ANTATTEN_INTERSIL_MAGIC 0x92 1077#define RTW_BBP_ANTATTEN_RFMD_MAGIC 0x93 1078#define RTW_BBP_ANTATTEN_MAXIM_MAGIC 0xb3 1079#define RTW_BBP_ANTATTEN_DFLANTB 0x40 1080#define RTW_BBP_ANTATTEN_CHAN14 0x0c 1081 1082#define RTW_BBP_TRL 0x11 /* guess: transmit/receive 1083 * switch latency 1084 */ 1085#define RTW_BBP_SYS2 0x12 1086#define RTW_BBP_SYS2_ANTDIV 0x80 /* enable antenna diversity */ 1087#define RTW_BBP_SYS2_RATE_MASK __BITS(5,4) /* loopback rate? 1088 * 0: 1Mbps 1089 * 1: 2Mbps 1090 * 2: 5.5Mbps 1091 * 3: 11Mbps 1092 */ 1093#define RTW_BBP_SYS3 0x13 1094/* carrier-sense threshold */ 1095#define RTW_BBP_SYS3_CSTHRESH_MASK __BITS(0,3) 1096#define RTW_BBP_CHESTLIM 0x19 /* guess: channel energy-detect 1097 * threshold 1098 */ 1099#define RTW_BBP_CHSQLIM 0x1a /* guess: channel signal-quality 1100 * threshold 1101 */ 1102