1124837Smtm/* $NetBSD: ncr5380var.h,v 1.34 2018/01/24 09:04:45 skrll Exp $ */ 2124837Smtm 3124837Smtm/* 4124837Smtm * Copyright (c) 1995 David Jones, Gordon W. Ross 5124837Smtm * Copyright (c) 1994 Jarle Greipsland 6124837Smtm * All rights reserved. 7124837Smtm * 8124837Smtm * Redistribution and use in source and binary forms, with or without 9124837Smtm * modification, are permitted provided that the following conditions 10124837Smtm * are met: 11124837Smtm * 1. Redistributions of source code must retain the above copyright 12124837Smtm * notice, this list of conditions and the following disclaimer. 13124837Smtm * 2. Redistributions in binary form must reproduce the above copyright 14124837Smtm * notice, this list of conditions and the following disclaimer in the 15124837Smtm * documentation and/or other materials provided with the distribution. 16124837Smtm * 3. The name of the authors may not be used to endorse or promote products 17124837Smtm * derived from this software without specific prior written permission. 18124837Smtm * 4. All advertising materials mentioning features or use of this software 19124837Smtm * must display the following acknowledgement: 20124837Smtm * This product includes software developed by 21124837Smtm * David Jones and Gordon Ross 22124837Smtm * 23124837Smtm * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 24124837Smtm * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25124837Smtm * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26124837Smtm * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27124837Smtm * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28130643Sru * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29124837Smtm * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30124837Smtm * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31131748Sru * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32124837Smtm * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33124837Smtm */ 34124837Smtm 35124837Smtm/* 36124837Smtm * This file defines the interface between the machine-dependent 37124837Smtm * module and the machine-independent ncr5380sbc.c module. 38124837Smtm */ 39124837Smtm 40124837Smtm/* 41124837Smtm * Currently amd64, alpha, i386, mips, news68k, sparc, sun2, and vax 42124837Smtm * use real bus space: 43124837Smtm * acorn32: csa driver; easy to convert 44124837Smtm * mac68k: sbc driver; easy to convert 45124837Smtm * pc532: ncr driver; need bus.h first 46124837Smtm * sun3: si driver; need bus.h first 47124837Smtm */ 48124837Smtm#if \ 49130643Sru defined(__alpha__) || \ 50124837Smtm defined(__amd64__) || \ 51124837Smtm defined(__i386__) || \ 52124837Smtm defined(__mips__) || \ 53124837Smtm defined(news68k) || \ 54124837Smtm defined(__sparc__) || \ 55124837Smtm defined(sun2) || \ 56124837Smtm defined(__vax__) 57124837Smtm# define NCR5380_USE_BUS_SPACE 58124837Smtm#endif 59124837Smtm 60124837Smtm/* 61124837Smtm * Handy read/write macros 62124837Smtm */ 63124837Smtm#ifdef NCR5380_USE_BUS_SPACE 64124837Smtm# include <sys/bus.h> 65124837Smtm/* bus_space() variety */ 66124837Smtm# define NCR5380_READ(sc, reg) bus_space_read_1(sc->sc_regt, \ 67124837Smtm sc->sc_regh, sc->reg) 68124837Smtm# define NCR5380_WRITE(sc, reg, val) bus_space_write_1(sc->sc_regt, \ 69130643Sru sc->sc_regh, sc->reg, val) 70130643Sru#else 71130643Sru/* legacy memory-mapped variety */ 72124837Smtm# define NCR5380_READ(sc, reg) (*sc->reg) 73130643Sru# define NCR5380_WRITE(sc, reg, val) do { *(sc->reg) = val; } while (0) 74130643Sru#endif 75124837Smtm 76124837Smtm#define SCI_CLR_INTR(sc) NCR5380_READ(sc, sci_iack) 77124837Smtm#define SCI_BUSY(sc) (NCR5380_READ(sc, sci_bus_csr) & SCI_BUS_BSY) 78124837Smtm 79124837Smtm/* These are NOT artibtrary, but map to bits in sci_tcmd */ 80124837Smtm#define PHASE_DATA_OUT 0x0 81124837Smtm#define PHASE_DATA_IN 0x1 82124837Smtm#define PHASE_COMMAND 0x2 83124837Smtm#define PHASE_STATUS 0x3 84124837Smtm#define PHASE_UNSPEC1 0x4 85124837Smtm#define PHASE_UNSPEC2 0x5 86124837Smtm#define PHASE_MSG_OUT 0x6 87124837Smtm#define PHASE_MSG_IN 0x7 88124837Smtm 89124837Smtm/* 90124837Smtm * This illegal phase is used to prevent the 5380 from having 91124837Smtm * a phase-match condition when we don't want one, such as 92124837Smtm * when setting up the DMA engine or whatever... 93124837Smtm */ 94124837Smtm#define PHASE_INVALID PHASE_UNSPEC1 95124837Smtm 96124837Smtm 97124837Smtm/* Per-request state. This is required in order to support reselection. */ 98124837Smtmstruct sci_req { 99124837Smtm struct scsipi_xfer *sr_xs; /* Pointer to xfer struct, NULL=unused */ 100124837Smtm int sr_target, sr_lun; /* For fast access */ 101124837Smtm void *sr_dma_hand; /* Current DMA hnadle */ 102124837Smtm uint8_t *sr_dataptr; /* Saved data pointer */ 103124837Smtm int sr_datalen; 104124837Smtm int sr_flags; /* Internal error code */ 105124837Smtm#define SR_IMMED 1 /* Immediate command */ 106124837Smtm#define SR_SENSE 2 /* We are getting sense */ 107124837Smtm#define SR_OVERDUE 4 /* Timeout while not current */ 108124837Smtm#define SR_ERROR 8 /* Error occurred */ 109124837Smtm int sr_status; /* Status code from last cmd */ 110124837Smtm}; 111124837Smtm#define SCI_OPENINGS 16 /* How many commands we can enqueue. */ 112124837Smtm 113124837Smtm 114124837Smtmstruct ncr5380_softc { 115130643Sru device_t sc_dev; 116130643Sru struct scsipi_adapter sc_adapter; 117124837Smtm struct scsipi_channel sc_channel; 118124837Smtm 119124837Smtm#ifdef NCR5380_USE_BUS_SPACE 120124837Smtm /* Pointers to bus_space */ 121124837Smtm bus_space_tag_t sc_regt; 122124837Smtm bus_space_handle_t sc_regh; 123124837Smtm 124172880Sru /* Pointers to 5380 registers. */ 125124837Smtm bus_size_t sci_r0; 126124837Smtm bus_size_t sci_r1; 127124837Smtm bus_size_t sci_r2; 128124837Smtm bus_size_t sci_r3; 129124837Smtm bus_size_t sci_r4; 130124837Smtm bus_size_t sci_r5; 131124837Smtm bus_size_t sci_r6; 132124837Smtm bus_size_t sci_r7; 133124837Smtm#else 134124837Smtm /* Pointers to 5380 registers. See ncr5380reg.h */ 135124837Smtm volatile uint8_t *sci_r0; 136124837Smtm volatile uint8_t *sci_r1; 137124837Smtm volatile uint8_t *sci_r2; 138124837Smtm volatile uint8_t *sci_r3; 139 volatile uint8_t *sci_r4; 140 volatile uint8_t *sci_r5; 141 volatile uint8_t *sci_r6; 142 volatile uint8_t *sci_r7; 143#endif 144 145 /* Functions set from MD code */ 146 int (*sc_pio_out)(struct ncr5380_softc *, 147 int, int, uint8_t *); 148 int (*sc_pio_in)(struct ncr5380_softc *, 149 int, int, uint8_t *); 150 void (*sc_dma_alloc)(struct ncr5380_softc *); 151 void (*sc_dma_free)(struct ncr5380_softc *); 152 153 void (*sc_dma_setup)(struct ncr5380_softc *); 154 void (*sc_dma_start)(struct ncr5380_softc *); 155 void (*sc_dma_poll)(struct ncr5380_softc *); 156 void (*sc_dma_eop)(struct ncr5380_softc *); 157 void (*sc_dma_stop)(struct ncr5380_softc *); 158 159 void (*sc_intr_on)(struct ncr5380_softc *); 160 void (*sc_intr_off)(struct ncr5380_softc *); 161 162 int sc_flags; /* Misc. flags and capabilities */ 163#define NCR5380_FORCE_POLLING 1 /* Do not use interrupts. */ 164 165 /* Set bits in this to disable disconnect per-target. */ 166 int sc_no_disconnect; 167 168 /* Set bits in this to disable parity for some target. */ 169 int sc_parity_disable; 170 171 int sc_min_dma_len; /* Smaller than this is done with PIO */ 172 173 /* Begin MI shared data */ 174 175 int sc_state; 176#define NCR_IDLE 0 /* Ready for new work. */ 177#define NCR_WORKING 0x01 /* Some command is in progress. */ 178#define NCR_ABORTING 0x02 /* Bailing out */ 179#define NCR_DOINGDMA 0x04 /* The FIFO data path is active! */ 180#define NCR_DROP_MSGIN 0x10 /* Discard all msgs (parity err detected) */ 181 182 /* The request that has the bus now. */ 183 struct sci_req *sc_current; 184 185 /* Active data pointer for current SCSI command. */ 186 uint8_t *sc_dataptr; 187 int sc_datalen; 188 189 /* Begin MI private data */ 190 191 /* The number of operations in progress on the bus */ 192 volatile int sc_ncmds; 193 194 /* Ring buffer of pending/active requests */ 195 struct sci_req sc_ring[SCI_OPENINGS]; 196 int sc_rr; /* Round-robin scan pointer */ 197 198 /* Active requests, by target/LUN */ 199 struct sci_req *sc_matrix[8][8]; 200 201 /* Message stuff */ 202 int sc_prevphase; 203 204 u_int sc_msgpriq; /* Messages we want to send */ 205 u_int sc_msgoutq; /* Messages sent during last MESSAGE OUT */ 206 u_int sc_msgout; /* Message last transmitted */ 207#define SEND_DEV_RESET 0x01 208#define SEND_PARITY_ERROR 0x02 209#define SEND_ABORT 0x04 210#define SEND_REJECT 0x08 211#define SEND_INIT_DET_ERR 0x10 212#define SEND_IDENTIFY 0x20 213#define SEND_SDTR 0x40 214#define SEND_WDTR 0x80 215#define NCR_MAX_MSG_LEN 8 216 uint8_t sc_omess[NCR_MAX_MSG_LEN]; 217 uint8_t *sc_omp; /* Outgoing message pointer */ 218 uint8_t sc_imess[NCR_MAX_MSG_LEN]; 219 uint8_t *sc_imp; /* Incoming message pointer */ 220 int sc_rev; /* Chip revision */ 221#define NCR_VARIANT_NCR5380 0 222#define NCR_VARIANT_DP8490 1 223#define NCR_VARIANT_NCR53C400 2 224#define NCR_VARIANT_PAS16 3 225#define NCR_VARIANT_CXD1180 4 226 227}; 228 229void ncr5380_attach(struct ncr5380_softc *); 230int ncr5380_detach(struct ncr5380_softc *, int); 231int ncr5380_intr(void *); 232void ncr5380_scsipi_request(struct scsipi_channel *, 233 scsipi_adapter_req_t, void *); 234int ncr5380_pio_in(struct ncr5380_softc *, int, int, uint8_t *); 235int ncr5380_pio_out(struct ncr5380_softc *, int, int, uint8_t *); 236void ncr5380_init(struct ncr5380_softc *); 237 238#ifdef NCR5380_DEBUG 239extern struct ncr5380_softc *ncr5380_debug_sc; 240void ncr5380_trace(const char *msg, long val); 241#define NCR_TRACE(msg, val) ncr5380_trace(msg, val) 242#else /* NCR5380_DEBUG */ 243#define NCR_TRACE(msg, val) /* nada */ 244#endif /* NCR5380_DEBUG */ 245