ispreg.h revision 1.9
1/* $NetBSD: ispreg.h,v 1.9 1998/12/05 19:48:23 mjacob Exp $ */ 2/* ispreg.h 1.7 */ 3/* 4 * Machine Independent (well, as best as possible) register 5 * definitions for Qlogic ISP SCSI adapters. 6 * 7 *--------------------------------------- 8 * Copyright (c) 1997 by Matthew Jacob 9 * NASA/Ames Research Center 10 * All rights reserved. 11 *--------------------------------------- 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice immediately at the beginning of the file, without modification, 17 * this list of conditions, and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 28 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36#ifndef _ISPREG_H 37#define _ISPREG_H 38 39/* 40 * Hardware definitions for the Qlogic ISP registers. 41 */ 42 43/* 44 * This defines types of access to various registers. 45 * 46 * R: Read Only 47 * W: Write Only 48 * RW: Read/Write 49 * 50 * R*, W*, RW*: Read Only, Write Only, Read/Write, but only 51 * if RISC processor in ISP is paused. 52 */ 53 54/* 55 * Offsets for various register blocks. 56 * 57 * Sad but true, different architectures have different offsets. 58 */ 59 60#define BIU_REGS_OFF 0x00 61 62#define PCI_MBOX_REGS_OFF 0x70 63#define PCI_MBOX_REGS2100_OFF 0x10 64#define SBUS_MBOX_REGS_OFF 0x80 65 66#define PCI_SXP_REGS_OFF 0x80 67#define SBUS_SXP_REGS_OFF 0x200 68 69#define PCI_RISC_REGS_OFF 0x80 70#define SBUS_RISC_REGS_OFF 0x400 71 72/* 73 * NB: The *_BLOCK definitions have no specific hardware meaning. 74 * They serve simply to note to the MD layer which block of 75 * registers offsets are being accessed. 76 */ 77 78/* 79 * Bus Interface Block Register Offsets 80 */ 81#define BIU_BLOCK 0x0100 82#define BIU_ID_LO BIU_BLOCK+0x0 /* R : Bus ID, Low */ 83#define BIU2100_FLASH_ADDR BIU_BLOCK+0x0 84#define BIU_ID_HI BIU_BLOCK+0x2 /* R : Bus ID, High */ 85#define BIU2100_FLASH_DATA BIU_BLOCK+0x2 86#define BIU_CONF0 BIU_BLOCK+0x4 /* R : Bus Configuration #0 */ 87#define BIU_CONF1 BIU_BLOCK+0x6 /* R : Bus Configuration #1 */ 88#define BIU2100_CSR BIU_BLOCK+0x6 89#define BIU_ICR BIU_BLOCK+0x8 /* RW : Bus Interface Ctrl */ 90#define BIU_ISR BIU_BLOCK+0xA /* R : Bus Interface Status */ 91#define BIU_SEMA BIU_BLOCK+0xC /* RW : Bus Semaphore */ 92#define BIU_NVRAM BIU_BLOCK+0xE /* RW : Bus NVRAM */ 93#define CDMA_CONF BIU_BLOCK+0x20 /* RW*: DMA Configuration */ 94#define CDMA2100_CONTROL CDMA_CONF 95#define CDMA_CONTROL BIU_BLOCK+0x22 /* RW*: DMA Control */ 96#define CDMA_STATUS BIU_BLOCK+0x24 /* R : DMA Status */ 97#define CDMA_FIFO_STS BIU_BLOCK+0x26 /* R : DMA FIFO Status */ 98#define CDMA_COUNT BIU_BLOCK+0x28 /* RW*: DMA Transfer Count */ 99#define CDMA_ADDR0 BIU_BLOCK+0x2C /* RW*: DMA Address, Word 0 */ 100#define CDMA_ADDR1 BIU_BLOCK+0x2E /* RW*: DMA Address, Word 1 */ 101/* these are for the 1040A cards */ 102#define CDMA_ADDR2 BIU_BLOCK+0x30 /* RW*: DMA Address, Word 2 */ 103#define CDMA_ADDR3 BIU_BLOCK+0x32 /* RW*: DMA Address, Word 3 */ 104 105#define DDMA_CONF BIU_BLOCK+0x40 /* RW*: DMA Configuration */ 106#define TDMA2100_CONTROL DDMA_CONF 107#define DDMA_CONTROL BIU_BLOCK+0x42 /* RW*: DMA Control */ 108#define DDMA_STATUS BIU_BLOCK+0x44 /* R : DMA Status */ 109#define DDMA_FIFO_STS BIU_BLOCK+0x46 /* R : DMA FIFO Status */ 110#define DDMA_COUNT_LO BIU_BLOCK+0x48 /* RW*: DMA Xfer Count, Low */ 111#define DDMA_COUNT_HI BIU_BLOCK+0x4A /* RW*: DMA Xfer Count, High */ 112#define DDMA_ADDR0 BIU_BLOCK+0x4C /* RW*: DMA Address, Word 0 */ 113#define DDMA_ADDR1 BIU_BLOCK+0x4E /* RW*: DMA Address, Word 1 */ 114/* these are for the 1040A cards */ 115#define DDMA_ADDR2 BIU_BLOCK+0x50 /* RW*: DMA Address, Word 2 */ 116#define DDMA_ADDR3 BIU_BLOCK+0x52 /* RW*: DMA Address, Word 3 */ 117 118#define DFIFO_COMMAND BIU_BLOCK+0x60 /* RW : Command FIFO Port */ 119#define RDMA2100_CONTROL DFIFO_COMMAND 120#define DFIFO_DATA BIU_BLOCK+0x62 /* RW : Data FIFO Port */ 121 122/* 123 * Bus Interface Block Register Definitions 124 */ 125/* BUS CONFIGURATION REGISTER #0 */ 126#define BIU_CONF0_HW_MASK 0x000F /* Hardware revision mask */ 127/* BUS CONFIGURATION REGISTER #1 */ 128 129#define BIU_SBUS_CONF1_PARITY 0x0100 /* Enable parity checking */ 130#define BIU_SBUS_CONF1_FCODE_MASK 0x00F0 /* Fcode cycle mask */ 131 132#define BIU_PCI_CONF1_FIFO_128 0x0040 /* 128 bytes FIFO threshold */ 133#define BIU_PCI_CONF1_FIFO_64 0x0030 /* 64 bytes FIFO threshold */ 134#define BIU_PCI_CONF1_FIFO_32 0x0020 /* 32 bytes FIFO threshold */ 135#define BIU_PCI_CONF1_FIFO_16 0x0010 /* 16 bytes FIFO threshold */ 136#define BIU_BURST_ENABLE 0x0004 /* Global enable Bus bursts */ 137#define BIU_SBUS_CONF1_FIFO_64 0x0003 /* 64 bytes FIFO threshold */ 138#define BIU_SBUS_CONF1_FIFO_32 0x0002 /* 32 bytes FIFO threshold */ 139#define BIU_SBUS_CONF1_FIFO_16 0x0001 /* 16 bytes FIFO threshold */ 140#define BIU_SBUS_CONF1_FIFO_8 0x0000 /* 8 bytes FIFO threshold */ 141#define BIU_SBUS_CONF1_BURST8 0x0008 /* Enable 8-byte bursts */ 142#define BIU_PCI_CONF1_SXP 0x0008 /* SXP register select */ 143 144 /* ISP2100 Bus Control/Status Register */ 145 146#define BIU2100_ICSR_REGBSEL 0x30 /* RW: register bank select */ 147#define BIU2100_RISC_REGS (0 << 4) /* RISC Regs */ 148#define BIU2100_FB_REGS (1 << 4) /* FrameBuffer Regs */ 149#define BIU2100_FPM0_REGS (2 << 4) /* FPM 0 Regs */ 150#define BIU2100_FPM1_REGS (3 << 4) /* FPM 1 Regs */ 151#define BIU2100_PCI64 0x04 /* R: 64 Bit PCI slot */ 152#define BIU2100_FLASH_ENABLE 0x02 /* RW: Enable Flash RAM */ 153#define BIU2100_SOFT_RESET 0x01 154/* SOFT RESET FOR ISP2100 is same bit, but in this register, not ICR */ 155 156 157/* BUS CONTROL REGISTER */ 158#define BIU_ICR_ENABLE_DMA_INT 0x0020 /* Enable DMA interrupts */ 159#define BIU_ICR_ENABLE_CDMA_INT 0x0010 /* Enable CDMA interrupts */ 160#define BIU_ICR_ENABLE_SXP_INT 0x0008 /* Enable SXP interrupts */ 161#define BIU_ICR_ENABLE_RISC_INT 0x0004 /* Enable Risc interrupts */ 162#define BIU_ICR_ENABLE_ALL_INTS 0x0002 /* Global enable all inter */ 163#define BIU_ICR_SOFT_RESET 0x0001 /* Soft Reset of ISP */ 164 165#define BIU2100_ICR_ENABLE_ALL_INTS 0x8000 166#define BIU2100_ICR_ENA_FPM_INT 0x0020 167#define BIU2100_ICR_ENA_FB_INT 0x0010 168#define BIU2100_ICR_ENA_RISC_INT 0x0008 169#define BIU2100_ICR_ENA_CDMA_INT 0x0004 170#define BIU2100_ICR_ENABLE_RXDMA_INT 0x0002 171#define BIU2100_ICR_ENABLE_TXDMA_INT 0x0001 172#define BIU2100_ICR_DISABLE_ALL_INTS 0x0000 173 174#define ENABLE_INTS(isp) (isp->isp_type & ISP_HA_SCSI)? \ 175 ISP_WRITE(isp, BIU_ICR, BIU_ICR_ENABLE_RISC_INT | BIU_ICR_ENABLE_ALL_INTS) : \ 176 ISP_WRITE(isp, BIU_ICR, BIU2100_ICR_ENA_RISC_INT | BIU2100_ICR_ENABLE_ALL_INTS) 177 178#define DISABLE_INTS(isp) ISP_WRITE(isp, BIU_ICR, 0) 179 180/* BUS STATUS REGISTER */ 181#define BIU_ISR_DMA_INT 0x0020 /* DMA interrupt pending */ 182#define BIU_ISR_CDMA_INT 0x0010 /* CDMA interrupt pending */ 183#define BIU_ISR_SXP_INT 0x0008 /* SXP interrupt pending */ 184#define BIU_ISR_RISC_INT 0x0004 /* Risc interrupt pending */ 185#define BIU_ISR_IPEND 0x0002 /* Global interrupt pending */ 186 187#define BIU2100_ISR_INT_PENDING 0x8000 /* Global interrupt pending */ 188#define BIU2100_ISR_FPM_INT 0x0020 /* FPM interrupt pending */ 189#define BIU2100_ISR_FB_INT 0x0010 /* FB interrupt pending */ 190#define BIU2100_ISR_RISC_INT 0x0008 /* Risc interrupt pending */ 191#define BIU2100_ISR_CDMA_INT 0x0004 /* CDMA interrupt pending */ 192#define BIU2100_ISR_RXDMA_INT_PENDING 0x0002 /* Global interrupt pending */ 193#define BIU2100_ISR_TXDMA_INT_PENDING 0x0001 /* Global interrupt pending */ 194 195 196/* BUS SEMAPHORE REGISTER */ 197#define BIU_SEMA_STATUS 0x0002 /* Semaphore Status Bit */ 198#define BIU_SEMA_LOCK 0x0001 /* Semaphore Lock Bit */ 199 200/* NVRAM SEMAPHORE REGISTER */ 201#define BIU_NVRAM_CLOCK 0x0001 202#define BIU_NVRAM_SELECT 0x0002 203#define BIU_NVRAM_DATAOUT 0x0004 204#define BIU_NVRAM_DATAIN 0x0008 205#define ISP_NVRAM_READ 6 206 207/* COMNMAND && DATA DMA CONFIGURATION REGISTER */ 208#define DMA_ENABLE_SXP_DMA 0x0008 /* Enable SXP to DMA Data */ 209#define DMA_ENABLE_INTS 0x0004 /* Enable interrupts to RISC */ 210#define DMA_ENABLE_BURST 0x0002 /* Enable Bus burst trans */ 211#define DMA_DMA_DIRECTION 0x0001 /* 212 * Set DMA direction: 213 * 0 - DMA FIFO to host 214 * 1 - Host to DMA FIFO 215 */ 216 217/* COMMAND && DATA DMA CONTROL REGISTER */ 218#define DMA_CNTRL_SUSPEND_CHAN 0x0010 /* Suspend DMA transfer */ 219#define DMA_CNTRL_CLEAR_CHAN 0x0008 /* 220 * Clear FIFO and DMA Channel, 221 * reset DMA registers 222 */ 223#define DMA_CNTRL_CLEAR_FIFO 0x0004 /* Clear DMA FIFO */ 224#define DMA_CNTRL_RESET_INT 0x0002 /* Clear DMA interrupt */ 225#define DMA_CNTRL_STROBE 0x0001 /* Start DMA transfer */ 226 227/* 228 * Variants of same for 2100 229 */ 230#define DMA_CNTRL2100_CLEAR_CHAN 0x0004 231#define DMA_CNTRL2100_RESET_INT 0x0002 232 233 234 235/* DMA STATUS REGISTER */ 236#define DMA_SBUS_STATUS_PIPE_MASK 0x00C0 /* DMA Pipeline status mask */ 237#define DMA_SBUS_STATUS_CHAN_MASK 0x0030 /* Channel status mask */ 238#define DMA_SBUS_STATUS_BUS_PARITY 0x0008 /* Parity Error on bus */ 239#define DMA_SBUS_STATUS_BUS_ERR 0x0004 /* Error Detected on bus */ 240#define DMA_SBUS_STATUS_TERM_COUNT 0x0002 /* DMA Transfer Completed */ 241#define DMA_SBUS_STATUS_INTERRUPT 0x0001 /* Enable DMA channel inter */ 242 243#define DMA_PCI_STATUS_INTERRUPT 0x8000 /* Enable DMA channel inter */ 244#define DMA_PCI_STATUS_RETRY_STAT 0x4000 /* Retry status */ 245#define DMA_PCI_STATUS_CHAN_MASK 0x3000 /* Channel status mask */ 246#define DMA_PCI_STATUS_FIFO_OVR 0x0100 /* DMA FIFO overrun cond */ 247#define DMA_PCI_STATUS_FIFO_UDR 0x0080 /* DMA FIFO underrun cond */ 248#define DMA_PCI_STATUS_BUS_ERR 0x0040 /* Error Detected on bus */ 249#define DMA_PCI_STATUS_BUS_PARITY 0x0020 /* Parity Error on bus */ 250#define DMA_PCI_STATUS_CLR_PEND 0x0010 /* DMA clear pending */ 251#define DMA_PCI_STATUS_TERM_COUNT 0x0008 /* DMA Transfer Completed */ 252#define DMA_PCI_STATUS_DMA_SUSP 0x0004 /* DMA suspended */ 253#define DMA_PCI_STATUS_PIPE_MASK 0x0003 /* DMA Pipeline status mask */ 254 255/* DMA Status Register, pipeline status bits */ 256#define DMA_SBUS_PIPE_FULL 0x00C0 /* Both pipeline stages full */ 257#define DMA_SBUS_PIPE_OVERRUN 0x0080 /* Pipeline overrun */ 258#define DMA_SBUS_PIPE_STAGE1 0x0040 /* 259 * Pipeline stage 1 Loaded, 260 * stage 2 empty 261 */ 262#define DMA_PCI_PIPE_FULL 0x0003 /* Both pipeline stages full */ 263#define DMA_PCI_PIPE_OVERRUN 0x0002 /* Pipeline overrun */ 264#define DMA_PCI_PIPE_STAGE1 0x0001 /* 265 * Pipeline stage 1 Loaded, 266 * stage 2 empty 267 */ 268#define DMA_PIPE_EMPTY 0x0000 /* All pipeline stages empty */ 269 270/* DMA Status Register, channel status bits */ 271#define DMA_SBUS_CHAN_SUSPEND 0x0030 /* Channel error or suspended */ 272#define DMA_SBUS_CHAN_TRANSFER 0x0020 /* Chan transfer in progress */ 273#define DMA_SBUS_CHAN_ACTIVE 0x0010 /* Chan trans to host active */ 274#define DMA_PCI_CHAN_TRANSFER 0x3000 /* Chan transfer in progress */ 275#define DMA_PCI_CHAN_SUSPEND 0x2000 /* Channel error or suspended */ 276#define DMA_PCI_CHAN_ACTIVE 0x1000 /* Chan trans to host active */ 277#define ISP_DMA_CHAN_IDLE 0x0000 /* Chan idle (normal comp) */ 278 279 280/* DMA FIFO STATUS REGISTER */ 281#define DMA_FIFO_STATUS_OVERRUN 0x0200 /* FIFO Overrun Condition */ 282#define DMA_FIFO_STATUS_UNDERRUN 0x0100 /* FIFO Underrun Condition */ 283#define DMA_FIFO_SBUS_COUNT_MASK 0x007F /* FIFO Byte count mask */ 284#define DMA_FIFO_PCI_COUNT_MASK 0x00FF /* FIFO Byte count mask */ 285 286/* 287 * Mailbox Block Register Offsets 288 */ 289 290#define MBOX_BLOCK 0x0200 291#define INMAILBOX0 MBOX_BLOCK+0x0 292#define INMAILBOX1 MBOX_BLOCK+0x2 293#define INMAILBOX2 MBOX_BLOCK+0x4 294#define INMAILBOX3 MBOX_BLOCK+0x6 295#define INMAILBOX4 MBOX_BLOCK+0x8 296#define INMAILBOX5 MBOX_BLOCK+0xA 297#define INMAILBOX6 MBOX_BLOCK+0xC 298#define INMAILBOX7 MBOX_BLOCK+0xE 299 300#define OUTMAILBOX0 MBOX_BLOCK+0x0 301#define OUTMAILBOX1 MBOX_BLOCK+0x2 302#define OUTMAILBOX2 MBOX_BLOCK+0x4 303#define OUTMAILBOX3 MBOX_BLOCK+0x6 304#define OUTMAILBOX4 MBOX_BLOCK+0x8 305#define OUTMAILBOX5 MBOX_BLOCK+0xA 306#define OUTMAILBOX6 MBOX_BLOCK+0xC 307#define OUTMAILBOX7 MBOX_BLOCK+0xE 308 309#define OMBOX_OFFN(n) (MBOX_BLOCK + (n * 2)) 310#define NMBOX(isp) \ 311 (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \ 312 ((isp)->isp_type & ISP_HA_FC))? 8 : 6) 313 314/* 315 * SXP Block Register Offsets 316 */ 317#define SXP_BLOCK 0x0400 318#define SXP_PART_ID SXP_BLOCK+0x0 /* R : Part ID Code */ 319#define SXP_CONFIG1 SXP_BLOCK+0x2 /* RW*: Configuration Reg #1 */ 320#define SXP_CONFIG2 SXP_BLOCK+0x4 /* RW*: Configuration Reg #2 */ 321#define SXP_CONFIG3 SXP_BLOCK+0x6 /* RW*: Configuration Reg #2 */ 322#define SXP_INSTRUCTION SXP_BLOCK+0xC /* RW*: Instruction Pointer */ 323#define SXP_RETURN_ADDR SXP_BLOCK+0x10 /* RW*: Return Address */ 324#define SXP_COMMAND SXP_BLOCK+0x14 /* RW*: Command */ 325#define SXP_INTERRUPT SXP_BLOCK+0x18 /* R : Interrupt */ 326#define SXP_SEQUENCE SXP_BLOCK+0x1C /* RW*: Sequence */ 327#define SXP_GROSS_ERR SXP_BLOCK+0x1E /* R : Gross Error */ 328#define SXP_EXCEPTION SXP_BLOCK+0x20 /* RW*: Exception Enable */ 329#define SXP_OVERRIDE SXP_BLOCK+0x24 /* RW*: Override */ 330#define SXP_LITERAL_BASE SXP_BLOCK+0x28 /* RW*: Literal Base */ 331#define SXP_USER_FLAGS SXP_BLOCK+0x2C /* RW*: User Flags */ 332#define SXP_USER_EXCEPT SXP_BLOCK+0x30 /* RW*: User Exception */ 333#define SXP_BREAKPOINT SXP_BLOCK+0x34 /* RW*: Breakpoint */ 334#define SXP_SCSI_ID SXP_BLOCK+0x40 /* RW*: SCSI ID */ 335#define SXP_DEV_CONFIG1 SXP_BLOCK+0x42 /* RW*: Device Config Reg #1 */ 336#define SXP_DEV_CONFIG2 SXP_BLOCK+0x44 /* RW*: Device Config Reg #2 */ 337#define SXP_PHASE_POINTER SXP_BLOCK+0x48 /* RW*: SCSI Phase Pointer */ 338#define SXP_BUF_POINTER SXP_BLOCK+0x4C /* RW*: SCSI Buffer Pointer */ 339#define SXP_BUF_COUNTER SXP_BLOCK+0x50 /* RW*: SCSI Buffer Counter */ 340#define SXP_BUFFER SXP_BLOCK+0x52 /* RW*: SCSI Buffer */ 341#define SXP_BUF_BYTE SXP_BLOCK+0x54 /* RW*: SCSI Buffer Byte */ 342#define SXP_BUF_WORD SXP_BLOCK+0x56 /* RW*: SCSI Buffer Word */ 343#define SXP_BUF_WORD_TRAN SXP_BLOCK+0x58 /* RW*: SCSI Buffer Wd xlate */ 344#define SXP_FIFO SXP_BLOCK+0x5A /* RW*: SCSI FIFO */ 345#define SXP_FIFO_STATUS SXP_BLOCK+0x5C /* RW*: SCSI FIFO Status */ 346#define SXP_FIFO_TOP SXP_BLOCK+0x5E /* RW*: SCSI FIFO Top Resid */ 347#define SXP_FIFO_BOTTOM SXP_BLOCK+0x60 /* RW*: SCSI FIFO Bot Resid */ 348#define SXP_TRAN_REG SXP_BLOCK+0x64 /* RW*: SCSI Transferr Reg */ 349#define SXP_TRAN_COUNT_LO SXP_BLOCK+0x68 /* RW*: SCSI Trans Count */ 350#define SXP_TRAN_COUNT_HI SXP_BLOCK+0x6A /* RW*: SCSI Trans Count */ 351#define SXP_TRAN_COUNTER_LO SXP_BLOCK+0x6C /* RW*: SCSI Trans Counter */ 352#define SXP_TRAN_COUNTER_HI SXP_BLOCK+0x6E /* RW*: SCSI Trans Counter */ 353#define SXP_ARB_DATA SXP_BLOCK+0x70 /* R : SCSI Arb Data */ 354#define SXP_PINS_CONTROL SXP_BLOCK+0x72 /* RW*: SCSI Control Pins */ 355#define SXP_PINS_DATA SXP_BLOCK+0x74 /* RW*: SCSI Data Pins */ 356#define SXP_PINS_DIFF SXP_BLOCK+0x76 /* RW*: SCSI Diff Pins */ 357 358 359/* SXP CONF1 REGISTER */ 360#define SXP_CONF1_ASYNCH_SETUP 0xF000 /* Asynchronous setup time */ 361#define SXP_CONF1_SELECTION_UNIT 0x0000 /* Selection time unit */ 362#define SXP_CONF1_SELECTION_TIMEOUT 0x0600 /* Selection timeout */ 363#define SXP_CONF1_CLOCK_FACTOR 0x00E0 /* Clock factor */ 364#define SXP_CONF1_SCSI_ID 0x000F /* SCSI id */ 365 366/* SXP CONF2 REGISTER */ 367#define SXP_CONF2_DISABLE_FILTER 0x0040 /* Disable SCSI rec filters */ 368#define SXP_CONF2_REQ_ACK_PULLUPS 0x0020 /* Enable req/ack pullups */ 369#define SXP_CONF2_DATA_PULLUPS 0x0010 /* Enable data pullups */ 370#define SXP_CONF2_CONFIG_AUTOLOAD 0x0008 /* Enable dev conf auto-load */ 371#define SXP_CONF2_RESELECT 0x0002 /* Enable reselection */ 372#define SXP_CONF2_SELECT 0x0001 /* Enable selection */ 373 374/* SXP INTERRUPT REGISTER */ 375#define SXP_INT_PARITY_ERR 0x8000 /* Parity error detected */ 376#define SXP_INT_GROSS_ERR 0x4000 /* Gross error detected */ 377#define SXP_INT_FUNCTION_ABORT 0x2000 /* Last cmd aborted */ 378#define SXP_INT_CONDITION_FAILED 0x1000 /* Last cond failed test */ 379#define SXP_INT_FIFO_EMPTY 0x0800 /* SCSI FIFO is empty */ 380#define SXP_INT_BUF_COUNTER_ZERO 0x0400 /* SCSI buf count == zero */ 381#define SXP_INT_XFER_ZERO 0x0200 /* SCSI trans count == zero */ 382#define SXP_INT_INT_PENDING 0x0080 /* SXP interrupt pending */ 383#define SXP_INT_CMD_RUNNING 0x0040 /* SXP is running a command */ 384#define SXP_INT_INT_RETURN_CODE 0x000F /* Interrupt return code */ 385 386 387/* SXP GROSS ERROR REGISTER */ 388#define SXP_GROSS_OFFSET_RESID 0x0040 /* Req/Ack offset not zero */ 389#define SXP_GROSS_OFFSET_UNDERFLOW 0x0020 /* Req/Ack offset underflow */ 390#define SXP_GROSS_OFFSET_OVERFLOW 0x0010 /* Req/Ack offset overflow */ 391#define SXP_GROSS_FIFO_UNDERFLOW 0x0008 /* SCSI FIFO underflow */ 392#define SXP_GROSS_FIFO_OVERFLOW 0x0004 /* SCSI FIFO overflow */ 393#define SXP_GROSS_WRITE_ERR 0x0002 /* SXP and RISC wrote to reg */ 394#define SXP_GROSS_ILLEGAL_INST 0x0001 /* Bad inst loaded into SXP */ 395 396/* SXP EXCEPTION REGISTER */ 397#define SXP_EXCEPT_USER_0 0x8000 /* Enable user exception #0 */ 398#define SXP_EXCEPT_USER_1 0x4000 /* Enable user exception #1 */ 399#define PCI_SXP_EXCEPT_SCAM 0x0400 /* SCAM Selection enable */ 400#define SXP_EXCEPT_BUS_FREE 0x0200 /* Enable Bus Free det */ 401#define SXP_EXCEPT_TARGET_ATN 0x0100 /* Enable TGT mode atten det */ 402#define SXP_EXCEPT_RESELECTED 0x0080 /* Enable ReSEL exc handling */ 403#define SXP_EXCEPT_SELECTED 0x0040 /* Enable SEL exc handling */ 404#define SXP_EXCEPT_ARBITRATION 0x0020 /* Enable ARB exc handling */ 405#define SXP_EXCEPT_GROSS_ERR 0x0010 /* Enable gross error except */ 406#define SXP_EXCEPT_BUS_RESET 0x0008 /* Enable Bus Reset except */ 407 408 /* SXP OVERRIDE REGISTER */ 409#define SXP_ORIDE_EXT_TRIGGER 0x8000 /* Enable external trigger */ 410#define SXP_ORIDE_STEP 0x4000 /* Enable single step mode */ 411#define SXP_ORIDE_BREAKPOINT 0x2000 /* Enable breakpoint reg */ 412#define SXP_ORIDE_PIN_WRITE 0x1000 /* Enable write to SCSI pins */ 413#define SXP_ORIDE_FORCE_OUTPUTS 0x0800 /* Force SCSI outputs on */ 414#define SXP_ORIDE_LOOPBACK 0x0400 /* Enable SCSI loopback mode */ 415#define SXP_ORIDE_PARITY_TEST 0x0200 /* Enable parity test mode */ 416#define SXP_ORIDE_TRISTATE_ENA_PINS 0x0100 /* Tristate SCSI enable pins */ 417#define SXP_ORIDE_TRISTATE_PINS 0x0080 /* Tristate SCSI pins */ 418#define SXP_ORIDE_FIFO_RESET 0x0008 /* Reset SCSI FIFO */ 419#define SXP_ORIDE_CMD_TERMINATE 0x0004 /* Terminate cur SXP com */ 420#define SXP_ORIDE_RESET_REG 0x0002 /* Reset SXP registers */ 421#define SXP_ORIDE_RESET_MODULE 0x0001 /* Reset SXP module */ 422 423/* SXP COMMANDS */ 424#define SXP_RESET_BUS_CMD 0x300b 425 426/* SXP SCSI ID REGISTER */ 427#define SXP_SELECTING_ID 0x0F00 /* (Re)Selecting id */ 428#define SXP_SELECT_ID 0x000F /* Select id */ 429 430/* SXP DEV CONFIG1 REGISTER */ 431#define SXP_DCONF1_SYNC_HOLD 0x7000 /* Synchronous data hold */ 432#define SXP_DCONF1_SYNC_SETUP 0x0F00 /* Synchronous data setup */ 433#define SXP_DCONF1_SYNC_OFFSET 0x000F /* Synchronous data offset */ 434 435 436/* SXP DEV CONFIG2 REGISTER */ 437#define SXP_DCONF2_FLAGS_MASK 0xF000 /* Device flags */ 438#define SXP_DCONF2_WIDE 0x0400 /* Enable wide SCSI */ 439#define SXP_DCONF2_PARITY 0x0200 /* Enable parity checking */ 440#define SXP_DCONF2_BLOCK_MODE 0x0100 /* Enable blk mode xfr count */ 441#define SXP_DCONF2_ASSERTION_MASK 0x0007 /* Assersion period mask */ 442 443 444/* SXP PHASE POINTER REGISTER */ 445#define SXP_PHASE_STATUS_PTR 0x1000 /* Status buffer offset */ 446#define SXP_PHASE_MSG_IN_PTR 0x0700 /* Msg in buffer offset */ 447#define SXP_PHASE_COM_PTR 0x00F0 /* Command buffer offset */ 448#define SXP_PHASE_MSG_OUT_PTR 0x0007 /* Msg out buffer offset */ 449 450 451/* SXP FIFO STATUS REGISTER */ 452#define SXP_FIFO_TOP_RESID 0x8000 /* Top residue reg full */ 453#define SXP_FIFO_ACK_RESID 0x4000 /* Wide transfers odd resid */ 454#define SXP_FIFO_COUNT_MASK 0x001C /* Words in SXP FIFO */ 455#define SXP_FIFO_BOTTOM_RESID 0x0001 /* Bottom residue reg full */ 456 457 458/* SXP CONTROL PINS REGISTER */ 459#define SXP_PINS_CON_PHASE 0x8000 /* Scsi phase valid */ 460#define SXP_PINS_CON_PARITY_HI 0x0400 /* Parity pin */ 461#define SXP_PINS_CON_PARITY_LO 0x0200 /* Parity pin */ 462#define SXP_PINS_CON_REQ 0x0100 /* SCSI bus REQUEST */ 463#define SXP_PINS_CON_ACK 0x0080 /* SCSI bus ACKNOWLEDGE */ 464#define SXP_PINS_CON_RST 0x0040 /* SCSI bus RESET */ 465#define SXP_PINS_CON_BSY 0x0020 /* SCSI bus BUSY */ 466#define SXP_PINS_CON_SEL 0x0010 /* SCSI bus SELECT */ 467#define SXP_PINS_CON_ATN 0x0008 /* SCSI bus ATTENTION */ 468#define SXP_PINS_CON_MSG 0x0004 /* SCSI bus MESSAGE */ 469#define SXP_PINS_CON_CD 0x0002 /* SCSI bus COMMAND */ 470#define SXP_PINS_CON_IO 0x0001 /* SCSI bus INPUT */ 471 472/* 473 * Set the hold time for the SCSI Bus Reset to be 250 ms 474 */ 475#define SXP_SCSI_BUS_RESET_HOLD_TIME 250 476 477/* SXP DIFF PINS REGISTER */ 478#define SXP_PINS_DIFF_SENSE 0x0200 /* DIFFSENS sig on SCSI bus */ 479#define SXP_PINS_DIFF_MODE 0x0100 /* DIFFM signal */ 480#define SXP_PINS_DIFF_ENABLE_OUTPUT 0x0080 /* Enable SXP SCSI data drv */ 481#define SXP_PINS_DIFF_PINS_MASK 0x007C /* Differential control pins */ 482#define SXP_PINS_DIFF_TARGET 0x0002 /* Enable SXP target mode */ 483#define SXP_PINS_DIFF_INITIATOR 0x0001 /* Enable SXP initiator mode */ 484 485/* 486 * RISC and Host Command and Control Block Register Offsets 487 */ 488#define RISC_BLOCK 0x0800 489 490#define RISC_ACC RISC_BLOCK+0x0 /* RW*: Accumulator */ 491#define RISC_R1 RISC_BLOCK+0x2 /* RW*: GP Reg R1 */ 492#define RISC_R2 RISC_BLOCK+0x4 /* RW*: GP Reg R2 */ 493#define RISC_R3 RISC_BLOCK+0x6 /* RW*: GP Reg R3 */ 494#define RISC_R4 RISC_BLOCK+0x8 /* RW*: GP Reg R4 */ 495#define RISC_R5 RISC_BLOCK+0xA /* RW*: GP Reg R5 */ 496#define RISC_R6 RISC_BLOCK+0xC /* RW*: GP Reg R6 */ 497#define RISC_R7 RISC_BLOCK+0xE /* RW*: GP Reg R7 */ 498#define RISC_R8 RISC_BLOCK+0x10 /* RW*: GP Reg R8 */ 499#define RISC_R9 RISC_BLOCK+0x12 /* RW*: GP Reg R9 */ 500#define RISC_R10 RISC_BLOCK+0x14 /* RW*: GP Reg R10 */ 501#define RISC_R11 RISC_BLOCK+0x16 /* RW*: GP Reg R11 */ 502#define RISC_R12 RISC_BLOCK+0x18 /* RW*: GP Reg R12 */ 503#define RISC_R13 RISC_BLOCK+0x1a /* RW*: GP Reg R13 */ 504#define RISC_R14 RISC_BLOCK+0x1c /* RW*: GP Reg R14 */ 505#define RISC_R15 RISC_BLOCK+0x1e /* RW*: GP Reg R15 */ 506#define RISC_PSR RISC_BLOCK+0x20 /* RW*: Processor Status */ 507#define RISC_IVR RISC_BLOCK+0x22 /* RW*: Interrupt Vector */ 508#define RISC_PCR RISC_BLOCK+0x24 /* RW*: Processor Ctrl */ 509#define RISC_RAR0 RISC_BLOCK+0x26 /* RW*: Ram Address #0 */ 510#define RISC_RAR1 RISC_BLOCK+0x28 /* RW*: Ram Address #1 */ 511#define RISC_LCR RISC_BLOCK+0x2a /* RW*: Loop Counter */ 512#define RISC_PC RISC_BLOCK+0x2c /* R : Program Counter */ 513#define RISC_MTR RISC_BLOCK+0x2e /* RW*: Memory Timing */ 514#define RISC_MTR2100 RISC_BLOCK+0x30 515 516#define RISC_EMB RISC_BLOCK+0x30 /* RW*: Ext Mem Boundary */ 517#define RISC_SP RISC_BLOCK+0x32 /* RW*: Stack Pointer */ 518#define RISC_HRL RISC_BLOCK+0x3e /* R *: Hardware Rev Level */ 519#define HCCR RISC_BLOCK+0x40 /* RW : Host Command & Ctrl */ 520#define BP0 RISC_BLOCK+0x42 /* RW : Processor Brkpt #0 */ 521#define BP1 RISC_BLOCK+0x44 /* RW : Processor Brkpt #1 */ 522#define TCR RISC_BLOCK+0x46 /* W : Test Control */ 523#define TMR RISC_BLOCK+0x48 /* W : Test Mode */ 524 525 526/* PROCESSOR STATUS REGISTER */ 527#define RISC_PSR_FORCE_TRUE 0x8000 528#define RISC_PSR_LOOP_COUNT_DONE 0x4000 529#define RISC_PSR_RISC_INT 0x2000 530#define RISC_PSR_TIMER_ROLLOVER 0x1000 531#define RISC_PSR_ALU_OVERFLOW 0x0800 532#define RISC_PSR_ALU_MSB 0x0400 533#define RISC_PSR_ALU_CARRY 0x0200 534#define RISC_PSR_ALU_ZERO 0x0100 535 536#define RISC_PSR_PCI_ULTRA 0x0080 537#define RISC_PSR_SBUS_ULTRA 0x0020 538 539#define RISC_PSR_DMA_INT 0x0010 540#define RISC_PSR_SXP_INT 0x0008 541#define RISC_PSR_HOST_INT 0x0004 542#define RISC_PSR_INT_PENDING 0x0002 543#define RISC_PSR_FORCE_FALSE 0x0001 544 545 546/* Host Command and Control */ 547#define HCCR_CMD_NOP 0x0000 /* NOP */ 548#define HCCR_CMD_RESET 0x1000 /* Reset RISC */ 549#define HCCR_CMD_PAUSE 0x2000 /* Pause RISC */ 550#define HCCR_CMD_RELEASE 0x3000 /* Release Paused RISC */ 551#define HCCR_CMD_STEP 0x4000 /* Single Step RISC */ 552#define HCCR_CMD_SET_HOST_INT 0x5000 /* Set Host Interrupt */ 553#define HCCR_CMD_CLEAR_HOST_INT 0x6000 /* Clear Host Interrupt */ 554#define HCCR_CMD_CLEAR_RISC_INT 0x7000 /* Clear RISC interrupt */ 555#define HCCR_CMD_BREAKPOINT 0x8000 /* Change breakpoint enables */ 556#define PCI_HCCR_CMD_BIOS 0x9000 /* Write BIOS (disable) */ 557#define PCI_HCCR_CMD_PARITY 0xA000 /* Write parity enable */ 558#define PCI_HCCR_CMD_PARITY_ERR 0xE000 /* Generate parity error */ 559#define HCCR_CMD_TEST_MODE 0xF000 /* Set Test Mode */ 560 561#define ISP2100_HCCR_PARITY_ENABLE_2 0x0400 562#define ISP2100_HCCR_PARITY_ENABLE_1 0x0200 563#define ISP2100_HCCR_PARITY_ENABLE_0 0x0100 564#define ISP2100_HCCR_PARITY 0x0001 565 566#define PCI_HCCR_PARITY 0x0400 /* Parity error flag */ 567#define PCI_HCCR_PARITY_ENABLE_1 0x0200 /* Parity enable bank 1 */ 568#define PCI_HCCR_PARITY_ENABLE_0 0x0100 /* Parity enable bank 0 */ 569 570#define HCCR_HOST_INT 0x0080 /* R : Host interrupt set */ 571#define HCCR_RESET 0x0040 /* R : reset in progress */ 572#define HCCR_PAUSE 0x0020 /* R : RISC paused */ 573 574#define PCI_HCCR_BIOS 0x0001 /* W : BIOS enable */ 575 576/* 577 * Qlogic 1XXX NVRAM is an array of 128 bytes. 578 * 579 * Some portion of the front of this is for general host adapter properties 580 * This is followed by an array of per-target parameters, and is tailed off 581 * with a checksum xor byte at offset 127. For non-byte entities data is 582 * stored in Little Endian order. 583 */ 584 585#define ISP_NVRAM_SIZE 128 586 587#define ISPBSMX(c, byte, shift, mask) \ 588 (((c)[(byte)] >> (shift)) & (mask)) 589 590#define ISP_NVRAM_VERSION(c) (c)[4] 591#define ISP_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 5, 0, 0x03) 592#define ISP_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 5, 2, 0x01) 593#define ISP_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 5, 3, 0x01) 594#define ISP_NVRAM_INITIATOR_ID(c) ISPBSMX(c, 5, 4, 0x0f) 595#define ISP_NVRAM_BUS_RESET_DELAY(c) (c)[6] 596#define ISP_NVRAM_BUS_RETRY_COUNT(c) (c)[7] 597#define ISP_NVRAM_BUS_RETRY_DELAY(c) (c)[8] 598#define ISP_NVRAM_ASYNC_DATA_SETUP_TIME(c) ISPBSMX(c, 9, 0, 0x0f) 599#define ISP_NVRAM_REQ_ACK_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 4, 0x01) 600#define ISP_NVRAM_DATA_LINE_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 5, 0x01) 601#define ISP_NVRAM_DATA_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 6, 0x01) 602#define ISP_NVRAM_CMD_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 7, 0x01) 603#define ISP_NVRAM_TAG_AGE_LIMIT(c) (c)[10] 604#define ISP_NVRAM_LOWTRM_ENABLE(c) ISPBSMX(c, 11, 0, 0x01) 605#define ISP_NVRAM_HITRM_ENABLE(c) ISPBSMX(c, 11, 1, 0x01) 606#define ISP_NVRAM_PCMC_BURST_ENABLE(c) ISPBSMX(c, 11, 2, 0x01) 607#define ISP_NVRAM_ENABLE_60_MHZ(c) ISPBSMX(c, 11, 3, 0x01) 608#define ISP_NVRAM_SCSI_RESET_DISABLE(c) ISPBSMX(c, 11, 4, 0x01) 609#define ISP_NVRAM_ENABLE_AUTO_TERM(c) ISPBSMX(c, 11, 5, 0x01) 610#define ISP_NVRAM_FIFO_THRESHOLD_128(c) ISPBSMX(c, 11, 6, 0x01) 611#define ISP_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 11, 7, 0x01) 612#define ISP_NVRAM_SELECTION_TIMEOUT(c) (((c)[12]) | ((c)[13] << 8)) 613#define ISP_NVRAM_MAX_QUEUE_DEPTH(c) (((c)[14]) | ((c)[15] << 8)) 614#define ISP_NVRAM_SCSI_BUS_SIZE(c) ISPBSMX(c, 16, 0, 0x01) 615#define ISP_NVRAM_SCSI_BUS_TYPE(c) ISPBSMX(c, 16, 1, 0x01) 616#define ISP_NVRAM_ADAPTER_CLK_SPEED(c) ISPBSMX(c, 16, 2, 0x01) 617#define ISP_NVRAM_SOFT_TERM_SUPPORT(c) ISPBSMX(c, 16, 3, 0x01) 618#define ISP_NVRAM_FLASH_ONBOARD(c) ISPBSMX(c, 16, 4, 0x01) 619#define ISP_NVRAM_FAST_MTTR_ENABLE(c) ISPBSMX(c, 22, 0, 0x01) 620 621#define ISP_NVRAM_TARGOFF 28 622#define ISP_NVARM_TARGSIZE 6 623#define _IxT(tgt, tidx) \ 624 (ISP_NVRAM_TARGOFF + (ISP_NVARM_TARGSIZE * (tgt)) + (tidx)) 625#define ISP_NVRAM_TGT_RENEG(c, t) ISPBSMX(c, _IxT(t, 0), 0, 0x01) 626#define ISP_NVRAM_TGT_QFRZ(c, t) ISPBSMX(c, _IxT(t, 0), 1, 0x01) 627#define ISP_NVRAM_TGT_ARQ(c, t) ISPBSMX(c, _IxT(t, 0), 2, 0x01) 628#define ISP_NVRAM_TGT_TQING(c, t) ISPBSMX(c, _IxT(t, 0), 3, 0x01) 629#define ISP_NVRAM_TGT_SYNC(c, t) ISPBSMX(c, _IxT(t, 0), 4, 0x01) 630#define ISP_NVRAM_TGT_WIDE(c, t) ISPBSMX(c, _IxT(t, 0), 5, 0x01) 631#define ISP_NVRAM_TGT_PARITY(c, t) ISPBSMX(c, _IxT(t, 0), 6, 0x01) 632#define ISP_NVRAM_TGT_DISC(c, t) ISPBSMX(c, _IxT(t, 0), 7, 0x01) 633#define ISP_NVRAM_TGT_EXEC_THROTTLE(c, t) ISPBSMX(c, _IxT(t, 1), 0, 0xff) 634#define ISP_NVRAM_TGT_SYNC_PERIOD(c, t) ISPBSMX(c, _IxT(t, 2), 0, 0xff) 635#define ISP_NVRAM_TGT_SYNC_OFFSET(c, t) ISPBSMX(c, _IxT(t, 3), 0, 0x0f) 636#define ISP_NVRAM_TGT_DEVICE_ENABLE(c, t) ISPBSMX(c, _IxT(t, 3), 4, 0x01) 637#define ISP_NVRAM_TGT_LUN_DISABLE(c, t) ISPBSMX(c, _IxT(t, 3), 5, 0x01) 638 639/* 640 * Qlogic 2XXX NVRAM is an array of 256 bytes. 641 * 642 * Some portion of the front of this is for general RISC engine parameters, 643 * mostly reflecting the state of the last INITIALIZE FIRMWARE mailbox command. 644 * 645 * This is followed by some general host adapter parameters, and ends with 646 * a checksum xor byte at offset 255. For non-byte entities data is stored 647 * in Little Endian order. 648 */ 649#define ISP2100_NVRAM_SIZE 256 650/* ISP_NVRAM_VERSION is in same overall place */ 651#define ISP2100_NVRAM_RISCVER(c) (c)[6] 652#define ISP2100_NVRAM_ENABLE_HARDLOOPID(c) ISPBSMX(c, 8, 0, 0x01) 653#define ISP2100_NVRAM_ENABLE_FAIRNESS(c) ISPBSMX(c, 8, 1, 0x01) 654#define ISP2100_NVRAM_ENABLE_FULLDUPLEX(c) ISPBSMX(c, 8, 2, 0x01) 655#define ISP2100_NVRAM_ENABLE_FAST_POSTING(c) ISPBSMX(c, 8, 3, 0x01) 656#define ISP2100_NVRAM_ENABLE_TARGET_MODE(c) ISPBSMX(c, 8, 4, 0x01) 657#define ISP2100_NVRAM_ENABLE_INITIATOR_MODE(c) ISPBSMX(c, 8, 5, 0x01) 658#define ISP2100_NVRAM_QFRZ(c) ISPBSMX(c, 8, 6, 0x01) 659#define ISP2100_NVRAM_MAXFRAMELENGTH(c) (((c)[10]) | ((c)[11] << 8)) 660#define ISP2100_NVRAM_MAXIOCBALLOCATION(c) (((c)[12]) | ((c)[13] << 8)) 661#define ISP2100_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8)) 662#define ISP2100_NVRAM_RETRY_COUNT(c) (c)[16] 663#define ISP2100_NVRAM_RETRY_DELAY(c) (c)[17] 664 665#define ISP2100_NVRAM_NODE_NAME(c) ( \ 666 (((u_int64_t)(c)[18]) << 56) | \ 667 (((u_int64_t)(c)[19]) << 48) | \ 668 (((u_int64_t)(c)[20]) << 40) | \ 669 (((u_int64_t)(c)[21]) << 32) | \ 670 (((u_int64_t)(c)[22]) << 24) | \ 671 (((u_int64_t)(c)[23]) << 16) | \ 672 (((u_int64_t)(c)[24]) << 8) | \ 673 (((u_int64_t)(c)[25]) << 0)) 674#define ISP2100_NVRAM_HARDLOOPID(c) (c)[26] 675 676#define ISP2100_NVRAM_HBA_DISABLE(c) ISPBSMX(c, 70, 0, 0x01) 677#define ISP2100_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 70, 1, 0x01) 678#define ISP2100_NVRAM_LUN_DISABLE(c) ISPBSMX(c, 70, 2, 0x01) 679#define ISP2100_NVRAM_ENABLE_SELECT_BOOT(c) ISPBSMX(c, 70, 3, 0x01) 680#define ISP2100_NVRAM_DISABLE_CODELOAD(c) ISPBSMX(c, 70, 4, 0x01) 681#define ISP2100_NVRAM_SET_CACHELINESZ(c) ISPBSMX(c, 70, 5, 0x01) 682 683#define ISP2100_NVRAM_BOOT_NODE_NAME(c) ( \ 684 (((u_int64_t)(c)[72]) << 56) | \ 685 (((u_int64_t)(c)[73]) << 48) | \ 686 (((u_int64_t)(c)[74]) << 40) | \ 687 (((u_int64_t)(c)[75]) << 32) | \ 688 (((u_int64_t)(c)[76]) << 24) | \ 689 (((u_int64_t)(c)[77]) << 16) | \ 690 (((u_int64_t)(c)[78]) << 8) | \ 691 (((u_int64_t)(c)[79]) << 0)) 692#define ISP2100_NVRAM_BOOT_LUN(c) (c)[80] 693 694#endif /* _ISPREG_H */ 695