ispreg.h revision 1.29
1/* $NetBSD: ispreg.h,v 1.29 2003/12/04 13:57:30 keihan Exp $ */ 2/* 3 * This driver, which is contained in NetBSD in the files: 4 * 5 * sys/dev/ic/isp.c 6 * sys/dev/ic/isp_inline.h 7 * sys/dev/ic/isp_netbsd.c 8 * sys/dev/ic/isp_netbsd.h 9 * sys/dev/ic/isp_target.c 10 * sys/dev/ic/isp_target.h 11 * sys/dev/ic/isp_tpublic.h 12 * sys/dev/ic/ispmbox.h 13 * sys/dev/ic/ispreg.h 14 * sys/dev/ic/ispvar.h 15 * sys/microcode/isp/asm_sbus.h 16 * sys/microcode/isp/asm_1040.h 17 * sys/microcode/isp/asm_1080.h 18 * sys/microcode/isp/asm_12160.h 19 * sys/microcode/isp/asm_2100.h 20 * sys/microcode/isp/asm_2200.h 21 * sys/pci/isp_pci.c 22 * sys/sbus/isp_sbus.c 23 * 24 * Is being actively maintained by Matthew Jacob (mjacob@NetBSD.org). 25 * This driver also is shared source with FreeBSD, OpenBSD, Linux, Solaris, 26 * Linux versions. This tends to be an interesting maintenance problem. 27 * 28 * Please coordinate with Matthew Jacob on changes you wish to make here. 29 */ 30/* release_6_5_99 */ 31/* 32 * Copyright (C) 1997, 1998, 1999 National Aeronautics & Space Administration 33 * All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. The name of the author may not be used to endorse or promote products 44 * derived from this software without specific prior written permission 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 48 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 49 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 50 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 51 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 52 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 53 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 54 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 55 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 56 */ 57/* 58 * Machine Independent (well, as best as possible) register 59 * definitions for Qlogic ISP SCSI adapters. 60 * 61 * Matthew Jacob <mjacob@nas.nasa.gov> 62 * 63 */ 64#ifndef _ISPREG_H 65#define _ISPREG_H 66 67/* 68 * Hardware definitions for the Qlogic ISP registers. 69 */ 70 71/* 72 * This defines types of access to various registers. 73 * 74 * R: Read Only 75 * W: Write Only 76 * RW: Read/Write 77 * 78 * R*, W*, RW*: Read Only, Write Only, Read/Write, but only 79 * if RISC processor in ISP is paused. 80 */ 81 82/* 83 * Offsets for various register blocks. 84 * 85 * Sad but true, different architectures have different offsets. 86 * 87 * Don't be alarmed if none of this makes sense. The original register 88 * layout set some defines in a certain pattern. Everything else has been 89 * grafted on since. For example, the ISP1080 manual will state that DMA 90 * registers start at 0x80 from the base of the register address space. 91 * That's true, but for our purposes, we define DMA_REGS_OFF for the 1080 92 * to start at offset 0x60 because the DMA registers are all defined to 93 * be DMA_BLOCK+0x20 and so on. Clear? 94 */ 95 96#define BIU_REGS_OFF 0x00 97 98#define PCI_MBOX_REGS_OFF 0x70 99#define PCI_MBOX_REGS2100_OFF 0x10 100#define PCI_MBOX_REGS2300_OFF 0x40 101#define SBUS_MBOX_REGS_OFF 0x80 102 103#define PCI_SXP_REGS_OFF 0x80 104#define SBUS_SXP_REGS_OFF 0x200 105 106#define PCI_RISC_REGS_OFF 0x80 107#define SBUS_RISC_REGS_OFF 0x400 108 109/* Bless me! Chip designers have putzed it again! */ 110#define ISP1080_DMA_REGS_OFF 0x60 111#define DMA_REGS_OFF 0x00 /* same as BIU block */ 112 113#define SBUS_REGSIZE 0x450 114#define PCI_REGSIZE 0x100 115 116/* 117 * NB: The *_BLOCK definitions have no specific hardware meaning. 118 * They serve simply to note to the MD layer which block of 119 * registers offsets are being accessed. 120 */ 121#define _NREG_BLKS 5 122#define _BLK_REG_SHFT 13 123#define _BLK_REG_MASK (7 << _BLK_REG_SHFT) 124#define BIU_BLOCK (0 << _BLK_REG_SHFT) 125#define MBOX_BLOCK (1 << _BLK_REG_SHFT) 126#define SXP_BLOCK (2 << _BLK_REG_SHFT) 127#define RISC_BLOCK (3 << _BLK_REG_SHFT) 128#define DMA_BLOCK (4 << _BLK_REG_SHFT) 129 130/* 131 * Bus Interface Block Register Offsets 132 */ 133 134#define BIU_ID_LO (BIU_BLOCK+0x0) /* R : Bus ID, Low */ 135#define BIU2100_FLASH_ADDR (BIU_BLOCK+0x0) 136#define BIU_ID_HI (BIU_BLOCK+0x2) /* R : Bus ID, High */ 137#define BIU2100_FLASH_DATA (BIU_BLOCK+0x2) 138#define BIU_CONF0 (BIU_BLOCK+0x4) /* R : Bus Configuration #0 */ 139#define BIU_CONF1 (BIU_BLOCK+0x6) /* R : Bus Configuration #1 */ 140#define BIU2100_CSR (BIU_BLOCK+0x6) 141#define BIU_ICR (BIU_BLOCK+0x8) /* RW : Bus Interface Ctrl */ 142#define BIU_ISR (BIU_BLOCK+0xA) /* R : Bus Interface Status */ 143#define BIU_SEMA (BIU_BLOCK+0xC) /* RW : Bus Semaphore */ 144#define BIU_NVRAM (BIU_BLOCK+0xE) /* RW : Bus NVRAM */ 145/* 146 * These are specific to the 2300. 147 * 148 * They *claim* you can read BIU_R2HSTSLO with a full 32 bit access 149 * and get both registers, but I'm a bit dubious about that. But the 150 * point here is that the top 16 bits are firmware defined bits that 151 * the RISC processor uses to inform the host about something- usually 152 * something which was nominally in a mailbox register. 153 */ 154#define BIU_REQINP (BIU_BLOCK+0x10) /* Request Queue In */ 155#define BIU_REQOUTP (BIU_BLOCK+0x12) /* Request Queue Out */ 156#define BIU_RSPINP (BIU_BLOCK+0x14) /* Response Queue In */ 157#define BIU_RSPOUTP (BIU_BLOCK+0x16) /* Response Queue Out */ 158 159#define BIU_R2HSTSLO (BIU_BLOCK+0x18) 160#define BIU_R2HSTSHI (BIU_BLOCK+0x1A) 161 162#define BIU_R2HST_INTR (1 << 15) /* RISC to Host Interrupt */ 163#define BIU_R2HST_PAUSED (1 << 8) /* RISC paused */ 164#define BIU_R2HST_ISTAT_MASK 0x3f /* intr information && status */ 165#define ISPR2HST_ROM_MBX_OK 0x1 /* ROM mailbox cmd done ok */ 166#define ISPR2HST_ROM_MBX_FAIL 0x2 /* ROM mailbox cmd done fail */ 167#define ISPR2HST_MBX_OK 0x10 /* mailbox cmd done ok */ 168#define ISPR2HST_MBX_FAIL 0x11 /* mailbox cmd done fail */ 169#define ISPR2HST_ASYNC_EVENT 0x12 /* Async Event */ 170#define ISPR2HST_RSPQ_UPDATE 0x13 /* Response Queue Update */ 171#define ISPR2HST_RQST_UPDATE 0x14 /* Resquest Queue Update */ 172#define ISPR2HST_RIO_16 0x15 /* RIO 1-16 */ 173#define ISPR2HST_FPOST 0x16 /* Low 16 bits fast post */ 174#define ISPR2HST_FPOST_CTIO 0x17 /* Low 16 bits fast post ctio */ 175 176#define DFIFO_COMMAND (BIU_BLOCK+0x60) /* RW : Command FIFO Port */ 177#define RDMA2100_CONTROL DFIFO_COMMAND 178#define DFIFO_DATA (BIU_BLOCK+0x62) /* RW : Data FIFO Port */ 179 180/* 181 * Putzed DMA register layouts. 182 */ 183#define CDMA_CONF (DMA_BLOCK+0x20) /* RW*: DMA Configuration */ 184#define CDMA2100_CONTROL CDMA_CONF 185#define CDMA_CONTROL (DMA_BLOCK+0x22) /* RW*: DMA Control */ 186#define CDMA_STATUS (DMA_BLOCK+0x24) /* R : DMA Status */ 187#define CDMA_FIFO_STS (DMA_BLOCK+0x26) /* R : DMA FIFO Status */ 188#define CDMA_COUNT (DMA_BLOCK+0x28) /* RW*: DMA Transfer Count */ 189#define CDMA_ADDR0 (DMA_BLOCK+0x2C) /* RW*: DMA Address, Word 0 */ 190#define CDMA_ADDR1 (DMA_BLOCK+0x2E) /* RW*: DMA Address, Word 1 */ 191#define CDMA_ADDR2 (DMA_BLOCK+0x30) /* RW*: DMA Address, Word 2 */ 192#define CDMA_ADDR3 (DMA_BLOCK+0x32) /* RW*: DMA Address, Word 3 */ 193 194#define DDMA_CONF (DMA_BLOCK+0x40) /* RW*: DMA Configuration */ 195#define TDMA2100_CONTROL DDMA_CONF 196#define DDMA_CONTROL (DMA_BLOCK+0x42) /* RW*: DMA Control */ 197#define DDMA_STATUS (DMA_BLOCK+0x44) /* R : DMA Status */ 198#define DDMA_FIFO_STS (DMA_BLOCK+0x46) /* R : DMA FIFO Status */ 199#define DDMA_COUNT_LO (DMA_BLOCK+0x48) /* RW*: DMA Xfer Count, Low */ 200#define DDMA_COUNT_HI (DMA_BLOCK+0x4A) /* RW*: DMA Xfer Count, High */ 201#define DDMA_ADDR0 (DMA_BLOCK+0x4C) /* RW*: DMA Address, Word 0 */ 202#define DDMA_ADDR1 (DMA_BLOCK+0x4E) /* RW*: DMA Address, Word 1 */ 203/* these are for the 1040A cards */ 204#define DDMA_ADDR2 (DMA_BLOCK+0x50) /* RW*: DMA Address, Word 2 */ 205#define DDMA_ADDR3 (DMA_BLOCK+0x52) /* RW*: DMA Address, Word 3 */ 206 207 208/* 209 * Bus Interface Block Register Definitions 210 */ 211/* BUS CONFIGURATION REGISTER #0 */ 212#define BIU_CONF0_HW_MASK 0x000F /* Hardware revision mask */ 213/* BUS CONFIGURATION REGISTER #1 */ 214 215#define BIU_SBUS_CONF1_PARITY 0x0100 /* Enable parity checking */ 216#define BIU_SBUS_CONF1_FCODE_MASK 0x00F0 /* Fcode cycle mask */ 217 218#define BIU_PCI_CONF1_FIFO_128 0x0040 /* 128 bytes FIFO threshold */ 219#define BIU_PCI_CONF1_FIFO_64 0x0030 /* 64 bytes FIFO threshold */ 220#define BIU_PCI_CONF1_FIFO_32 0x0020 /* 32 bytes FIFO threshold */ 221#define BIU_PCI_CONF1_FIFO_16 0x0010 /* 16 bytes FIFO threshold */ 222#define BIU_BURST_ENABLE 0x0004 /* Global enable Bus bursts */ 223#define BIU_SBUS_CONF1_FIFO_64 0x0003 /* 64 bytes FIFO threshold */ 224#define BIU_SBUS_CONF1_FIFO_32 0x0002 /* 32 bytes FIFO threshold */ 225#define BIU_SBUS_CONF1_FIFO_16 0x0001 /* 16 bytes FIFO threshold */ 226#define BIU_SBUS_CONF1_FIFO_8 0x0000 /* 8 bytes FIFO threshold */ 227#define BIU_SBUS_CONF1_BURST8 0x0008 /* Enable 8-byte bursts */ 228#define BIU_PCI_CONF1_SXP 0x0008 /* SXP register select */ 229 230#define BIU_PCI1080_CONF1_SXP0 0x0100 /* SXP bank #1 select */ 231#define BIU_PCI1080_CONF1_SXP1 0x0200 /* SXP bank #2 select */ 232#define BIU_PCI1080_CONF1_DMA 0x0300 /* DMA bank select */ 233 234/* ISP2100 Bus Control/Status Register */ 235 236#define BIU2100_ICSR_REGBSEL 0x30 /* RW: register bank select */ 237#define BIU2100_RISC_REGS (0 << 4) /* RISC Regs */ 238#define BIU2100_FB_REGS (1 << 4) /* FrameBuffer Regs */ 239#define BIU2100_FPM0_REGS (2 << 4) /* FPM 0 Regs */ 240#define BIU2100_FPM1_REGS (3 << 4) /* FPM 1 Regs */ 241#define BIU2100_PCI64 0x04 /* R: 64 Bit PCI slot */ 242#define BIU2100_FLASH_ENABLE 0x02 /* RW: Enable Flash RAM */ 243#define BIU2100_SOFT_RESET 0x01 244/* SOFT RESET FOR ISP2100 is same bit, but in this register, not ICR */ 245 246 247/* BUS CONTROL REGISTER */ 248#define BIU_ICR_ENABLE_DMA_INT 0x0020 /* Enable DMA interrupts */ 249#define BIU_ICR_ENABLE_CDMA_INT 0x0010 /* Enable CDMA interrupts */ 250#define BIU_ICR_ENABLE_SXP_INT 0x0008 /* Enable SXP interrupts */ 251#define BIU_ICR_ENABLE_RISC_INT 0x0004 /* Enable Risc interrupts */ 252#define BIU_ICR_ENABLE_ALL_INTS 0x0002 /* Global enable all inter */ 253#define BIU_ICR_SOFT_RESET 0x0001 /* Soft Reset of ISP */ 254 255#define BIU2100_ICR_ENABLE_ALL_INTS 0x8000 256#define BIU2100_ICR_ENA_FPM_INT 0x0020 257#define BIU2100_ICR_ENA_FB_INT 0x0010 258#define BIU2100_ICR_ENA_RISC_INT 0x0008 259#define BIU2100_ICR_ENA_CDMA_INT 0x0004 260#define BIU2100_ICR_ENABLE_RXDMA_INT 0x0002 261#define BIU2100_ICR_ENABLE_TXDMA_INT 0x0001 262#define BIU2100_ICR_DISABLE_ALL_INTS 0x0000 263 264#define ENABLE_INTS(isp) (IS_SCSI(isp))? \ 265 ISP_WRITE(isp, BIU_ICR, BIU_ICR_ENABLE_RISC_INT | BIU_ICR_ENABLE_ALL_INTS) : \ 266 ISP_WRITE(isp, BIU_ICR, BIU2100_ICR_ENA_RISC_INT | BIU2100_ICR_ENABLE_ALL_INTS) 267 268#define INTS_ENABLED(isp) ((IS_SCSI(isp))? \ 269 (ISP_READ(isp, BIU_ICR) & (BIU_ICR_ENABLE_RISC_INT|BIU_ICR_ENABLE_ALL_INTS)) :\ 270 (ISP_READ(isp, BIU_ICR) & \ 271 (BIU2100_ICR_ENA_RISC_INT|BIU2100_ICR_ENABLE_ALL_INTS))) 272 273#define DISABLE_INTS(isp) ISP_WRITE(isp, BIU_ICR, 0) 274 275/* BUS STATUS REGISTER */ 276#define BIU_ISR_DMA_INT 0x0020 /* DMA interrupt pending */ 277#define BIU_ISR_CDMA_INT 0x0010 /* CDMA interrupt pending */ 278#define BIU_ISR_SXP_INT 0x0008 /* SXP interrupt pending */ 279#define BIU_ISR_RISC_INT 0x0004 /* Risc interrupt pending */ 280#define BIU_ISR_IPEND 0x0002 /* Global interrupt pending */ 281 282#define BIU2100_ISR_INT_PENDING 0x8000 /* Global interrupt pending */ 283#define BIU2100_ISR_FPM_INT 0x0020 /* FPM interrupt pending */ 284#define BIU2100_ISR_FB_INT 0x0010 /* FB interrupt pending */ 285#define BIU2100_ISR_RISC_INT 0x0008 /* Risc interrupt pending */ 286#define BIU2100_ISR_CDMA_INT 0x0004 /* CDMA interrupt pending */ 287#define BIU2100_ISR_RXDMA_INT_PENDING 0x0002 /* Global interrupt pending */ 288#define BIU2100_ISR_TXDMA_INT_PENDING 0x0001 /* Global interrupt pending */ 289 290#define INT_PENDING(isp, isr) (IS_FC(isp)? \ 291 ((isr & BIU2100_ISR_RISC_INT) != 0) : ((isr & BIU_ISR_RISC_INT) != 0)) 292 293#define INT_PENDING_MASK(isp) \ 294 (IS_FC(isp)? BIU2100_ISR_RISC_INT: BIU_ISR_RISC_INT) 295 296/* BUS SEMAPHORE REGISTER */ 297#define BIU_SEMA_STATUS 0x0002 /* Semaphore Status Bit */ 298#define BIU_SEMA_LOCK 0x0001 /* Semaphore Lock Bit */ 299 300/* NVRAM SEMAPHORE REGISTER */ 301#define BIU_NVRAM_CLOCK 0x0001 302#define BIU_NVRAM_SELECT 0x0002 303#define BIU_NVRAM_DATAOUT 0x0004 304#define BIU_NVRAM_DATAIN 0x0008 305#define ISP_NVRAM_READ 6 306 307/* COMNMAND && DATA DMA CONFIGURATION REGISTER */ 308#define DMA_ENABLE_SXP_DMA 0x0008 /* Enable SXP to DMA Data */ 309#define DMA_ENABLE_INTS 0x0004 /* Enable interrupts to RISC */ 310#define DMA_ENABLE_BURST 0x0002 /* Enable Bus burst trans */ 311#define DMA_DMA_DIRECTION 0x0001 /* 312 * Set DMA direction: 313 * 0 - DMA FIFO to host 314 * 1 - Host to DMA FIFO 315 */ 316 317/* COMMAND && DATA DMA CONTROL REGISTER */ 318#define DMA_CNTRL_SUSPEND_CHAN 0x0010 /* Suspend DMA transfer */ 319#define DMA_CNTRL_CLEAR_CHAN 0x0008 /* 320 * Clear FIFO and DMA Channel, 321 * reset DMA registers 322 */ 323#define DMA_CNTRL_CLEAR_FIFO 0x0004 /* Clear DMA FIFO */ 324#define DMA_CNTRL_RESET_INT 0x0002 /* Clear DMA interrupt */ 325#define DMA_CNTRL_STROBE 0x0001 /* Start DMA transfer */ 326 327/* 328 * Variants of same for 2100 329 */ 330#define DMA_CNTRL2100_CLEAR_CHAN 0x0004 331#define DMA_CNTRL2100_RESET_INT 0x0002 332 333 334 335/* DMA STATUS REGISTER */ 336#define DMA_SBUS_STATUS_PIPE_MASK 0x00C0 /* DMA Pipeline status mask */ 337#define DMA_SBUS_STATUS_CHAN_MASK 0x0030 /* Channel status mask */ 338#define DMA_SBUS_STATUS_BUS_PARITY 0x0008 /* Parity Error on bus */ 339#define DMA_SBUS_STATUS_BUS_ERR 0x0004 /* Error Detected on bus */ 340#define DMA_SBUS_STATUS_TERM_COUNT 0x0002 /* DMA Transfer Completed */ 341#define DMA_SBUS_STATUS_INTERRUPT 0x0001 /* Enable DMA channel inter */ 342 343#define DMA_PCI_STATUS_INTERRUPT 0x8000 /* Enable DMA channel inter */ 344#define DMA_PCI_STATUS_RETRY_STAT 0x4000 /* Retry status */ 345#define DMA_PCI_STATUS_CHAN_MASK 0x3000 /* Channel status mask */ 346#define DMA_PCI_STATUS_FIFO_OVR 0x0100 /* DMA FIFO overrun cond */ 347#define DMA_PCI_STATUS_FIFO_UDR 0x0080 /* DMA FIFO underrun cond */ 348#define DMA_PCI_STATUS_BUS_ERR 0x0040 /* Error Detected on bus */ 349#define DMA_PCI_STATUS_BUS_PARITY 0x0020 /* Parity Error on bus */ 350#define DMA_PCI_STATUS_CLR_PEND 0x0010 /* DMA clear pending */ 351#define DMA_PCI_STATUS_TERM_COUNT 0x0008 /* DMA Transfer Completed */ 352#define DMA_PCI_STATUS_DMA_SUSP 0x0004 /* DMA suspended */ 353#define DMA_PCI_STATUS_PIPE_MASK 0x0003 /* DMA Pipeline status mask */ 354 355/* DMA Status Register, pipeline status bits */ 356#define DMA_SBUS_PIPE_FULL 0x00C0 /* Both pipeline stages full */ 357#define DMA_SBUS_PIPE_OVERRUN 0x0080 /* Pipeline overrun */ 358#define DMA_SBUS_PIPE_STAGE1 0x0040 /* 359 * Pipeline stage 1 Loaded, 360 * stage 2 empty 361 */ 362#define DMA_PCI_PIPE_FULL 0x0003 /* Both pipeline stages full */ 363#define DMA_PCI_PIPE_OVERRUN 0x0002 /* Pipeline overrun */ 364#define DMA_PCI_PIPE_STAGE1 0x0001 /* 365 * Pipeline stage 1 Loaded, 366 * stage 2 empty 367 */ 368#define DMA_PIPE_EMPTY 0x0000 /* All pipeline stages empty */ 369 370/* DMA Status Register, channel status bits */ 371#define DMA_SBUS_CHAN_SUSPEND 0x0030 /* Channel error or suspended */ 372#define DMA_SBUS_CHAN_TRANSFER 0x0020 /* Chan transfer in progress */ 373#define DMA_SBUS_CHAN_ACTIVE 0x0010 /* Chan trans to host active */ 374#define DMA_PCI_CHAN_TRANSFER 0x3000 /* Chan transfer in progress */ 375#define DMA_PCI_CHAN_SUSPEND 0x2000 /* Channel error or suspended */ 376#define DMA_PCI_CHAN_ACTIVE 0x1000 /* Chan trans to host active */ 377#define ISP_DMA_CHAN_IDLE 0x0000 /* Chan idle (normal comp) */ 378 379 380/* DMA FIFO STATUS REGISTER */ 381#define DMA_FIFO_STATUS_OVERRUN 0x0200 /* FIFO Overrun Condition */ 382#define DMA_FIFO_STATUS_UNDERRUN 0x0100 /* FIFO Underrun Condition */ 383#define DMA_FIFO_SBUS_COUNT_MASK 0x007F /* FIFO Byte count mask */ 384#define DMA_FIFO_PCI_COUNT_MASK 0x00FF /* FIFO Byte count mask */ 385 386/* 387 * Mailbox Block Register Offsets 388 */ 389 390#define INMAILBOX0 (MBOX_BLOCK+0x0) 391#define INMAILBOX1 (MBOX_BLOCK+0x2) 392#define INMAILBOX2 (MBOX_BLOCK+0x4) 393#define INMAILBOX3 (MBOX_BLOCK+0x6) 394#define INMAILBOX4 (MBOX_BLOCK+0x8) 395#define INMAILBOX5 (MBOX_BLOCK+0xA) 396#define INMAILBOX6 (MBOX_BLOCK+0xC) 397#define INMAILBOX7 (MBOX_BLOCK+0xE) 398 399#define OUTMAILBOX0 (MBOX_BLOCK+0x0) 400#define OUTMAILBOX1 (MBOX_BLOCK+0x2) 401#define OUTMAILBOX2 (MBOX_BLOCK+0x4) 402#define OUTMAILBOX3 (MBOX_BLOCK+0x6) 403#define OUTMAILBOX4 (MBOX_BLOCK+0x8) 404#define OUTMAILBOX5 (MBOX_BLOCK+0xA) 405#define OUTMAILBOX6 (MBOX_BLOCK+0xC) 406#define OUTMAILBOX7 (MBOX_BLOCK+0xE) 407 408#define MBOX_OFF(n) (MBOX_BLOCK + ((n) << 1)) 409#define NMBOX(isp) \ 410 (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \ 411 ((isp)->isp_type & ISP_HA_FC))? 8 : 6) 412#define NMBOX_BMASK(isp) \ 413 (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \ 414 ((isp)->isp_type & ISP_HA_FC))? 0xff : 0x3f) 415 416#define MAX_MAILBOX 8 417 418/* 419 * Fibre Protocol Module and Frame Buffer Register Offsets/Definitions (2X00). 420 * NB: The RISC processor must be paused and the appropriate register 421 * bank selected via BIU2100_CSR bits. 422 */ 423 424#define FPM_DIAG_CONFIG (BIU_BLOCK + 0x96) 425#define FPM_SOFT_RESET 0x0100 426 427#define FBM_CMD (BIU_BLOCK + 0xB8) 428#define FBMCMD_FIFO_RESET_ALL 0xA000 429 430 431/* 432 * SXP Block Register Offsets 433 */ 434#define SXP_PART_ID (SXP_BLOCK+0x0) /* R : Part ID Code */ 435#define SXP_CONFIG1 (SXP_BLOCK+0x2) /* RW*: Configuration Reg #1 */ 436#define SXP_CONFIG2 (SXP_BLOCK+0x4) /* RW*: Configuration Reg #2 */ 437#define SXP_CONFIG3 (SXP_BLOCK+0x6) /* RW*: Configuration Reg #2 */ 438#define SXP_INSTRUCTION (SXP_BLOCK+0xC) /* RW*: Instruction Pointer */ 439#define SXP_RETURN_ADDR (SXP_BLOCK+0x10) /* RW*: Return Address */ 440#define SXP_COMMAND (SXP_BLOCK+0x14) /* RW*: Command */ 441#define SXP_INTERRUPT (SXP_BLOCK+0x18) /* R : Interrupt */ 442#define SXP_SEQUENCE (SXP_BLOCK+0x1C) /* RW*: Sequence */ 443#define SXP_GROSS_ERR (SXP_BLOCK+0x1E) /* R : Gross Error */ 444#define SXP_EXCEPTION (SXP_BLOCK+0x20) /* RW*: Exception Enable */ 445#define SXP_OVERRIDE (SXP_BLOCK+0x24) /* RW*: Override */ 446#define SXP_LIT_BASE (SXP_BLOCK+0x28) /* RW*: Literal Base */ 447#define SXP_USER_FLAGS (SXP_BLOCK+0x2C) /* RW*: User Flags */ 448#define SXP_USER_EXCEPT (SXP_BLOCK+0x30) /* RW*: User Exception */ 449#define SXP_BREAKPOINT (SXP_BLOCK+0x34) /* RW*: Breakpoint */ 450#define SXP_SCSI_ID (SXP_BLOCK+0x40) /* RW*: SCSI ID */ 451#define SXP_DEV_CONFIG1 (SXP_BLOCK+0x42) /* RW*: Device Config Reg #1 */ 452#define SXP_DEV_CONFIG2 (SXP_BLOCK+0x44) /* RW*: Device Config Reg #2 */ 453#define SXP_PHASE_PTR (SXP_BLOCK+0x48) /* RW*: SCSI Phase Pointer */ 454#define SXP_BUF_PTR (SXP_BLOCK+0x4C) /* RW*: SCSI Buffer Pointer */ 455#define SXP_BUF_CTR (SXP_BLOCK+0x50) /* RW*: SCSI Buffer Counter */ 456#define SXP_BUFFER (SXP_BLOCK+0x52) /* RW*: SCSI Buffer */ 457#define SXP_BUF_BYTE (SXP_BLOCK+0x54) /* RW*: SCSI Buffer Byte */ 458#define SXP_BUF_WD (SXP_BLOCK+0x56) /* RW*: SCSI Buffer Word */ 459#define SXP_BUF_WD_TRAN (SXP_BLOCK+0x58) /* RW*: SCSI Buffer Wd xlate */ 460#define SXP_FIFO (SXP_BLOCK+0x5A) /* RW*: SCSI FIFO */ 461#define SXP_FIFO_STATUS (SXP_BLOCK+0x5C) /* RW*: SCSI FIFO Status */ 462#define SXP_FIFO_TOP (SXP_BLOCK+0x5E) /* RW*: SCSI FIFO Top Resid */ 463#define SXP_FIFO_BOTTOM (SXP_BLOCK+0x60) /* RW*: SCSI FIFO Bot Resid */ 464#define SXP_TRAN_REG (SXP_BLOCK+0x64) /* RW*: SCSI Transfer Reg */ 465#define SXP_TRAN_CNT_LO (SXP_BLOCK+0x68) /* RW*: SCSI Trans Count */ 466#define SXP_TRAN_CNT_HI (SXP_BLOCK+0x6A) /* RW*: SCSI Trans Count */ 467#define SXP_TRAN_CTR_LO (SXP_BLOCK+0x6C) /* RW*: SCSI Trans Counter */ 468#define SXP_TRAN_CTR_HI (SXP_BLOCK+0x6E) /* RW*: SCSI Trans Counter */ 469#define SXP_ARB_DATA (SXP_BLOCK+0x70) /* R : SCSI Arb Data */ 470#define SXP_PINS_CTRL (SXP_BLOCK+0x72) /* RW*: SCSI Control Pins */ 471#define SXP_PINS_DATA (SXP_BLOCK+0x74) /* RW*: SCSI Data Pins */ 472#define SXP_PINS_DIFF (SXP_BLOCK+0x76) /* RW*: SCSI Diff Pins */ 473 474/* for 1080/1280/1240 only */ 475#define SXP_BANK1_SELECT 0x100 476 477 478/* SXP CONF1 REGISTER */ 479#define SXP_CONF1_ASYNCH_SETUP 0xF000 /* Asynchronous setup time */ 480#define SXP_CONF1_SELECTION_UNIT 0x0000 /* Selection time unit */ 481#define SXP_CONF1_SELECTION_TIMEOUT 0x0600 /* Selection timeout */ 482#define SXP_CONF1_CLOCK_FACTOR 0x00E0 /* Clock factor */ 483#define SXP_CONF1_SCSI_ID 0x000F /* SCSI id */ 484 485/* SXP CONF2 REGISTER */ 486#define SXP_CONF2_DISABLE_FILTER 0x0040 /* Disable SCSI rec filters */ 487#define SXP_CONF2_REQ_ACK_PULLUPS 0x0020 /* Enable req/ack pullups */ 488#define SXP_CONF2_DATA_PULLUPS 0x0010 /* Enable data pullups */ 489#define SXP_CONF2_CONFIG_AUTOLOAD 0x0008 /* Enable dev conf auto-load */ 490#define SXP_CONF2_RESELECT 0x0002 /* Enable reselection */ 491#define SXP_CONF2_SELECT 0x0001 /* Enable selection */ 492 493/* SXP INTERRUPT REGISTER */ 494#define SXP_INT_PARITY_ERR 0x8000 /* Parity error detected */ 495#define SXP_INT_GROSS_ERR 0x4000 /* Gross error detected */ 496#define SXP_INT_FUNCTION_ABORT 0x2000 /* Last cmd aborted */ 497#define SXP_INT_CONDITION_FAILED 0x1000 /* Last cond failed test */ 498#define SXP_INT_FIFO_EMPTY 0x0800 /* SCSI FIFO is empty */ 499#define SXP_INT_BUF_COUNTER_ZERO 0x0400 /* SCSI buf count == zero */ 500#define SXP_INT_XFER_ZERO 0x0200 /* SCSI trans count == zero */ 501#define SXP_INT_INT_PENDING 0x0080 /* SXP interrupt pending */ 502#define SXP_INT_CMD_RUNNING 0x0040 /* SXP is running a command */ 503#define SXP_INT_INT_RETURN_CODE 0x000F /* Interrupt return code */ 504 505 506/* SXP GROSS ERROR REGISTER */ 507#define SXP_GROSS_OFFSET_RESID 0x0040 /* Req/Ack offset not zero */ 508#define SXP_GROSS_OFFSET_UNDERFLOW 0x0020 /* Req/Ack offset underflow */ 509#define SXP_GROSS_OFFSET_OVERFLOW 0x0010 /* Req/Ack offset overflow */ 510#define SXP_GROSS_FIFO_UNDERFLOW 0x0008 /* SCSI FIFO underflow */ 511#define SXP_GROSS_FIFO_OVERFLOW 0x0004 /* SCSI FIFO overflow */ 512#define SXP_GROSS_WRITE_ERR 0x0002 /* SXP and RISC wrote to reg */ 513#define SXP_GROSS_ILLEGAL_INST 0x0001 /* Bad inst loaded into SXP */ 514 515/* SXP EXCEPTION REGISTER */ 516#define SXP_EXCEPT_USER_0 0x8000 /* Enable user exception #0 */ 517#define SXP_EXCEPT_USER_1 0x4000 /* Enable user exception #1 */ 518#define PCI_SXP_EXCEPT_SCAM 0x0400 /* SCAM Selection enable */ 519#define SXP_EXCEPT_BUS_FREE 0x0200 /* Enable Bus Free det */ 520#define SXP_EXCEPT_TARGET_ATN 0x0100 /* Enable TGT mode atten det */ 521#define SXP_EXCEPT_RESELECTED 0x0080 /* Enable ReSEL exc handling */ 522#define SXP_EXCEPT_SELECTED 0x0040 /* Enable SEL exc handling */ 523#define SXP_EXCEPT_ARBITRATION 0x0020 /* Enable ARB exc handling */ 524#define SXP_EXCEPT_GROSS_ERR 0x0010 /* Enable gross error except */ 525#define SXP_EXCEPT_BUS_RESET 0x0008 /* Enable Bus Reset except */ 526 527 /* SXP OVERRIDE REGISTER */ 528#define SXP_ORIDE_EXT_TRIGGER 0x8000 /* Enable external trigger */ 529#define SXP_ORIDE_STEP 0x4000 /* Enable single step mode */ 530#define SXP_ORIDE_BREAKPOINT 0x2000 /* Enable breakpoint reg */ 531#define SXP_ORIDE_PIN_WRITE 0x1000 /* Enable write to SCSI pins */ 532#define SXP_ORIDE_FORCE_OUTPUTS 0x0800 /* Force SCSI outputs on */ 533#define SXP_ORIDE_LOOPBACK 0x0400 /* Enable SCSI loopback mode */ 534#define SXP_ORIDE_PARITY_TEST 0x0200 /* Enable parity test mode */ 535#define SXP_ORIDE_TRISTATE_ENA_PINS 0x0100 /* Tristate SCSI enable pins */ 536#define SXP_ORIDE_TRISTATE_PINS 0x0080 /* Tristate SCSI pins */ 537#define SXP_ORIDE_FIFO_RESET 0x0008 /* Reset SCSI FIFO */ 538#define SXP_ORIDE_CMD_TERMINATE 0x0004 /* Terminate cur SXP com */ 539#define SXP_ORIDE_RESET_REG 0x0002 /* Reset SXP registers */ 540#define SXP_ORIDE_RESET_MODULE 0x0001 /* Reset SXP module */ 541 542/* SXP COMMANDS */ 543#define SXP_RESET_BUS_CMD 0x300b 544 545/* SXP SCSI ID REGISTER */ 546#define SXP_SELECTING_ID 0x0F00 /* (Re)Selecting id */ 547#define SXP_SELECT_ID 0x000F /* Select id */ 548 549/* SXP DEV CONFIG1 REGISTER */ 550#define SXP_DCONF1_SYNC_HOLD 0x7000 /* Synchronous data hold */ 551#define SXP_DCONF1_SYNC_SETUP 0x0F00 /* Synchronous data setup */ 552#define SXP_DCONF1_SYNC_OFFSET 0x000F /* Synchronous data offset */ 553 554 555/* SXP DEV CONFIG2 REGISTER */ 556#define SXP_DCONF2_FLAGS_MASK 0xF000 /* Device flags */ 557#define SXP_DCONF2_WIDE 0x0400 /* Enable wide SCSI */ 558#define SXP_DCONF2_PARITY 0x0200 /* Enable parity checking */ 559#define SXP_DCONF2_BLOCK_MODE 0x0100 /* Enable blk mode xfr count */ 560#define SXP_DCONF2_ASSERTION_MASK 0x0007 /* Assersion period mask */ 561 562 563/* SXP PHASE POINTER REGISTER */ 564#define SXP_PHASE_STATUS_PTR 0x1000 /* Status buffer offset */ 565#define SXP_PHASE_MSG_IN_PTR 0x0700 /* Msg in buffer offset */ 566#define SXP_PHASE_COM_PTR 0x00F0 /* Command buffer offset */ 567#define SXP_PHASE_MSG_OUT_PTR 0x0007 /* Msg out buffer offset */ 568 569 570/* SXP FIFO STATUS REGISTER */ 571#define SXP_FIFO_TOP_RESID 0x8000 /* Top residue reg full */ 572#define SXP_FIFO_ACK_RESID 0x4000 /* Wide transfers odd resid */ 573#define SXP_FIFO_COUNT_MASK 0x001C /* Words in SXP FIFO */ 574#define SXP_FIFO_BOTTOM_RESID 0x0001 /* Bottom residue reg full */ 575 576 577/* SXP CONTROL PINS REGISTER */ 578#define SXP_PINS_CON_PHASE 0x8000 /* Scsi phase valid */ 579#define SXP_PINS_CON_PARITY_HI 0x0400 /* Parity pin */ 580#define SXP_PINS_CON_PARITY_LO 0x0200 /* Parity pin */ 581#define SXP_PINS_CON_REQ 0x0100 /* SCSI bus REQUEST */ 582#define SXP_PINS_CON_ACK 0x0080 /* SCSI bus ACKNOWLEDGE */ 583#define SXP_PINS_CON_RST 0x0040 /* SCSI bus RESET */ 584#define SXP_PINS_CON_BSY 0x0020 /* SCSI bus BUSY */ 585#define SXP_PINS_CON_SEL 0x0010 /* SCSI bus SELECT */ 586#define SXP_PINS_CON_ATN 0x0008 /* SCSI bus ATTENTION */ 587#define SXP_PINS_CON_MSG 0x0004 /* SCSI bus MESSAGE */ 588#define SXP_PINS_CON_CD 0x0002 /* SCSI bus COMMAND */ 589#define SXP_PINS_CON_IO 0x0001 /* SCSI bus INPUT */ 590 591/* 592 * Set the hold time for the SCSI Bus Reset to be 250 ms 593 */ 594#define SXP_SCSI_BUS_RESET_HOLD_TIME 250 595 596/* SXP DIFF PINS REGISTER */ 597#define SXP_PINS_DIFF_SENSE 0x0200 /* DIFFSENS sig on SCSI bus */ 598#define SXP_PINS_DIFF_MODE 0x0100 /* DIFFM signal */ 599#define SXP_PINS_DIFF_ENABLE_OUTPUT 0x0080 /* Enable SXP SCSI data drv */ 600#define SXP_PINS_DIFF_PINS_MASK 0x007C /* Differential control pins */ 601#define SXP_PINS_DIFF_TARGET 0x0002 /* Enable SXP target mode */ 602#define SXP_PINS_DIFF_INITIATOR 0x0001 /* Enable SXP initiator mode */ 603 604/* Ultra2 only */ 605#define SXP_PINS_LVD_MODE 0x1000 606#define SXP_PINS_HVD_MODE 0x0800 607#define SXP_PINS_SE_MODE 0x0400 608 609/* The above have to be put together with the DIFFM pin to make sense */ 610#define ISP1080_LVD_MODE (SXP_PINS_LVD_MODE) 611#define ISP1080_HVD_MODE (SXP_PINS_HVD_MODE|SXP_PINS_DIFF_MODE) 612#define ISP1080_SE_MODE (SXP_PINS_SE_MODE) 613#define ISP1080_MODE_MASK \ 614 (SXP_PINS_LVD_MODE|SXP_PINS_HVD_MODE|SXP_PINS_SE_MODE|SXP_PINS_DIFF_MODE) 615 616/* 617 * RISC and Host Command and Control Block Register Offsets 618 */ 619 620#define RISC_ACC RISC_BLOCK+0x0 /* RW*: Accumulator */ 621#define RISC_R1 RISC_BLOCK+0x2 /* RW*: GP Reg R1 */ 622#define RISC_R2 RISC_BLOCK+0x4 /* RW*: GP Reg R2 */ 623#define RISC_R3 RISC_BLOCK+0x6 /* RW*: GP Reg R3 */ 624#define RISC_R4 RISC_BLOCK+0x8 /* RW*: GP Reg R4 */ 625#define RISC_R5 RISC_BLOCK+0xA /* RW*: GP Reg R5 */ 626#define RISC_R6 RISC_BLOCK+0xC /* RW*: GP Reg R6 */ 627#define RISC_R7 RISC_BLOCK+0xE /* RW*: GP Reg R7 */ 628#define RISC_R8 RISC_BLOCK+0x10 /* RW*: GP Reg R8 */ 629#define RISC_R9 RISC_BLOCK+0x12 /* RW*: GP Reg R9 */ 630#define RISC_R10 RISC_BLOCK+0x14 /* RW*: GP Reg R10 */ 631#define RISC_R11 RISC_BLOCK+0x16 /* RW*: GP Reg R11 */ 632#define RISC_R12 RISC_BLOCK+0x18 /* RW*: GP Reg R12 */ 633#define RISC_R13 RISC_BLOCK+0x1a /* RW*: GP Reg R13 */ 634#define RISC_R14 RISC_BLOCK+0x1c /* RW*: GP Reg R14 */ 635#define RISC_R15 RISC_BLOCK+0x1e /* RW*: GP Reg R15 */ 636#define RISC_PSR RISC_BLOCK+0x20 /* RW*: Processor Status */ 637#define RISC_IVR RISC_BLOCK+0x22 /* RW*: Interrupt Vector */ 638#define RISC_PCR RISC_BLOCK+0x24 /* RW*: Processor Ctrl */ 639#define RISC_RAR0 RISC_BLOCK+0x26 /* RW*: Ram Address #0 */ 640#define RISC_RAR1 RISC_BLOCK+0x28 /* RW*: Ram Address #1 */ 641#define RISC_LCR RISC_BLOCK+0x2a /* RW*: Loop Counter */ 642#define RISC_PC RISC_BLOCK+0x2c /* R : Program Counter */ 643#define RISC_MTR RISC_BLOCK+0x2e /* RW*: Memory Timing */ 644#define RISC_MTR2100 RISC_BLOCK+0x30 645 646#define RISC_EMB RISC_BLOCK+0x30 /* RW*: Ext Mem Boundary */ 647#define DUAL_BANK 8 648#define RISC_SP RISC_BLOCK+0x32 /* RW*: Stack Pointer */ 649#define RISC_HRL RISC_BLOCK+0x3e /* R *: Hardware Rev Level */ 650#define HCCR RISC_BLOCK+0x40 /* RW : Host Command & Ctrl */ 651#define BP0 RISC_BLOCK+0x42 /* RW : Processor Brkpt #0 */ 652#define BP1 RISC_BLOCK+0x44 /* RW : Processor Brkpt #1 */ 653#define TCR RISC_BLOCK+0x46 /* W : Test Control */ 654#define TMR RISC_BLOCK+0x48 /* W : Test Mode */ 655 656 657/* PROCESSOR STATUS REGISTER */ 658#define RISC_PSR_FORCE_TRUE 0x8000 659#define RISC_PSR_LOOP_COUNT_DONE 0x4000 660#define RISC_PSR_RISC_INT 0x2000 661#define RISC_PSR_TIMER_ROLLOVER 0x1000 662#define RISC_PSR_ALU_OVERFLOW 0x0800 663#define RISC_PSR_ALU_MSB 0x0400 664#define RISC_PSR_ALU_CARRY 0x0200 665#define RISC_PSR_ALU_ZERO 0x0100 666 667#define RISC_PSR_PCI_ULTRA 0x0080 668#define RISC_PSR_SBUS_ULTRA 0x0020 669 670#define RISC_PSR_DMA_INT 0x0010 671#define RISC_PSR_SXP_INT 0x0008 672#define RISC_PSR_HOST_INT 0x0004 673#define RISC_PSR_INT_PENDING 0x0002 674#define RISC_PSR_FORCE_FALSE 0x0001 675 676 677/* Host Command and Control */ 678#define HCCR_CMD_NOP 0x0000 /* NOP */ 679#define HCCR_CMD_RESET 0x1000 /* Reset RISC */ 680#define HCCR_CMD_PAUSE 0x2000 /* Pause RISC */ 681#define HCCR_CMD_RELEASE 0x3000 /* Release Paused RISC */ 682#define HCCR_CMD_STEP 0x4000 /* Single Step RISC */ 683#define HCCR_2X00_DISABLE_PARITY_PAUSE 0x4001 /* 684 * Disable RISC pause on FPM 685 * parity error. 686 */ 687#define HCCR_CMD_SET_HOST_INT 0x5000 /* Set Host Interrupt */ 688#define HCCR_CMD_CLEAR_HOST_INT 0x6000 /* Clear Host Interrupt */ 689#define HCCR_CMD_CLEAR_RISC_INT 0x7000 /* Clear RISC interrupt */ 690#define HCCR_CMD_BREAKPOINT 0x8000 /* Change breakpoint enables */ 691#define PCI_HCCR_CMD_BIOS 0x9000 /* Write BIOS (disable) */ 692#define PCI_HCCR_CMD_PARITY 0xA000 /* Write parity enable */ 693#define PCI_HCCR_CMD_PARITY_ERR 0xE000 /* Generate parity error */ 694#define HCCR_CMD_TEST_MODE 0xF000 /* Set Test Mode */ 695 696#define ISP2100_HCCR_PARITY_ENABLE_2 0x0400 697#define ISP2100_HCCR_PARITY_ENABLE_1 0x0200 698#define ISP2100_HCCR_PARITY_ENABLE_0 0x0100 699#define ISP2100_HCCR_PARITY 0x0001 700 701#define PCI_HCCR_PARITY 0x0400 /* Parity error flag */ 702#define PCI_HCCR_PARITY_ENABLE_1 0x0200 /* Parity enable bank 1 */ 703#define PCI_HCCR_PARITY_ENABLE_0 0x0100 /* Parity enable bank 0 */ 704 705#define HCCR_HOST_INT 0x0080 /* R : Host interrupt set */ 706#define HCCR_RESET 0x0040 /* R : reset in progress */ 707#define HCCR_PAUSE 0x0020 /* R : RISC paused */ 708 709#define PCI_HCCR_BIOS 0x0001 /* W : BIOS enable */ 710 711/* 712 * NVRAM Definitions (PCI cards only) 713 */ 714 715#define ISPBSMX(c, byte, shift, mask) \ 716 (((c)[(byte)] >> (shift)) & (mask)) 717/* 718 * Qlogic 1020/1040 NVRAM is an array of 128 bytes. 719 * 720 * Some portion of the front of this is for general host adapter properties 721 * This is followed by an array of per-target parameters, and is tailed off 722 * with a checksum xor byte at offset 127. For non-byte entities data is 723 * stored in Little Endian order. 724 */ 725 726#define ISP_NVRAM_SIZE 128 727 728#define ISP_NVRAM_VERSION(c) (c)[4] 729#define ISP_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 5, 0, 0x03) 730#define ISP_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 5, 2, 0x01) 731#define ISP_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 5, 3, 0x01) 732#define ISP_NVRAM_INITIATOR_ID(c) ISPBSMX(c, 5, 4, 0x0f) 733#define ISP_NVRAM_BUS_RESET_DELAY(c) (c)[6] 734#define ISP_NVRAM_BUS_RETRY_COUNT(c) (c)[7] 735#define ISP_NVRAM_BUS_RETRY_DELAY(c) (c)[8] 736#define ISP_NVRAM_ASYNC_DATA_SETUP_TIME(c) ISPBSMX(c, 9, 0, 0x0f) 737#define ISP_NVRAM_REQ_ACK_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 4, 0x01) 738#define ISP_NVRAM_DATA_LINE_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 5, 0x01) 739#define ISP_NVRAM_DATA_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 6, 0x01) 740#define ISP_NVRAM_CMD_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 7, 0x01) 741#define ISP_NVRAM_TAG_AGE_LIMIT(c) (c)[10] 742#define ISP_NVRAM_LOWTRM_ENABLE(c) ISPBSMX(c, 11, 0, 0x01) 743#define ISP_NVRAM_HITRM_ENABLE(c) ISPBSMX(c, 11, 1, 0x01) 744#define ISP_NVRAM_PCMC_BURST_ENABLE(c) ISPBSMX(c, 11, 2, 0x01) 745#define ISP_NVRAM_ENABLE_60_MHZ(c) ISPBSMX(c, 11, 3, 0x01) 746#define ISP_NVRAM_SCSI_RESET_DISABLE(c) ISPBSMX(c, 11, 4, 0x01) 747#define ISP_NVRAM_ENABLE_AUTO_TERM(c) ISPBSMX(c, 11, 5, 0x01) 748#define ISP_NVRAM_FIFO_THRESHOLD_128(c) ISPBSMX(c, 11, 6, 0x01) 749#define ISP_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 11, 7, 0x01) 750#define ISP_NVRAM_SELECTION_TIMEOUT(c) (((c)[12]) | ((c)[13] << 8)) 751#define ISP_NVRAM_MAX_QUEUE_DEPTH(c) (((c)[14]) | ((c)[15] << 8)) 752#define ISP_NVRAM_SCSI_BUS_SIZE(c) ISPBSMX(c, 16, 0, 0x01) 753#define ISP_NVRAM_SCSI_BUS_TYPE(c) ISPBSMX(c, 16, 1, 0x01) 754#define ISP_NVRAM_ADAPTER_CLK_SPEED(c) ISPBSMX(c, 16, 2, 0x01) 755#define ISP_NVRAM_SOFT_TERM_SUPPORT(c) ISPBSMX(c, 16, 3, 0x01) 756#define ISP_NVRAM_FLASH_ONBOARD(c) ISPBSMX(c, 16, 4, 0x01) 757#define ISP_NVRAM_FAST_MTTR_ENABLE(c) ISPBSMX(c, 22, 0, 0x01) 758 759#define ISP_NVRAM_TARGOFF 28 760#define ISP_NVARM_TARGSIZE 6 761#define _IxT(tgt, tidx) \ 762 (ISP_NVRAM_TARGOFF + (ISP_NVARM_TARGSIZE * (tgt)) + (tidx)) 763#define ISP_NVRAM_TGT_RENEG(c, t) ISPBSMX(c, _IxT(t, 0), 0, 0x01) 764#define ISP_NVRAM_TGT_QFRZ(c, t) ISPBSMX(c, _IxT(t, 0), 1, 0x01) 765#define ISP_NVRAM_TGT_ARQ(c, t) ISPBSMX(c, _IxT(t, 0), 2, 0x01) 766#define ISP_NVRAM_TGT_TQING(c, t) ISPBSMX(c, _IxT(t, 0), 3, 0x01) 767#define ISP_NVRAM_TGT_SYNC(c, t) ISPBSMX(c, _IxT(t, 0), 4, 0x01) 768#define ISP_NVRAM_TGT_WIDE(c, t) ISPBSMX(c, _IxT(t, 0), 5, 0x01) 769#define ISP_NVRAM_TGT_PARITY(c, t) ISPBSMX(c, _IxT(t, 0), 6, 0x01) 770#define ISP_NVRAM_TGT_DISC(c, t) ISPBSMX(c, _IxT(t, 0), 7, 0x01) 771#define ISP_NVRAM_TGT_EXEC_THROTTLE(c, t) ISPBSMX(c, _IxT(t, 1), 0, 0xff) 772#define ISP_NVRAM_TGT_SYNC_PERIOD(c, t) ISPBSMX(c, _IxT(t, 2), 0, 0xff) 773#define ISP_NVRAM_TGT_SYNC_OFFSET(c, t) ISPBSMX(c, _IxT(t, 3), 0, 0x0f) 774#define ISP_NVRAM_TGT_DEVICE_ENABLE(c, t) ISPBSMX(c, _IxT(t, 3), 4, 0x01) 775#define ISP_NVRAM_TGT_LUN_DISABLE(c, t) ISPBSMX(c, _IxT(t, 3), 5, 0x01) 776 777/* 778 * Qlogic 1080/1240 NVRAM is an array of 256 bytes. 779 * 780 * Some portion of the front of this is for general host adapter properties 781 * This is followed by an array of per-target parameters, and is tailed off 782 * with a checksum xor byte at offset 256. For non-byte entities data is 783 * stored in Little Endian order. 784 */ 785 786#define ISP1080_NVRAM_SIZE 256 787 788#define ISP1080_NVRAM_VERSION(c) ISP_NVRAM_VERSION(c) 789 790/* Offset 5 */ 791/* 792 u_int8_t bios_configuration_mode :2; 793 u_int8_t bios_disable :1; 794 u_int8_t selectable_scsi_boot_enable :1; 795 u_int8_t cd_rom_boot_enable :1; 796 u_int8_t disable_loading_risc_code :1; 797 u_int8_t enable_64bit_addressing :1; 798 u_int8_t unused_7 :1; 799 */ 800 801/* Offsets 6, 7 */ 802/* 803 u_int8_t boot_lun_number :5; 804 u_int8_t scsi_bus_number :1; 805 u_int8_t unused_6 :1; 806 u_int8_t unused_7 :1; 807 u_int8_t boot_target_number :4; 808 u_int8_t unused_12 :1; 809 u_int8_t unused_13 :1; 810 u_int8_t unused_14 :1; 811 u_int8_t unused_15 :1; 812 */ 813 814#define ISP1080_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 16, 3, 0x01) 815 816#define ISP1080_NVRAM_BURST_ENABLE(c) ISPBSMX(c, 16, 1, 0x01) 817#define ISP1080_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 16, 4, 0x0f) 818 819#define ISP1080_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 17, 7, 0x01) 820#define ISP1080_NVRAM_BUS0_TERM_MODE(c) ISPBSMX(c, 17, 0, 0x03) 821#define ISP1080_NVRAM_BUS1_TERM_MODE(c) ISPBSMX(c, 17, 2, 0x03) 822 823#define ISP1080_ISP_PARAMETER(c) \ 824 (((c)[18]) | ((c)[19] << 8)) 825 826#define ISP1080_FAST_POST(c) ISPBSMX(c, 20, 0, 0x01) 827#define ISP1080_REPORT_LVD_TRANSITION(c) ISPBSMX(c, 20, 1, 0x01) 828 829#define ISP1080_BUS1_OFF 112 830 831#define ISP1080_NVRAM_INITIATOR_ID(c, b) \ 832 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 24, 0, 0x0f) 833#define ISP1080_NVRAM_BUS_RESET_DELAY(c, b) \ 834 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 25] 835#define ISP1080_NVRAM_BUS_RETRY_COUNT(c, b) \ 836 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 26] 837#define ISP1080_NVRAM_BUS_RETRY_DELAY(c, b) \ 838 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 27] 839 840#define ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME(c, b) \ 841 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 0, 0x0f) 842#define ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION(c, b) \ 843 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 4, 0x01) 844#define ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION(c, b) \ 845 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 5, 0x01) 846#define ISP1080_NVRAM_SELECTION_TIMEOUT(c, b) \ 847 (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 30]) | \ 848 ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 31] << 8)) 849#define ISP1080_NVRAM_MAX_QUEUE_DEPTH(c, b) \ 850 (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 32]) | \ 851 ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 33] << 8)) 852 853#define ISP1080_NVRAM_TARGOFF(b) \ 854 ((b == 0)? 40: (40 + ISP1080_BUS1_OFF)) 855#define ISP1080_NVRAM_TARGSIZE 6 856#define _IxT8(tgt, tidx, b) \ 857 (ISP1080_NVRAM_TARGOFF((b)) + (ISP1080_NVRAM_TARGSIZE * (tgt)) + (tidx)) 858 859#define ISP1080_NVRAM_TGT_RENEG(c, t, b) \ 860 ISPBSMX(c, _IxT8(t, 0, (b)), 0, 0x01) 861#define ISP1080_NVRAM_TGT_QFRZ(c, t, b) \ 862 ISPBSMX(c, _IxT8(t, 0, (b)), 1, 0x01) 863#define ISP1080_NVRAM_TGT_ARQ(c, t, b) \ 864 ISPBSMX(c, _IxT8(t, 0, (b)), 2, 0x01) 865#define ISP1080_NVRAM_TGT_TQING(c, t, b) \ 866 ISPBSMX(c, _IxT8(t, 0, (b)), 3, 0x01) 867#define ISP1080_NVRAM_TGT_SYNC(c, t, b) \ 868 ISPBSMX(c, _IxT8(t, 0, (b)), 4, 0x01) 869#define ISP1080_NVRAM_TGT_WIDE(c, t, b) \ 870 ISPBSMX(c, _IxT8(t, 0, (b)), 5, 0x01) 871#define ISP1080_NVRAM_TGT_PARITY(c, t, b) \ 872 ISPBSMX(c, _IxT8(t, 0, (b)), 6, 0x01) 873#define ISP1080_NVRAM_TGT_DISC(c, t, b) \ 874 ISPBSMX(c, _IxT8(t, 0, (b)), 7, 0x01) 875#define ISP1080_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \ 876 ISPBSMX(c, _IxT8(t, 1, (b)), 0, 0xff) 877#define ISP1080_NVRAM_TGT_SYNC_PERIOD(c, t, b) \ 878 ISPBSMX(c, _IxT8(t, 2, (b)), 0, 0xff) 879#define ISP1080_NVRAM_TGT_SYNC_OFFSET(c, t, b) \ 880 ISPBSMX(c, _IxT8(t, 3, (b)), 0, 0x0f) 881#define ISP1080_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \ 882 ISPBSMX(c, _IxT8(t, 3, (b)), 4, 0x01) 883#define ISP1080_NVRAM_TGT_LUN_DISABLE(c, t, b) \ 884 ISPBSMX(c, _IxT8(t, 3, (b)), 5, 0x01) 885 886#define ISP12160_NVRAM_HBA_ENABLE ISP1080_NVRAM_HBA_ENABLE 887#define ISP12160_NVRAM_BURST_ENABLE ISP1080_NVRAM_BURST_ENABLE 888#define ISP12160_NVRAM_FIFO_THRESHOLD ISP1080_NVRAM_FIFO_THRESHOLD 889#define ISP12160_NVRAM_AUTO_TERM_SUPPORT ISP1080_NVRAM_AUTO_TERM_SUPPORT 890#define ISP12160_NVRAM_BUS0_TERM_MODE ISP1080_NVRAM_BUS0_TERM_MODE 891#define ISP12160_NVRAM_BUS1_TERM_MODE ISP1080_NVRAM_BUS1_TERM_MODE 892#define ISP12160_ISP_PARAMETER ISP12160_ISP_PARAMETER 893#define ISP12160_FAST_POST ISP1080_FAST_POST 894#define ISP12160_REPORT_LVD_TRANSITION ISP1080_REPORT_LVD_TRANSTION 895 896#define ISP12160_NVRAM_INITIATOR_ID \ 897 ISP1080_NVRAM_INITIATOR_ID 898#define ISP12160_NVRAM_BUS_RESET_DELAY \ 899 ISP1080_NVRAM_BUS_RESET_DELAY 900#define ISP12160_NVRAM_BUS_RETRY_COUNT \ 901 ISP1080_NVRAM_BUS_RETRY_COUNT 902#define ISP12160_NVRAM_BUS_RETRY_DELAY \ 903 ISP1080_NVRAM_BUS_RETRY_DELAY 904#define ISP12160_NVRAM_ASYNC_DATA_SETUP_TIME \ 905 ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME 906#define ISP12160_NVRAM_REQ_ACK_ACTIVE_NEGATION \ 907 ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION 908#define ISP12160_NVRAM_DATA_LINE_ACTIVE_NEGATION \ 909 ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION 910#define ISP12160_NVRAM_SELECTION_TIMEOUT \ 911 ISP1080_NVRAM_SELECTION_TIMEOUT 912#define ISP12160_NVRAM_MAX_QUEUE_DEPTH \ 913 ISP1080_NVRAM_MAX_QUEUE_DEPTH 914 915 916#define ISP12160_BUS0_OFF 24 917#define ISP12160_BUS1_OFF 136 918 919#define ISP12160_NVRAM_TARGOFF(b) \ 920 (((b == 0)? ISP12160_BUS0_OFF : ISP12160_BUS1_OFF) + 16) 921 922#define ISP12160_NVRAM_TARGSIZE 6 923#define _IxT16(tgt, tidx, b) \ 924 (ISP12160_NVRAM_TARGOFF((b))+(ISP12160_NVRAM_TARGSIZE * (tgt))+(tidx)) 925 926#define ISP12160_NVRAM_TGT_RENEG(c, t, b) \ 927 ISPBSMX(c, _IxT16(t, 0, (b)), 0, 0x01) 928#define ISP12160_NVRAM_TGT_QFRZ(c, t, b) \ 929 ISPBSMX(c, _IxT16(t, 0, (b)), 1, 0x01) 930#define ISP12160_NVRAM_TGT_ARQ(c, t, b) \ 931 ISPBSMX(c, _IxT16(t, 0, (b)), 2, 0x01) 932#define ISP12160_NVRAM_TGT_TQING(c, t, b) \ 933 ISPBSMX(c, _IxT16(t, 0, (b)), 3, 0x01) 934#define ISP12160_NVRAM_TGT_SYNC(c, t, b) \ 935 ISPBSMX(c, _IxT16(t, 0, (b)), 4, 0x01) 936#define ISP12160_NVRAM_TGT_WIDE(c, t, b) \ 937 ISPBSMX(c, _IxT16(t, 0, (b)), 5, 0x01) 938#define ISP12160_NVRAM_TGT_PARITY(c, t, b) \ 939 ISPBSMX(c, _IxT16(t, 0, (b)), 6, 0x01) 940#define ISP12160_NVRAM_TGT_DISC(c, t, b) \ 941 ISPBSMX(c, _IxT16(t, 0, (b)), 7, 0x01) 942 943#define ISP12160_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \ 944 ISPBSMX(c, _IxT16(t, 1, (b)), 0, 0xff) 945#define ISP12160_NVRAM_TGT_SYNC_PERIOD(c, t, b) \ 946 ISPBSMX(c, _IxT16(t, 2, (b)), 0, 0xff) 947 948#define ISP12160_NVRAM_TGT_SYNC_OFFSET(c, t, b) \ 949 ISPBSMX(c, _IxT16(t, 3, (b)), 0, 0x1f) 950#define ISP12160_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \ 951 ISPBSMX(c, _IxT16(t, 3, (b)), 5, 0x01) 952 953#define ISP12160_NVRAM_PPR_OPTIONS(c, t, b) \ 954 ISPBSMX(c, _IxT16(t, 4, (b)), 0, 0x0f) 955#define ISP12160_NVRAM_PPR_WIDTH(c, t, b) \ 956 ISPBSMX(c, _IxT16(t, 4, (b)), 4, 0x03) 957#define ISP12160_NVRAM_PPR_ENABLE(c, t, b) \ 958 ISPBSMX(c, _IxT16(t, 4, (b)), 7, 0x01) 959 960/* 961 * Qlogic 2XXX NVRAM is an array of 256 bytes. 962 * 963 * Some portion of the front of this is for general RISC engine parameters, 964 * mostly reflecting the state of the last INITIALIZE FIRMWARE mailbox command. 965 * 966 * This is followed by some general host adapter parameters, and ends with 967 * a checksum xor byte at offset 255. For non-byte entities data is stored 968 * in Little Endian order. 969 */ 970#define ISP2100_NVRAM_SIZE 256 971/* ISP_NVRAM_VERSION is in same overall place */ 972#define ISP2100_NVRAM_RISCVER(c) (c)[6] 973#define ISP2100_NVRAM_OPTIONS(c) (c)[8] 974#define ISP2100_NVRAM_MAXFRAMELENGTH(c) (((c)[10]) | ((c)[11] << 8)) 975#define ISP2100_NVRAM_MAXIOCBALLOCATION(c) (((c)[12]) | ((c)[13] << 8)) 976#define ISP2100_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8)) 977#define ISP2100_NVRAM_RETRY_COUNT(c) (c)[16] 978#define ISP2100_NVRAM_RETRY_DELAY(c) (c)[17] 979 980#define ISP2100_NVRAM_PORT_NAME(c) (\ 981 (((u_int64_t)(c)[18]) << 56) | \ 982 (((u_int64_t)(c)[19]) << 48) | \ 983 (((u_int64_t)(c)[20]) << 40) | \ 984 (((u_int64_t)(c)[21]) << 32) | \ 985 (((u_int64_t)(c)[22]) << 24) | \ 986 (((u_int64_t)(c)[23]) << 16) | \ 987 (((u_int64_t)(c)[24]) << 8) | \ 988 (((u_int64_t)(c)[25]) << 0)) 989 990#define ISP2100_NVRAM_HARDLOOPID(c) (c)[26] 991 992#define ISP2200_NVRAM_NODE_NAME(c) (\ 993 (((u_int64_t)(c)[30]) << 56) | \ 994 (((u_int64_t)(c)[31]) << 48) | \ 995 (((u_int64_t)(c)[32]) << 40) | \ 996 (((u_int64_t)(c)[33]) << 32) | \ 997 (((u_int64_t)(c)[34]) << 24) | \ 998 (((u_int64_t)(c)[35]) << 16) | \ 999 (((u_int64_t)(c)[36]) << 8) | \ 1000 (((u_int64_t)(c)[37]) << 0)) 1001 1002#define ISP2100_NVRAM_HBA_OPTIONS(c) (c)[70] 1003#define ISP2100_NVRAM_HBA_DISABLE(c) ISPBSMX(c, 70, 0, 0x01) 1004#define ISP2100_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 70, 1, 0x01) 1005#define ISP2100_NVRAM_LUN_DISABLE(c) ISPBSMX(c, 70, 2, 0x01) 1006#define ISP2100_NVRAM_ENABLE_SELECT_BOOT(c) ISPBSMX(c, 70, 3, 0x01) 1007#define ISP2100_NVRAM_DISABLE_CODELOAD(c) ISPBSMX(c, 70, 4, 0x01) 1008#define ISP2100_NVRAM_SET_CACHELINESZ(c) ISPBSMX(c, 70, 5, 0x01) 1009 1010#define ISP2100_NVRAM_BOOT_NODE_NAME(c) (\ 1011 (((u_int64_t)(c)[72]) << 56) | \ 1012 (((u_int64_t)(c)[73]) << 48) | \ 1013 (((u_int64_t)(c)[74]) << 40) | \ 1014 (((u_int64_t)(c)[75]) << 32) | \ 1015 (((u_int64_t)(c)[76]) << 24) | \ 1016 (((u_int64_t)(c)[77]) << 16) | \ 1017 (((u_int64_t)(c)[78]) << 8) | \ 1018 (((u_int64_t)(c)[79]) << 0)) 1019 1020#define ISP2100_NVRAM_BOOT_LUN(c) (c)[80] 1021 1022#define ISP2200_HBA_FEATURES(c) (c)[232] | ((c)[233] << 8) 1023 1024/* 1025 * Firmware Crash Dump 1026 * 1027 * QLogic needs specific information format when they look at firmware crashes. 1028 * 1029 * This is incredibly kernel memory consumptive (to say the least), so this 1030 * code is only compiled in when needed. 1031 */ 1032 1033#define QLA2200_RISC_IMAGE_DUMP_SIZE \ 1034 (1 * sizeof (u_int16_t)) + /* 'used' flag (also HBA type) */ \ 1035 (352 * sizeof (u_int16_t)) + /* RISC registers */ \ 1036 (61440 * sizeof (u_int16_t)) /* RISC SRAM (offset 0x1000..0xffff) */ 1037#define QLA2300_RISC_IMAGE_DUMP_SIZE \ 1038 (1 * sizeof (u_int16_t)) + /* 'used' flag (also HBA type) */ \ 1039 (464 * sizeof (u_int16_t)) + /* RISC registers */ \ 1040 (63488 * sizeof (u_int16_t)) + /* RISC SRAM (0x0800..0xffff) */ \ 1041 (4096 * sizeof (u_int16_t)) + /* RISC SRAM (0x10000..0x10FFF) */ \ 1042 (61440 * sizeof (u_int16_t)) /* RISC SRAM (0x11000..0x1FFFF) */ 1043/* the larger of the two */ 1044#define ISP_CRASH_IMAGE_SIZE QLA2300_RISC_IMAGE_DUMP_SIZE 1045#endif /* _ISPREG_H */ 1046