igsfb_subr.c revision 1.10
1/* $NetBSD: igsfb_subr.c,v 1.10 2009/11/11 17:01:17 macallan Exp $ */ 2 3/* 4 * Copyright (c) 2002 Valeriy E. Ushakov 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30/* 31 * Integraphics Systems IGA 168x and CyberPro series. 32 */ 33#include <sys/cdefs.h> 34__KERNEL_RCSID(0, "$NetBSD: igsfb_subr.c,v 1.10 2009/11/11 17:01:17 macallan Exp $"); 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/kernel.h> 39#include <sys/device.h> 40 41#include <sys/bus.h> 42 43#include <dev/wscons/wsdisplayvar.h> 44#include <dev/wscons/wsconsio.h> 45#include <dev/rasops/rasops.h> 46#include <dev/wscons/wsdisplay_vconsvar.h> 47 48#include <dev/ic/igsfbreg.h> 49#include <dev/ic/igsfbvar.h> 50 51#ifdef IGSFB_DEBUG 52#define DPRINTF printf 53#else 54#define DPRINTF while (0) printf 55#endif 56 57static void igsfb_init_seq(struct igsfb_devconfig *); 58static void igsfb_init_crtc(struct igsfb_devconfig *); 59static void igsfb_init_grfx(struct igsfb_devconfig *); 60static void igsfb_init_attr(struct igsfb_devconfig *); 61static void igsfb_init_ext(struct igsfb_devconfig *); 62static void igsfb_init_dac(struct igsfb_devconfig *); 63 64static void igsfb_freq_latch(struct igsfb_devconfig *); 65static void igsfb_video_on(struct igsfb_devconfig *); 66static void igsfb_calc_pll(int, int *, int *, int *, int, int, int, int); 67 68 69 70/* 71 * Enable chip. 72 */ 73int 74igsfb_enable(bus_space_tag_t iot, bus_addr_t iobase, int ioflags) 75{ 76 bus_space_handle_t vdoh; 77 bus_space_handle_t vseh; 78 bus_space_handle_t regh; 79 int ret; 80 81 ret = bus_space_map(iot, iobase + IGS_VDO, 1, ioflags, &vdoh); 82 if (ret != 0) { 83 printf("unable to map VDO register\n"); 84 goto out0; 85 } 86 87 ret = bus_space_map(iot, iobase + IGS_VSE, 1, ioflags, &vseh); 88 if (ret != 0) { 89 printf("unable to map VSE register\n"); 90 goto out1; 91 } 92 93 ret = bus_space_map(iot, iobase + IGS_REG_BASE, IGS_REG_SIZE, ioflags, 94 ®h); 95 if (ret != 0) { 96 printf("unable to map I/O registers\n"); 97 goto out2; 98 } 99 100 /* 101 * Start decoding i/o space accesses. 102 */ 103 bus_space_write_1(iot, vdoh, 0, IGS_VDO_ENABLE | IGS_VDO_SETUP); 104 bus_space_write_1(iot, vseh, 0, IGS_VSE_ENABLE); 105 bus_space_write_1(iot, vdoh, 0, IGS_VDO_ENABLE); 106 107 /* 108 * Start decoding memory space accesses (XXX: move out of here? 109 * we program this register in igsfb_init_ext). 110 * While here, enable coprocessor and select IGS_COP_BASE_B. 111 */ 112 igs_ext_write(iot, regh, IGS_EXT_BIU_MISC_CTL, 113 (IGS_EXT_BIU_LINEAREN 114 | IGS_EXT_BIU_COPREN | IGS_EXT_BIU_COPASELB)); 115 116 bus_space_unmap(iot, regh, IGS_REG_SIZE); 117 out2: bus_space_unmap(iot, vseh, 1); 118 out1: bus_space_unmap(iot, vdoh, 1); 119 out0: return ret; 120} 121 122 123/* 124 * Init sequencer. 125 * This is common for all video modes. 126 */ 127static void 128igsfb_init_seq(struct igsfb_devconfig *dc) 129{ 130 bus_space_tag_t iot = dc->dc_iot; 131 bus_space_handle_t ioh = dc->dc_ioh; 132 133 /* start messing with sequencer */ 134 igs_seq_write(iot, ioh, IGS_SEQ_RESET, 0); 135 136 igs_seq_write(iot, ioh, 1, 0x01); /* 8 dot clock */ 137 igs_seq_write(iot, ioh, 2, 0x0f); /* enable all maps */ 138 igs_seq_write(iot, ioh, 3, 0x00); /* character generator */ 139 igs_seq_write(iot, ioh, 4, 0x0e); /* memory mode */ 140 141 /* this selects color mode among other things */ 142 bus_space_write_1(iot, ioh, IGS_MISC_OUTPUT_W, 0xef); 143 144 /* normal sequencer operation */ 145 igs_seq_write(iot, ioh, IGS_SEQ_RESET, 146 IGS_SEQ_RESET_SYNC | IGS_SEQ_RESET_ASYNC); 147} 148 149 150/* 151 * Init CRTC to 640x480 8bpp at 60Hz 152 */ 153static void 154igsfb_init_crtc(struct igsfb_devconfig *dc) 155{ 156 bus_space_tag_t iot = dc->dc_iot; 157 bus_space_handle_t ioh = dc->dc_ioh; 158 159 igs_crtc_write(iot, ioh, 0x00, 0x5f); 160 igs_crtc_write(iot, ioh, 0x01, 0x4f); 161 igs_crtc_write(iot, ioh, 0x02, 0x50); 162 igs_crtc_write(iot, ioh, 0x03, 0x80); 163 igs_crtc_write(iot, ioh, 0x04, 0x52); 164 igs_crtc_write(iot, ioh, 0x05, 0x9d); 165 igs_crtc_write(iot, ioh, 0x06, 0x0b); 166 igs_crtc_write(iot, ioh, 0x07, 0x3e); 167 168 /* next block is almost constant, only bit 6 in reg 9 differs */ 169 igs_crtc_write(iot, ioh, 0x08, 0x00); 170 igs_crtc_write(iot, ioh, 0x09, 0x40); /* <- either 0x40 or 0x60 */ 171 igs_crtc_write(iot, ioh, 0x0a, 0x00); 172 igs_crtc_write(iot, ioh, 0x0b, 0x00); 173 igs_crtc_write(iot, ioh, 0x0c, 0x00); 174 igs_crtc_write(iot, ioh, 0x0d, 0x00); 175 igs_crtc_write(iot, ioh, 0x0e, 0x00); 176 igs_crtc_write(iot, ioh, 0x0f, 0x00); 177 178 igs_crtc_write(iot, ioh, 0x10, 0xe9); 179 igs_crtc_write(iot, ioh, 0x11, 0x8b); 180 igs_crtc_write(iot, ioh, 0x12, 0xdf); 181 igs_crtc_write(iot, ioh, 0x13, 0x50); 182 igs_crtc_write(iot, ioh, 0x14, 0x00); 183 igs_crtc_write(iot, ioh, 0x15, 0xe6); 184 igs_crtc_write(iot, ioh, 0x16, 0x04); 185 igs_crtc_write(iot, ioh, 0x17, 0xc3); 186 187 igs_crtc_write(iot, ioh, 0x18, 0xff); 188} 189 190 191/* 192 * Init graphics controller. 193 * This is common for all video modes. 194 */ 195static void 196igsfb_init_grfx(struct igsfb_devconfig *dc) 197{ 198 bus_space_tag_t iot = dc->dc_iot; 199 bus_space_handle_t ioh = dc->dc_ioh; 200 201 igs_grfx_write(iot, ioh, 0, 0x00); 202 igs_grfx_write(iot, ioh, 1, 0x00); 203 igs_grfx_write(iot, ioh, 2, 0x00); 204 igs_grfx_write(iot, ioh, 3, 0x00); 205 igs_grfx_write(iot, ioh, 4, 0x00); 206 igs_grfx_write(iot, ioh, 5, 0x60); /* SRMODE, MODE256 */ 207 igs_grfx_write(iot, ioh, 6, 0x05); /* 64k @ a0000, GRAPHICS */ 208 igs_grfx_write(iot, ioh, 7, 0x0f); /* color compare all */ 209 igs_grfx_write(iot, ioh, 8, 0xff); /* bitmask = all bits mutable */ 210} 211 212 213/* 214 * Init attribute controller. 215 * This is common for all video modes. 216 */ 217static void 218igsfb_init_attr(struct igsfb_devconfig *dc) 219{ 220 bus_space_tag_t iot = dc->dc_iot; 221 bus_space_handle_t ioh = dc->dc_ioh; 222 int i; 223 224 igs_attr_flip_flop(iot, ioh); /* reset attr flip-flop to address */ 225 226 for (i = 0; i < 16; ++i) /* crt palette */ 227 igs_attr_write(iot, ioh, i, i); 228 229 igs_attr_write(iot, ioh, 0x10, 0x01); /* select graphic mode */ 230 igs_attr_write(iot, ioh, 0x11, 0x00); /* crt overscan color */ 231 igs_attr_write(iot, ioh, 0x12, 0x0f); /* color plane enable */ 232 igs_attr_write(iot, ioh, 0x13, 0x00); 233 igs_attr_write(iot, ioh, 0x14, 0x00); 234} 235 236 237/* 238 * When done with ATTR controller, call this to unblank the screen. 239 */ 240static void 241igsfb_video_on(struct igsfb_devconfig *dc) 242{ 243 bus_space_tag_t iot = dc->dc_iot; 244 bus_space_handle_t ioh = dc->dc_ioh; 245 246 igs_attr_flip_flop(iot, ioh); 247 bus_space_write_1(iot, ioh, IGS_ATTR_IDX, 0x20); 248 bus_space_write_1(iot, ioh, IGS_ATTR_IDX, 0x20); 249} 250 251 252/* 253 * Latch VCLK (b0/b1) and MCLK (b2/b3) values. 254 */ 255static void 256igsfb_freq_latch(struct igsfb_devconfig *dc) 257{ 258 bus_space_tag_t iot = dc->dc_iot; 259 bus_space_handle_t ioh = dc->dc_ioh; 260 261 bus_space_write_1(iot, ioh, IGS_EXT_IDX, 0xb9); 262 bus_space_write_1(iot, ioh, IGS_EXT_PORT, 0x80); 263 bus_space_write_1(iot, ioh, IGS_EXT_PORT, 0x00); 264} 265 266 267static void 268igsfb_init_ext(struct igsfb_devconfig *dc) 269{ 270 bus_space_tag_t iot = dc->dc_iot; 271 bus_space_handle_t ioh = dc->dc_ioh; 272 int is_cyberpro = (dc->dc_id >= 0x2000); 273 274 igs_ext_write(iot, ioh, 0x10, 0x10); /* IGS_EXT_START_ADDR enable */ 275 igs_ext_write(iot, ioh, 0x12, 0x00); /* IGS_EXT_IRQ_CTL disable */ 276 igs_ext_write(iot, ioh, 0x13, 0x00); /* MBZ for normal operation */ 277 278 igs_ext_write(iot, ioh, 0x31, 0x00); /* segment write ptr */ 279 igs_ext_write(iot, ioh, 0x32, 0x00); /* segment read ptr */ 280 281 /* IGS_EXT_BIU_MISC_CTL: linearen, copren, copaselb, segon */ 282 igs_ext_write(iot, ioh, 0x33, 0x1d); 283 284 /* sprite location */ 285 igs_ext_write(iot, ioh, 0x50, 0x00); 286 igs_ext_write(iot, ioh, 0x51, 0x00); 287 igs_ext_write(iot, ioh, 0x52, 0x00); 288 igs_ext_write(iot, ioh, 0x53, 0x00); 289 igs_ext_write(iot, ioh, 0x54, 0x00); 290 igs_ext_write(iot, ioh, 0x55, 0x00); 291 igs_ext_write(iot, ioh, 0x56, 0x00); /* sprite control */ 292 293 /* IGS_EXT_GRFX_MODE */ 294 igs_ext_write(iot, ioh, 0x57, 0x01); /* raster fb */ 295 296 /* overscan R/G/B */ 297 igs_ext_write(iot, ioh, 0x58, 0x00); 298 igs_ext_write(iot, ioh, 0x59, 0x00); 299 igs_ext_write(iot, ioh, 0x5A, 0x00); 300 301 /* 302 * Video memory size &c. We rely on firmware to program 303 * BUS_CTL(30), MEM_CTL1(71), MEM_CTL2(72) appropriately. 304 */ 305 306 /* ext memory ctl0 */ 307 igs_ext_write(iot, ioh, 0x70, 0x0B); /* enable fifo, seq */ 308 309 /* ext hidden ctl1 */ 310 igs_ext_write(iot, ioh, 0x73, 0x30); /* XXX: krups: 0x20 */ 311 312 /* ext fifo control */ 313 igs_ext_write(iot, ioh, 0x74, 0x10); /* XXX: krups: 0x1b */ 314 igs_ext_write(iot, ioh, 0x75, 0x10); /* XXX: krups: 0x1e */ 315 316 igs_ext_write(iot, ioh, 0x76, 0x00); /* ext seq. */ 317 igs_ext_write(iot, ioh, 0x7A, 0xC8); /* ext. hidden ctl */ 318 319 /* ext graphics ctl: GCEXTPATH. krups 1, nettrom 1, docs 3 */ 320 igs_ext_write(iot, ioh, 0x90, 0x01); 321 322 if (is_cyberpro) /* select normal vclk/mclk registers */ 323 igs_ext_write(iot, ioh, 0xBF, 0x00); 324 325 igs_ext_write(iot, ioh, 0xB0, 0xD2); /* VCLK = 25.175MHz */ 326 igs_ext_write(iot, ioh, 0xB1, 0xD3); 327 igs_ext_write(iot, ioh, 0xB2, 0xDB); /* MCLK = 75MHz*/ 328 igs_ext_write(iot, ioh, 0xB3, 0x54); 329 igsfb_freq_latch(dc); 330 331 if (is_cyberpro) 332 igs_ext_write(iot, ioh, 0xF8, 0x04); /* XXX: ??? */ 333 334 /* 640x480 8bpp at 60Hz */ 335 igs_ext_write(iot, ioh, 0x11, 0x00); 336 igs_ext_write(iot, ioh, 0x77, 0x01); /* 8bpp, indexed */ 337 igs_ext_write(iot, ioh, 0x14, 0x51); 338 igs_ext_write(iot, ioh, 0x15, 0x00); 339} 340 341 342static void 343igsfb_init_dac(struct igsfb_devconfig *dc) 344{ 345 bus_space_tag_t iot = dc->dc_iot; 346 bus_space_handle_t ioh = dc->dc_ioh; 347 uint8_t reg; 348 349 /* RAMDAC address 2 select */ 350 reg = igs_ext_read(iot, ioh, IGS_EXT_SPRITE_CTL); 351 igs_ext_write(iot, ioh, IGS_EXT_SPRITE_CTL, 352 reg | IGS_EXT_SPRITE_DAC_PEL); 353 354 /* VREFEN, DAC8 */ 355 bus_space_write_1(iot, ioh, IGS_DAC_CMD, 0x06); 356 357 /* restore */ 358 igs_ext_write(iot, ioh, IGS_EXT_SPRITE_CTL, reg); 359 360 bus_space_write_1(iot, ioh, IGS_PEL_MASK, 0xff); 361} 362 363 364void 365igsfb_1024x768_8bpp_60Hz(struct igsfb_devconfig *dc) 366{ 367 bus_space_tag_t iot = dc->dc_iot; 368 bus_space_handle_t ioh = dc->dc_ioh; 369 370 igs_crtc_write(iot, ioh, 0x11, 0x00); /* write enable CRTC 0..7 */ 371 372 igs_crtc_write(iot, ioh, 0x00, 0xa3); 373 igs_crtc_write(iot, ioh, 0x01, 0x7f); 374 igs_crtc_write(iot, ioh, 0x02, 0x7f); /* krups: 80 */ 375 igs_crtc_write(iot, ioh, 0x03, 0x85); /* krups: 84 */ 376 igs_crtc_write(iot, ioh, 0x04, 0x84); /* krups: 88 */ 377 igs_crtc_write(iot, ioh, 0x05, 0x95); /* krups: 99 */ 378 igs_crtc_write(iot, ioh, 0x06, 0x24); 379 igs_crtc_write(iot, ioh, 0x07, 0xfd); 380 381 /* next block is almost constant, only bit 6 in reg 9 differs */ 382 igs_crtc_write(iot, ioh, 0x08, 0x00); 383 igs_crtc_write(iot, ioh, 0x09, 0x60); /* <- either 0x40 or 0x60 */ 384 igs_crtc_write(iot, ioh, 0x0a, 0x00); 385 igs_crtc_write(iot, ioh, 0x0b, 0x00); 386 igs_crtc_write(iot, ioh, 0x0c, 0x00); 387 igs_crtc_write(iot, ioh, 0x0d, 0x00); 388 igs_crtc_write(iot, ioh, 0x0e, 0x00); 389 igs_crtc_write(iot, ioh, 0x0f, 0x00); 390 391 igs_crtc_write(iot, ioh, 0x10, 0x06); 392 igs_crtc_write(iot, ioh, 0x11, 0x8c); 393 igs_crtc_write(iot, ioh, 0x12, 0xff); 394 igs_crtc_write(iot, ioh, 0x13, 0x80); /* depends on BPP */ 395 igs_crtc_write(iot, ioh, 0x14, 0x0f); 396 igs_crtc_write(iot, ioh, 0x15, 0x02); 397 igs_crtc_write(iot, ioh, 0x16, 0x21); 398 igs_crtc_write(iot, ioh, 0x17, 0xe3); 399 igs_crtc_write(iot, ioh, 0x18, 0xff); 400 401 igs_ext_write(iot, ioh, 0xB0, 0xE2); /* VCLK */ 402 igs_ext_write(iot, ioh, 0xB1, 0x58); 403#if 1 404 /* XXX: hmm, krups does this */ 405 igs_ext_write(iot, ioh, 0xB2, 0xE2); /* MCLK */ 406 igs_ext_write(iot, ioh, 0xB3, 0x58); 407#endif 408 igsfb_freq_latch(dc); 409 410 igs_ext_write(iot, ioh, 0x11, 0x00); 411 igs_ext_write(iot, ioh, 0x77, 0x01); /* 8bpp, indexed */ 412 igs_ext_write(iot, ioh, 0x14, 0x81); 413 igs_ext_write(iot, ioh, 0x15, 0x00); 414 415 dc->dc_width = 1024; 416 dc->dc_height = 768; 417 dc->dc_depth = 8; 418 dc->dc_stride = dc->dc_width; 419} 420 421 422/* 423 * igs-video-init from krups prom 424 */ 425void 426igsfb_hw_setup(struct igsfb_devconfig *dc) 427{ 428 const struct videomode *mode = NULL; 429 int i; 430 431 igsfb_init_seq(dc); 432 igsfb_init_crtc(dc); 433 igsfb_init_attr(dc); 434 igsfb_init_grfx(dc); 435 igsfb_init_ext(dc); 436 igsfb_init_dac(dc); 437 438 i = 0; 439 while ((strcmp(dc->dc_modestring, videomode_list[i].name) != 0) && 440 ( i < videomode_count)) { 441 i++; 442 } 443 444 if (i < videomode_count) { 445 /* found a mode, now let's see if we can display it */ 446 if ((videomode_list[i].dot_clock <= IGS_MAX_CLOCK) && 447 (videomode_list[i].hdisplay <= 2048) && 448 (videomode_list[i].hdisplay >= 320) && 449 (videomode_list[i].vdisplay <= 2048) && 450 (videomode_list[i].vdisplay >= 200)) { 451 mode = &videomode_list[i]; 452 } 453 } 454 455 if (mode != NULL) { 456 igsfb_set_mode(dc, mode, 8); 457 } else 458 igsfb_1024x768_8bpp_60Hz(dc); 459 460 igsfb_video_on(dc); 461} 462 463void 464igsfb_set_mode(struct igsfb_devconfig *dc, const struct videomode *mode, 465 int depth) 466{ 467 bus_space_tag_t iot = dc->dc_iot; 468 bus_space_handle_t ioh = dc->dc_ioh; 469 int i, m, n, p, hoffset, bytes_per_pixel, memfetch; 470 int vsync_start, hsync_start, vsync_end, hsync_end; 471 int vblank_start, vblank_end, hblank_start, hblank_end; 472 uint8_t vclk1, vclk2, vclk3, overflow; 473 474 bytes_per_pixel = depth >> 3; 475 hoffset = (mode->hdisplay >> 3) * bytes_per_pixel; 476 memfetch = hoffset + 1; 477 overflow = (((mode->vtotal - 2) & 0x400) >> 10) | 478 (((mode->vdisplay -1) & 0x400) >> 9) | 479 ((mode->vsync_start & 0x400) >> 8) | 480 ((mode->vsync_start & 0x400) >> 7) | 481 0x10; 482 483 if (depth == 8) { 484 /* palette mode */ 485 bus_space_write_1(dc->dc_iot, dc->dc_ioh, IGS_DAC_CMD, 0x06); 486 } else { 487 /* bypass palette */ 488 bus_space_write_1(dc->dc_iot, dc->dc_ioh, IGS_DAC_CMD, 0x16); 489 } 490 491 igs_crtc_write(iot, ioh, 0x11, 0x00); /* write enable CRTC 0..7 */ 492 493 hsync_start = mode->hsync_start; 494 hsync_end = mode->hsync_end; 495 496 hblank_start = min(mode->hsync_start, mode->hdisplay); 497 hblank_end = hsync_end; 498 if ((hblank_end - hblank_start) >= 63 * 8) { 499 500 /* 501 * H Blanking size must be < 63*8. Same remark as above. 502 */ 503 hblank_start = hblank_end - 63 * 8; 504 } 505 506 vblank_start = min(mode->vsync_start, mode->vdisplay); 507 vblank_end = mode->vsync_end; 508 509 vsync_start = mode->vsync_start; 510 vsync_end = mode->vsync_end; 511 igs_crtc_write(iot, ioh, 0x00, (mode->htotal >> 3) - 5); 512 igs_crtc_write(iot, ioh, 0x01, (mode->hdisplay >> 3) - 1); 513 igs_crtc_write(iot, ioh, 0x02, (hblank_start >> 3) - 1); 514 igs_crtc_write(iot, ioh, 0x03, 0x80 | (((hblank_end >> 3) - 1) & 0x1f)); 515 igs_crtc_write(iot, ioh, 0x04, hsync_start >> 3); 516 igs_crtc_write(iot, ioh, 0x05, ((((hblank_end >> 3) - 1) & 0x20) << 2) 517 | ((hsync_end >> 3) & 0x1f)); 518 igs_crtc_write(iot, ioh, 0x06, (mode->vtotal - 2) & 0xff); 519 igs_crtc_write(iot, ioh, 0x07, 520 ((vsync_start & 0x200) >> 2) | 521 (((mode->vdisplay - 1) & 0x200) >> 3) | 522 (((mode->vtotal - 2) & 0x200) >> 4) | 523 0x10 | 524 (((vblank_start - 1) & 0x100) >> 5) | 525 ((vsync_start & 0x100) >> 6) | 526 (((mode->vdisplay - 1) & 0x100) >> 7) | 527 ((mode->vtotal & 0x100) >> 8)); 528 529 igs_crtc_write(iot, ioh, 0x08, 0x00); 530 igs_crtc_write(iot, ioh, 0x09, 0x40 | 531 (((vblank_start - 1) & 0x200) >> 4)); 532 igs_crtc_write(iot, ioh, 0x0a, 0x00); 533 igs_crtc_write(iot, ioh, 0x0b, 0x00); 534 igs_crtc_write(iot, ioh, 0x0c, 0x00); 535 igs_crtc_write(iot, ioh, 0x0d, 0x00); 536 igs_crtc_write(iot, ioh, 0x0e, 0x00); 537 igs_crtc_write(iot, ioh, 0x0f, 0x00); 538 539 igs_crtc_write(iot, ioh, 0x10, vsync_start & 0xff); 540 igs_crtc_write(iot, ioh, 0x11, (vsync_end & 0x0f) | 0x20); 541 igs_crtc_write(iot, ioh, 0x12, (mode->vdisplay - 1) & 0xff); 542 igs_crtc_write(iot, ioh, 0x13, hoffset & 0xff); 543 igs_crtc_write(iot, ioh, 0x14, 0x0f); 544 igs_crtc_write(iot, ioh, 0x15, (vblank_start - 1) & 0xff); 545 igs_crtc_write(iot, ioh, 0x16, (vblank_end - 1) & 0xff); 546 igs_crtc_write(iot, ioh, 0x17, 0xe3); 547 igs_crtc_write(iot, ioh, 0x18, 0xff); 548 549 for (i = 0; i < 0x10; i++) 550 igs_attr_write(iot, ioh, i, i); 551 552 igs_attr_write(iot, ioh, 0x10, 0x01); 553 igs_attr_write(iot, ioh, 0x11, 0x00); 554 igs_attr_write(iot, ioh, 0x12, 0x0f); 555 igs_attr_write(iot, ioh, 0x13, 0x00); 556 557 igs_grfx_write(iot, ioh, 0x00, 0x00); 558 igs_grfx_write(iot, ioh, 0x01, 0x00); 559 igs_grfx_write(iot, ioh, 0x02, 0x00); 560 igs_grfx_write(iot, ioh, 0x03, 0x00); 561 igs_grfx_write(iot, ioh, 0x04, 0x00); 562 igs_grfx_write(iot, ioh, 0x05, 0x60); 563 igs_grfx_write(iot, ioh, 0x06, 0x05); 564 igs_grfx_write(iot, ioh, 0x07, 0x0f); 565 igs_grfx_write(iot, ioh, 0x08, 0xff); 566 567 /* crank up memory clock to 95MHz - needed for higher resolutions */ 568 igs_ext_write(iot, ioh, 0xB2, 0x91); 569 igs_ext_write(iot, ioh, 0xB3, 0x6a); 570 igsfb_freq_latch(dc); 571 572 igs_ext_write(iot, ioh, 0x11, overflow); 573 igs_ext_write(iot, ioh, 0x77, bytes_per_pixel); 574 igs_ext_write(iot, ioh, 0x14, memfetch & 0xff); 575 igs_ext_write(iot, ioh, 0x15, 576 ((memfetch & 0x300) >> 8) | ((hoffset & 0x300) >> 4)); 577 igs_ext_write(iot, ioh, 0x56, 0x00); 578 579 /* finally set the dot clock */ 580 igsfb_calc_pll(mode->dot_clock, &m, &n, &p, 2047, 255, 7, IGS_MIN_VCO); 581 DPRINTF("m: %x, n: %x, p: %x\n", m, n, p); 582 vclk1 = m & 0xff; 583 vclk2 = (n & 0x1f) | ((p << 6) & 0xc0) | 584 (mode->dot_clock > 180000 ? 0x20 : 0); 585 vclk3 = ((m >> 8) & 0x7) | ((n >> 2) & 0x38) | ((p << 4) & 0x40); 586 DPRINTF("clk: %02x %02x %02x\n", vclk1, vclk2, vclk3); 587 igs_ext_write(iot, ioh, 0xB0, vclk1); 588 igs_ext_write(iot, ioh, 0xB1, vclk2); 589 igs_ext_write(iot, ioh, 0xBA, vclk3); 590 igsfb_freq_latch(dc); 591 DPRINTF("clock: %d\n", IGS_CLOCK(m, n, p)); 592 593 dc->dc_width = mode->hdisplay; 594 dc->dc_height = mode->vdisplay; 595 dc->dc_depth = depth; 596 dc->dc_stride = dc->dc_width * bytes_per_pixel; 597} 598 599 600static void 601igsfb_calc_pll(int target, int *Mp, int *Np, int *Pp, int maxM, int maxN, 602 int maxP, int minVco) 603{ 604 int M, N, P, bestM = 0, bestN = 0; 605 int f_vco, f_out; 606 int err, besterr; 607 608 /* 609 * Compute correct P value to keep VCO in range 610 */ 611 for (P = 0; P <= maxP; P++) 612 { 613 f_vco = target * IGS_SCALE(P); 614 if (f_vco >= minVco) 615 break; 616 } 617 618 /* M = f_out / f_ref * ((N + 1) * IGS_SCALE(P)); */ 619 besterr = target; 620 for (N = 1; N <= maxN; N++) 621 { 622 M = ((target * (N + 1) * IGS_SCALE(P) + (IGS_CLOCK_REF/2)) + 623 IGS_CLOCK_REF/2) / IGS_CLOCK_REF - 1; 624 if (0 <= M && M <= maxM) 625 { 626 f_out = IGS_CLOCK(M,N,P); 627 err = target - f_out; 628 if (err < 0) 629 err = -err; 630 if (err < besterr) 631 { 632 besterr = err; 633 bestM = M; 634 bestN = N; 635 } 636 } 637 } 638 *Mp = bestM; 639 *Np = bestN; 640 *Pp = P; 641} 642