igpioreg.h revision 1.1
1/* $NetBSD: igpioreg.h,v 1.1 2022/03/24 02:24:25 manu Exp $ */ 2 3/* 4 * Copyright (c) 2021 Emmanuel Dreyfus 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef _IGPIOREG_H 30#define _IGPIOREG_H 31 32#define IGPIO_REVID 0x0000 33#define IGPIO_CAPLIST 0x0004 34#define IGPIO_PADBAR 0x000c 35 36#define IGPIO_PADCFG0 0x0000 37 38#define IGPIO_PADCFG0_RXEVCFG_SHIFT 25 39#define IGPIO_PADCFG0_RXEVCFG_MASK __BITS(26, 25) 40#define IGPIO_PADCFG0_RXEVCFG_LEVEL 0 41#define IGPIO_PADCFG0_RXEVCFG_EDGE 1 42#define IGPIO_PADCFG0_RXEVCFG_DISABLED 2 43#define IGPIO_PADCFG0_RXEVCFG_EDGE_BOTH 3 44#define IGPIO_PADCFG0_PREGFRXSEL __BIT(24) 45#define IGPIO_PADCFG0_RXINV __BIT(23) 46#define IGPIO_PADCFG0_GPIROUTIOXAPIC __BIT(20) 47#define IGPIO_PADCFG0_GPIROUTSCI __BIT(19) 48#define IGPIO_PADCFG0_GPIROUTSMI __BIT(18) 49#define IGPIO_PADCFG0_GPIROUTNMI __BIT(17) 50#define IGPIO_PADCFG0_PMODE_SHIFT 10 51#define IGPIO_PADCFG0_PMODE_MASK __BITS(13, 10) 52#define IGPIO_PADCFG0_PMODE_GPIO 0 53#define IGPIO_PADCFG0_GPIORXDIS __BIT(9) 54#define IGPIO_PADCFG0_GPIOTXDIS __BIT(8) 55#define IGPIO_PADCFG0_GPIORXSTATE __BIT(1) 56#define IGPIO_PADCFG0_GPIOTXSTATE __BIT(0) 57 58#define IGPIO_PADCFG1 0x0004 59#define IGPIO_PADCFG1_TERM_UP __BIT(13) 60#define IGPIO_PADCFG1_TERM_SHIFT 10 61#define IGPIO_PADCFG1_TERM_MASK __BITS(12, 10) 62#define IGPIO_PADCFG1_TERM_20K __BIT(2) 63#define IGPIO_PADCFG1_TERM_5K __BIT(1) 64#define IGPIO_PADCFG1_TERM_1K __BIT(0) 65#define IGPIO_PADCFG1_TERM_833 (__BIT(1) | BIT(0)) 66 67#define IGPIO_CAPLIST_ID_GPIO_HW_INFO 1 68#define IGPIO_CAPLIST_ID_PWM 2 69#define IGPIO_CAPLIST_ID_BLINK 3 70#define IGPIO_CAPLIST_ID_EXP 4 71 72 73#define IGPIO_PINCTRL_FEATURE_DEBOUNCE 0x001 74#define IGPIO_PINCTRL_FEATURE_1K_PD 0x002 75#define IGPIO_PINCTRL_FEATURE_GPIO_HW_INFO 0x004 76#define IGPIO_PINCTRL_FEATURE_PWM 0x010 77#define IGPIO_PINCTRL_FEATURE_BLINK 0x020 78#define IGPIO_PINCTRL_FEATURE_EXP 0x040 79 80struct igpio_bank_setup { 81 const char *ibs_acpi_hid; 82 int ibs_barno; 83 int ibs_first_pin; 84 int ibs_last_pin; 85 int ibs_gpi_is; 86 int ibs_gpi_ie; 87}; 88 89struct igpio_pin_group { 90 const char *ipg_acpi_hid; 91 int ipg_groupno; 92 int ipg_first_pin; 93 const char *ipg_name; 94}; 95 96struct igpio_bank_setup igpio_bank_setup[] = { 97 /* Sunrisepoint-LP */ 98 { "INT344B", 0, 0, 47, 0x100, 0x120 }, 99 { "INT344B", 1, 48, 119, 0x100, 0x120 }, 100 { "INT344B", 2, 120, 151, 0x100, 0x120 }, 101 102 /* Sunrisepoint-H */ 103 { "INT3451", 0, 0, 47, 0x100, 0x120 }, 104 { "INT3451", 1, 48, 180, 0x100, 0x120 }, 105 { "INT3451", 2, 181, 191, 0x100, 0x120 }, 106 107 /* Sunrisepoint-H */ 108 { "INT345D", 0, 0, 47, 0x100, 0x120 }, 109 { "INT345D", 1, 48, 180, 0x100, 0x120 }, 110 { "INT345D", 2, 181, 191, 0x100, 0x120 }, 111 112 /* Baytrail XXX GPI_IS and GPI_IE */ 113 { "INT33B2", 0, 0, 101, 0x000, 0x000 }, 114 { "INT33FC", 0, 0, 101, 0x000, 0x000 }, 115 116 /* Lynxpoint XXX GPI_IS and GPI_IE */ 117 { "INT33C7", 0, 0, 94, 0x000, 0x000 }, 118 { "INT3437", 0, 0, 94, 0x000, 0x000 }, 119 120 /* Cannonlake-H */ 121 { "INT3450", 0, 0, 50, 0x100, 0x120 }, 122 { "INT3450", 1, 51, 154, 0x100, 0x120 }, 123 { "INT3450", 2, 155, 248, 0x100, 0x120 }, 124 { "INT3450", 3, 249, 298, 0x100, 0x120 }, 125 126 /* Cannonlake-LP */ 127 { "INT34BB", 0, 0, 67, 0x100, 0x120 }, 128 { "INT34BB", 1, 68, 180, 0x100, 0x120 }, 129 { "INT34BB", 2, 181, 243, 0x100, 0x120 }, 130 131 /* Alderlake */ 132 { "INTC1056", 0, 0, 94, 0x200, 0x220 }, 133 { "INTC1056", 1, 95, 150, 0x200, 0x220 }, 134 { "INTC1056", 2, 151, 199, 0x200, 0x220 }, 135 { "INTC1056", 3, 200, 269, 0x200, 0x220 }, 136 { "INTC1056", 4, 270, 303, 0x200, 0x220 }, 137 138 /* Icelake */ 139 { "INT3455", 0, 0, 58, 0x100, 0x110 }, 140 { "INT3455", 1, 59, 152, 0x100, 0x110 }, 141 { "INT3455", 2, 153, 215, 0x100, 0x110 }, 142 { "INT3455", 3, 216, 240, 0x100, 0x110 }, 143 144 /* Lakefield */ 145 { "INT34C4", 0, 0, 59, 0x100, 0x110 }, 146 { "INT34C4", 1, 60, 148, 0x100, 0x110 }, 147 { "INT34C4", 2, 149, 237, 0x100, 0x110 }, 148 { "INT34C4", 3, 238, 266, 0x100, 0x110 }, 149 150 /* Tigerlake-LP */ 151 { "INT34C5", 0, 0, 66, 0x100, 0x120 }, 152 { "INT34C5", 1, 67, 170, 0x100, 0x120 }, 153 { "INT34C5", 2, 171, 259, 0x100, 0x120 }, 154 { "INT34C5", 3, 260, 276, 0x100, 0x120 }, 155 156 /* Tigerlake-LP */ 157 { "INTC1055", 0, 0, 66, 0x100, 0x120 }, 158 { "INTC1055", 1, 67, 170, 0x100, 0x120 }, 159 { "INTC1055", 2, 171, 259, 0x100, 0x120 }, 160 { "INTC1055", 3, 260, 276, 0x100, 0x120 }, 161 162 /* Tigerlake-LP */ 163 { "INTC1057", 0, 0, 66, 0x100, 0x120 }, 164 { "INTC1057", 1, 67, 170, 0x100, 0x120 }, 165 { "INTC1057", 2, 171, 259, 0x100, 0x120 }, 166 { "INTC1057", 3, 260, 276, 0x100, 0x120 }, 167 168 /* Tigerlake-H */ 169 { "INT34C6", 0, 0, 78, 0x100, 0x120 }, 170 { "INT34C6", 1, 79, 180, 0x100, 0x120 }, 171 { "INT34C6", 2, 181, 217, 0x100, 0x120 }, 172 { "INT34C6", 3, 218, 266, 0x100, 0x120 }, 173 { "INT34C6", 4, 267, 290, 0x100, 0x120 }, 174 175 /* Jasperlake */ 176 { "INT34C8", 0, 0, 91, 0x100, 0x120 }, 177 { "INT34C8", 1, 92, 194, 0x100, 0x120 }, 178 { "INT34C8", 2, 195, 224, 0x100, 0x120 }, 179 { "INT34C8", 3, 225, 232, 0x100, 0x120 }, 180 181 /* Lewisburg */ 182 { "INT3536", 0, 0, 7, 0x100, 0x110 }, 183 { "INT3536", 1, 72, 13, 0x100, 0x110 }, 184 { "INT3536", 3, 133, 14, 0x100, 0x110 }, 185 { "INT3536", 4, 144, 17, 0x100, 0x110 }, 186 { "INT3536", 5, 179, 246, 0x100, 0x110 }, 187 188 /* Emmitsburg */ 189 { "INTC1071", 0, 0, 65, 0x200, 0x210 }, 190 { "INTC1071", 1, 66, 111, 0x200, 0x210 }, 191 { "INTC1071", 2, 112, 145, 0x200, 0x210 }, 192 { "INTC1071", 3, 146, 183, 0x200, 0x210 }, 193 { "INTC1071", 4, 184, 261, 0x200, 0x210 }, 194 195 /* Denverton */ 196 { "INTC3000", 0, 0, 40, 0x100, 0x120 }, 197 { "INTC3000", 1, 41, 153, 0x100, 0x120 }, 198 199 /* Cedarfork */ 200 { "INTC3001", 0, 0, 167, 0x200, 0x230 }, 201 { "INTC3001", 1, 168, 236, 0x200, 0x230 }, 202 203 /* Geminilake */ 204 { "INT3453", 0, 0, 34, 0x100, 0x110 }, 205 206#ifdef notyet 207 /* 208 * BAR mappings not obvious, further studying required 209 */ 210 /* Broxton */ 211 { "apollolake-pinctrl", 0, 0, 0, 0x100, 0x110 }, 212 { "broxton-pinctrl", 0, 0, 0, 0x100, 0x110 }, 213 { "INT34D1", 0, 0, 0, 0x100, 0x110 }, 214 { "INT3452", 0, 0, 0, 0x100, 0x110 }, 215 216 /* Cherryview */ 217 { "INT33FF", 0, 0, 0, 0x000, 0x000 }, 218#endif 219 220 { NULL, 0, 0, 0, 0x000, 0x000 }, 221}; 222 223struct igpio_pin_group igpio_pin_group[] = { 224 /* Sunrisepoint-LP */ 225 { "INT344B", 0, 151, "A" }, 226 227 /* Sunrisepoint-H */ 228 { "INT3451", 0, 0, "A" }, 229 { "INT3451", 1, 24, "B" }, 230 { "INT3451", 0, 48, "C" }, 231 { "INT3451", 1, 72, "D" }, 232 { "INT3451", 2, 96, "E" }, 233 { "INT3451", 3, 109, "F" }, 234 { "INT3451", 4, 133, "G" }, 235 { "INT3451", 5, 157, "H" }, 236 { "INT3451", 0, 181, "I" }, 237 238 /* Sunrisepoint-H */ 239 { "INT345D", 0, 0, "A" }, 240 { "INT345D", 1, 24, "B" }, 241 { "INT345D", 0, 48, "C" }, 242 { "INT345D", 1, 72, "D" }, 243 { "INT345D", 2, 96, "E" }, 244 { "INT345D", 3, 109, "F" }, 245 { "INT345D", 4, 133, "G" }, 246 { "INT345D", 5, 157, "H" }, 247 { "INT345D", 0, 181, "I" }, 248 249 250 /* Baytrail */ 251 { "INT33B2", 0, 101, "A" }, 252 253 /* Lynxpoint */ 254 { "INT33C7", 0, 94, "A" }, 255 { "INT3437", 0, 94, "A" }, 256 257 /* Cannonlake-H */ 258 { "INT3450", 0, 0, "GPP_A" }, 259 { "INT3450", 1, 25, "GPP_B" }, 260 { "INT3450", 0, 51, "GPP_C" }, 261 { "INT3450", 1, 75, "GPP_D" }, 262 { "INT3450", 2, 99, "GPP_G" }, 263 { "INT3450", 3, 107, "AZA" }, 264 { "INT3450", 4, 115, "vGPIO_0" }, 265 { "INT3450", 5, 147, "vGPIO_1" }, 266 { "INT3450", 0, 155, "GPP_K" }, 267 { "INT3450", 1, 179, "GPP_H" }, 268 { "INT3450", 2, 203, "GPP_E" }, 269 { "INT3450", 3, 216, "GPP_F" }, 270 { "INT3450", 4, 240, "SPI" }, 271 { "INT3450", 0, 249, "CPU" }, 272 { "INT3450", 1, 260, "JTAG" }, 273 { "INT3450", 2, 269, "GPP_I" }, 274 { "INT3450", 3, 287, "GPP_J" }, 275 276 /* Cannonlake-LP */ 277 { "INT34BB", 0, 0, "GPP_A" }, 278 { "INT34BB", 1, 25, "GPP_B" }, 279 { "INT34BB", 2, 51, "GPP_G" }, 280 { "INT34BB", 3, 59, "SPI" }, 281 { "INT34BB", 0, 68, "GPP_D" }, 282 { "INT34BB", 1, 93, "GPP_F" }, 283 { "INT34BB", 2, 117, "GPP_H" }, 284 { "INT34BB", 3, 141, "vGPIO" }, 285 { "INT34BB", 4, 173, "vGPIO" }, 286 { "INT34BB", 0, 181, "GPP_C" }, 287 { "INT34BB", 1, 205, "GPP_E" }, 288 { "INT34BB", 2, 229, "JTAG" }, 289 { "INT34BB", 3, 238, "HVCMOS" }, 290 291 /* Alderlake */ 292 { "INTC1056", 0, 0, "GPP_I" }, 293 { "INTC1056", 1, 25, "GPP_R" }, 294 { "INTC1056", 2, 48, "GPP_J" }, 295 { "INTC1056", 3, 60, "vGPIO" }, 296 { "INTC1056", 4, 87, "vGPIO_0" }, 297 { "INTC1056", 0, 95, "GPP_B" }, 298 { "INTC1056", 1, 119, "GPP_G" }, 299 { "INTC1056", 2, 127, "GPP_H" }, 300 { "INTC1056", 0, 151, "SPI0" }, 301 { "INTC1056", 1, 160, "GPP_A" }, 302 { "INTC1056", 2, 176, "GPP_C" }, 303 { "INTC1056", 0, 200, "GPP_S" }, 304 { "INTC1056", 1, 208, "GPP_E" }, 305 { "INTC1056", 2, 231, "GPP_K" }, 306 { "INTC1056", 3, 246, "GPP_F" }, 307 { "INTC1056", 0, 270, "GPP_D" }, 308 { "INTC1056", 1, 295, "JTAG" }, 309 310 311 /* Icelake */ 312 { "INT3455", 0, 0, "GPP_G" }, 313 { "INT3455", 1, 8, "GPP_B" }, 314 { "INT3455", 2, 34, "GPP_A" }, 315 { "INT3455", 0, 59, "GPP_H" }, 316 { "INT3455", 1, 83, "GPP_D" }, 317 { "INT3455", 2, 104, "GPP_F" }, 318 { "INT3455", 3, 124, "vGPIO" }, 319 { "INT3455", 0, 153, "GPP_C" }, 320 { "INT3455", 1, 177, "HVCMOS" }, 321 { "INT3455", 2, 183, "GPP_E" }, 322 { "INT3455", 3, 207, "JTAG" }, 323 { "INT3455", 2, 232, "SPI" }, 324 325 326 /* Lakefield */ 327 { "INT34C4", 0, 0, "EAST_0" }, 328 { "INT34C4", 1, 32, "EAST_1" }, 329 { "INT34C4", 0, 60, "NORTHWEST_0" }, 330 { "INT34C4", 1, 92, "NORTHWEST_1" }, 331 { "INT34C4", 2, 124, "NORTHWEST_2" }, 332 { "INT34C4", 0, 149, "WEST_0" }, 333 { "INT34C4", 1, 181, "WEST_1" }, 334 { "INT34C4", 2, 213, "WEST_2" }, 335 { "INT34C4", 0, 238, "SOUTHEAST" }, 336 337 338 /* Tigerlake-LP */ 339 { "INT34C5", 0, 0, "GPP_A" }, 340 { "INT34C5", 1, 25, "GPP_R" }, 341 { "INT34C5", 2, 45, "GPP_B" }, 342 { "INT34C5", 3, 71, "vGPIO_0" }, 343 { "INT34C5", 0, 79, "GPP_D" }, 344 { "INT34C5", 1, 105, "GPP_C" }, 345 { "INT34C5", 2, 129, "GPP_S" }, 346 { "INT34C5", 3, 137, "GPP_G" }, 347 { "INT34C5", 4, 154, "vGPIO" }, 348 { "INT34C5", 0, 181, "GPP_E" }, 349 { "INT34C5", 1, 194, "GPP_F" }, 350 { "INT34C5", 0, 218, "GPP_H" }, 351 { "INT34C5", 1, 242, "GPP_J" }, 352 { "INT34C5", 2, 252, "GPP_K" }, 353 { "INT34C5", 0, 267, "GPP_I" }, 354 { "INT34C5", 1, 282, "JTAG" }, 355 356 357 /* Tigerlake-LP */ 358 { "INTC1055", 0, 0, "GPP_A" }, 359 { "INTC1055", 1, 25, "GPP_R" }, 360 { "INTC1055", 2, 45, "GPP_B" }, 361 { "INTC1055", 3, 71, "vGPIO_0" }, 362 { "INTC1055", 0, 79, "GPP_D" }, 363 { "INTC1055", 1, 105, "GPP_C" }, 364 { "INTC1055", 2, 129, "GPP_S" }, 365 { "INTC1055", 3, 137, "GPP_G" }, 366 { "INTC1055", 4, 154, "vGPIO" }, 367 { "INTC1055", 0, 181, "GPP_E" }, 368 { "INTC1055", 1, 194, "GPP_F" }, 369 { "INTC1055", 0, 218, "GPP_H" }, 370 { "INTC1055", 1, 242, "GPP_J" }, 371 { "INTC1055", 2, 252, "GPP_K" }, 372 { "INTC1055", 0, 267, "GPP_I" }, 373 { "INTC1055", 1, 282, "JTAG" }, 374 375 376 /* Tigerlake-LP */ 377 { "INTC1057", 0, 0, "GPP_A" }, 378 { "INTC1057", 1, 25, "GPP_R" }, 379 { "INTC1057", 2, 45, "GPP_B" }, 380 { "INTC1057", 3, 71, "vGPIO_0" }, 381 { "INTC1057", 0, 79, "GPP_D" }, 382 { "INTC1057", 1, 105, "GPP_C" }, 383 { "INTC1057", 2, 129, "GPP_S" }, 384 { "INTC1057", 3, 137, "GPP_G" }, 385 { "INTC1057", 4, 154, "vGPIO" }, 386 { "INTC1057", 0, 181, "GPP_E" }, 387 { "INTC1057", 1, 194, "GPP_F" }, 388 { "INTC1057", 0, 218, "GPP_H" }, 389 { "INTC1057", 1, 242, "GPP_J" }, 390 { "INTC1057", 2, 252, "GPP_K" }, 391 { "INTC1057", 0, 267, "GPP_I" }, 392 { "INTC1057", 1, 282, "JTAG" }, 393 394 /* Tigerlake-H */ 395 { "INT34C6", 0, 0, "GPP_B" }, 396 { "INT34C6", 1, 26, "GPP_T" }, 397 { "INT34C6", 2, 42, "GPP_A" }, 398 { "INT34C6", 0, 67, "GPP_S" }, 399 { "INT34C6", 1, 75, "GPP_H" }, 400 { "INT34C6", 2, 99, "GPP_D" }, 401 { "INT34C6", 3, 120, "GPP_U" }, 402 { "INT34C6", 4, 144, "vGPIO" }, 403 { "INT34C6", 0, 171, "GPP_C" }, 404 { "INT34C6", 1, 195, "GPP_F" }, 405 { "INT34C6", 2, 220, "HVCMOS" }, 406 { "INT34C6", 3, 226, "GPP_E" }, 407 { "INT34C6", 4, 251, "JTAG" }, 408 { "INT34C6", 0, 260, "GPP_R" }, 409 { "INT34C6", 1, 268, "SPI" }, 410 411 /* Jasperlake */ 412 { "INT34C8", 0, 0, "GPP_F" }, 413 { "INT34C8", 1, 20, "SPI" }, 414 { "INT34C8", 2, 29, "GPP_B" }, 415 { "INT34C8", 3, 55, "GPP_A" }, 416 { "INT34C8", 4, 76, "GPP_S" }, 417 { "INT34C8", 5, 84, "GPP_R" }, 418 { "INT34C8", 0, 92, "GPP_H" }, 419 { "INT34C8", 1, 116, "GPP_D" }, 420 { "INT34C8", 2, 142, "vGPIO" }, 421 { "INT34C8", 3, 171, "GPP_C" }, 422 { "INT34C8", 0, 195, "HVCMOS" }, 423 { "INT34C8", 1, 201, "GPP_E" }, 424 { "INT34C8", 0, 225, "GPP_G" }, 425 426 427 /* Lewisburg */ 428 { "INT3536", 0, 7, "" }, 429 430 /* Emmitsburg */ 431 { "INTC1071", 0, 0, "GPP_A" }, 432 { "INTC1071", 1, 21, "GPP_B" }, 433 { "INTC1071", 2, 45, "SPI" }, 434 { "INTC1071", 0, 66, "GPP_C" }, 435 { "INTC1071", 1, 88, "GPP_D" }, 436 { "INTC1071", 0, 112, "GPP_E" }, 437 { "INTC1071", 1, 136, "JTAG" }, 438 { "INTC1071", 0, 146, "GPP_H" }, 439 { "INTC1071", 1, 166, "GPP_J" }, 440 { "INTC1071", 0, 184, "GPP_I" }, 441 { "INTC1071", 1, 208, "GPP_L" }, 442 { "INTC1071", 2, 226, "GPP_M" }, 443 { "INTC1071", 3, 244, "GPP_N" }, 444 445 /* Denverton */ 446 { "INTC3000", 0, 0, "North" }, 447 { "INTC3000", 1, 32, "North" }, 448 { "INTC3000", 0, 41, "South" }, 449 { "INTC3000", 1, 59, "South" }, 450 { "INTC3000", 2, 91, "South" }, 451 { "INTC3000", 3, 112, "South" }, 452 { "INTC3000", 4, 144, "South" }, 453 454 455 /* Cedarfork */ 456 { "INTC3001", 0, 0, "WEST2" }, 457 { "INTC3001", 1, 24, "WEST3" }, 458 { "INTC3001", 2, 48, "WEST01" }, 459 { "INTC3001", 3, 71, "WEST5" }, 460 { "INTC3001", 4, 91, "WESTC" }, 461 { "INTC3001", 5, 97, "WESTC_DFX" }, 462 { "INTC3001", 6, 102, "WESTA" }, 463 { "INTC3001", 7, 112, "WESTB" }, 464 { "INTC3001", 8, 124, "WESTD" }, 465 { "INTC3001", 9, 144, "WESTD_PECI" }, 466 { "INTC3001", 10, 145, "WESTF" }, 467 { "INTC3001", 0, 168, "EAST2" }, 468 { "INTC3001", 1, 192, "EAST3" }, 469 { "INTC3001", 2, 203, "EAST0" }, 470 { "INTC3001", 3, 226, "EMMC" }, 471 472 /* Geminilake */ 473 { "INT3453", 0, 34, "" }, 474 475#ifdef notyet 476 /* 477 * BAR mappings not obvious, further studying required 478 */ 479 /* Broxton */ 480 { "apollolake-pinctrl", 0, 0, "" }, 481 { "broxton-pinctrl", 0, 0, "" }, 482 { "INT34D1", 0, 0, "" }, 483 { "INT3452", 0, 0, "" }, 484 485 /* Cherryview */ 486 { "INT33FF", 0, 0, "" }, 487#endif 488 489 { NULL, 0, 0, 0 }, 490}; 491 492#endif /* _IGPIOREG_H */ 493 494