i82557.c revision 1.79
1/* $NetBSD: i82557.c,v 1.79 2004/02/09 22:29:26 hpeyerl Exp $ */ 2 3/*- 4 * Copyright (c) 1997, 1998, 1999, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40/* 41 * Copyright (c) 1995, David Greenman 42 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice unmodified, this list of conditions, and the following 50 * disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 68 */ 69 70/* 71 * Device driver for the Intel i82557 fast Ethernet controller, 72 * and its successors, the i82558 and i82559. 73 */ 74 75#include <sys/cdefs.h> 76__KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.79 2004/02/09 22:29:26 hpeyerl Exp $"); 77 78#include "bpfilter.h" 79#include "rnd.h" 80 81#include <sys/param.h> 82#include <sys/systm.h> 83#include <sys/callout.h> 84#include <sys/mbuf.h> 85#include <sys/malloc.h> 86#include <sys/kernel.h> 87#include <sys/socket.h> 88#include <sys/ioctl.h> 89#include <sys/errno.h> 90#include <sys/device.h> 91 92#include <machine/endian.h> 93 94#include <uvm/uvm_extern.h> 95 96#if NRND > 0 97#include <sys/rnd.h> 98#endif 99 100#include <net/if.h> 101#include <net/if_dl.h> 102#include <net/if_media.h> 103#include <net/if_ether.h> 104 105#if NBPFILTER > 0 106#include <net/bpf.h> 107#endif 108 109#include <machine/bus.h> 110#include <machine/intr.h> 111 112#include <dev/mii/miivar.h> 113 114#include <dev/ic/i82557reg.h> 115#include <dev/ic/i82557var.h> 116 117#include <dev/microcode/i8255x/rcvbundl.h> 118 119/* 120 * NOTE! On the Alpha, we have an alignment constraint. The 121 * card DMAs the packet immediately following the RFA. However, 122 * the first thing in the packet is a 14-byte Ethernet header. 123 * This means that the packet is misaligned. To compensate, 124 * we actually offset the RFA 2 bytes into the cluster. This 125 * alignes the packet after the Ethernet header at a 32-bit 126 * boundary. HOWEVER! This means that the RFA is misaligned! 127 */ 128#define RFA_ALIGNMENT_FUDGE 2 129 130/* 131 * The configuration byte map has several undefined fields which 132 * must be one or must be zero. Set up a template for these bits 133 * only (assuming an i82557 chip), leaving the actual configuration 134 * for fxp_init(). 135 * 136 * See the definition of struct fxp_cb_config for the bit definitions. 137 */ 138const u_int8_t fxp_cb_config_template[] = { 139 0x0, 0x0, /* cb_status */ 140 0x0, 0x0, /* cb_command */ 141 0x0, 0x0, 0x0, 0x0, /* link_addr */ 142 0x0, /* 0 */ 143 0x0, /* 1 */ 144 0x0, /* 2 */ 145 0x0, /* 3 */ 146 0x0, /* 4 */ 147 0x0, /* 5 */ 148 0x32, /* 6 */ 149 0x0, /* 7 */ 150 0x0, /* 8 */ 151 0x0, /* 9 */ 152 0x6, /* 10 */ 153 0x0, /* 11 */ 154 0x0, /* 12 */ 155 0x0, /* 13 */ 156 0xf2, /* 14 */ 157 0x48, /* 15 */ 158 0x0, /* 16 */ 159 0x40, /* 17 */ 160 0xf0, /* 18 */ 161 0x0, /* 19 */ 162 0x3f, /* 20 */ 163 0x5, /* 21 */ 164 0x0, /* 22 */ 165 0x0, /* 23 */ 166 0x0, /* 24 */ 167 0x0, /* 25 */ 168 0x0, /* 26 */ 169 0x0, /* 27 */ 170 0x0, /* 28 */ 171 0x0, /* 29 */ 172 0x0, /* 30 */ 173 0x0, /* 31 */ 174}; 175 176void fxp_mii_initmedia(struct fxp_softc *); 177int fxp_mii_mediachange(struct ifnet *); 178void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 179 180void fxp_80c24_initmedia(struct fxp_softc *); 181int fxp_80c24_mediachange(struct ifnet *); 182void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 183 184void fxp_start(struct ifnet *); 185int fxp_ioctl(struct ifnet *, u_long, caddr_t); 186void fxp_watchdog(struct ifnet *); 187int fxp_init(struct ifnet *); 188void fxp_stop(struct ifnet *, int); 189 190void fxp_txintr(struct fxp_softc *); 191void fxp_rxintr(struct fxp_softc *); 192 193void fxp_rx_hwcksum(struct mbuf *, const struct fxp_rfa *); 194 195void fxp_rxdrain(struct fxp_softc *); 196int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 197int fxp_mdi_read(struct device *, int, int); 198void fxp_statchg(struct device *); 199void fxp_mdi_write(struct device *, int, int, int); 200void fxp_autosize_eeprom(struct fxp_softc*); 201void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 202void fxp_write_eeprom(struct fxp_softc *, u_int16_t *, int, int); 203void fxp_eeprom_update_cksum(struct fxp_softc *); 204void fxp_get_info(struct fxp_softc *, u_int8_t *); 205void fxp_tick(void *); 206void fxp_mc_setup(struct fxp_softc *); 207void fxp_load_ucode(struct fxp_softc *); 208 209void fxp_shutdown(void *); 210void fxp_power(int, void *); 211 212int fxp_copy_small = 0; 213 214/* 215 * Variables for interrupt mitigating microcode. 216 */ 217int fxp_int_delay = 1000; /* usec */ 218int fxp_bundle_max = 6; /* packets */ 219 220struct fxp_phytype { 221 int fp_phy; /* type of PHY, -1 for MII at the end. */ 222 void (*fp_init)(struct fxp_softc *); 223} fxp_phytype_table[] = { 224 { FXP_PHY_80C24, fxp_80c24_initmedia }, 225 { -1, fxp_mii_initmedia }, 226}; 227 228/* 229 * Set initial transmit threshold at 64 (512 bytes). This is 230 * increased by 64 (512 bytes) at a time, to maximum of 192 231 * (1536 bytes), if an underrun occurs. 232 */ 233static int tx_threshold = 64; 234 235/* 236 * Wait for the previous command to be accepted (but not necessarily 237 * completed). 238 */ 239static __inline void 240fxp_scb_wait(struct fxp_softc *sc) 241{ 242 int i = 10000; 243 244 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 245 delay(2); 246 if (i == 0) 247 printf("%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 248} 249 250/* 251 * Submit a command to the i82557. 252 */ 253static __inline void 254fxp_scb_cmd(struct fxp_softc *sc, u_int8_t cmd) 255{ 256 257 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 258} 259 260/* 261 * Finish attaching an i82557 interface. Called by bus-specific front-end. 262 */ 263void 264fxp_attach(struct fxp_softc *sc) 265{ 266 u_int8_t enaddr[ETHER_ADDR_LEN]; 267 struct ifnet *ifp; 268 bus_dma_segment_t seg; 269 int rseg, i, error; 270 struct fxp_phytype *fp; 271 272 callout_init(&sc->sc_callout); 273 274 /* 275 * Enable some good stuff on i82558 and later. 276 */ 277 if (sc->sc_rev >= FXP_REV_82558_A4) { 278 /* Enable the extended TxCB. */ 279 sc->sc_flags |= FXPF_EXT_TXCB; 280 } 281 282 /* 283 * Enable use of extended RFDs and TCBs for 82550 284 * and later chips. Note: we need extended TXCB support 285 * too, but that's already enabled by the code above. 286 * Be careful to do this only on the right devices. 287 */ 288 if (sc->sc_rev == FXP_REV_82550 || sc->sc_rev == FXP_REV_82550_C) { 289 sc->sc_flags |= FXPF_EXT_RFA | FXPF_IPCB; 290 sc->sc_txcmd = htole16(FXP_CB_COMMAND_IPCBXMIT); 291 } else { 292 sc->sc_txcmd = htole16(FXP_CB_COMMAND_XMIT); 293 } 294 295 sc->sc_rfa_size = 296 (sc->sc_flags & FXPF_EXT_RFA) ? RFA_EXT_SIZE : RFA_SIZE; 297 298 /* 299 * Allocate the control data structures, and create and load the 300 * DMA map for it. 301 */ 302 if ((error = bus_dmamem_alloc(sc->sc_dmat, 303 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 304 0)) != 0) { 305 aprint_error( 306 "%s: unable to allocate control data, error = %d\n", 307 sc->sc_dev.dv_xname, error); 308 goto fail_0; 309 } 310 311 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 312 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 313 BUS_DMA_COHERENT)) != 0) { 314 aprint_error("%s: unable to map control data, error = %d\n", 315 sc->sc_dev.dv_xname, error); 316 goto fail_1; 317 } 318 sc->sc_cdseg = seg; 319 sc->sc_cdnseg = rseg; 320 321 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 322 323 if ((error = bus_dmamap_create(sc->sc_dmat, 324 sizeof(struct fxp_control_data), 1, 325 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 326 aprint_error("%s: unable to create control data DMA map, " 327 "error = %d\n", sc->sc_dev.dv_xname, error); 328 goto fail_2; 329 } 330 331 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 332 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 333 0)) != 0) { 334 aprint_error( 335 "%s: can't load control data DMA map, error = %d\n", 336 sc->sc_dev.dv_xname, error); 337 goto fail_3; 338 } 339 340 /* 341 * Create the transmit buffer DMA maps. 342 */ 343 for (i = 0; i < FXP_NTXCB; i++) { 344 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 345 (sc->sc_flags & FXPF_IPCB) ? FXP_IPCB_NTXSEG : FXP_NTXSEG, 346 MCLBYTES, 0, 0, &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 347 aprint_error("%s: unable to create tx DMA map %d, " 348 "error = %d\n", sc->sc_dev.dv_xname, i, error); 349 goto fail_4; 350 } 351 } 352 353 /* 354 * Create the receive buffer DMA maps. 355 */ 356 for (i = 0; i < FXP_NRFABUFS; i++) { 357 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 358 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 359 aprint_error("%s: unable to create rx DMA map %d, " 360 "error = %d\n", sc->sc_dev.dv_xname, i, error); 361 goto fail_5; 362 } 363 } 364 365 /* Initialize MAC address and media structures. */ 366 fxp_get_info(sc, enaddr); 367 368 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 369 ether_sprintf(enaddr)); 370 371 ifp = &sc->sc_ethercom.ec_if; 372 373 /* 374 * Get info about our media interface, and initialize it. Note 375 * the table terminates itself with a phy of -1, indicating 376 * that we're using MII. 377 */ 378 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 379 if (fp->fp_phy == sc->phy_primary_device) 380 break; 381 (*fp->fp_init)(sc); 382 383 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 384 ifp->if_softc = sc; 385 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 386 ifp->if_ioctl = fxp_ioctl; 387 ifp->if_start = fxp_start; 388 ifp->if_watchdog = fxp_watchdog; 389 ifp->if_init = fxp_init; 390 ifp->if_stop = fxp_stop; 391 IFQ_SET_READY(&ifp->if_snd); 392 393 if (sc->sc_flags & FXPF_IPCB) { 394 KASSERT(sc->sc_flags & FXPF_EXT_RFA); /* we have both or none */ 395 /* 396 * IFCAP_CSUM_IPv4 seems to have a problem, 397 * at least, on i82550 rev.12. 398 * specifically, it doesn't calculate ipv4 checksum correctly 399 * when sending 20 byte ipv4 header + 1 or 2 byte data. 400 * FreeBSD driver has related comments. 401 * 402 * XXX we should have separate IFCAP flags 403 * for transmit and receive. 404 */ 405 ifp->if_capabilities = 406 /*IFCAP_CSUM_IPv4 |*/ IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 407 } 408 409 /* 410 * We can support 802.1Q VLAN-sized frames. 411 */ 412 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 413 414 /* 415 * Attach the interface. 416 */ 417 if_attach(ifp); 418 ether_ifattach(ifp, enaddr); 419#if NRND > 0 420 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 421 RND_TYPE_NET, 0); 422#endif 423 424#ifdef FXP_EVENT_COUNTERS 425 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 426 NULL, sc->sc_dev.dv_xname, "txstall"); 427 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 428 NULL, sc->sc_dev.dv_xname, "txintr"); 429 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 430 NULL, sc->sc_dev.dv_xname, "rxintr"); 431#endif /* FXP_EVENT_COUNTERS */ 432 433 /* 434 * Add shutdown hook so that DMA is disabled prior to reboot. Not 435 * doing do could allow DMA to corrupt kernel memory during the 436 * reboot before the driver initializes. 437 */ 438 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 439 if (sc->sc_sdhook == NULL) 440 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 441 sc->sc_dev.dv_xname); 442 /* 443 * Add suspend hook, for similar reasons.. 444 */ 445 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 446 if (sc->sc_powerhook == NULL) 447 aprint_error("%s: WARNING: unable to establish power hook\n", 448 sc->sc_dev.dv_xname); 449 450 /* The attach is successful. */ 451 sc->sc_flags |= FXPF_ATTACHED; 452 453 return; 454 455 /* 456 * Free any resources we've allocated during the failed attach 457 * attempt. Do this in reverse order and fall though. 458 */ 459 fail_5: 460 for (i = 0; i < FXP_NRFABUFS; i++) { 461 if (sc->sc_rxmaps[i] != NULL) 462 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 463 } 464 fail_4: 465 for (i = 0; i < FXP_NTXCB; i++) { 466 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 467 bus_dmamap_destroy(sc->sc_dmat, 468 FXP_DSTX(sc, i)->txs_dmamap); 469 } 470 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 471 fail_3: 472 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 473 fail_2: 474 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 475 sizeof(struct fxp_control_data)); 476 fail_1: 477 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 478 fail_0: 479 return; 480} 481 482void 483fxp_mii_initmedia(struct fxp_softc *sc) 484{ 485 int flags; 486 487 sc->sc_flags |= FXPF_MII; 488 489 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 490 sc->sc_mii.mii_readreg = fxp_mdi_read; 491 sc->sc_mii.mii_writereg = fxp_mdi_write; 492 sc->sc_mii.mii_statchg = fxp_statchg; 493 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, fxp_mii_mediachange, 494 fxp_mii_mediastatus); 495 496 flags = MIIF_NOISOLATE; 497 if (sc->sc_rev >= FXP_REV_82558_A4) 498 flags |= MIIF_DOPAUSE; 499 /* 500 * The i82557 wedges if all of its PHYs are isolated! 501 */ 502 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 503 MII_OFFSET_ANY, flags); 504 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 505 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 506 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 507 } else 508 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 509} 510 511void 512fxp_80c24_initmedia(struct fxp_softc *sc) 513{ 514 515 /* 516 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 517 * doesn't have a programming interface of any sort. The 518 * media is sensed automatically based on how the link partner 519 * is configured. This is, in essence, manual configuration. 520 */ 521 aprint_normal("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 522 sc->sc_dev.dv_xname); 523 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 524 fxp_80c24_mediastatus); 525 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 526 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 527} 528 529/* 530 * Device shutdown routine. Called at system shutdown after sync. The 531 * main purpose of this routine is to shut off receiver DMA so that 532 * kernel memory doesn't get clobbered during warmboot. 533 */ 534void 535fxp_shutdown(void *arg) 536{ 537 struct fxp_softc *sc = arg; 538 539 /* 540 * Since the system's going to halt shortly, don't bother 541 * freeing mbufs. 542 */ 543 fxp_stop(&sc->sc_ethercom.ec_if, 0); 544} 545/* 546 * Power handler routine. Called when the system is transitioning 547 * into/out of power save modes. As with fxp_shutdown, the main 548 * purpose of this routine is to shut off receiver DMA so it doesn't 549 * clobber kernel memory at the wrong time. 550 */ 551void 552fxp_power(int why, void *arg) 553{ 554 struct fxp_softc *sc = arg; 555 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 556 int s; 557 558 s = splnet(); 559 switch (why) { 560 case PWR_SUSPEND: 561 case PWR_STANDBY: 562 fxp_stop(ifp, 0); 563 break; 564 case PWR_RESUME: 565 if (ifp->if_flags & IFF_UP) 566 fxp_init(ifp); 567 break; 568 case PWR_SOFTSUSPEND: 569 case PWR_SOFTSTANDBY: 570 case PWR_SOFTRESUME: 571 break; 572 } 573 splx(s); 574} 575 576/* 577 * Initialize the interface media. 578 */ 579void 580fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 581{ 582 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 583 584 /* 585 * Reset to a stable state. 586 */ 587 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 588 DELAY(100); 589 590 sc->sc_eeprom_size = 0; 591 fxp_autosize_eeprom(sc); 592 if (sc->sc_eeprom_size == 0) { 593 aprint_error("%s: failed to detect EEPROM size\n", 594 sc->sc_dev.dv_xname); 595 sc->sc_eeprom_size = 6; /* XXX panic here? */ 596 } 597#ifdef DEBUG 598 aprint_debug("%s: detected %d word EEPROM\n", 599 sc->sc_dev.dv_xname, 1 << sc->sc_eeprom_size); 600#endif 601 602 /* 603 * Get info about the primary PHY 604 */ 605 fxp_read_eeprom(sc, &data, 6, 1); 606 sc->phy_primary_device = 607 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 608 609 /* 610 * Read MAC address. 611 */ 612 fxp_read_eeprom(sc, myea, 0, 3); 613 enaddr[0] = myea[0] & 0xff; 614 enaddr[1] = myea[0] >> 8; 615 enaddr[2] = myea[1] & 0xff; 616 enaddr[3] = myea[1] >> 8; 617 enaddr[4] = myea[2] & 0xff; 618 enaddr[5] = myea[2] >> 8; 619 620 /* 621 * Systems based on the ICH2/ICH2-M chip from Intel, as well 622 * as some i82559 designs, have a defect where the chip can 623 * cause a PCI protocol violation if it receives a CU_RESUME 624 * command when it is entering the IDLE state. 625 * 626 * The work-around is to disable Dynamic Standby Mode, so that 627 * the chip never deasserts #CLKRUN, and always remains in the 628 * active state. 629 * 630 * Unfortunately, the only way to disable Dynamic Standby is 631 * to frob an EEPROM setting and reboot (the EEPROM setting 632 * is only consulted when the PCI bus comes out of reset). 633 * 634 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 635 */ 636 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 637 fxp_read_eeprom(sc, &data, 10, 1); 638 if (data & 0x02) { /* STB enable */ 639 aprint_error("%s: WARNING: " 640 "Disabling dynamic standby mode in EEPROM " 641 "to work around a\n", 642 sc->sc_dev.dv_xname); 643 aprint_normal( 644 "%s: WARNING: hardware bug. You must reset " 645 "the system before using this\n", 646 sc->sc_dev.dv_xname); 647 aprint_normal("%s: WARNING: interface.\n", 648 sc->sc_dev.dv_xname); 649 data &= ~0x02; 650 fxp_write_eeprom(sc, &data, 10, 1); 651 aprint_normal("%s: new EEPROM ID: 0x%04x\n", 652 sc->sc_dev.dv_xname, data); 653 fxp_eeprom_update_cksum(sc); 654 } 655 } 656} 657 658static void 659fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 660{ 661 uint16_t reg; 662 int x; 663 664 for (x = 1 << (len - 1); x != 0; x >>= 1) { 665 DELAY(40); 666 if (data & x) 667 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 668 else 669 reg = FXP_EEPROM_EECS; 670 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 671 DELAY(40); 672 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 673 reg | FXP_EEPROM_EESK); 674 DELAY(40); 675 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 676 } 677 DELAY(40); 678} 679 680/* 681 * Figure out EEPROM size. 682 * 683 * 559's can have either 64-word or 256-word EEPROMs, the 558 684 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 685 * talks about the existence of 16 to 256 word EEPROMs. 686 * 687 * The only known sizes are 64 and 256, where the 256 version is used 688 * by CardBus cards to store CIS information. 689 * 690 * The address is shifted in msb-to-lsb, and after the last 691 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 692 * after which follows the actual data. We try to detect this zero, by 693 * probing the data-out bit in the EEPROM control register just after 694 * having shifted in a bit. If the bit is zero, we assume we've 695 * shifted enough address bits. The data-out should be tri-state, 696 * before this, which should translate to a logical one. 697 * 698 * Other ways to do this would be to try to read a register with known 699 * contents with a varying number of address bits, but no such 700 * register seem to be available. The high bits of register 10 are 01 701 * on the 558 and 559, but apparently not on the 557. 702 * 703 * The Linux driver computes a checksum on the EEPROM data, but the 704 * value of this checksum is not very well documented. 705 */ 706 707void 708fxp_autosize_eeprom(struct fxp_softc *sc) 709{ 710 int x; 711 712 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 713 DELAY(40); 714 715 /* Shift in read opcode. */ 716 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 717 718 /* 719 * Shift in address, wait for the dummy zero following a correct 720 * address shift. 721 */ 722 for (x = 1; x <= 8; x++) { 723 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 724 DELAY(40); 725 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 726 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 727 DELAY(40); 728 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 729 FXP_EEPROM_EEDO) == 0) 730 break; 731 DELAY(40); 732 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 733 DELAY(40); 734 } 735 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 736 DELAY(40); 737 if (x != 6 && x != 8) { 738#ifdef DEBUG 739 printf("%s: strange EEPROM size (%d)\n", 740 sc->sc_dev.dv_xname, 1 << x); 741#endif 742 } else 743 sc->sc_eeprom_size = x; 744} 745 746/* 747 * Read from the serial EEPROM. Basically, you manually shift in 748 * the read opcode (one bit at a time) and then shift in the address, 749 * and then you shift out the data (all of this one bit at a time). 750 * The word size is 16 bits, so you have to provide the address for 751 * every 16 bits of data. 752 */ 753void 754fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 755{ 756 u_int16_t reg; 757 int i, x; 758 759 for (i = 0; i < words; i++) { 760 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 761 762 /* Shift in read opcode. */ 763 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 764 765 /* Shift in address. */ 766 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 767 768 reg = FXP_EEPROM_EECS; 769 data[i] = 0; 770 771 /* Shift out data. */ 772 for (x = 16; x > 0; x--) { 773 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 774 reg | FXP_EEPROM_EESK); 775 DELAY(40); 776 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 777 FXP_EEPROM_EEDO) 778 data[i] |= (1 << (x - 1)); 779 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 780 DELAY(40); 781 } 782 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 783 DELAY(40); 784 } 785} 786 787/* 788 * Write data to the serial EEPROM. 789 */ 790void 791fxp_write_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 792{ 793 int i, j; 794 795 for (i = 0; i < words; i++) { 796 /* Erase/write enable. */ 797 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 798 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 799 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 800 sc->sc_eeprom_size); 801 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 802 DELAY(4); 803 804 /* Shift in write opcode, address, data. */ 805 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 806 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 807 fxp_eeprom_shiftin(sc, offset, sc->sc_eeprom_size); 808 fxp_eeprom_shiftin(sc, data[i], 16); 809 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 810 DELAY(4); 811 812 /* Wait for the EEPROM to finish up. */ 813 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 814 DELAY(4); 815 for (j = 0; j < 1000; j++) { 816 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 817 FXP_EEPROM_EEDO) 818 break; 819 DELAY(50); 820 } 821 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 822 DELAY(4); 823 824 /* Erase/write disable. */ 825 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 826 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 827 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 828 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 829 DELAY(4); 830 } 831} 832 833/* 834 * Update the checksum of the EEPROM. 835 */ 836void 837fxp_eeprom_update_cksum(struct fxp_softc *sc) 838{ 839 int i; 840 uint16_t data, cksum; 841 842 cksum = 0; 843 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 844 fxp_read_eeprom(sc, &data, i, 1); 845 cksum += data; 846 } 847 i = (1 << sc->sc_eeprom_size) - 1; 848 cksum = 0xbaba - cksum; 849 fxp_read_eeprom(sc, &data, i, 1); 850 fxp_write_eeprom(sc, &cksum, i, 1); 851 printf("%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 852 sc->sc_dev.dv_xname, i, data, cksum); 853} 854 855/* 856 * Start packet transmission on the interface. 857 */ 858void 859fxp_start(struct ifnet *ifp) 860{ 861 struct fxp_softc *sc = ifp->if_softc; 862 struct mbuf *m0, *m; 863 struct fxp_txdesc *txd; 864 struct fxp_txsoft *txs; 865 bus_dmamap_t dmamap; 866 int error, lasttx, nexttx, opending, seg; 867 868 /* 869 * If we want a re-init, bail out now. 870 */ 871 if (sc->sc_flags & FXPF_WANTINIT) { 872 ifp->if_flags |= IFF_OACTIVE; 873 return; 874 } 875 876 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 877 return; 878 879 /* 880 * Remember the previous txpending and the current lasttx. 881 */ 882 opending = sc->sc_txpending; 883 lasttx = sc->sc_txlast; 884 885 /* 886 * Loop through the send queue, setting up transmit descriptors 887 * until we drain the queue, or use up all available transmit 888 * descriptors. 889 */ 890 for (;;) { 891 struct fxp_tbd *tbdp; 892 int csum_flags; 893 894 /* 895 * Grab a packet off the queue. 896 */ 897 IFQ_POLL(&ifp->if_snd, m0); 898 if (m0 == NULL) 899 break; 900 m = NULL; 901 902 if (sc->sc_txpending == FXP_NTXCB) { 903 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 904 break; 905 } 906 907 /* 908 * Get the next available transmit descriptor. 909 */ 910 nexttx = FXP_NEXTTX(sc->sc_txlast); 911 txd = FXP_CDTX(sc, nexttx); 912 txs = FXP_DSTX(sc, nexttx); 913 dmamap = txs->txs_dmamap; 914 915 /* 916 * Load the DMA map. If this fails, the packet either 917 * didn't fit in the allotted number of frags, or we were 918 * short on resources. In this case, we'll copy and try 919 * again. 920 */ 921 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 922 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 923 MGETHDR(m, M_DONTWAIT, MT_DATA); 924 if (m == NULL) { 925 printf("%s: unable to allocate Tx mbuf\n", 926 sc->sc_dev.dv_xname); 927 break; 928 } 929 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 930 if (m0->m_pkthdr.len > MHLEN) { 931 MCLGET(m, M_DONTWAIT); 932 if ((m->m_flags & M_EXT) == 0) { 933 printf("%s: unable to allocate Tx " 934 "cluster\n", sc->sc_dev.dv_xname); 935 m_freem(m); 936 break; 937 } 938 } 939 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 940 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 941 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 942 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 943 if (error) { 944 printf("%s: unable to load Tx buffer, " 945 "error = %d\n", sc->sc_dev.dv_xname, error); 946 break; 947 } 948 } 949 950 IFQ_DEQUEUE(&ifp->if_snd, m0); 951 csum_flags = m0->m_pkthdr.csum_flags; 952 if (m != NULL) { 953 m_freem(m0); 954 m0 = m; 955 } 956 957 /* Initialize the fraglist. */ 958 tbdp = txd->txd_tbd; 959 if (sc->sc_flags & FXPF_IPCB) 960 tbdp++; 961 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 962 tbdp[seg].tb_addr = 963 htole32(dmamap->dm_segs[seg].ds_addr); 964 tbdp[seg].tb_size = 965 htole32(dmamap->dm_segs[seg].ds_len); 966 } 967 968 /* Sync the DMA map. */ 969 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 970 BUS_DMASYNC_PREWRITE); 971 972 /* 973 * Store a pointer to the packet so we can free it later. 974 */ 975 txs->txs_mbuf = m0; 976 977 /* 978 * Initialize the transmit descriptor. 979 */ 980 /* BIG_ENDIAN: no need to swap to store 0 */ 981 txd->txd_txcb.cb_status = 0; 982 txd->txd_txcb.cb_command = 983 sc->sc_txcmd | htole16(FXP_CB_COMMAND_SF); 984 txd->txd_txcb.tx_threshold = tx_threshold; 985 txd->txd_txcb.tbd_number = dmamap->dm_nsegs; 986 987 KASSERT((csum_flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) == 0); 988 if (sc->sc_flags & FXPF_IPCB) { 989 struct fxp_ipcb *ipcb; 990 /* 991 * Deal with TCP/IP checksum offload. Note that 992 * in order for TCP checksum offload to work, 993 * the pseudo header checksum must have already 994 * been computed and stored in the checksum field 995 * in the TCP header. The stack should have 996 * already done this for us. 997 */ 998 ipcb = &txd->txd_u.txdu_ipcb; 999 memset(ipcb, 0, sizeof(*ipcb)); 1000 /* 1001 * always do hardware parsing. 1002 */ 1003 ipcb->ipcb_ip_activation_high = 1004 FXP_IPCB_HARDWAREPARSING_ENABLE; 1005 /* 1006 * ip checksum offloading. 1007 */ 1008 if (csum_flags & M_CSUM_IPv4) { 1009 ipcb->ipcb_ip_schedule |= 1010 FXP_IPCB_IP_CHECKSUM_ENABLE; 1011 } 1012 /* 1013 * TCP/UDP checksum offloading. 1014 */ 1015 if (csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1016 ipcb->ipcb_ip_schedule |= 1017 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1018 } 1019 } else { 1020 KASSERT((csum_flags & 1021 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) == 0); 1022 } 1023 1024 FXP_CDTXSYNC(sc, nexttx, 1025 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1026 1027 /* Advance the tx pointer. */ 1028 sc->sc_txpending++; 1029 sc->sc_txlast = nexttx; 1030 1031#if NBPFILTER > 0 1032 /* 1033 * Pass packet to bpf if there is a listener. 1034 */ 1035 if (ifp->if_bpf) 1036 bpf_mtap(ifp->if_bpf, m0); 1037#endif 1038 } 1039 1040 if (sc->sc_txpending == FXP_NTXCB) { 1041 /* No more slots; notify upper layer. */ 1042 ifp->if_flags |= IFF_OACTIVE; 1043 } 1044 1045 if (sc->sc_txpending != opending) { 1046 /* 1047 * We enqueued packets. If the transmitter was idle, 1048 * reset the txdirty pointer. 1049 */ 1050 if (opending == 0) 1051 sc->sc_txdirty = FXP_NEXTTX(lasttx); 1052 1053 /* 1054 * Cause the chip to interrupt and suspend command 1055 * processing once the last packet we've enqueued 1056 * has been transmitted. 1057 */ 1058 FXP_CDTX(sc, sc->sc_txlast)->txd_txcb.cb_command |= 1059 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 1060 FXP_CDTXSYNC(sc, sc->sc_txlast, 1061 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1062 1063 /* 1064 * The entire packet chain is set up. Clear the suspend bit 1065 * on the command prior to the first packet we set up. 1066 */ 1067 FXP_CDTXSYNC(sc, lasttx, 1068 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1069 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 1070 htole16(~FXP_CB_COMMAND_S); 1071 FXP_CDTXSYNC(sc, lasttx, 1072 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1073 1074 /* 1075 * Issue a Resume command in case the chip was suspended. 1076 */ 1077 fxp_scb_wait(sc); 1078 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1079 1080 /* Set a watchdog timer in case the chip flakes out. */ 1081 ifp->if_timer = 5; 1082 } 1083} 1084 1085/* 1086 * Process interface interrupts. 1087 */ 1088int 1089fxp_intr(void *arg) 1090{ 1091 struct fxp_softc *sc = arg; 1092 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1093 bus_dmamap_t rxmap; 1094 int claimed = 0; 1095 u_int8_t statack; 1096 1097 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0 || sc->sc_enabled == 0) 1098 return (0); 1099 /* 1100 * If the interface isn't running, don't try to 1101 * service the interrupt.. just ack it and bail. 1102 */ 1103 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1104 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1105 if (statack) { 1106 claimed = 1; 1107 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1108 } 1109 return (claimed); 1110 } 1111 1112 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1113 claimed = 1; 1114 1115 /* 1116 * First ACK all the interrupts in this pass. 1117 */ 1118 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1119 1120 /* 1121 * Process receiver interrupts. If a no-resource (RNR) 1122 * condition exists, get whatever packets we can and 1123 * re-start the receiver. 1124 */ 1125 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 1126 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1127 fxp_rxintr(sc); 1128 } 1129 1130 if (statack & FXP_SCB_STATACK_RNR) { 1131 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1132 fxp_scb_wait(sc); 1133 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1134 rxmap->dm_segs[0].ds_addr + 1135 RFA_ALIGNMENT_FUDGE); 1136 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1137 } 1138 1139 /* 1140 * Free any finished transmit mbuf chains. 1141 */ 1142 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1143 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1144 fxp_txintr(sc); 1145 1146 /* 1147 * Try to get more packets going. 1148 */ 1149 fxp_start(ifp); 1150 1151 if (sc->sc_txpending == 0) { 1152 /* 1153 * If we want a re-init, do that now. 1154 */ 1155 if (sc->sc_flags & FXPF_WANTINIT) 1156 (void) fxp_init(ifp); 1157 } 1158 } 1159 } 1160 1161#if NRND > 0 1162 if (claimed) 1163 rnd_add_uint32(&sc->rnd_source, statack); 1164#endif 1165 return (claimed); 1166} 1167 1168/* 1169 * Handle transmit completion interrupts. 1170 */ 1171void 1172fxp_txintr(struct fxp_softc *sc) 1173{ 1174 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1175 struct fxp_txdesc *txd; 1176 struct fxp_txsoft *txs; 1177 int i; 1178 u_int16_t txstat; 1179 1180 ifp->if_flags &= ~IFF_OACTIVE; 1181 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1182 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1183 txd = FXP_CDTX(sc, i); 1184 txs = FXP_DSTX(sc, i); 1185 1186 FXP_CDTXSYNC(sc, i, 1187 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1188 1189 txstat = le16toh(txd->txd_txcb.cb_status); 1190 1191 if ((txstat & FXP_CB_STATUS_C) == 0) 1192 break; 1193 1194 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1195 0, txs->txs_dmamap->dm_mapsize, 1196 BUS_DMASYNC_POSTWRITE); 1197 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1198 m_freem(txs->txs_mbuf); 1199 txs->txs_mbuf = NULL; 1200 } 1201 1202 /* Update the dirty transmit buffer pointer. */ 1203 sc->sc_txdirty = i; 1204 1205 /* 1206 * Cancel the watchdog timer if there are no pending 1207 * transmissions. 1208 */ 1209 if (sc->sc_txpending == 0) 1210 ifp->if_timer = 0; 1211} 1212 1213void 1214fxp_rx_hwcksum(struct mbuf *m, const struct fxp_rfa *rfa) 1215{ 1216 u_int16_t rxparsestat; 1217 u_int16_t csum_stat; 1218 u_int32_t csum_data; 1219 int csum_flags; 1220 1221 rxparsestat = le16toh(rfa->rx_parse_stat); 1222 csum_stat = le16toh(rfa->cksum_stat); 1223 if (!(rfa->rfa_status & htole16(FXP_RFA_STATUS_PARSE))) 1224 return; 1225 1226 csum_flags = 0; 1227 csum_data = 0; 1228 1229 if (csum_stat & FXP_RFDX_CS_IP_CSUM_BIT_VALID) { 1230 csum_flags = M_CSUM_IPv4; 1231 if (!(csum_stat & FXP_RFDX_CS_IP_CSUM_VALID)) 1232 csum_flags |= M_CSUM_IPv4_BAD; 1233 } 1234 1235 if (csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) { 1236 csum_flags |= (M_CSUM_TCPv4|M_CSUM_UDPv4); /* XXX */ 1237 if (!(csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) 1238 csum_flags |= M_CSUM_TCP_UDP_BAD; 1239 } 1240 1241 m->m_pkthdr.csum_flags = csum_flags; 1242 m->m_pkthdr.csum_data = csum_data; 1243} 1244 1245/* 1246 * Handle receive interrupts. 1247 */ 1248void 1249fxp_rxintr(struct fxp_softc *sc) 1250{ 1251 struct ethercom *ec = &sc->sc_ethercom; 1252 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1253 struct mbuf *m, *m0; 1254 bus_dmamap_t rxmap; 1255 struct fxp_rfa *rfa; 1256 u_int16_t len, rxstat; 1257 1258 for (;;) { 1259 m = sc->sc_rxq.ifq_head; 1260 rfa = FXP_MTORFA(m); 1261 rxmap = M_GETCTX(m, bus_dmamap_t); 1262 1263 FXP_RFASYNC(sc, m, 1264 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1265 1266 rxstat = le16toh(rfa->rfa_status); 1267 1268 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1269 /* 1270 * We have processed all of the 1271 * receive buffers. 1272 */ 1273 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1274 return; 1275 } 1276 1277 IF_DEQUEUE(&sc->sc_rxq, m); 1278 1279 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1280 1281 len = le16toh(rfa->actual_size) & 1282 (m->m_ext.ext_size - 1); 1283 1284 if (len < sizeof(struct ether_header)) { 1285 /* 1286 * Runt packet; drop it now. 1287 */ 1288 FXP_INIT_RFABUF(sc, m); 1289 continue; 1290 } 1291 1292 /* 1293 * If support for 802.1Q VLAN sized frames is 1294 * enabled, we need to do some additional error 1295 * checking (as we are saving bad frames, in 1296 * order to receive the larger ones). 1297 */ 1298 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1299 (rxstat & (FXP_RFA_STATUS_OVERRUN| 1300 FXP_RFA_STATUS_RNR| 1301 FXP_RFA_STATUS_ALIGN| 1302 FXP_RFA_STATUS_CRC)) != 0) { 1303 FXP_INIT_RFABUF(sc, m); 1304 continue; 1305 } 1306 1307 /* Do checksum checking. */ 1308 m->m_pkthdr.csum_flags = 0; 1309 if (sc->sc_flags & FXPF_EXT_RFA) 1310 fxp_rx_hwcksum(m, rfa); 1311 1312 /* 1313 * If the packet is small enough to fit in a 1314 * single header mbuf, allocate one and copy 1315 * the data into it. This greatly reduces 1316 * memory consumption when we receive lots 1317 * of small packets. 1318 * 1319 * Otherwise, we add a new buffer to the receive 1320 * chain. If this fails, we drop the packet and 1321 * recycle the old buffer. 1322 */ 1323 if (fxp_copy_small != 0 && len <= MHLEN) { 1324 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1325 if (m0 == NULL) 1326 goto dropit; 1327 MCLAIM(m0, &sc->sc_ethercom.ec_rx_mowner); 1328 memcpy(mtod(m0, caddr_t), 1329 mtod(m, caddr_t), len); 1330 m0->m_pkthdr.csum_flags = m->m_pkthdr.csum_flags; 1331 m0->m_pkthdr.csum_data = m->m_pkthdr.csum_data; 1332 FXP_INIT_RFABUF(sc, m); 1333 m = m0; 1334 } else { 1335 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1336 dropit: 1337 ifp->if_ierrors++; 1338 FXP_INIT_RFABUF(sc, m); 1339 continue; 1340 } 1341 } 1342 1343 m->m_pkthdr.rcvif = ifp; 1344 m->m_pkthdr.len = m->m_len = len; 1345 1346#if NBPFILTER > 0 1347 /* 1348 * Pass this up to any BPF listeners, but only 1349 * pass it up the stack it its for us. 1350 */ 1351 if (ifp->if_bpf) 1352 bpf_mtap(ifp->if_bpf, m); 1353#endif 1354 1355 /* Pass it on. */ 1356 (*ifp->if_input)(ifp, m); 1357 } 1358} 1359 1360/* 1361 * Update packet in/out/collision statistics. The i82557 doesn't 1362 * allow you to access these counters without doing a fairly 1363 * expensive DMA to get _all_ of the statistics it maintains, so 1364 * we do this operation here only once per second. The statistics 1365 * counters in the kernel are updated from the previous dump-stats 1366 * DMA and then a new dump-stats DMA is started. The on-chip 1367 * counters are zeroed when the DMA completes. If we can't start 1368 * the DMA immediately, we don't wait - we just prepare to read 1369 * them again next time. 1370 */ 1371void 1372fxp_tick(void *arg) 1373{ 1374 struct fxp_softc *sc = arg; 1375 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1376 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1377 int s; 1378 1379 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1380 return; 1381 1382 s = splnet(); 1383 1384 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1385 1386 ifp->if_opackets += le32toh(sp->tx_good); 1387 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1388 if (sp->rx_good) { 1389 ifp->if_ipackets += le32toh(sp->rx_good); 1390 sc->sc_rxidle = 0; 1391 } else { 1392 sc->sc_rxidle++; 1393 } 1394 ifp->if_ierrors += 1395 le32toh(sp->rx_crc_errors) + 1396 le32toh(sp->rx_alignment_errors) + 1397 le32toh(sp->rx_rnr_errors) + 1398 le32toh(sp->rx_overrun_errors); 1399 /* 1400 * If any transmit underruns occurred, bump up the transmit 1401 * threshold by another 512 bytes (64 * 8). 1402 */ 1403 if (sp->tx_underruns) { 1404 ifp->if_oerrors += le32toh(sp->tx_underruns); 1405 if (tx_threshold < 192) 1406 tx_threshold += 64; 1407 } 1408 1409 /* 1410 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1411 * then assume the receiver has locked up and attempt to clear 1412 * the condition by reprogramming the multicast filter (actually, 1413 * resetting the interface). This is a work-around for a bug in 1414 * the 82557 where the receiver locks up if it gets certain types 1415 * of garbage in the synchronization bits prior to the packet header. 1416 * This bug is supposed to only occur in 10Mbps mode, but has been 1417 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1418 * speed transition). 1419 */ 1420 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1421 (void) fxp_init(ifp); 1422 splx(s); 1423 return; 1424 } 1425 /* 1426 * If there is no pending command, start another stats 1427 * dump. Otherwise punt for now. 1428 */ 1429 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1430 /* 1431 * Start another stats dump. 1432 */ 1433 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1434 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1435 } else { 1436 /* 1437 * A previous command is still waiting to be accepted. 1438 * Just zero our copy of the stats and wait for the 1439 * next timer event to update them. 1440 */ 1441 /* BIG_ENDIAN: no swap required to store 0 */ 1442 sp->tx_good = 0; 1443 sp->tx_underruns = 0; 1444 sp->tx_total_collisions = 0; 1445 1446 sp->rx_good = 0; 1447 sp->rx_crc_errors = 0; 1448 sp->rx_alignment_errors = 0; 1449 sp->rx_rnr_errors = 0; 1450 sp->rx_overrun_errors = 0; 1451 } 1452 1453 if (sc->sc_flags & FXPF_MII) { 1454 /* Tick the MII clock. */ 1455 mii_tick(&sc->sc_mii); 1456 } 1457 1458 splx(s); 1459 1460 /* 1461 * Schedule another timeout one second from now. 1462 */ 1463 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1464} 1465 1466/* 1467 * Drain the receive queue. 1468 */ 1469void 1470fxp_rxdrain(struct fxp_softc *sc) 1471{ 1472 bus_dmamap_t rxmap; 1473 struct mbuf *m; 1474 1475 for (;;) { 1476 IF_DEQUEUE(&sc->sc_rxq, m); 1477 if (m == NULL) 1478 break; 1479 rxmap = M_GETCTX(m, bus_dmamap_t); 1480 bus_dmamap_unload(sc->sc_dmat, rxmap); 1481 FXP_RXMAP_PUT(sc, rxmap); 1482 m_freem(m); 1483 } 1484} 1485 1486/* 1487 * Stop the interface. Cancels the statistics updater and resets 1488 * the interface. 1489 */ 1490void 1491fxp_stop(struct ifnet *ifp, int disable) 1492{ 1493 struct fxp_softc *sc = ifp->if_softc; 1494 struct fxp_txsoft *txs; 1495 int i; 1496 1497 /* 1498 * Turn down interface (done early to avoid bad interactions 1499 * between panics, shutdown hooks, and the watchdog timer) 1500 */ 1501 ifp->if_timer = 0; 1502 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1503 1504 /* 1505 * Cancel stats updater. 1506 */ 1507 callout_stop(&sc->sc_callout); 1508 if (sc->sc_flags & FXPF_MII) { 1509 /* Down the MII. */ 1510 mii_down(&sc->sc_mii); 1511 } 1512 1513 /* 1514 * Issue software reset. This unloads any microcode that 1515 * might already be loaded. 1516 */ 1517 sc->sc_flags &= ~FXPF_UCODE_LOADED; 1518 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1519 DELAY(50); 1520 1521 /* 1522 * Release any xmit buffers. 1523 */ 1524 for (i = 0; i < FXP_NTXCB; i++) { 1525 txs = FXP_DSTX(sc, i); 1526 if (txs->txs_mbuf != NULL) { 1527 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1528 m_freem(txs->txs_mbuf); 1529 txs->txs_mbuf = NULL; 1530 } 1531 } 1532 sc->sc_txpending = 0; 1533 1534 if (disable) { 1535 fxp_rxdrain(sc); 1536 fxp_disable(sc); 1537 } 1538 1539} 1540 1541/* 1542 * Watchdog/transmission transmit timeout handler. Called when a 1543 * transmission is started on the interface, but no interrupt is 1544 * received before the timeout. This usually indicates that the 1545 * card has wedged for some reason. 1546 */ 1547void 1548fxp_watchdog(struct ifnet *ifp) 1549{ 1550 struct fxp_softc *sc = ifp->if_softc; 1551 1552 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1553 ifp->if_oerrors++; 1554 1555 (void) fxp_init(ifp); 1556} 1557 1558/* 1559 * Initialize the interface. Must be called at splnet(). 1560 */ 1561int 1562fxp_init(struct ifnet *ifp) 1563{ 1564 struct fxp_softc *sc = ifp->if_softc; 1565 struct fxp_cb_config *cbp; 1566 struct fxp_cb_ias *cb_ias; 1567 struct fxp_txdesc *txd; 1568 bus_dmamap_t rxmap; 1569 int i, prm, save_bf, lrxen, allm, error = 0; 1570 1571 if ((error = fxp_enable(sc)) != 0) 1572 goto out; 1573 1574 /* 1575 * Cancel any pending I/O 1576 */ 1577 fxp_stop(ifp, 0); 1578 1579 /* 1580 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1581 * flag, and this prevents the MII from detaching resulting in 1582 * a panic. The flags field should perhaps be split in runtime 1583 * flags and more static information. For now, just clear the 1584 * only other flag set. 1585 */ 1586 1587 sc->sc_flags &= ~FXPF_WANTINIT; 1588 1589 /* 1590 * Initialize base of CBL and RFA memory. Loading with zero 1591 * sets it up for regular linear addressing. 1592 */ 1593 fxp_scb_wait(sc); 1594 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1595 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1596 1597 fxp_scb_wait(sc); 1598 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1599 1600 /* 1601 * Initialize the multicast filter. Do this now, since we might 1602 * have to setup the config block differently. 1603 */ 1604 fxp_mc_setup(sc); 1605 1606 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1607 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1608 1609 /* 1610 * In order to support receiving 802.1Q VLAN frames, we have to 1611 * enable "save bad frames", since they are 4 bytes larger than 1612 * the normal Ethernet maximum frame length. On i82558 and later, 1613 * we have a better mechanism for this. 1614 */ 1615 save_bf = 0; 1616 lrxen = 0; 1617 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1618 if (sc->sc_rev < FXP_REV_82558_A4) 1619 save_bf = 1; 1620 else 1621 lrxen = 1; 1622 } 1623 1624 /* 1625 * Initialize base of dump-stats buffer. 1626 */ 1627 fxp_scb_wait(sc); 1628 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1629 sc->sc_cddma + FXP_CDSTATSOFF); 1630 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1631 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1632 1633 cbp = &sc->sc_control_data->fcd_configcb; 1634 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1635 1636 /* 1637 * Load microcode for this controller. 1638 */ 1639 fxp_load_ucode(sc); 1640 1641 /* 1642 * This copy is kind of disgusting, but there are a bunch of must be 1643 * zero and must be one bits in this structure and this is the easiest 1644 * way to initialize them all to proper values. 1645 */ 1646 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1647 1648 /* BIG_ENDIAN: no need to swap to store 0 */ 1649 cbp->cb_status = 0; 1650 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1651 FXP_CB_COMMAND_EL); 1652 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1653 cbp->link_addr = 0xffffffff; /* (no) next command */ 1654 /* bytes in config block */ 1655 cbp->byte_count = (sc->sc_flags & FXPF_EXT_RFA) ? 1656 FXP_EXT_CONFIG_LEN : FXP_CONFIG_LEN; 1657 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1658 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1659 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1660 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1661 cbp->type_enable = 0; /* actually reserved */ 1662 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1663 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1664 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1665 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1666 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1667 cbp->late_scb = 0; /* (don't) defer SCB update */ 1668 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1669 cbp->ci_int = 1; /* interrupt on CU idle */ 1670 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1671 cbp->ext_stats_dis = 1; /* disable extended counters */ 1672 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1673 cbp->save_bf = save_bf;/* save bad frames */ 1674 cbp->disc_short_rx = !prm; /* discard short packets */ 1675 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1676 cbp->ext_rfa = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1677 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1678 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1679 /* interface mode */ 1680 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1681 cbp->csma_dis = 0; /* (don't) disable link */ 1682 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1683 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1684 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1685 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1686 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1687 cbp->nsai = 1; /* (don't) disable source addr insert */ 1688 cbp->preamble_length = 2; /* (7 byte) preamble */ 1689 cbp->loopback = 0; /* (don't) loopback */ 1690 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1691 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1692 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1693 cbp->promiscuous = prm; /* promiscuous mode */ 1694 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1695 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1696 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1697 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1698 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1699 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1700 cbp->padding = 1; /* (do) pad short tx packets */ 1701 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1702 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1703 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1704 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1705 /* must set wake_en in PMCSR also */ 1706 cbp->force_fdx = 0; /* (don't) force full duplex */ 1707 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1708 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1709 cbp->mc_all = allm; /* accept all multicasts */ 1710 cbp->ext_rx_mode = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1711 1712 if (sc->sc_rev < FXP_REV_82558_A4) { 1713 /* 1714 * The i82557 has no hardware flow control, the values 1715 * here are the defaults for the chip. 1716 */ 1717 cbp->fc_delay_lsb = 0; 1718 cbp->fc_delay_msb = 0x40; 1719 cbp->pri_fc_thresh = 3; 1720 cbp->tx_fc_dis = 0; 1721 cbp->rx_fc_restop = 0; 1722 cbp->rx_fc_restart = 0; 1723 cbp->fc_filter = 0; 1724 cbp->pri_fc_loc = 1; 1725 } else { 1726 cbp->fc_delay_lsb = 0x1f; 1727 cbp->fc_delay_msb = 0x01; 1728 cbp->pri_fc_thresh = 3; 1729 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1730 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1731 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1732 cbp->fc_filter = !prm; /* drop FC frames to host */ 1733 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1734 } 1735 1736 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1737 1738 /* 1739 * Start the config command/DMA. 1740 */ 1741 fxp_scb_wait(sc); 1742 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1743 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1744 /* ...and wait for it to complete. */ 1745 i = 1000; 1746 do { 1747 FXP_CDCONFIGSYNC(sc, 1748 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1749 DELAY(1); 1750 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1751 if (i == 0) { 1752 printf("%s at line %d: dmasync timeout\n", 1753 sc->sc_dev.dv_xname, __LINE__); 1754 return (ETIMEDOUT); 1755 } 1756 1757 /* 1758 * Initialize the station address. 1759 */ 1760 cb_ias = &sc->sc_control_data->fcd_iascb; 1761 /* BIG_ENDIAN: no need to swap to store 0 */ 1762 cb_ias->cb_status = 0; 1763 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1764 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1765 cb_ias->link_addr = 0xffffffff; 1766 memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1767 1768 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1769 1770 /* 1771 * Start the IAS (Individual Address Setup) command/DMA. 1772 */ 1773 fxp_scb_wait(sc); 1774 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1775 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1776 /* ...and wait for it to complete. */ 1777 i = 1000; 1778 do { 1779 FXP_CDIASSYNC(sc, 1780 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1781 DELAY(1); 1782 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1783 if (i == 0) { 1784 printf("%s at line %d: dmasync timeout\n", 1785 sc->sc_dev.dv_xname, __LINE__); 1786 return (ETIMEDOUT); 1787 } 1788 1789 /* 1790 * Initialize the transmit descriptor ring. txlast is initialized 1791 * to the end of the list so that it will wrap around to the first 1792 * descriptor when the first packet is transmitted. 1793 */ 1794 for (i = 0; i < FXP_NTXCB; i++) { 1795 txd = FXP_CDTX(sc, i); 1796 memset(txd, 0, sizeof(*txd)); 1797 txd->txd_txcb.cb_command = 1798 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1799 txd->txd_txcb.link_addr = 1800 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1801 if (sc->sc_flags & FXPF_EXT_TXCB) 1802 txd->txd_txcb.tbd_array_addr = 1803 htole32(FXP_CDTBDADDR(sc, i) + 1804 (2 * sizeof(struct fxp_tbd))); 1805 else 1806 txd->txd_txcb.tbd_array_addr = 1807 htole32(FXP_CDTBDADDR(sc, i)); 1808 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1809 } 1810 sc->sc_txpending = 0; 1811 sc->sc_txdirty = 0; 1812 sc->sc_txlast = FXP_NTXCB - 1; 1813 1814 /* 1815 * Initialize the receive buffer list. 1816 */ 1817 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1818 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1819 rxmap = FXP_RXMAP_GET(sc); 1820 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1821 printf("%s: unable to allocate or map rx " 1822 "buffer %d, error = %d\n", 1823 sc->sc_dev.dv_xname, 1824 sc->sc_rxq.ifq_len, error); 1825 /* 1826 * XXX Should attempt to run with fewer receive 1827 * XXX buffers instead of just failing. 1828 */ 1829 FXP_RXMAP_PUT(sc, rxmap); 1830 fxp_rxdrain(sc); 1831 goto out; 1832 } 1833 } 1834 sc->sc_rxidle = 0; 1835 1836 /* 1837 * Give the transmit ring to the chip. We do this by pointing 1838 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1839 * issuing a start command. It will execute the NOP and then 1840 * suspend, pointing at the first descriptor. 1841 */ 1842 fxp_scb_wait(sc); 1843 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1844 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1845 1846 /* 1847 * Initialize receiver buffer area - RFA. 1848 */ 1849 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1850 fxp_scb_wait(sc); 1851 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1852 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1853 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1854 1855 if (sc->sc_flags & FXPF_MII) { 1856 /* 1857 * Set current media. 1858 */ 1859 mii_mediachg(&sc->sc_mii); 1860 } 1861 1862 /* 1863 * ...all done! 1864 */ 1865 ifp->if_flags |= IFF_RUNNING; 1866 ifp->if_flags &= ~IFF_OACTIVE; 1867 1868 /* 1869 * Start the one second timer. 1870 */ 1871 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1872 1873 /* 1874 * Attempt to start output on the interface. 1875 */ 1876 fxp_start(ifp); 1877 1878 out: 1879 if (error) { 1880 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1881 ifp->if_timer = 0; 1882 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1883 } 1884 return (error); 1885} 1886 1887/* 1888 * Change media according to request. 1889 */ 1890int 1891fxp_mii_mediachange(struct ifnet *ifp) 1892{ 1893 struct fxp_softc *sc = ifp->if_softc; 1894 1895 if (ifp->if_flags & IFF_UP) 1896 mii_mediachg(&sc->sc_mii); 1897 return (0); 1898} 1899 1900/* 1901 * Notify the world which media we're using. 1902 */ 1903void 1904fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1905{ 1906 struct fxp_softc *sc = ifp->if_softc; 1907 1908 if (sc->sc_enabled == 0) { 1909 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1910 ifmr->ifm_status = 0; 1911 return; 1912 } 1913 1914 mii_pollstat(&sc->sc_mii); 1915 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1916 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1917} 1918 1919int 1920fxp_80c24_mediachange(struct ifnet *ifp) 1921{ 1922 1923 /* Nothing to do here. */ 1924 return (0); 1925} 1926 1927void 1928fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1929{ 1930 struct fxp_softc *sc = ifp->if_softc; 1931 1932 /* 1933 * Media is currently-selected media. We cannot determine 1934 * the link status. 1935 */ 1936 ifmr->ifm_status = 0; 1937 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1938} 1939 1940/* 1941 * Add a buffer to the end of the RFA buffer list. 1942 * Return 0 if successful, error code on failure. 1943 * 1944 * The RFA struct is stuck at the beginning of mbuf cluster and the 1945 * data pointer is fixed up to point just past it. 1946 */ 1947int 1948fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 1949{ 1950 struct mbuf *m; 1951 int error; 1952 1953 MGETHDR(m, M_DONTWAIT, MT_DATA); 1954 if (m == NULL) 1955 return (ENOBUFS); 1956 1957 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1958 MCLGET(m, M_DONTWAIT); 1959 if ((m->m_flags & M_EXT) == 0) { 1960 m_freem(m); 1961 return (ENOBUFS); 1962 } 1963 1964 if (unload) 1965 bus_dmamap_unload(sc->sc_dmat, rxmap); 1966 1967 M_SETCTX(m, rxmap); 1968 1969 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1970 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, 1971 BUS_DMA_READ|BUS_DMA_NOWAIT); 1972 if (error) { 1973 printf("%s: can't load rx DMA map %d, error = %d\n", 1974 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 1975 panic("fxp_add_rfabuf"); /* XXX */ 1976 } 1977 1978 FXP_INIT_RFABUF(sc, m); 1979 1980 return (0); 1981} 1982 1983int 1984fxp_mdi_read(struct device *self, int phy, int reg) 1985{ 1986 struct fxp_softc *sc = (struct fxp_softc *)self; 1987 int count = 10000; 1988 int value; 1989 1990 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1991 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1992 1993 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 1994 0x10000000) == 0 && count--) 1995 DELAY(10); 1996 1997 if (count <= 0) 1998 printf("%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 1999 2000 return (value & 0xffff); 2001} 2002 2003void 2004fxp_statchg(struct device *self) 2005{ 2006 2007 /* Nothing to do. */ 2008} 2009 2010void 2011fxp_mdi_write(struct device *self, int phy, int reg, int value) 2012{ 2013 struct fxp_softc *sc = (struct fxp_softc *)self; 2014 int count = 10000; 2015 2016 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2017 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2018 (value & 0xffff)); 2019 2020 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2021 count--) 2022 DELAY(10); 2023 2024 if (count <= 0) 2025 printf("%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 2026} 2027 2028int 2029fxp_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2030{ 2031 struct fxp_softc *sc = ifp->if_softc; 2032 struct ifreq *ifr = (struct ifreq *)data; 2033 int s, error; 2034 2035 s = splnet(); 2036 2037 switch (cmd) { 2038 case SIOCSIFMEDIA: 2039 case SIOCGIFMEDIA: 2040 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2041 break; 2042 2043 default: 2044 error = ether_ioctl(ifp, cmd, data); 2045 if (error == ENETRESET) { 2046 if (sc->sc_enabled) { 2047 /* 2048 * Multicast list has changed; set the 2049 * hardware filter accordingly. 2050 */ 2051 if (sc->sc_txpending) { 2052 sc->sc_flags |= FXPF_WANTINIT; 2053 error = 0; 2054 } else 2055 error = fxp_init(ifp); 2056 } else 2057 error = 0; 2058 } 2059 break; 2060 } 2061 2062 /* Try to get more packets going. */ 2063 if (sc->sc_enabled) 2064 fxp_start(ifp); 2065 2066 splx(s); 2067 return (error); 2068} 2069 2070/* 2071 * Program the multicast filter. 2072 * 2073 * This function must be called at splnet(). 2074 */ 2075void 2076fxp_mc_setup(struct fxp_softc *sc) 2077{ 2078 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 2079 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2080 struct ethercom *ec = &sc->sc_ethercom; 2081 struct ether_multi *enm; 2082 struct ether_multistep step; 2083 int count, nmcasts; 2084 2085#ifdef DIAGNOSTIC 2086 if (sc->sc_txpending) 2087 panic("fxp_mc_setup: pending transmissions"); 2088#endif 2089 2090 ifp->if_flags &= ~IFF_ALLMULTI; 2091 2092 /* 2093 * Initialize multicast setup descriptor. 2094 */ 2095 nmcasts = 0; 2096 ETHER_FIRST_MULTI(step, ec, enm); 2097 while (enm != NULL) { 2098 /* 2099 * Check for too many multicast addresses or if we're 2100 * listening to a range. Either way, we simply have 2101 * to accept all multicasts. 2102 */ 2103 if (nmcasts >= MAXMCADDR || 2104 memcmp(enm->enm_addrlo, enm->enm_addrhi, 2105 ETHER_ADDR_LEN) != 0) { 2106 /* 2107 * Callers of this function must do the 2108 * right thing with this. If we're called 2109 * from outside fxp_init(), the caller must 2110 * detect if the state if IFF_ALLMULTI changes. 2111 * If it does, the caller must then call 2112 * fxp_init(), since allmulti is handled by 2113 * the config block. 2114 */ 2115 ifp->if_flags |= IFF_ALLMULTI; 2116 return; 2117 } 2118 memcpy((void *)&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 2119 ETHER_ADDR_LEN); 2120 nmcasts++; 2121 ETHER_NEXT_MULTI(step, enm); 2122 } 2123 2124 /* BIG_ENDIAN: no need to swap to store 0 */ 2125 mcsp->cb_status = 0; 2126 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2127 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 2128 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2129 2130 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2131 2132 /* 2133 * Wait until the command unit is not active. This should never 2134 * happen since nothing is queued, but make sure anyway. 2135 */ 2136 count = 100; 2137 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2138 FXP_SCB_CUS_ACTIVE && --count) 2139 DELAY(1); 2140 if (count == 0) { 2141 printf("%s at line %d: command queue timeout\n", 2142 sc->sc_dev.dv_xname, __LINE__); 2143 return; 2144 } 2145 2146 /* 2147 * Start the multicast setup command/DMA. 2148 */ 2149 fxp_scb_wait(sc); 2150 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2151 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2152 2153 /* ...and wait for it to complete. */ 2154 count = 1000; 2155 do { 2156 FXP_CDMCSSYNC(sc, 2157 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2158 DELAY(1); 2159 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2160 if (count == 0) { 2161 printf("%s at line %d: dmasync timeout\n", 2162 sc->sc_dev.dv_xname, __LINE__); 2163 return; 2164 } 2165} 2166 2167static const uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2168static const uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2169static const uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2170static const uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2171static const uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2172static const uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2173 2174#define UCODE(x) x, sizeof(x) 2175 2176static const struct ucode { 2177 int32_t revision; 2178 const uint32_t *ucode; 2179 size_t length; 2180 uint16_t int_delay_offset; 2181 uint16_t bundle_max_offset; 2182} ucode_table[] = { 2183 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), 2184 D101_CPUSAVER_DWORD, 0 }, 2185 2186 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), 2187 D101_CPUSAVER_DWORD, 0 }, 2188 2189 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2190 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2191 2192 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2193 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2194 2195 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2196 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2197 2198 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2199 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2200 2201 { 0, NULL, 0, 0, 0 } 2202}; 2203 2204void 2205fxp_load_ucode(struct fxp_softc *sc) 2206{ 2207 const struct ucode *uc; 2208 struct fxp_cb_ucode *cbp = &sc->sc_control_data->fcd_ucode; 2209 int count; 2210 2211 if (sc->sc_flags & FXPF_UCODE_LOADED) 2212 return; 2213 2214 /* 2215 * Only load the uCode if the user has requested that 2216 * we do so. 2217 */ 2218 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK0) == 0) { 2219 sc->sc_int_delay = 0; 2220 sc->sc_bundle_max = 0; 2221 return; 2222 } 2223 2224 for (uc = ucode_table; uc->ucode != NULL; uc++) { 2225 if (sc->sc_rev == uc->revision) 2226 break; 2227 } 2228 if (uc->ucode == NULL) 2229 return; 2230 2231 /* BIG ENDIAN: no need to swap to store 0 */ 2232 cbp->cb_status = 0; 2233 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2234 cbp->link_addr = 0xffffffff; /* (no) next command */ 2235 memcpy((void *) cbp->ucode, uc->ucode, uc->length); 2236 2237 if (uc->int_delay_offset) 2238 *(uint16_t *) &cbp->ucode[uc->int_delay_offset] = 2239 htole16(fxp_int_delay + (fxp_int_delay / 2)); 2240 2241 if (uc->bundle_max_offset) 2242 *(uint16_t *) &cbp->ucode[uc->bundle_max_offset] = 2243 htole16(fxp_bundle_max); 2244 2245 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2246 2247 /* 2248 * Download the uCode to the chip. 2249 */ 2250 fxp_scb_wait(sc); 2251 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDUCODEOFF); 2252 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2253 2254 /* ...and wait for it to complete. */ 2255 count = 10000; 2256 do { 2257 FXP_CDUCODESYNC(sc, 2258 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2259 DELAY(2); 2260 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2261 if (count == 0) { 2262 sc->sc_int_delay = 0; 2263 sc->sc_bundle_max = 0; 2264 printf("%s: timeout loading microcode\n", 2265 sc->sc_dev.dv_xname); 2266 return; 2267 } 2268 2269 if (sc->sc_int_delay != fxp_int_delay || 2270 sc->sc_bundle_max != fxp_bundle_max) { 2271 sc->sc_int_delay = fxp_int_delay; 2272 sc->sc_bundle_max = fxp_bundle_max; 2273 printf("%s: Microcode loaded: int delay: %d usec, " 2274 "max bundle: %d\n", sc->sc_dev.dv_xname, 2275 sc->sc_int_delay, 2276 uc->bundle_max_offset == 0 ? 0 : sc->sc_bundle_max); 2277 } 2278 2279 sc->sc_flags |= FXPF_UCODE_LOADED; 2280} 2281 2282int 2283fxp_enable(struct fxp_softc *sc) 2284{ 2285 2286 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2287 if ((*sc->sc_enable)(sc) != 0) { 2288 printf("%s: device enable failed\n", 2289 sc->sc_dev.dv_xname); 2290 return (EIO); 2291 } 2292 } 2293 2294 sc->sc_enabled = 1; 2295 return (0); 2296} 2297 2298void 2299fxp_disable(struct fxp_softc *sc) 2300{ 2301 2302 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2303 (*sc->sc_disable)(sc); 2304 sc->sc_enabled = 0; 2305 } 2306} 2307 2308/* 2309 * fxp_activate: 2310 * 2311 * Handle device activation/deactivation requests. 2312 */ 2313int 2314fxp_activate(struct device *self, enum devact act) 2315{ 2316 struct fxp_softc *sc = (void *) self; 2317 int s, error = 0; 2318 2319 s = splnet(); 2320 switch (act) { 2321 case DVACT_ACTIVATE: 2322 error = EOPNOTSUPP; 2323 break; 2324 2325 case DVACT_DEACTIVATE: 2326 if (sc->sc_flags & FXPF_MII) 2327 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 2328 MII_OFFSET_ANY); 2329 if_deactivate(&sc->sc_ethercom.ec_if); 2330 break; 2331 } 2332 splx(s); 2333 2334 return (error); 2335} 2336 2337/* 2338 * fxp_detach: 2339 * 2340 * Detach an i82557 interface. 2341 */ 2342int 2343fxp_detach(struct fxp_softc *sc) 2344{ 2345 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2346 int i; 2347 2348 /* Succeed now if there's no work to do. */ 2349 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2350 return (0); 2351 2352 /* Unhook our tick handler. */ 2353 callout_stop(&sc->sc_callout); 2354 2355 if (sc->sc_flags & FXPF_MII) { 2356 /* Detach all PHYs */ 2357 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2358 } 2359 2360 /* Delete all remaining media. */ 2361 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2362 2363#if NRND > 0 2364 rnd_detach_source(&sc->rnd_source); 2365#endif 2366 ether_ifdetach(ifp); 2367 if_detach(ifp); 2368 2369 for (i = 0; i < FXP_NRFABUFS; i++) { 2370 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2371 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2372 } 2373 2374 for (i = 0; i < FXP_NTXCB; i++) { 2375 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2376 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2377 } 2378 2379 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2380 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2381 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2382 sizeof(struct fxp_control_data)); 2383 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2384 2385 shutdownhook_disestablish(sc->sc_sdhook); 2386 powerhook_disestablish(sc->sc_powerhook); 2387 2388 return (0); 2389} 2390