i82557.c revision 1.71
1/* $NetBSD: i82557.c,v 1.71 2003/01/31 00:26:30 thorpej Exp $ */ 2 3/*- 4 * Copyright (c) 1997, 1998, 1999, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40/* 41 * Copyright (c) 1995, David Greenman 42 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice unmodified, this list of conditions, and the following 50 * disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 68 */ 69 70/* 71 * Device driver for the Intel i82557 fast Ethernet controller, 72 * and its successors, the i82558 and i82559. 73 */ 74 75#include <sys/cdefs.h> 76__KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.71 2003/01/31 00:26:30 thorpej Exp $"); 77 78#include "bpfilter.h" 79#include "rnd.h" 80 81#include <sys/param.h> 82#include <sys/systm.h> 83#include <sys/callout.h> 84#include <sys/mbuf.h> 85#include <sys/malloc.h> 86#include <sys/kernel.h> 87#include <sys/socket.h> 88#include <sys/ioctl.h> 89#include <sys/errno.h> 90#include <sys/device.h> 91 92#include <machine/endian.h> 93 94#include <uvm/uvm_extern.h> 95 96#if NRND > 0 97#include <sys/rnd.h> 98#endif 99 100#include <net/if.h> 101#include <net/if_dl.h> 102#include <net/if_media.h> 103#include <net/if_ether.h> 104 105#if NBPFILTER > 0 106#include <net/bpf.h> 107#endif 108 109#include <machine/bus.h> 110#include <machine/intr.h> 111 112#include <dev/mii/miivar.h> 113 114#include <dev/ic/i82557reg.h> 115#include <dev/ic/i82557var.h> 116 117#include <dev/microcode/i8255x/rcvbundl.h> 118 119/* 120 * NOTE! On the Alpha, we have an alignment constraint. The 121 * card DMAs the packet immediately following the RFA. However, 122 * the first thing in the packet is a 14-byte Ethernet header. 123 * This means that the packet is misaligned. To compensate, 124 * we actually offset the RFA 2 bytes into the cluster. This 125 * alignes the packet after the Ethernet header at a 32-bit 126 * boundary. HOWEVER! This means that the RFA is misaligned! 127 */ 128#define RFA_ALIGNMENT_FUDGE 2 129 130/* 131 * The configuration byte map has several undefined fields which 132 * must be one or must be zero. Set up a template for these bits 133 * only (assuming an i82557 chip), leaving the actual configuration 134 * for fxp_init(). 135 * 136 * See the definition of struct fxp_cb_config for the bit definitions. 137 */ 138const u_int8_t fxp_cb_config_template[] = { 139 0x0, 0x0, /* cb_status */ 140 0x0, 0x0, /* cb_command */ 141 0x0, 0x0, 0x0, 0x0, /* link_addr */ 142 0x0, /* 0 */ 143 0x0, /* 1 */ 144 0x0, /* 2 */ 145 0x0, /* 3 */ 146 0x0, /* 4 */ 147 0x0, /* 5 */ 148 0x32, /* 6 */ 149 0x0, /* 7 */ 150 0x0, /* 8 */ 151 0x0, /* 9 */ 152 0x6, /* 10 */ 153 0x0, /* 11 */ 154 0x0, /* 12 */ 155 0x0, /* 13 */ 156 0xf2, /* 14 */ 157 0x48, /* 15 */ 158 0x0, /* 16 */ 159 0x40, /* 17 */ 160 0xf0, /* 18 */ 161 0x0, /* 19 */ 162 0x3f, /* 20 */ 163 0x5, /* 21 */ 164 0x0, /* 22 */ 165 0x0, /* 23 */ 166 0x0, /* 24 */ 167 0x0, /* 25 */ 168 0x0, /* 26 */ 169 0x0, /* 27 */ 170 0x0, /* 28 */ 171 0x0, /* 29 */ 172 0x0, /* 30 */ 173 0x0, /* 31 */ 174}; 175 176void fxp_mii_initmedia(struct fxp_softc *); 177int fxp_mii_mediachange(struct ifnet *); 178void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 179 180void fxp_80c24_initmedia(struct fxp_softc *); 181int fxp_80c24_mediachange(struct ifnet *); 182void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 183 184void fxp_start(struct ifnet *); 185int fxp_ioctl(struct ifnet *, u_long, caddr_t); 186void fxp_watchdog(struct ifnet *); 187int fxp_init(struct ifnet *); 188void fxp_stop(struct ifnet *, int); 189 190void fxp_txintr(struct fxp_softc *); 191void fxp_rxintr(struct fxp_softc *); 192 193void fxp_rxdrain(struct fxp_softc *); 194int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 195int fxp_mdi_read(struct device *, int, int); 196void fxp_statchg(struct device *); 197void fxp_mdi_write(struct device *, int, int, int); 198void fxp_autosize_eeprom(struct fxp_softc*); 199void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 200void fxp_write_eeprom(struct fxp_softc *, u_int16_t *, int, int); 201void fxp_eeprom_update_cksum(struct fxp_softc *); 202void fxp_get_info(struct fxp_softc *, u_int8_t *); 203void fxp_tick(void *); 204void fxp_mc_setup(struct fxp_softc *); 205void fxp_load_ucode(struct fxp_softc *); 206 207void fxp_shutdown(void *); 208void fxp_power(int, void *); 209 210int fxp_copy_small = 0; 211 212/* 213 * Variables for interrupt mitigating microcode. 214 */ 215int fxp_int_delay = 1000; /* usec */ 216int fxp_bundle_max = 6; /* packets */ 217 218struct fxp_phytype { 219 int fp_phy; /* type of PHY, -1 for MII at the end. */ 220 void (*fp_init)(struct fxp_softc *); 221} fxp_phytype_table[] = { 222 { FXP_PHY_80C24, fxp_80c24_initmedia }, 223 { -1, fxp_mii_initmedia }, 224}; 225 226/* 227 * Set initial transmit threshold at 64 (512 bytes). This is 228 * increased by 64 (512 bytes) at a time, to maximum of 192 229 * (1536 bytes), if an underrun occurs. 230 */ 231static int tx_threshold = 64; 232 233/* 234 * Wait for the previous command to be accepted (but not necessarily 235 * completed). 236 */ 237static __inline void 238fxp_scb_wait(struct fxp_softc *sc) 239{ 240 int i = 10000; 241 242 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 243 delay(2); 244 if (i == 0) 245 printf("%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 246} 247 248/* 249 * Submit a command to the i82557. 250 */ 251static __inline void 252fxp_scb_cmd(struct fxp_softc *sc, u_int8_t cmd) 253{ 254 255 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 256} 257 258/* 259 * Finish attaching an i82557 interface. Called by bus-specific front-end. 260 */ 261void 262fxp_attach(struct fxp_softc *sc) 263{ 264 u_int8_t enaddr[ETHER_ADDR_LEN]; 265 struct ifnet *ifp; 266 bus_dma_segment_t seg; 267 int rseg, i, error; 268 struct fxp_phytype *fp; 269 270 callout_init(&sc->sc_callout); 271 272 /* Start out using the standard RFA. */ 273 sc->sc_rfa_size = RFA_SIZE; 274 275 /* 276 * Enable some good stuff on i82558 and later. 277 */ 278 if (sc->sc_rev >= FXP_REV_82558_A4) { 279 /* Enable the extended TxCB. */ 280 sc->sc_flags |= FXPF_EXT_TXCB; 281 } 282 283 /* 284 * Allocate the control data structures, and create and load the 285 * DMA map for it. 286 */ 287 if ((error = bus_dmamem_alloc(sc->sc_dmat, 288 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 289 0)) != 0) { 290 aprint_error( 291 "%s: unable to allocate control data, error = %d\n", 292 sc->sc_dev.dv_xname, error); 293 goto fail_0; 294 } 295 296 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 297 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 298 BUS_DMA_COHERENT)) != 0) { 299 aprint_error("%s: unable to map control data, error = %d\n", 300 sc->sc_dev.dv_xname, error); 301 goto fail_1; 302 } 303 sc->sc_cdseg = seg; 304 sc->sc_cdnseg = rseg; 305 306 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 307 308 if ((error = bus_dmamap_create(sc->sc_dmat, 309 sizeof(struct fxp_control_data), 1, 310 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 311 aprint_error("%s: unable to create control data DMA map, " 312 "error = %d\n", sc->sc_dev.dv_xname, error); 313 goto fail_2; 314 } 315 316 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 317 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 318 0)) != 0) { 319 aprint_error( 320 "%s: can't load control data DMA map, error = %d\n", 321 sc->sc_dev.dv_xname, error); 322 goto fail_3; 323 } 324 325 /* 326 * Create the transmit buffer DMA maps. 327 */ 328 for (i = 0; i < FXP_NTXCB; i++) { 329 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 330 FXP_NTXSEG, MCLBYTES, 0, 0, 331 &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 332 aprint_error("%s: unable to create tx DMA map %d, " 333 "error = %d\n", sc->sc_dev.dv_xname, i, error); 334 goto fail_4; 335 } 336 } 337 338 /* 339 * Create the receive buffer DMA maps. 340 */ 341 for (i = 0; i < FXP_NRFABUFS; i++) { 342 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 343 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 344 aprint_error("%s: unable to create rx DMA map %d, " 345 "error = %d\n", sc->sc_dev.dv_xname, i, error); 346 goto fail_5; 347 } 348 } 349 350 /* Initialize MAC address and media structures. */ 351 fxp_get_info(sc, enaddr); 352 353 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 354 ether_sprintf(enaddr)); 355 356 ifp = &sc->sc_ethercom.ec_if; 357 358 /* 359 * Get info about our media interface, and initialize it. Note 360 * the table terminates itself with a phy of -1, indicating 361 * that we're using MII. 362 */ 363 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 364 if (fp->fp_phy == sc->phy_primary_device) 365 break; 366 (*fp->fp_init)(sc); 367 368 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 369 ifp->if_softc = sc; 370 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 371 ifp->if_ioctl = fxp_ioctl; 372 ifp->if_start = fxp_start; 373 ifp->if_watchdog = fxp_watchdog; 374 ifp->if_init = fxp_init; 375 ifp->if_stop = fxp_stop; 376 IFQ_SET_READY(&ifp->if_snd); 377 378 /* 379 * We can support 802.1Q VLAN-sized frames. 380 */ 381 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 382 383 /* 384 * Attach the interface. 385 */ 386 if_attach(ifp); 387 ether_ifattach(ifp, enaddr); 388#if NRND > 0 389 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 390 RND_TYPE_NET, 0); 391#endif 392 393#ifdef FXP_EVENT_COUNTERS 394 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 395 NULL, sc->sc_dev.dv_xname, "txstall"); 396 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 397 NULL, sc->sc_dev.dv_xname, "txintr"); 398 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 399 NULL, sc->sc_dev.dv_xname, "rxintr"); 400#endif /* FXP_EVENT_COUNTERS */ 401 402 /* 403 * Add shutdown hook so that DMA is disabled prior to reboot. Not 404 * doing do could allow DMA to corrupt kernel memory during the 405 * reboot before the driver initializes. 406 */ 407 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 408 if (sc->sc_sdhook == NULL) 409 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 410 sc->sc_dev.dv_xname); 411 /* 412 * Add suspend hook, for similar reasons.. 413 */ 414 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 415 if (sc->sc_powerhook == NULL) 416 aprint_error("%s: WARNING: unable to establish power hook\n", 417 sc->sc_dev.dv_xname); 418 419 /* The attach is successful. */ 420 sc->sc_flags |= FXPF_ATTACHED; 421 422 return; 423 424 /* 425 * Free any resources we've allocated during the failed attach 426 * attempt. Do this in reverse order and fall though. 427 */ 428 fail_5: 429 for (i = 0; i < FXP_NRFABUFS; i++) { 430 if (sc->sc_rxmaps[i] != NULL) 431 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 432 } 433 fail_4: 434 for (i = 0; i < FXP_NTXCB; i++) { 435 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 436 bus_dmamap_destroy(sc->sc_dmat, 437 FXP_DSTX(sc, i)->txs_dmamap); 438 } 439 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 440 fail_3: 441 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 442 fail_2: 443 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 444 sizeof(struct fxp_control_data)); 445 fail_1: 446 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 447 fail_0: 448 return; 449} 450 451void 452fxp_mii_initmedia(struct fxp_softc *sc) 453{ 454 int flags; 455 456 sc->sc_flags |= FXPF_MII; 457 458 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 459 sc->sc_mii.mii_readreg = fxp_mdi_read; 460 sc->sc_mii.mii_writereg = fxp_mdi_write; 461 sc->sc_mii.mii_statchg = fxp_statchg; 462 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, fxp_mii_mediachange, 463 fxp_mii_mediastatus); 464 465 flags = MIIF_NOISOLATE; 466 if (sc->sc_rev >= FXP_REV_82558_A4) 467 flags |= MIIF_DOPAUSE; 468 /* 469 * The i82557 wedges if all of its PHYs are isolated! 470 */ 471 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 472 MII_OFFSET_ANY, flags); 473 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 474 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 475 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 476 } else 477 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 478} 479 480void 481fxp_80c24_initmedia(struct fxp_softc *sc) 482{ 483 484 /* 485 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 486 * doesn't have a programming interface of any sort. The 487 * media is sensed automatically based on how the link partner 488 * is configured. This is, in essence, manual configuration. 489 */ 490 aprint_normal("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 491 sc->sc_dev.dv_xname); 492 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 493 fxp_80c24_mediastatus); 494 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 495 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 496} 497 498/* 499 * Device shutdown routine. Called at system shutdown after sync. The 500 * main purpose of this routine is to shut off receiver DMA so that 501 * kernel memory doesn't get clobbered during warmboot. 502 */ 503void 504fxp_shutdown(void *arg) 505{ 506 struct fxp_softc *sc = arg; 507 508 /* 509 * Since the system's going to halt shortly, don't bother 510 * freeing mbufs. 511 */ 512 fxp_stop(&sc->sc_ethercom.ec_if, 0); 513} 514/* 515 * Power handler routine. Called when the system is transitioning 516 * into/out of power save modes. As with fxp_shutdown, the main 517 * purpose of this routine is to shut off receiver DMA so it doesn't 518 * clobber kernel memory at the wrong time. 519 */ 520void 521fxp_power(int why, void *arg) 522{ 523 struct fxp_softc *sc = arg; 524 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 525 int s; 526 527 s = splnet(); 528 switch (why) { 529 case PWR_SUSPEND: 530 case PWR_STANDBY: 531 fxp_stop(ifp, 0); 532 break; 533 case PWR_RESUME: 534 if (ifp->if_flags & IFF_UP) 535 fxp_init(ifp); 536 break; 537 case PWR_SOFTSUSPEND: 538 case PWR_SOFTSTANDBY: 539 case PWR_SOFTRESUME: 540 break; 541 } 542 splx(s); 543} 544 545/* 546 * Initialize the interface media. 547 */ 548void 549fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 550{ 551 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 552 553 /* 554 * Reset to a stable state. 555 */ 556 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 557 DELAY(10); 558 559 sc->sc_eeprom_size = 0; 560 fxp_autosize_eeprom(sc); 561 if (sc->sc_eeprom_size == 0) { 562 aprint_error("%s: failed to detect EEPROM size\n", 563 sc->sc_dev.dv_xname); 564 sc->sc_eeprom_size = 6; /* XXX panic here? */ 565 } 566#ifdef DEBUG 567 aprint_debug("%s: detected %d word EEPROM\n", 568 sc->sc_dev.dv_xname, 1 << sc->sc_eeprom_size); 569#endif 570 571 /* 572 * Get info about the primary PHY 573 */ 574 fxp_read_eeprom(sc, &data, 6, 1); 575 sc->phy_primary_device = 576 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 577 578 /* 579 * Read MAC address. 580 */ 581 fxp_read_eeprom(sc, myea, 0, 3); 582 enaddr[0] = myea[0] & 0xff; 583 enaddr[1] = myea[0] >> 8; 584 enaddr[2] = myea[1] & 0xff; 585 enaddr[3] = myea[1] >> 8; 586 enaddr[4] = myea[2] & 0xff; 587 enaddr[5] = myea[2] >> 8; 588 589 /* 590 * Systems based on the ICH2/ICH2-M chip from Intel, as well 591 * as some i82559 designs, have a defect where the chip can 592 * cause a PCI protocol violation if it receives a CU_RESUME 593 * command when it is entering the IDLE state. 594 * 595 * The work-around is to disable Dynamic Standby Mode, so that 596 * the chip never deasserts #CLKRUN, and always remains in the 597 * active state. 598 * 599 * Unfortunately, the only way to disable Dynamic Standby is 600 * to frob an EEPROM setting and reboot (the EEPROM setting 601 * is only consulted when the PCI bus comes out of reset). 602 * 603 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 604 */ 605 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 606 fxp_read_eeprom(sc, &data, 10, 1); 607 if (data & 0x02) { /* STB enable */ 608 aprint_error("%s: WARNING: " 609 "Disabling dynamic standby mode in EEPROM " 610 "to work around a\n", 611 sc->sc_dev.dv_xname); 612 aprint_normal( 613 "%s: WARNING: hardware bug. You must reset " 614 "the system before using this\n", 615 sc->sc_dev.dv_xname); 616 aprint_normal("%s: WARNING: interface.\n", 617 sc->sc_dev.dv_xname); 618 data &= ~0x02; 619 fxp_write_eeprom(sc, &data, 10, 1); 620 aprint_normal("%s: new EEPROM ID: 0x%04x\n", 621 sc->sc_dev.dv_xname, data); 622 fxp_eeprom_update_cksum(sc); 623 } 624 } 625} 626 627static void 628fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 629{ 630 uint16_t reg; 631 int x; 632 633 for (x = 1 << (len - 1); x != 0; x >>= 1) { 634 if (data & x) 635 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 636 else 637 reg = FXP_EEPROM_EECS; 638 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 639 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 640 reg | FXP_EEPROM_EESK); 641 DELAY(4); 642 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 643 DELAY(4); 644 } 645} 646 647/* 648 * Figure out EEPROM size. 649 * 650 * 559's can have either 64-word or 256-word EEPROMs, the 558 651 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 652 * talks about the existance of 16 to 256 word EEPROMs. 653 * 654 * The only known sizes are 64 and 256, where the 256 version is used 655 * by CardBus cards to store CIS information. 656 * 657 * The address is shifted in msb-to-lsb, and after the last 658 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 659 * after which follows the actual data. We try to detect this zero, by 660 * probing the data-out bit in the EEPROM control register just after 661 * having shifted in a bit. If the bit is zero, we assume we've 662 * shifted enough address bits. The data-out should be tri-state, 663 * before this, which should translate to a logical one. 664 * 665 * Other ways to do this would be to try to read a register with known 666 * contents with a varying number of address bits, but no such 667 * register seem to be available. The high bits of register 10 are 01 668 * on the 558 and 559, but apparently not on the 557. 669 * 670 * The Linux driver computes a checksum on the EEPROM data, but the 671 * value of this checksum is not very well documented. 672 */ 673 674void 675fxp_autosize_eeprom(struct fxp_softc *sc) 676{ 677 int x; 678 679 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 680 681 /* Shift in read opcode. */ 682 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 683 684 /* 685 * Shift in address, wait for the dummy zero following a correct 686 * address shift. 687 */ 688 for (x = 1; x <= 8; x++) { 689 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 690 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 691 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 692 DELAY(4); 693 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 694 FXP_EEPROM_EEDO) == 0) 695 break; 696 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 697 DELAY(4); 698 } 699 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 700 DELAY(4); 701 if (x != 6 && x != 8) { 702#ifdef DEBUG 703 printf("%s: strange EEPROM size (%d)\n", 704 sc->sc_dev.dv_xname, 1 << x); 705#endif 706 } else 707 sc->sc_eeprom_size = x; 708} 709 710/* 711 * Read from the serial EEPROM. Basically, you manually shift in 712 * the read opcode (one bit at a time) and then shift in the address, 713 * and then you shift out the data (all of this one bit at a time). 714 * The word size is 16 bits, so you have to provide the address for 715 * every 16 bits of data. 716 */ 717void 718fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 719{ 720 u_int16_t reg; 721 int i, x; 722 723 for (i = 0; i < words; i++) { 724 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 725 726 /* Shift in read opcode. */ 727 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 728 729 /* Shift in address. */ 730 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 731 732 reg = FXP_EEPROM_EECS; 733 data[i] = 0; 734 735 /* Shift out data. */ 736 for (x = 16; x > 0; x--) { 737 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 738 reg | FXP_EEPROM_EESK); 739 DELAY(4); 740 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 741 FXP_EEPROM_EEDO) 742 data[i] |= (1 << (x - 1)); 743 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 744 DELAY(4); 745 } 746 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 747 DELAY(4); 748 } 749} 750 751/* 752 * Write data to the serial EEPROM. 753 */ 754void 755fxp_write_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 756{ 757 int i, j; 758 759 for (i = 0; i < words; i++) { 760 /* Erase/write enable. */ 761 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 762 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 763 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 764 sc->sc_eeprom_size); 765 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 766 DELAY(4); 767 768 /* Shift in write opcode, address, data. */ 769 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 770 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 771 fxp_eeprom_shiftin(sc, offset, sc->sc_eeprom_size); 772 fxp_eeprom_shiftin(sc, data[i], 16); 773 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 774 DELAY(4); 775 776 /* Wait for the EEPROM to finish up. */ 777 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 778 DELAY(4); 779 for (j = 0; j < 1000; j++) { 780 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 781 FXP_EEPROM_EEDO) 782 break; 783 DELAY(50); 784 } 785 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 786 DELAY(4); 787 788 /* Erase/write disable. */ 789 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 790 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 791 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 792 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 793 DELAY(4); 794 } 795} 796 797/* 798 * Update the checksum of the EEPROM. 799 */ 800void 801fxp_eeprom_update_cksum(struct fxp_softc *sc) 802{ 803 int i; 804 uint16_t data, cksum; 805 806 cksum = 0; 807 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 808 fxp_read_eeprom(sc, &data, i, 1); 809 cksum += data; 810 } 811 i = (1 << sc->sc_eeprom_size) - 1; 812 cksum = 0xbaba - cksum; 813 fxp_read_eeprom(sc, &data, i, 1); 814 fxp_write_eeprom(sc, &cksum, i, 1); 815 printf("%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 816 sc->sc_dev.dv_xname, i, data, cksum); 817} 818 819/* 820 * Start packet transmission on the interface. 821 */ 822void 823fxp_start(struct ifnet *ifp) 824{ 825 struct fxp_softc *sc = ifp->if_softc; 826 struct mbuf *m0, *m; 827 struct fxp_txdesc *txd; 828 struct fxp_txsoft *txs; 829 bus_dmamap_t dmamap; 830 int error, lasttx, nexttx, opending, seg; 831 832 /* 833 * If we want a re-init, bail out now. 834 */ 835 if (sc->sc_flags & FXPF_WANTINIT) { 836 ifp->if_flags |= IFF_OACTIVE; 837 return; 838 } 839 840 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 841 return; 842 843 /* 844 * Remember the previous txpending and the current lasttx. 845 */ 846 opending = sc->sc_txpending; 847 lasttx = sc->sc_txlast; 848 849 /* 850 * Loop through the send queue, setting up transmit descriptors 851 * until we drain the queue, or use up all available transmit 852 * descriptors. 853 */ 854 for (;;) { 855 /* 856 * Grab a packet off the queue. 857 */ 858 IFQ_POLL(&ifp->if_snd, m0); 859 if (m0 == NULL) 860 break; 861 m = NULL; 862 863 if (sc->sc_txpending == FXP_NTXCB) { 864 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 865 break; 866 } 867 868 /* 869 * Get the next available transmit descriptor. 870 */ 871 nexttx = FXP_NEXTTX(sc->sc_txlast); 872 txd = FXP_CDTX(sc, nexttx); 873 txs = FXP_DSTX(sc, nexttx); 874 dmamap = txs->txs_dmamap; 875 876 /* 877 * Load the DMA map. If this fails, the packet either 878 * didn't fit in the allotted number of frags, or we were 879 * short on resources. In this case, we'll copy and try 880 * again. 881 */ 882 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 883 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 884 MGETHDR(m, M_DONTWAIT, MT_DATA); 885 if (m == NULL) { 886 printf("%s: unable to allocate Tx mbuf\n", 887 sc->sc_dev.dv_xname); 888 break; 889 } 890 if (m0->m_pkthdr.len > MHLEN) { 891 MCLGET(m, M_DONTWAIT); 892 if ((m->m_flags & M_EXT) == 0) { 893 printf("%s: unable to allocate Tx " 894 "cluster\n", sc->sc_dev.dv_xname); 895 m_freem(m); 896 break; 897 } 898 } 899 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 900 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 901 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 902 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 903 if (error) { 904 printf("%s: unable to load Tx buffer, " 905 "error = %d\n", sc->sc_dev.dv_xname, error); 906 break; 907 } 908 } 909 910 IFQ_DEQUEUE(&ifp->if_snd, m0); 911 if (m != NULL) { 912 m_freem(m0); 913 m0 = m; 914 } 915 916 /* Initialize the fraglist. */ 917 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 918 txd->txd_tbd[seg].tb_addr = 919 htole32(dmamap->dm_segs[seg].ds_addr); 920 txd->txd_tbd[seg].tb_size = 921 htole32(dmamap->dm_segs[seg].ds_len); 922 } 923 924 /* Sync the DMA map. */ 925 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 926 BUS_DMASYNC_PREWRITE); 927 928 /* 929 * Store a pointer to the packet so we can free it later. 930 */ 931 txs->txs_mbuf = m0; 932 933 /* 934 * Initialize the transmit descriptor. 935 */ 936 /* BIG_ENDIAN: no need to swap to store 0 */ 937 txd->txd_txcb.cb_status = 0; 938 txd->txd_txcb.cb_command = 939 htole16(FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF); 940 txd->txd_txcb.tx_threshold = tx_threshold; 941 txd->txd_txcb.tbd_number = dmamap->dm_nsegs; 942 943 FXP_CDTXSYNC(sc, nexttx, 944 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 945 946 /* Advance the tx pointer. */ 947 sc->sc_txpending++; 948 sc->sc_txlast = nexttx; 949 950#if NBPFILTER > 0 951 /* 952 * Pass packet to bpf if there is a listener. 953 */ 954 if (ifp->if_bpf) 955 bpf_mtap(ifp->if_bpf, m0); 956#endif 957 } 958 959 if (sc->sc_txpending == FXP_NTXCB) { 960 /* No more slots; notify upper layer. */ 961 ifp->if_flags |= IFF_OACTIVE; 962 } 963 964 if (sc->sc_txpending != opending) { 965 /* 966 * We enqueued packets. If the transmitter was idle, 967 * reset the txdirty pointer. 968 */ 969 if (opending == 0) 970 sc->sc_txdirty = FXP_NEXTTX(lasttx); 971 972 /* 973 * Cause the chip to interrupt and suspend command 974 * processing once the last packet we've enqueued 975 * has been transmitted. 976 */ 977 FXP_CDTX(sc, sc->sc_txlast)->txd_txcb.cb_command |= 978 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 979 FXP_CDTXSYNC(sc, sc->sc_txlast, 980 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 981 982 /* 983 * The entire packet chain is set up. Clear the suspend bit 984 * on the command prior to the first packet we set up. 985 */ 986 FXP_CDTXSYNC(sc, lasttx, 987 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 988 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 989 htole16(~FXP_CB_COMMAND_S); 990 FXP_CDTXSYNC(sc, lasttx, 991 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 992 993 /* 994 * Issue a Resume command in case the chip was suspended. 995 */ 996 fxp_scb_wait(sc); 997 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 998 999 /* Set a watchdog timer in case the chip flakes out. */ 1000 ifp->if_timer = 5; 1001 } 1002} 1003 1004/* 1005 * Process interface interrupts. 1006 */ 1007int 1008fxp_intr(void *arg) 1009{ 1010 struct fxp_softc *sc = arg; 1011 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1012 bus_dmamap_t rxmap; 1013 int claimed = 0; 1014 u_int8_t statack; 1015 1016 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1017 return (0); 1018 /* 1019 * If the interface isn't running, don't try to 1020 * service the interrupt.. just ack it and bail. 1021 */ 1022 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1023 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1024 if (statack) { 1025 claimed = 1; 1026 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1027 } 1028 return (claimed); 1029 } 1030 1031 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1032 claimed = 1; 1033 1034 /* 1035 * First ACK all the interrupts in this pass. 1036 */ 1037 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1038 1039 /* 1040 * Process receiver interrupts. If a no-resource (RNR) 1041 * condition exists, get whatever packets we can and 1042 * re-start the receiver. 1043 */ 1044 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 1045 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1046 fxp_rxintr(sc); 1047 } 1048 1049 if (statack & FXP_SCB_STATACK_RNR) { 1050 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1051 fxp_scb_wait(sc); 1052 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1053 rxmap->dm_segs[0].ds_addr + 1054 RFA_ALIGNMENT_FUDGE); 1055 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1056 } 1057 1058 /* 1059 * Free any finished transmit mbuf chains. 1060 */ 1061 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1062 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1063 fxp_txintr(sc); 1064 1065 /* 1066 * Try to get more packets going. 1067 */ 1068 fxp_start(ifp); 1069 1070 if (sc->sc_txpending == 0) { 1071 /* 1072 * If we want a re-init, do that now. 1073 */ 1074 if (sc->sc_flags & FXPF_WANTINIT) 1075 (void) fxp_init(ifp); 1076 } 1077 } 1078 } 1079 1080#if NRND > 0 1081 if (claimed) 1082 rnd_add_uint32(&sc->rnd_source, statack); 1083#endif 1084 return (claimed); 1085} 1086 1087/* 1088 * Handle transmit completion interrupts. 1089 */ 1090void 1091fxp_txintr(struct fxp_softc *sc) 1092{ 1093 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1094 struct fxp_txdesc *txd; 1095 struct fxp_txsoft *txs; 1096 int i; 1097 u_int16_t txstat; 1098 1099 ifp->if_flags &= ~IFF_OACTIVE; 1100 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1101 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1102 txd = FXP_CDTX(sc, i); 1103 txs = FXP_DSTX(sc, i); 1104 1105 FXP_CDTXSYNC(sc, i, 1106 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1107 1108 txstat = le16toh(txd->txd_txcb.cb_status); 1109 1110 if ((txstat & FXP_CB_STATUS_C) == 0) 1111 break; 1112 1113 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1114 0, txs->txs_dmamap->dm_mapsize, 1115 BUS_DMASYNC_POSTWRITE); 1116 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1117 m_freem(txs->txs_mbuf); 1118 txs->txs_mbuf = NULL; 1119 } 1120 1121 /* Update the dirty transmit buffer pointer. */ 1122 sc->sc_txdirty = i; 1123 1124 /* 1125 * Cancel the watchdog timer if there are no pending 1126 * transmissions. 1127 */ 1128 if (sc->sc_txpending == 0) 1129 ifp->if_timer = 0; 1130} 1131 1132/* 1133 * Handle receive interrupts. 1134 */ 1135void 1136fxp_rxintr(struct fxp_softc *sc) 1137{ 1138 struct ethercom *ec = &sc->sc_ethercom; 1139 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1140 struct mbuf *m, *m0; 1141 bus_dmamap_t rxmap; 1142 struct fxp_rfa *rfa; 1143 u_int16_t len, rxstat; 1144 1145 for (;;) { 1146 m = sc->sc_rxq.ifq_head; 1147 rfa = FXP_MTORFA(m); 1148 rxmap = M_GETCTX(m, bus_dmamap_t); 1149 1150 FXP_RFASYNC(sc, m, 1151 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1152 1153 rxstat = le16toh(rfa->rfa_status); 1154 1155 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1156 /* 1157 * We have processed all of the 1158 * receive buffers. 1159 */ 1160 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1161 return; 1162 } 1163 1164 IF_DEQUEUE(&sc->sc_rxq, m); 1165 1166 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1167 1168 len = le16toh(rfa->actual_size) & 1169 (m->m_ext.ext_size - 1); 1170 1171 if (len < sizeof(struct ether_header)) { 1172 /* 1173 * Runt packet; drop it now. 1174 */ 1175 FXP_INIT_RFABUF(sc, m); 1176 continue; 1177 } 1178 1179 /* 1180 * If support for 802.1Q VLAN sized frames is 1181 * enabled, we need to do some additional error 1182 * checking (as we are saving bad frames, in 1183 * order to receive the larger ones). 1184 */ 1185 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1186 (rxstat & (FXP_RFA_STATUS_OVERRUN| 1187 FXP_RFA_STATUS_RNR| 1188 FXP_RFA_STATUS_ALIGN| 1189 FXP_RFA_STATUS_CRC)) != 0) { 1190 FXP_INIT_RFABUF(sc, m); 1191 continue; 1192 } 1193 1194 /* 1195 * If the packet is small enough to fit in a 1196 * single header mbuf, allocate one and copy 1197 * the data into it. This greatly reduces 1198 * memory consumption when we receive lots 1199 * of small packets. 1200 * 1201 * Otherwise, we add a new buffer to the receive 1202 * chain. If this fails, we drop the packet and 1203 * recycle the old buffer. 1204 */ 1205 if (fxp_copy_small != 0 && len <= MHLEN) { 1206 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1207 if (m == NULL) 1208 goto dropit; 1209 memcpy(mtod(m0, caddr_t), 1210 mtod(m, caddr_t), len); 1211 FXP_INIT_RFABUF(sc, m); 1212 m = m0; 1213 } else { 1214 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1215 dropit: 1216 ifp->if_ierrors++; 1217 FXP_INIT_RFABUF(sc, m); 1218 continue; 1219 } 1220 } 1221 1222 m->m_pkthdr.rcvif = ifp; 1223 m->m_pkthdr.len = m->m_len = len; 1224 1225#if NBPFILTER > 0 1226 /* 1227 * Pass this up to any BPF listeners, but only 1228 * pass it up the stack it its for us. 1229 */ 1230 if (ifp->if_bpf) 1231 bpf_mtap(ifp->if_bpf, m); 1232#endif 1233 1234 /* Pass it on. */ 1235 (*ifp->if_input)(ifp, m); 1236 } 1237} 1238 1239/* 1240 * Update packet in/out/collision statistics. The i82557 doesn't 1241 * allow you to access these counters without doing a fairly 1242 * expensive DMA to get _all_ of the statistics it maintains, so 1243 * we do this operation here only once per second. The statistics 1244 * counters in the kernel are updated from the previous dump-stats 1245 * DMA and then a new dump-stats DMA is started. The on-chip 1246 * counters are zeroed when the DMA completes. If we can't start 1247 * the DMA immediately, we don't wait - we just prepare to read 1248 * them again next time. 1249 */ 1250void 1251fxp_tick(void *arg) 1252{ 1253 struct fxp_softc *sc = arg; 1254 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1255 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1256 int s; 1257 1258 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1259 return; 1260 1261 s = splnet(); 1262 1263 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1264 1265 ifp->if_opackets += le32toh(sp->tx_good); 1266 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1267 if (sp->rx_good) { 1268 ifp->if_ipackets += le32toh(sp->rx_good); 1269 sc->sc_rxidle = 0; 1270 } else { 1271 sc->sc_rxidle++; 1272 } 1273 ifp->if_ierrors += 1274 le32toh(sp->rx_crc_errors) + 1275 le32toh(sp->rx_alignment_errors) + 1276 le32toh(sp->rx_rnr_errors) + 1277 le32toh(sp->rx_overrun_errors); 1278 /* 1279 * If any transmit underruns occurred, bump up the transmit 1280 * threshold by another 512 bytes (64 * 8). 1281 */ 1282 if (sp->tx_underruns) { 1283 ifp->if_oerrors += le32toh(sp->tx_underruns); 1284 if (tx_threshold < 192) 1285 tx_threshold += 64; 1286 } 1287 1288 /* 1289 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1290 * then assume the receiver has locked up and attempt to clear 1291 * the condition by reprogramming the multicast filter (actually, 1292 * resetting the interface). This is a work-around for a bug in 1293 * the 82557 where the receiver locks up if it gets certain types 1294 * of garbage in the synchronization bits prior to the packet header. 1295 * This bug is supposed to only occur in 10Mbps mode, but has been 1296 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1297 * speed transition). 1298 */ 1299 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1300 (void) fxp_init(ifp); 1301 splx(s); 1302 return; 1303 } 1304 /* 1305 * If there is no pending command, start another stats 1306 * dump. Otherwise punt for now. 1307 */ 1308 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1309 /* 1310 * Start another stats dump. 1311 */ 1312 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1313 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1314 } else { 1315 /* 1316 * A previous command is still waiting to be accepted. 1317 * Just zero our copy of the stats and wait for the 1318 * next timer event to update them. 1319 */ 1320 /* BIG_ENDIAN: no swap required to store 0 */ 1321 sp->tx_good = 0; 1322 sp->tx_underruns = 0; 1323 sp->tx_total_collisions = 0; 1324 1325 sp->rx_good = 0; 1326 sp->rx_crc_errors = 0; 1327 sp->rx_alignment_errors = 0; 1328 sp->rx_rnr_errors = 0; 1329 sp->rx_overrun_errors = 0; 1330 } 1331 1332 if (sc->sc_flags & FXPF_MII) { 1333 /* Tick the MII clock. */ 1334 mii_tick(&sc->sc_mii); 1335 } 1336 1337 splx(s); 1338 1339 /* 1340 * Schedule another timeout one second from now. 1341 */ 1342 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1343} 1344 1345/* 1346 * Drain the receive queue. 1347 */ 1348void 1349fxp_rxdrain(struct fxp_softc *sc) 1350{ 1351 bus_dmamap_t rxmap; 1352 struct mbuf *m; 1353 1354 for (;;) { 1355 IF_DEQUEUE(&sc->sc_rxq, m); 1356 if (m == NULL) 1357 break; 1358 rxmap = M_GETCTX(m, bus_dmamap_t); 1359 bus_dmamap_unload(sc->sc_dmat, rxmap); 1360 FXP_RXMAP_PUT(sc, rxmap); 1361 m_freem(m); 1362 } 1363} 1364 1365/* 1366 * Stop the interface. Cancels the statistics updater and resets 1367 * the interface. 1368 */ 1369void 1370fxp_stop(struct ifnet *ifp, int disable) 1371{ 1372 struct fxp_softc *sc = ifp->if_softc; 1373 struct fxp_txsoft *txs; 1374 int i; 1375 1376 /* 1377 * Turn down interface (done early to avoid bad interactions 1378 * between panics, shutdown hooks, and the watchdog timer) 1379 */ 1380 ifp->if_timer = 0; 1381 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1382 1383 /* 1384 * Cancel stats updater. 1385 */ 1386 callout_stop(&sc->sc_callout); 1387 if (sc->sc_flags & FXPF_MII) { 1388 /* Down the MII. */ 1389 mii_down(&sc->sc_mii); 1390 } 1391 1392 /* 1393 * Issue software reset. This unloads any microcode that 1394 * might already be loaded. 1395 */ 1396 sc->sc_flags &= ~FXPF_UCODE_LOADED; 1397 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1398 DELAY(50); 1399 1400 /* 1401 * Release any xmit buffers. 1402 */ 1403 for (i = 0; i < FXP_NTXCB; i++) { 1404 txs = FXP_DSTX(sc, i); 1405 if (txs->txs_mbuf != NULL) { 1406 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1407 m_freem(txs->txs_mbuf); 1408 txs->txs_mbuf = NULL; 1409 } 1410 } 1411 sc->sc_txpending = 0; 1412 1413 if (disable) { 1414 fxp_rxdrain(sc); 1415 fxp_disable(sc); 1416 } 1417 1418} 1419 1420/* 1421 * Watchdog/transmission transmit timeout handler. Called when a 1422 * transmission is started on the interface, but no interrupt is 1423 * received before the timeout. This usually indicates that the 1424 * card has wedged for some reason. 1425 */ 1426void 1427fxp_watchdog(struct ifnet *ifp) 1428{ 1429 struct fxp_softc *sc = ifp->if_softc; 1430 1431 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1432 ifp->if_oerrors++; 1433 1434 (void) fxp_init(ifp); 1435} 1436 1437/* 1438 * Initialize the interface. Must be called at splnet(). 1439 */ 1440int 1441fxp_init(struct ifnet *ifp) 1442{ 1443 struct fxp_softc *sc = ifp->if_softc; 1444 struct fxp_cb_config *cbp; 1445 struct fxp_cb_ias *cb_ias; 1446 struct fxp_txdesc *txd; 1447 bus_dmamap_t rxmap; 1448 int i, prm, save_bf, lrxen, allm, error = 0; 1449 1450 if ((error = fxp_enable(sc)) != 0) 1451 goto out; 1452 1453 /* 1454 * Cancel any pending I/O 1455 */ 1456 fxp_stop(ifp, 0); 1457 1458 /* 1459 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1460 * flag, and this prevents the MII from detaching resulting in 1461 * a panic. The flags field should perhaps be split in runtime 1462 * flags and more static information. For now, just clear the 1463 * only other flag set. 1464 */ 1465 1466 sc->sc_flags &= ~FXPF_WANTINIT; 1467 1468 /* 1469 * Initialize base of CBL and RFA memory. Loading with zero 1470 * sets it up for regular linear addressing. 1471 */ 1472 fxp_scb_wait(sc); 1473 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1474 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1475 1476 fxp_scb_wait(sc); 1477 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1478 1479 /* 1480 * Initialize the multicast filter. Do this now, since we might 1481 * have to setup the config block differently. 1482 */ 1483 fxp_mc_setup(sc); 1484 1485 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1486 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1487 1488 /* 1489 * In order to support receiving 802.1Q VLAN frames, we have to 1490 * enable "save bad frames", since they are 4 bytes larger than 1491 * the normal Ethernet maximum frame length. On i82558 and later, 1492 * we have a better mechanism for this. 1493 */ 1494 save_bf = 0; 1495 lrxen = 0; 1496 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1497 if (sc->sc_rev < FXP_REV_82558_A4) 1498 save_bf = 1; 1499 else 1500 lrxen = 1; 1501 } 1502 1503 /* 1504 * Initialize base of dump-stats buffer. 1505 */ 1506 fxp_scb_wait(sc); 1507 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1508 sc->sc_cddma + FXP_CDSTATSOFF); 1509 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1510 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1511 1512 cbp = &sc->sc_control_data->fcd_configcb; 1513 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1514 1515 /* 1516 * Load microcode for this controller. 1517 */ 1518 fxp_load_ucode(sc); 1519 1520 /* 1521 * This copy is kind of disgusting, but there are a bunch of must be 1522 * zero and must be one bits in this structure and this is the easiest 1523 * way to initialize them all to proper values. 1524 */ 1525 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1526 1527 /* BIG_ENDIAN: no need to swap to store 0 */ 1528 cbp->cb_status = 0; 1529 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1530 FXP_CB_COMMAND_EL); 1531 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1532 cbp->link_addr = 0xffffffff; /* (no) next command */ 1533 /* bytes in config block */ 1534 cbp->byte_count = FXP_CONFIG_LEN; 1535 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1536 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1537 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1538 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1539 cbp->type_enable = 0; /* actually reserved */ 1540 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1541 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1542 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1543 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1544 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1545 cbp->late_scb = 0; /* (don't) defer SCB update */ 1546 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1547 cbp->ci_int = 1; /* interrupt on CU idle */ 1548 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1549 cbp->ext_stats_dis = 1; /* disable extended counters */ 1550 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1551 cbp->save_bf = save_bf;/* save bad frames */ 1552 cbp->disc_short_rx = !prm; /* discard short packets */ 1553 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1554 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1555 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1556 /* interface mode */ 1557 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1558 cbp->csma_dis = 0; /* (don't) disable link */ 1559 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1560 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1561 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1562 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1563 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1564 cbp->nsai = 1; /* (don't) disable source addr insert */ 1565 cbp->preamble_length = 2; /* (7 byte) preamble */ 1566 cbp->loopback = 0; /* (don't) loopback */ 1567 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1568 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1569 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1570 cbp->promiscuous = prm; /* promiscuous mode */ 1571 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1572 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1573 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1574 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1575 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1576 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1577 cbp->padding = 1; /* (do) pad short tx packets */ 1578 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1579 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1580 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1581 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1582 /* must set wake_en in PMCSR also */ 1583 cbp->force_fdx = 0; /* (don't) force full duplex */ 1584 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1585 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1586 cbp->mc_all = allm; /* accept all multicasts */ 1587 1588 if (sc->sc_rev < FXP_REV_82558_A4) { 1589 /* 1590 * The i82557 has no hardware flow control, the values 1591 * here are the defaults for the chip. 1592 */ 1593 cbp->fc_delay_lsb = 0; 1594 cbp->fc_delay_msb = 0x40; 1595 cbp->pri_fc_thresh = 3; 1596 cbp->tx_fc_dis = 0; 1597 cbp->rx_fc_restop = 0; 1598 cbp->rx_fc_restart = 0; 1599 cbp->fc_filter = 0; 1600 cbp->pri_fc_loc = 1; 1601 } else { 1602 cbp->fc_delay_lsb = 0x1f; 1603 cbp->fc_delay_msb = 0x01; 1604 cbp->pri_fc_thresh = 3; 1605 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1606 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1607 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1608 cbp->fc_filter = !prm; /* drop FC frames to host */ 1609 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1610 } 1611 1612 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1613 1614 /* 1615 * Start the config command/DMA. 1616 */ 1617 fxp_scb_wait(sc); 1618 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1619 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1620 /* ...and wait for it to complete. */ 1621 i = 1000; 1622 do { 1623 FXP_CDCONFIGSYNC(sc, 1624 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1625 DELAY(1); 1626 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1627 if (i == 0) { 1628 printf("%s at line %d: dmasync timeout\n", 1629 sc->sc_dev.dv_xname, __LINE__); 1630 return (ETIMEDOUT); 1631 } 1632 1633 /* 1634 * Initialize the station address. 1635 */ 1636 cb_ias = &sc->sc_control_data->fcd_iascb; 1637 /* BIG_ENDIAN: no need to swap to store 0 */ 1638 cb_ias->cb_status = 0; 1639 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1640 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1641 cb_ias->link_addr = 0xffffffff; 1642 memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1643 1644 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1645 1646 /* 1647 * Start the IAS (Individual Address Setup) command/DMA. 1648 */ 1649 fxp_scb_wait(sc); 1650 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1651 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1652 /* ...and wait for it to complete. */ 1653 i = 1000; 1654 do { 1655 FXP_CDIASSYNC(sc, 1656 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1657 DELAY(1); 1658 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1659 if (i == 0) { 1660 printf("%s at line %d: dmasync timeout\n", 1661 sc->sc_dev.dv_xname, __LINE__); 1662 return (ETIMEDOUT); 1663 } 1664 1665 /* 1666 * Initialize the transmit descriptor ring. txlast is initialized 1667 * to the end of the list so that it will wrap around to the first 1668 * descriptor when the first packet is transmitted. 1669 */ 1670 for (i = 0; i < FXP_NTXCB; i++) { 1671 txd = FXP_CDTX(sc, i); 1672 memset(txd, 0, sizeof(*txd)); 1673 txd->txd_txcb.cb_command = 1674 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1675 txd->txd_txcb.link_addr = 1676 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1677 if (sc->sc_flags & FXPF_EXT_TXCB) 1678 txd->txd_txcb.tbd_array_addr = 1679 htole32(FXP_CDTBDADDR(sc, i) + 1680 (2 * sizeof(struct fxp_tbd))); 1681 else 1682 txd->txd_txcb.tbd_array_addr = 1683 htole32(FXP_CDTBDADDR(sc, i)); 1684 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1685 } 1686 sc->sc_txpending = 0; 1687 sc->sc_txdirty = 0; 1688 sc->sc_txlast = FXP_NTXCB - 1; 1689 1690 /* 1691 * Initialize the receive buffer list. 1692 */ 1693 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1694 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1695 rxmap = FXP_RXMAP_GET(sc); 1696 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1697 printf("%s: unable to allocate or map rx " 1698 "buffer %d, error = %d\n", 1699 sc->sc_dev.dv_xname, 1700 sc->sc_rxq.ifq_len, error); 1701 /* 1702 * XXX Should attempt to run with fewer receive 1703 * XXX buffers instead of just failing. 1704 */ 1705 FXP_RXMAP_PUT(sc, rxmap); 1706 fxp_rxdrain(sc); 1707 goto out; 1708 } 1709 } 1710 sc->sc_rxidle = 0; 1711 1712 /* 1713 * Give the transmit ring to the chip. We do this by pointing 1714 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1715 * issuing a start command. It will execute the NOP and then 1716 * suspend, pointing at the first descriptor. 1717 */ 1718 fxp_scb_wait(sc); 1719 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1720 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1721 1722 /* 1723 * Initialize receiver buffer area - RFA. 1724 */ 1725 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1726 fxp_scb_wait(sc); 1727 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1728 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1729 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1730 1731 if (sc->sc_flags & FXPF_MII) { 1732 /* 1733 * Set current media. 1734 */ 1735 mii_mediachg(&sc->sc_mii); 1736 } 1737 1738 /* 1739 * ...all done! 1740 */ 1741 ifp->if_flags |= IFF_RUNNING; 1742 ifp->if_flags &= ~IFF_OACTIVE; 1743 1744 /* 1745 * Start the one second timer. 1746 */ 1747 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1748 1749 /* 1750 * Attempt to start output on the interface. 1751 */ 1752 fxp_start(ifp); 1753 1754 out: 1755 if (error) { 1756 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1757 ifp->if_timer = 0; 1758 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1759 } 1760 return (error); 1761} 1762 1763/* 1764 * Change media according to request. 1765 */ 1766int 1767fxp_mii_mediachange(struct ifnet *ifp) 1768{ 1769 struct fxp_softc *sc = ifp->if_softc; 1770 1771 if (ifp->if_flags & IFF_UP) 1772 mii_mediachg(&sc->sc_mii); 1773 return (0); 1774} 1775 1776/* 1777 * Notify the world which media we're using. 1778 */ 1779void 1780fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1781{ 1782 struct fxp_softc *sc = ifp->if_softc; 1783 1784 if (sc->sc_enabled == 0) { 1785 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1786 ifmr->ifm_status = 0; 1787 return; 1788 } 1789 1790 mii_pollstat(&sc->sc_mii); 1791 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1792 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1793} 1794 1795int 1796fxp_80c24_mediachange(struct ifnet *ifp) 1797{ 1798 1799 /* Nothing to do here. */ 1800 return (0); 1801} 1802 1803void 1804fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1805{ 1806 struct fxp_softc *sc = ifp->if_softc; 1807 1808 /* 1809 * Media is currently-selected media. We cannot determine 1810 * the link status. 1811 */ 1812 ifmr->ifm_status = 0; 1813 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1814} 1815 1816/* 1817 * Add a buffer to the end of the RFA buffer list. 1818 * Return 0 if successful, error code on failure. 1819 * 1820 * The RFA struct is stuck at the beginning of mbuf cluster and the 1821 * data pointer is fixed up to point just past it. 1822 */ 1823int 1824fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 1825{ 1826 struct mbuf *m; 1827 int error; 1828 1829 MGETHDR(m, M_DONTWAIT, MT_DATA); 1830 if (m == NULL) 1831 return (ENOBUFS); 1832 1833 MCLGET(m, M_DONTWAIT); 1834 if ((m->m_flags & M_EXT) == 0) { 1835 m_freem(m); 1836 return (ENOBUFS); 1837 } 1838 1839 if (unload) 1840 bus_dmamap_unload(sc->sc_dmat, rxmap); 1841 1842 M_SETCTX(m, rxmap); 1843 1844 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1845 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1846 BUS_DMA_READ|BUS_DMA_NOWAIT); 1847 if (error) { 1848 printf("%s: can't load rx DMA map %d, error = %d\n", 1849 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 1850 panic("fxp_add_rfabuf"); /* XXX */ 1851 } 1852 1853 FXP_INIT_RFABUF(sc, m); 1854 1855 return (0); 1856} 1857 1858int 1859fxp_mdi_read(struct device *self, int phy, int reg) 1860{ 1861 struct fxp_softc *sc = (struct fxp_softc *)self; 1862 int count = 10000; 1863 int value; 1864 1865 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1866 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1867 1868 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 1869 0x10000000) == 0 && count--) 1870 DELAY(10); 1871 1872 if (count <= 0) 1873 printf("%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 1874 1875 return (value & 0xffff); 1876} 1877 1878void 1879fxp_statchg(struct device *self) 1880{ 1881 1882 /* Nothing to do. */ 1883} 1884 1885void 1886fxp_mdi_write(struct device *self, int phy, int reg, int value) 1887{ 1888 struct fxp_softc *sc = (struct fxp_softc *)self; 1889 int count = 10000; 1890 1891 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1892 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1893 (value & 0xffff)); 1894 1895 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1896 count--) 1897 DELAY(10); 1898 1899 if (count <= 0) 1900 printf("%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 1901} 1902 1903int 1904fxp_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1905{ 1906 struct fxp_softc *sc = ifp->if_softc; 1907 struct ifreq *ifr = (struct ifreq *)data; 1908 int s, error; 1909 1910 s = splnet(); 1911 1912 switch (cmd) { 1913 case SIOCSIFMEDIA: 1914 case SIOCGIFMEDIA: 1915 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1916 break; 1917 1918 default: 1919 error = ether_ioctl(ifp, cmd, data); 1920 if (error == ENETRESET) { 1921 if (sc->sc_enabled) { 1922 /* 1923 * Multicast list has changed; set the 1924 * hardware filter accordingly. 1925 */ 1926 if (sc->sc_txpending) { 1927 sc->sc_flags |= FXPF_WANTINIT; 1928 error = 0; 1929 } else 1930 error = fxp_init(ifp); 1931 } else 1932 error = 0; 1933 } 1934 break; 1935 } 1936 1937 /* Try to get more packets going. */ 1938 if (sc->sc_enabled) 1939 fxp_start(ifp); 1940 1941 splx(s); 1942 return (error); 1943} 1944 1945/* 1946 * Program the multicast filter. 1947 * 1948 * This function must be called at splnet(). 1949 */ 1950void 1951fxp_mc_setup(struct fxp_softc *sc) 1952{ 1953 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 1954 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1955 struct ethercom *ec = &sc->sc_ethercom; 1956 struct ether_multi *enm; 1957 struct ether_multistep step; 1958 int count, nmcasts; 1959 1960#ifdef DIAGNOSTIC 1961 if (sc->sc_txpending) 1962 panic("fxp_mc_setup: pending transmissions"); 1963#endif 1964 1965 ifp->if_flags &= ~IFF_ALLMULTI; 1966 1967 /* 1968 * Initialize multicast setup descriptor. 1969 */ 1970 nmcasts = 0; 1971 ETHER_FIRST_MULTI(step, ec, enm); 1972 while (enm != NULL) { 1973 /* 1974 * Check for too many multicast addresses or if we're 1975 * listening to a range. Either way, we simply have 1976 * to accept all multicasts. 1977 */ 1978 if (nmcasts >= MAXMCADDR || 1979 memcmp(enm->enm_addrlo, enm->enm_addrhi, 1980 ETHER_ADDR_LEN) != 0) { 1981 /* 1982 * Callers of this function must do the 1983 * right thing with this. If we're called 1984 * from outside fxp_init(), the caller must 1985 * detect if the state if IFF_ALLMULTI changes. 1986 * If it does, the caller must then call 1987 * fxp_init(), since allmulti is handled by 1988 * the config block. 1989 */ 1990 ifp->if_flags |= IFF_ALLMULTI; 1991 return; 1992 } 1993 memcpy((void *)&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 1994 ETHER_ADDR_LEN); 1995 nmcasts++; 1996 ETHER_NEXT_MULTI(step, enm); 1997 } 1998 1999 /* BIG_ENDIAN: no need to swap to store 0 */ 2000 mcsp->cb_status = 0; 2001 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2002 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 2003 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2004 2005 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2006 2007 /* 2008 * Wait until the command unit is not active. This should never 2009 * happen since nothing is queued, but make sure anyway. 2010 */ 2011 count = 100; 2012 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2013 FXP_SCB_CUS_ACTIVE && --count) 2014 DELAY(1); 2015 if (count == 0) { 2016 printf("%s at line %d: command queue timeout\n", 2017 sc->sc_dev.dv_xname, __LINE__); 2018 return; 2019 } 2020 2021 /* 2022 * Start the multicast setup command/DMA. 2023 */ 2024 fxp_scb_wait(sc); 2025 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2026 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2027 2028 /* ...and wait for it to complete. */ 2029 count = 1000; 2030 do { 2031 FXP_CDMCSSYNC(sc, 2032 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2033 DELAY(1); 2034 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2035 if (count == 0) { 2036 printf("%s at line %d: dmasync timeout\n", 2037 sc->sc_dev.dv_xname, __LINE__); 2038 return; 2039 } 2040} 2041 2042static const uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2043static const uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2044static const uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2045static const uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2046static const uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2047static const uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2048 2049#define UCODE(x) x, sizeof(x) 2050 2051static const struct ucode { 2052 int32_t revision; 2053 const uint32_t *ucode; 2054 size_t length; 2055 uint16_t int_delay_offset; 2056 uint16_t bundle_max_offset; 2057} ucode_table[] = { 2058 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), 2059 D101_CPUSAVER_DWORD, 0 }, 2060 2061 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), 2062 D101_CPUSAVER_DWORD, 0 }, 2063 2064 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2065 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2066 2067 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2068 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2069 2070 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2071 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2072 2073 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2074 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2075 2076 { 0, NULL, 0, 0, 0 } 2077}; 2078 2079void 2080fxp_load_ucode(struct fxp_softc *sc) 2081{ 2082 const struct ucode *uc; 2083 struct fxp_cb_ucode *cbp = &sc->sc_control_data->fcd_ucode; 2084 int count; 2085 2086 if (sc->sc_flags & FXPF_UCODE_LOADED) 2087 return; 2088 2089 /* 2090 * Only load the uCode if the user has requested that 2091 * we do so. 2092 */ 2093 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK0) == 0) { 2094 sc->sc_int_delay = 0; 2095 sc->sc_bundle_max = 0; 2096 return; 2097 } 2098 2099 for (uc = ucode_table; uc->ucode != NULL; uc++) { 2100 if (sc->sc_rev == uc->revision) 2101 break; 2102 } 2103 if (uc->ucode == NULL) 2104 return; 2105 2106 /* BIG ENDIAN: no need to swap to store 0 */ 2107 cbp->cb_status = 0; 2108 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2109 cbp->link_addr = 0xffffffff; /* (no) next command */ 2110 memcpy((void *) cbp->ucode, uc->ucode, uc->length); 2111 2112 if (uc->int_delay_offset) 2113 *(uint16_t *) &cbp->ucode[uc->int_delay_offset] = 2114 htole16(fxp_int_delay + (fxp_int_delay / 2)); 2115 2116 if (uc->bundle_max_offset) 2117 *(uint16_t *) &cbp->ucode[uc->bundle_max_offset] = 2118 htole16(fxp_bundle_max); 2119 2120 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2121 2122 /* 2123 * Download the uCode to the chip. 2124 */ 2125 fxp_scb_wait(sc); 2126 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDUCODEOFF); 2127 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2128 2129 /* ...and wait for it to complete. */ 2130 count = 10000; 2131 do { 2132 FXP_CDUCODESYNC(sc, 2133 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2134 DELAY(2); 2135 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2136 if (count == 0) { 2137 sc->sc_int_delay = 0; 2138 sc->sc_bundle_max = 0; 2139 printf("%s: timeout loading microcode\n", 2140 sc->sc_dev.dv_xname); 2141 return; 2142 } 2143 2144 if (sc->sc_int_delay != fxp_int_delay || 2145 sc->sc_bundle_max != fxp_bundle_max) { 2146 sc->sc_int_delay = fxp_int_delay; 2147 sc->sc_bundle_max = fxp_bundle_max; 2148 printf("%s: Microcode loaded: int delay: %d usec, " 2149 "max bundle: %d\n", sc->sc_dev.dv_xname, 2150 sc->sc_int_delay, 2151 uc->bundle_max_offset == 0 ? 0 : sc->sc_bundle_max); 2152 } 2153 2154 sc->sc_flags |= FXPF_UCODE_LOADED; 2155} 2156 2157int 2158fxp_enable(struct fxp_softc *sc) 2159{ 2160 2161 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2162 if ((*sc->sc_enable)(sc) != 0) { 2163 printf("%s: device enable failed\n", 2164 sc->sc_dev.dv_xname); 2165 return (EIO); 2166 } 2167 } 2168 2169 sc->sc_enabled = 1; 2170 return (0); 2171} 2172 2173void 2174fxp_disable(struct fxp_softc *sc) 2175{ 2176 2177 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2178 (*sc->sc_disable)(sc); 2179 sc->sc_enabled = 0; 2180 } 2181} 2182 2183/* 2184 * fxp_activate: 2185 * 2186 * Handle device activation/deactivation requests. 2187 */ 2188int 2189fxp_activate(struct device *self, enum devact act) 2190{ 2191 struct fxp_softc *sc = (void *) self; 2192 int s, error = 0; 2193 2194 s = splnet(); 2195 switch (act) { 2196 case DVACT_ACTIVATE: 2197 error = EOPNOTSUPP; 2198 break; 2199 2200 case DVACT_DEACTIVATE: 2201 if (sc->sc_flags & FXPF_MII) 2202 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 2203 MII_OFFSET_ANY); 2204 if_deactivate(&sc->sc_ethercom.ec_if); 2205 break; 2206 } 2207 splx(s); 2208 2209 return (error); 2210} 2211 2212/* 2213 * fxp_detach: 2214 * 2215 * Detach an i82557 interface. 2216 */ 2217int 2218fxp_detach(struct fxp_softc *sc) 2219{ 2220 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2221 int i; 2222 2223 /* Succeed now if there's no work to do. */ 2224 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2225 return (0); 2226 2227 /* Unhook our tick handler. */ 2228 callout_stop(&sc->sc_callout); 2229 2230 if (sc->sc_flags & FXPF_MII) { 2231 /* Detach all PHYs */ 2232 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2233 } 2234 2235 /* Delete all remaining media. */ 2236 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2237 2238#if NRND > 0 2239 rnd_detach_source(&sc->rnd_source); 2240#endif 2241 ether_ifdetach(ifp); 2242 if_detach(ifp); 2243 2244 for (i = 0; i < FXP_NRFABUFS; i++) { 2245 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2246 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2247 } 2248 2249 for (i = 0; i < FXP_NTXCB; i++) { 2250 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2251 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2252 } 2253 2254 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2255 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2256 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2257 sizeof(struct fxp_control_data)); 2258 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2259 2260 shutdownhook_disestablish(sc->sc_sdhook); 2261 powerhook_disestablish(sc->sc_powerhook); 2262 2263 return (0); 2264} 2265