i82557.c revision 1.64
1/* $NetBSD: i82557.c,v 1.64 2002/04/05 19:51:04 thorpej Exp $ */ 2 3/*- 4 * Copyright (c) 1997, 1998, 1999, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40/* 41 * Copyright (c) 1995, David Greenman 42 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice unmodified, this list of conditions, and the following 50 * disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 68 */ 69 70/* 71 * Device driver for the Intel i82557 fast Ethernet controller, 72 * and its successors, the i82558 and i82559. 73 */ 74 75#include <sys/cdefs.h> 76__KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.64 2002/04/05 19:51:04 thorpej Exp $"); 77 78#include "bpfilter.h" 79#include "rnd.h" 80 81#include <sys/param.h> 82#include <sys/systm.h> 83#include <sys/callout.h> 84#include <sys/mbuf.h> 85#include <sys/malloc.h> 86#include <sys/kernel.h> 87#include <sys/socket.h> 88#include <sys/ioctl.h> 89#include <sys/errno.h> 90#include <sys/device.h> 91 92#include <machine/endian.h> 93 94#include <uvm/uvm_extern.h> 95 96#if NRND > 0 97#include <sys/rnd.h> 98#endif 99 100#include <net/if.h> 101#include <net/if_dl.h> 102#include <net/if_media.h> 103#include <net/if_ether.h> 104 105#if NBPFILTER > 0 106#include <net/bpf.h> 107#endif 108 109#include <machine/bus.h> 110#include <machine/intr.h> 111 112#include <dev/mii/miivar.h> 113 114#include <dev/ic/i82557reg.h> 115#include <dev/ic/i82557var.h> 116 117#include <dev/microcode/i8255x/rcvbundl.h> 118 119/* 120 * NOTE! On the Alpha, we have an alignment constraint. The 121 * card DMAs the packet immediately following the RFA. However, 122 * the first thing in the packet is a 14-byte Ethernet header. 123 * This means that the packet is misaligned. To compensate, 124 * we actually offset the RFA 2 bytes into the cluster. This 125 * alignes the packet after the Ethernet header at a 32-bit 126 * boundary. HOWEVER! This means that the RFA is misaligned! 127 */ 128#define RFA_ALIGNMENT_FUDGE 2 129 130/* 131 * The configuration byte map has several undefined fields which 132 * must be one or must be zero. Set up a template for these bits 133 * only (assuming an i82557 chip), leaving the actual configuration 134 * for fxp_init(). 135 * 136 * See the definition of struct fxp_cb_config for the bit definitions. 137 */ 138const u_int8_t fxp_cb_config_template[] = { 139 0x0, 0x0, /* cb_status */ 140 0x0, 0x0, /* cb_command */ 141 0x0, 0x0, 0x0, 0x0, /* link_addr */ 142 0x0, /* 0 */ 143 0x0, /* 1 */ 144 0x0, /* 2 */ 145 0x0, /* 3 */ 146 0x0, /* 4 */ 147 0x0, /* 5 */ 148 0x32, /* 6 */ 149 0x0, /* 7 */ 150 0x0, /* 8 */ 151 0x0, /* 9 */ 152 0x6, /* 10 */ 153 0x0, /* 11 */ 154 0x0, /* 12 */ 155 0x0, /* 13 */ 156 0xf2, /* 14 */ 157 0x48, /* 15 */ 158 0x0, /* 16 */ 159 0x40, /* 17 */ 160 0xf0, /* 18 */ 161 0x0, /* 19 */ 162 0x3f, /* 20 */ 163 0x5, /* 21 */ 164 0x0, /* 22 */ 165 0x0, /* 23 */ 166 0x0, /* 24 */ 167 0x0, /* 25 */ 168 0x0, /* 26 */ 169 0x0, /* 27 */ 170 0x0, /* 28 */ 171 0x0, /* 29 */ 172 0x0, /* 30 */ 173 0x0, /* 31 */ 174}; 175 176void fxp_mii_initmedia(struct fxp_softc *); 177int fxp_mii_mediachange(struct ifnet *); 178void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 179 180void fxp_80c24_initmedia(struct fxp_softc *); 181int fxp_80c24_mediachange(struct ifnet *); 182void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 183 184void fxp_start(struct ifnet *); 185int fxp_ioctl(struct ifnet *, u_long, caddr_t); 186void fxp_watchdog(struct ifnet *); 187int fxp_init(struct ifnet *); 188void fxp_stop(struct ifnet *, int); 189 190void fxp_txintr(struct fxp_softc *); 191void fxp_rxintr(struct fxp_softc *); 192 193void fxp_rxdrain(struct fxp_softc *); 194int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 195int fxp_mdi_read(struct device *, int, int); 196void fxp_statchg(struct device *); 197void fxp_mdi_write(struct device *, int, int, int); 198void fxp_autosize_eeprom(struct fxp_softc*); 199void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 200void fxp_write_eeprom(struct fxp_softc *, u_int16_t *, int, int); 201void fxp_eeprom_update_cksum(struct fxp_softc *); 202void fxp_get_info(struct fxp_softc *, u_int8_t *); 203void fxp_tick(void *); 204void fxp_mc_setup(struct fxp_softc *); 205void fxp_load_ucode(struct fxp_softc *); 206 207void fxp_shutdown(void *); 208void fxp_power(int, void *); 209 210int fxp_copy_small = 0; 211 212/* 213 * Variables for interrupt mitigating microcode. 214 */ 215int fxp_int_delay = 1000; /* usec */ 216int fxp_bundle_max = 6; /* packets */ 217 218struct fxp_phytype { 219 int fp_phy; /* type of PHY, -1 for MII at the end. */ 220 void (*fp_init)(struct fxp_softc *); 221} fxp_phytype_table[] = { 222 { FXP_PHY_80C24, fxp_80c24_initmedia }, 223 { -1, fxp_mii_initmedia }, 224}; 225 226/* 227 * Set initial transmit threshold at 64 (512 bytes). This is 228 * increased by 64 (512 bytes) at a time, to maximum of 192 229 * (1536 bytes), if an underrun occurs. 230 */ 231static int tx_threshold = 64; 232 233/* 234 * Wait for the previous command to be accepted (but not necessarily 235 * completed). 236 */ 237static __inline void 238fxp_scb_wait(struct fxp_softc *sc) 239{ 240 int i = 10000; 241 242 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 243 delay(2); 244 if (i == 0) 245 printf("%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 246} 247 248/* 249 * Submit a command to the i82557. 250 */ 251static __inline void 252fxp_scb_cmd(struct fxp_softc *sc, u_int8_t cmd) 253{ 254 255 if (cmd == FXP_SCB_COMMAND_CU_RESUME && 256 (sc->sc_flags & FXPF_FIX_RESUME_BUG) != 0) { 257 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_NOP); 258 fxp_scb_wait(sc); 259 } 260 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 261} 262 263/* 264 * Finish attaching an i82557 interface. Called by bus-specific front-end. 265 */ 266void 267fxp_attach(struct fxp_softc *sc) 268{ 269 u_int8_t enaddr[ETHER_ADDR_LEN]; 270 struct ifnet *ifp; 271 bus_dma_segment_t seg; 272 int rseg, i, error; 273 struct fxp_phytype *fp; 274 275 callout_init(&sc->sc_callout); 276 277 /* Start out using the standard RFA. */ 278 sc->sc_rfa_size = RFA_SIZE; 279 280 /* 281 * Enable some good stuff on i82558 and later. 282 */ 283 if (sc->sc_rev >= FXP_REV_82558_A4) { 284 /* Enable the extended TxCB. */ 285 sc->sc_flags |= FXPF_EXT_TXCB; 286 } 287 288 /* 289 * Allocate the control data structures, and create and load the 290 * DMA map for it. 291 */ 292 if ((error = bus_dmamem_alloc(sc->sc_dmat, 293 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 294 0)) != 0) { 295 printf("%s: unable to allocate control data, error = %d\n", 296 sc->sc_dev.dv_xname, error); 297 goto fail_0; 298 } 299 300 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 301 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 302 BUS_DMA_COHERENT)) != 0) { 303 printf("%s: unable to map control data, error = %d\n", 304 sc->sc_dev.dv_xname, error); 305 goto fail_1; 306 } 307 sc->sc_cdseg = seg; 308 sc->sc_cdnseg = rseg; 309 310 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 311 312 if ((error = bus_dmamap_create(sc->sc_dmat, 313 sizeof(struct fxp_control_data), 1, 314 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 315 printf("%s: unable to create control data DMA map, " 316 "error = %d\n", sc->sc_dev.dv_xname, error); 317 goto fail_2; 318 } 319 320 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 321 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 322 0)) != 0) { 323 printf("%s: can't load control data DMA map, error = %d\n", 324 sc->sc_dev.dv_xname, error); 325 goto fail_3; 326 } 327 328 /* 329 * Create the transmit buffer DMA maps. 330 */ 331 for (i = 0; i < FXP_NTXCB; i++) { 332 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 333 FXP_NTXSEG, MCLBYTES, 0, 0, 334 &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 335 printf("%s: unable to create tx DMA map %d, " 336 "error = %d\n", sc->sc_dev.dv_xname, i, error); 337 goto fail_4; 338 } 339 } 340 341 /* 342 * Create the receive buffer DMA maps. 343 */ 344 for (i = 0; i < FXP_NRFABUFS; i++) { 345 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 346 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 347 printf("%s: unable to create rx DMA map %d, " 348 "error = %d\n", sc->sc_dev.dv_xname, i, error); 349 goto fail_5; 350 } 351 } 352 353 /* Initialize MAC address and media structures. */ 354 fxp_get_info(sc, enaddr); 355 356 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 357 ether_sprintf(enaddr)); 358 359 ifp = &sc->sc_ethercom.ec_if; 360 361 /* 362 * Get info about our media interface, and initialize it. Note 363 * the table terminates itself with a phy of -1, indicating 364 * that we're using MII. 365 */ 366 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 367 if (fp->fp_phy == sc->phy_primary_device) 368 break; 369 (*fp->fp_init)(sc); 370 371 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 372 ifp->if_softc = sc; 373 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 374 ifp->if_ioctl = fxp_ioctl; 375 ifp->if_start = fxp_start; 376 ifp->if_watchdog = fxp_watchdog; 377 ifp->if_init = fxp_init; 378 ifp->if_stop = fxp_stop; 379 IFQ_SET_READY(&ifp->if_snd); 380 381 /* 382 * We can support 802.1Q VLAN-sized frames. 383 */ 384 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 385 386 /* 387 * Attach the interface. 388 */ 389 if_attach(ifp); 390 ether_ifattach(ifp, enaddr); 391#if NRND > 0 392 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 393 RND_TYPE_NET, 0); 394#endif 395 396#ifdef FXP_EVENT_COUNTERS 397 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 398 NULL, sc->sc_dev.dv_xname, "txstall"); 399 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 400 NULL, sc->sc_dev.dv_xname, "txintr"); 401 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 402 NULL, sc->sc_dev.dv_xname, "rxintr"); 403#endif /* FXP_EVENT_COUNTERS */ 404 405 /* 406 * Add shutdown hook so that DMA is disabled prior to reboot. Not 407 * doing do could allow DMA to corrupt kernel memory during the 408 * reboot before the driver initializes. 409 */ 410 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 411 if (sc->sc_sdhook == NULL) 412 printf("%s: WARNING: unable to establish shutdown hook\n", 413 sc->sc_dev.dv_xname); 414 /* 415 * Add suspend hook, for similar reasons.. 416 */ 417 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 418 if (sc->sc_powerhook == NULL) 419 printf("%s: WARNING: unable to establish power hook\n", 420 sc->sc_dev.dv_xname); 421 422 /* The attach is successful. */ 423 sc->sc_flags |= FXPF_ATTACHED; 424 425 return; 426 427 /* 428 * Free any resources we've allocated during the failed attach 429 * attempt. Do this in reverse order and fall though. 430 */ 431 fail_5: 432 for (i = 0; i < FXP_NRFABUFS; i++) { 433 if (sc->sc_rxmaps[i] != NULL) 434 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 435 } 436 fail_4: 437 for (i = 0; i < FXP_NTXCB; i++) { 438 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 439 bus_dmamap_destroy(sc->sc_dmat, 440 FXP_DSTX(sc, i)->txs_dmamap); 441 } 442 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 443 fail_3: 444 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 445 fail_2: 446 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 447 sizeof(struct fxp_control_data)); 448 fail_1: 449 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 450 fail_0: 451 return; 452} 453 454void 455fxp_mii_initmedia(struct fxp_softc *sc) 456{ 457 int flags; 458 459 sc->sc_flags |= FXPF_MII; 460 461 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 462 sc->sc_mii.mii_readreg = fxp_mdi_read; 463 sc->sc_mii.mii_writereg = fxp_mdi_write; 464 sc->sc_mii.mii_statchg = fxp_statchg; 465 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_mii_mediachange, 466 fxp_mii_mediastatus); 467 468 flags = MIIF_NOISOLATE; 469 if (sc->sc_rev >= FXP_REV_82558_A4) 470 flags |= MIIF_DOPAUSE; 471 /* 472 * The i82557 wedges if all of its PHYs are isolated! 473 */ 474 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 475 MII_OFFSET_ANY, flags); 476 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 477 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 478 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 479 } else 480 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 481} 482 483void 484fxp_80c24_initmedia(struct fxp_softc *sc) 485{ 486 487 /* 488 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 489 * doesn't have a programming interface of any sort. The 490 * media is sensed automatically based on how the link partner 491 * is configured. This is, in essence, manual configuration. 492 */ 493 printf("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 494 sc->sc_dev.dv_xname); 495 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 496 fxp_80c24_mediastatus); 497 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 498 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 499} 500 501/* 502 * Device shutdown routine. Called at system shutdown after sync. The 503 * main purpose of this routine is to shut off receiver DMA so that 504 * kernel memory doesn't get clobbered during warmboot. 505 */ 506void 507fxp_shutdown(void *arg) 508{ 509 struct fxp_softc *sc = arg; 510 511 /* 512 * Since the system's going to halt shortly, don't bother 513 * freeing mbufs. 514 */ 515 fxp_stop(&sc->sc_ethercom.ec_if, 0); 516} 517/* 518 * Power handler routine. Called when the system is transitioning 519 * into/out of power save modes. As with fxp_shutdown, the main 520 * purpose of this routine is to shut off receiver DMA so it doesn't 521 * clobber kernel memory at the wrong time. 522 */ 523void 524fxp_power(int why, void *arg) 525{ 526 struct fxp_softc *sc = arg; 527 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 528 int s; 529 530 s = splnet(); 531 switch (why) { 532 case PWR_SUSPEND: 533 case PWR_STANDBY: 534 fxp_stop(ifp, 0); 535 break; 536 case PWR_RESUME: 537 if (ifp->if_flags & IFF_UP) 538 fxp_init(ifp); 539 break; 540 case PWR_SOFTSUSPEND: 541 case PWR_SOFTSTANDBY: 542 case PWR_SOFTRESUME: 543 break; 544 } 545 splx(s); 546} 547 548/* 549 * Initialize the interface media. 550 */ 551void 552fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 553{ 554 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 555 556 /* 557 * Reset to a stable state. 558 */ 559 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 560 DELAY(10); 561 562 sc->sc_eeprom_size = 0; 563 fxp_autosize_eeprom(sc); 564 if(sc->sc_eeprom_size == 0) { 565 printf("%s: failed to detect EEPROM size\n", sc->sc_dev.dv_xname); 566 sc->sc_eeprom_size = 6; /* XXX panic here? */ 567 } 568#ifdef DEBUG 569 printf("%s: detected %d word EEPROM\n", 570 sc->sc_dev.dv_xname, 571 1 << sc->sc_eeprom_size); 572#endif 573 574 /* 575 * Get info about the primary PHY 576 */ 577 fxp_read_eeprom(sc, &data, 6, 1); 578 sc->phy_primary_device = 579 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 580 581 /* 582 * Read MAC address. 583 */ 584 fxp_read_eeprom(sc, myea, 0, 3); 585 enaddr[0] = myea[0] & 0xff; 586 enaddr[1] = myea[0] >> 8; 587 enaddr[2] = myea[1] & 0xff; 588 enaddr[3] = myea[1] >> 8; 589 enaddr[4] = myea[2] & 0xff; 590 enaddr[5] = myea[2] >> 8; 591 592 /* 593 * Systems based on the ICH2/ICH2-M chip from Intel, as well 594 * as some i82559 designs, have a defect where the chip can 595 * cause a PCI protocol violation if it receives a CU_RESUME 596 * command when it is entering the IDLE state. 597 * 598 * The work-around is to disable Dynamic Standby Mode, so that 599 * the chip never deasserts #CLKRUN, and always remains in the 600 * active state. 601 * 602 * Unfortunately, the only way to disable Dynamic Standby is 603 * to frob an EEPROM setting and reboot (the EEPROM setting 604 * is only consulted when the PCI bus comes out of reset). 605 * 606 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 607 */ 608 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 609 fxp_read_eeprom(sc, &data, 10, 1); 610 if (data & 0x02) { /* STB enable */ 611 printf("%s: disabling Dynamic Standby Mode in EEPROM\n", 612 sc->sc_dev.dv_xname); 613 data &= ~0x02; 614 fxp_write_eeprom(sc, &data, 10, 1); 615 printf("%s: new EEPROM ID: 0x%04x\n", 616 sc->sc_dev.dv_xname, data); 617 fxp_eeprom_update_cksum(sc); 618 printf("%s: PLEASE RESET YOUR SYSTEM FOR CHANGE TO " 619 "TAKE EFFECT!\n", sc->sc_dev.dv_xname); 620 } else { 621#if 1 622 /* 623 * If Dynamic Standby Mode is disabled, we don't 624 * need to work around the Resume bug anymore. 625 */ 626 sc->sc_flags &= ~FXPF_HAS_RESUME_BUG; 627#endif 628 } 629 } 630} 631 632static void 633fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 634{ 635 uint16_t reg; 636 int x; 637 638 for (x = 1 << (len - 1); x != 0; x >>= 1) { 639 if (data & x) 640 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 641 else 642 reg = FXP_EEPROM_EECS; 643 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 644 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 645 reg | FXP_EEPROM_EESK); 646 DELAY(4); 647 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 648 DELAY(4); 649 } 650} 651 652/* 653 * Figure out EEPROM size. 654 * 655 * 559's can have either 64-word or 256-word EEPROMs, the 558 656 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 657 * talks about the existance of 16 to 256 word EEPROMs. 658 * 659 * The only known sizes are 64 and 256, where the 256 version is used 660 * by CardBus cards to store CIS information. 661 * 662 * The address is shifted in msb-to-lsb, and after the last 663 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 664 * after which follows the actual data. We try to detect this zero, by 665 * probing the data-out bit in the EEPROM control register just after 666 * having shifted in a bit. If the bit is zero, we assume we've 667 * shifted enough address bits. The data-out should be tri-state, 668 * before this, which should translate to a logical one. 669 * 670 * Other ways to do this would be to try to read a register with known 671 * contents with a varying number of address bits, but no such 672 * register seem to be available. The high bits of register 10 are 01 673 * on the 558 and 559, but apparently not on the 557. 674 * 675 * The Linux driver computes a checksum on the EEPROM data, but the 676 * value of this checksum is not very well documented. 677 */ 678 679void 680fxp_autosize_eeprom(struct fxp_softc *sc) 681{ 682 int x; 683 684 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 685 686 /* Shift in read opcode. */ 687 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 688 689 /* 690 * Shift in address, wait for the dummy zero following a correct 691 * address shift. 692 */ 693 for (x = 1; x <= 8; x++) { 694 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 695 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 696 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 697 DELAY(4); 698 if((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 699 FXP_EEPROM_EEDO) == 0) 700 break; 701 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 702 DELAY(4); 703 } 704 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 705 DELAY(4); 706 if(x != 6 && x != 8) { 707#ifdef DEBUG 708 printf("%s: strange EEPROM size (%d)\n", 709 sc->sc_dev.dv_xname, 1 << x); 710#endif 711 } else 712 sc->sc_eeprom_size = x; 713} 714 715/* 716 * Read from the serial EEPROM. Basically, you manually shift in 717 * the read opcode (one bit at a time) and then shift in the address, 718 * and then you shift out the data (all of this one bit at a time). 719 * The word size is 16 bits, so you have to provide the address for 720 * every 16 bits of data. 721 */ 722void 723fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 724{ 725 u_int16_t reg; 726 int i, x; 727 728 for (i = 0; i < words; i++) { 729 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 730 731 /* Shift in read opcode. */ 732 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 733 734 /* Shift in address. */ 735 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 736 737 reg = FXP_EEPROM_EECS; 738 data[i] = 0; 739 740 /* Shift out data. */ 741 for (x = 16; x > 0; x--) { 742 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 743 reg | FXP_EEPROM_EESK); 744 DELAY(4); 745 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 746 FXP_EEPROM_EEDO) 747 data[i] |= (1 << (x - 1)); 748 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 749 DELAY(4); 750 } 751 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 752 DELAY(4); 753 } 754} 755 756/* 757 * Write data to the serial EEPROM. 758 */ 759void 760fxp_write_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 761{ 762 int i, j; 763 764 for (i = 0; i < words; i++) { 765 /* Erase/write enable. */ 766 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 767 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 768 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 769 sc->sc_eeprom_size); 770 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 771 DELAY(4); 772 773 /* Shift in write opcode, address, data. */ 774 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 775 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 776 fxp_eeprom_shiftin(sc, offset, sc->sc_eeprom_size); 777 fxp_eeprom_shiftin(sc, data[i], 16); 778 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 779 DELAY(4); 780 781 /* Wait for the EEPROM to finish up. */ 782 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 783 DELAY(4); 784 for (j = 0; j < 1000; j++) { 785 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 786 FXP_EEPROM_EEDO) 787 break; 788 DELAY(50); 789 } 790 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 791 DELAY(4); 792 793 /* Erase/write disable. */ 794 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 795 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 796 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 797 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 798 DELAY(4); 799 } 800} 801 802/* 803 * Update the checksum of the EEPROM. 804 */ 805void 806fxp_eeprom_update_cksum(struct fxp_softc *sc) 807{ 808 int i; 809 uint16_t data, cksum; 810 811 cksum = 0; 812 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 813 fxp_read_eeprom(sc, &data, i, 1); 814 cksum += data; 815 } 816 i = (1 << sc->sc_eeprom_size) - 1; 817 cksum = 0xbaba - cksum; 818 fxp_read_eeprom(sc, &data, i, 1); 819 fxp_write_eeprom(sc, &cksum, i, 1); 820 printf("%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 821 sc->sc_dev.dv_xname, i, data, cksum); 822} 823 824/* 825 * Start packet transmission on the interface. 826 */ 827void 828fxp_start(struct ifnet *ifp) 829{ 830 struct fxp_softc *sc = ifp->if_softc; 831 struct mbuf *m0, *m; 832 struct fxp_txdesc *txd; 833 struct fxp_txsoft *txs; 834 bus_dmamap_t dmamap; 835 int error, lasttx, nexttx, opending, seg; 836 837 /* 838 * If we want a re-init, bail out now. 839 */ 840 if (sc->sc_flags & FXPF_WANTINIT) { 841 ifp->if_flags |= IFF_OACTIVE; 842 return; 843 } 844 845 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 846 return; 847 848 /* 849 * Remember the previous txpending and the current lasttx. 850 */ 851 opending = sc->sc_txpending; 852 lasttx = sc->sc_txlast; 853 854 /* 855 * Loop through the send queue, setting up transmit descriptors 856 * until we drain the queue, or use up all available transmit 857 * descriptors. 858 */ 859 for (;;) { 860 /* 861 * Grab a packet off the queue. 862 */ 863 IFQ_POLL(&ifp->if_snd, m0); 864 if (m0 == NULL) 865 break; 866 m = NULL; 867 868 if (sc->sc_txpending == FXP_NTXCB) { 869 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 870 break; 871 } 872 873 /* 874 * Get the next available transmit descriptor. 875 */ 876 nexttx = FXP_NEXTTX(sc->sc_txlast); 877 txd = FXP_CDTX(sc, nexttx); 878 txs = FXP_DSTX(sc, nexttx); 879 dmamap = txs->txs_dmamap; 880 881 /* 882 * Load the DMA map. If this fails, the packet either 883 * didn't fit in the allotted number of frags, or we were 884 * short on resources. In this case, we'll copy and try 885 * again. 886 */ 887 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 888 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 889 MGETHDR(m, M_DONTWAIT, MT_DATA); 890 if (m == NULL) { 891 printf("%s: unable to allocate Tx mbuf\n", 892 sc->sc_dev.dv_xname); 893 break; 894 } 895 if (m0->m_pkthdr.len > MHLEN) { 896 MCLGET(m, M_DONTWAIT); 897 if ((m->m_flags & M_EXT) == 0) { 898 printf("%s: unable to allocate Tx " 899 "cluster\n", sc->sc_dev.dv_xname); 900 m_freem(m); 901 break; 902 } 903 } 904 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 905 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 906 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 907 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 908 if (error) { 909 printf("%s: unable to load Tx buffer, " 910 "error = %d\n", sc->sc_dev.dv_xname, error); 911 break; 912 } 913 } 914 915 IFQ_DEQUEUE(&ifp->if_snd, m0); 916 if (m != NULL) { 917 m_freem(m0); 918 m0 = m; 919 } 920 921 /* Initialize the fraglist. */ 922 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 923 txd->txd_tbd[seg].tb_addr = 924 htole32(dmamap->dm_segs[seg].ds_addr); 925 txd->txd_tbd[seg].tb_size = 926 htole32(dmamap->dm_segs[seg].ds_len); 927 } 928 929 /* Sync the DMA map. */ 930 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 931 BUS_DMASYNC_PREWRITE); 932 933 /* 934 * Store a pointer to the packet so we can free it later. 935 */ 936 txs->txs_mbuf = m0; 937 938 /* 939 * Initialize the transmit descriptor. 940 */ 941 /* BIG_ENDIAN: no need to swap to store 0 */ 942 txd->txd_txcb.cb_status = 0; 943 txd->txd_txcb.cb_command = 944 htole16(FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF); 945 txd->txd_txcb.tx_threshold = tx_threshold; 946 txd->txd_txcb.tbd_number = dmamap->dm_nsegs; 947 948 FXP_CDTXSYNC(sc, nexttx, 949 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 950 951 /* Advance the tx pointer. */ 952 sc->sc_txpending++; 953 sc->sc_txlast = nexttx; 954 955#if NBPFILTER > 0 956 /* 957 * Pass packet to bpf if there is a listener. 958 */ 959 if (ifp->if_bpf) 960 bpf_mtap(ifp->if_bpf, m0); 961#endif 962 } 963 964 if (sc->sc_txpending == FXP_NTXCB) { 965 /* No more slots; notify upper layer. */ 966 ifp->if_flags |= IFF_OACTIVE; 967 } 968 969 if (sc->sc_txpending != opending) { 970 /* 971 * We enqueued packets. If the transmitter was idle, 972 * reset the txdirty pointer. 973 */ 974 if (opending == 0) 975 sc->sc_txdirty = FXP_NEXTTX(lasttx); 976 977 /* 978 * Cause the chip to interrupt and suspend command 979 * processing once the last packet we've enqueued 980 * has been transmitted. 981 */ 982 FXP_CDTX(sc, sc->sc_txlast)->txd_txcb.cb_command |= 983 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 984 FXP_CDTXSYNC(sc, sc->sc_txlast, 985 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 986 987 /* 988 * The entire packet chain is set up. Clear the suspend bit 989 * on the command prior to the first packet we set up. 990 */ 991 FXP_CDTXSYNC(sc, lasttx, 992 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 993 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 994 htole16(~FXP_CB_COMMAND_S); 995 FXP_CDTXSYNC(sc, lasttx, 996 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 997 998 /* 999 * Issue a Resume command in case the chip was suspended. 1000 */ 1001 fxp_scb_wait(sc); 1002 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1003 1004 /* Set a watchdog timer in case the chip flakes out. */ 1005 ifp->if_timer = 5; 1006 } 1007} 1008 1009/* 1010 * Process interface interrupts. 1011 */ 1012int 1013fxp_intr(void *arg) 1014{ 1015 struct fxp_softc *sc = arg; 1016 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1017 bus_dmamap_t rxmap; 1018 int claimed = 0; 1019 u_int8_t statack; 1020 1021 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1022 return (0); 1023 /* 1024 * If the interface isn't running, don't try to 1025 * service the interrupt.. just ack it and bail. 1026 */ 1027 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1028 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1029 if (statack) { 1030 claimed = 1; 1031 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1032 } 1033 return (claimed); 1034 } 1035 1036 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1037 claimed = 1; 1038 1039 /* 1040 * First ACK all the interrupts in this pass. 1041 */ 1042 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1043 1044 /* 1045 * Process receiver interrupts. If a no-resource (RNR) 1046 * condition exists, get whatever packets we can and 1047 * re-start the receiver. 1048 */ 1049 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 1050 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1051 fxp_rxintr(sc); 1052 } 1053 1054 if (statack & FXP_SCB_STATACK_RNR) { 1055 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1056 fxp_scb_wait(sc); 1057 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1058 rxmap->dm_segs[0].ds_addr + 1059 RFA_ALIGNMENT_FUDGE); 1060 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1061 } 1062 1063 /* 1064 * Free any finished transmit mbuf chains. 1065 */ 1066 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1067 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1068 fxp_txintr(sc); 1069 1070 /* 1071 * Try to get more packets going. 1072 */ 1073 fxp_start(ifp); 1074 1075 if (sc->sc_txpending == 0) { 1076 /* 1077 * If we want a re-init, do that now. 1078 */ 1079 if (sc->sc_flags & FXPF_WANTINIT) 1080 (void) fxp_init(ifp); 1081 } 1082 } 1083 } 1084 1085#if NRND > 0 1086 if (claimed) 1087 rnd_add_uint32(&sc->rnd_source, statack); 1088#endif 1089 return (claimed); 1090} 1091 1092/* 1093 * Handle transmit completion interrupts. 1094 */ 1095void 1096fxp_txintr(struct fxp_softc *sc) 1097{ 1098 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1099 struct fxp_txdesc *txd; 1100 struct fxp_txsoft *txs; 1101 int i; 1102 u_int16_t txstat; 1103 1104 ifp->if_flags &= ~IFF_OACTIVE; 1105 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1106 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1107 txd = FXP_CDTX(sc, i); 1108 txs = FXP_DSTX(sc, i); 1109 1110 FXP_CDTXSYNC(sc, i, 1111 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1112 1113 txstat = le16toh(txd->txd_txcb.cb_status); 1114 1115 if ((txstat & FXP_CB_STATUS_C) == 0) 1116 break; 1117 1118 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1119 0, txs->txs_dmamap->dm_mapsize, 1120 BUS_DMASYNC_POSTWRITE); 1121 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1122 m_freem(txs->txs_mbuf); 1123 txs->txs_mbuf = NULL; 1124 } 1125 1126 /* Update the dirty transmit buffer pointer. */ 1127 sc->sc_txdirty = i; 1128 1129 /* 1130 * Cancel the watchdog timer if there are no pending 1131 * transmissions. 1132 */ 1133 if (sc->sc_txpending == 0) 1134 ifp->if_timer = 0; 1135} 1136 1137/* 1138 * Handle receive interrupts. 1139 */ 1140void 1141fxp_rxintr(struct fxp_softc *sc) 1142{ 1143 struct ethercom *ec = &sc->sc_ethercom; 1144 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1145 struct mbuf *m, *m0; 1146 bus_dmamap_t rxmap; 1147 struct fxp_rfa *rfa; 1148 u_int16_t len, rxstat; 1149 1150 for (;;) { 1151 m = sc->sc_rxq.ifq_head; 1152 rfa = FXP_MTORFA(m); 1153 rxmap = M_GETCTX(m, bus_dmamap_t); 1154 1155 FXP_RFASYNC(sc, m, 1156 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1157 1158 rxstat = le16toh(rfa->rfa_status); 1159 1160 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1161 /* 1162 * We have processed all of the 1163 * receive buffers. 1164 */ 1165 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1166 return; 1167 } 1168 1169 IF_DEQUEUE(&sc->sc_rxq, m); 1170 1171 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1172 1173 len = le16toh(rfa->actual_size) & 1174 (m->m_ext.ext_size - 1); 1175 1176 if (len < sizeof(struct ether_header)) { 1177 /* 1178 * Runt packet; drop it now. 1179 */ 1180 FXP_INIT_RFABUF(sc, m); 1181 continue; 1182 } 1183 1184 /* 1185 * If support for 802.1Q VLAN sized frames is 1186 * enabled, we need to do some additional error 1187 * checking (as we are saving bad frames, in 1188 * order to receive the larger ones). 1189 */ 1190 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1191 (rxstat & (FXP_RFA_STATUS_OVERRUN| 1192 FXP_RFA_STATUS_RNR| 1193 FXP_RFA_STATUS_ALIGN| 1194 FXP_RFA_STATUS_CRC)) != 0) { 1195 FXP_INIT_RFABUF(sc, m); 1196 continue; 1197 } 1198 1199 /* 1200 * If the packet is small enough to fit in a 1201 * single header mbuf, allocate one and copy 1202 * the data into it. This greatly reduces 1203 * memory consumption when we receive lots 1204 * of small packets. 1205 * 1206 * Otherwise, we add a new buffer to the receive 1207 * chain. If this fails, we drop the packet and 1208 * recycle the old buffer. 1209 */ 1210 if (fxp_copy_small != 0 && len <= MHLEN) { 1211 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1212 if (m == NULL) 1213 goto dropit; 1214 memcpy(mtod(m0, caddr_t), 1215 mtod(m, caddr_t), len); 1216 FXP_INIT_RFABUF(sc, m); 1217 m = m0; 1218 } else { 1219 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1220 dropit: 1221 ifp->if_ierrors++; 1222 FXP_INIT_RFABUF(sc, m); 1223 continue; 1224 } 1225 } 1226 1227 m->m_pkthdr.rcvif = ifp; 1228 m->m_pkthdr.len = m->m_len = len; 1229 1230#if NBPFILTER > 0 1231 /* 1232 * Pass this up to any BPF listeners, but only 1233 * pass it up the stack it its for us. 1234 */ 1235 if (ifp->if_bpf) 1236 bpf_mtap(ifp->if_bpf, m); 1237#endif 1238 1239 /* Pass it on. */ 1240 (*ifp->if_input)(ifp, m); 1241 } 1242} 1243 1244/* 1245 * Update packet in/out/collision statistics. The i82557 doesn't 1246 * allow you to access these counters without doing a fairly 1247 * expensive DMA to get _all_ of the statistics it maintains, so 1248 * we do this operation here only once per second. The statistics 1249 * counters in the kernel are updated from the previous dump-stats 1250 * DMA and then a new dump-stats DMA is started. The on-chip 1251 * counters are zeroed when the DMA completes. If we can't start 1252 * the DMA immediately, we don't wait - we just prepare to read 1253 * them again next time. 1254 */ 1255void 1256fxp_tick(void *arg) 1257{ 1258 struct fxp_softc *sc = arg; 1259 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1260 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1261 int s; 1262 1263 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1264 return; 1265 1266 s = splnet(); 1267 1268 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1269 1270 ifp->if_opackets += le32toh(sp->tx_good); 1271 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1272 if (sp->rx_good) { 1273 ifp->if_ipackets += le32toh(sp->rx_good); 1274 sc->sc_rxidle = 0; 1275 } else { 1276 sc->sc_rxidle++; 1277 } 1278 ifp->if_ierrors += 1279 le32toh(sp->rx_crc_errors) + 1280 le32toh(sp->rx_alignment_errors) + 1281 le32toh(sp->rx_rnr_errors) + 1282 le32toh(sp->rx_overrun_errors); 1283 /* 1284 * If any transmit underruns occurred, bump up the transmit 1285 * threshold by another 512 bytes (64 * 8). 1286 */ 1287 if (sp->tx_underruns) { 1288 ifp->if_oerrors += le32toh(sp->tx_underruns); 1289 if (tx_threshold < 192) 1290 tx_threshold += 64; 1291 } 1292 1293 /* 1294 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1295 * then assume the receiver has locked up and attempt to clear 1296 * the condition by reprogramming the multicast filter (actually, 1297 * resetting the interface). This is a work-around for a bug in 1298 * the 82557 where the receiver locks up if it gets certain types 1299 * of garbage in the syncronization bits prior to the packet header. 1300 * This bug is supposed to only occur in 10Mbps mode, but has been 1301 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1302 * speed transition). 1303 */ 1304 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1305 (void) fxp_init(ifp); 1306 splx(s); 1307 return; 1308 } 1309 /* 1310 * If there is no pending command, start another stats 1311 * dump. Otherwise punt for now. 1312 */ 1313 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1314 /* 1315 * Start another stats dump. 1316 */ 1317 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1318 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1319 } else { 1320 /* 1321 * A previous command is still waiting to be accepted. 1322 * Just zero our copy of the stats and wait for the 1323 * next timer event to update them. 1324 */ 1325 /* BIG_ENDIAN: no swap required to store 0 */ 1326 sp->tx_good = 0; 1327 sp->tx_underruns = 0; 1328 sp->tx_total_collisions = 0; 1329 1330 sp->rx_good = 0; 1331 sp->rx_crc_errors = 0; 1332 sp->rx_alignment_errors = 0; 1333 sp->rx_rnr_errors = 0; 1334 sp->rx_overrun_errors = 0; 1335 } 1336 1337 if (sc->sc_flags & FXPF_MII) { 1338 /* Tick the MII clock. */ 1339 mii_tick(&sc->sc_mii); 1340 } 1341 1342 splx(s); 1343 1344 /* 1345 * Schedule another timeout one second from now. 1346 */ 1347 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1348} 1349 1350/* 1351 * Drain the receive queue. 1352 */ 1353void 1354fxp_rxdrain(struct fxp_softc *sc) 1355{ 1356 bus_dmamap_t rxmap; 1357 struct mbuf *m; 1358 1359 for (;;) { 1360 IF_DEQUEUE(&sc->sc_rxq, m); 1361 if (m == NULL) 1362 break; 1363 rxmap = M_GETCTX(m, bus_dmamap_t); 1364 bus_dmamap_unload(sc->sc_dmat, rxmap); 1365 FXP_RXMAP_PUT(sc, rxmap); 1366 m_freem(m); 1367 } 1368} 1369 1370/* 1371 * Stop the interface. Cancels the statistics updater and resets 1372 * the interface. 1373 */ 1374void 1375fxp_stop(struct ifnet *ifp, int disable) 1376{ 1377 struct fxp_softc *sc = ifp->if_softc; 1378 struct fxp_txsoft *txs; 1379 int i; 1380 1381 /* 1382 * Turn down interface (done early to avoid bad interactions 1383 * between panics, shutdown hooks, and the watchdog timer) 1384 */ 1385 ifp->if_timer = 0; 1386 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1387 1388 /* 1389 * Cancel stats updater. 1390 */ 1391 callout_stop(&sc->sc_callout); 1392 if (sc->sc_flags & FXPF_MII) { 1393 /* Down the MII. */ 1394 mii_down(&sc->sc_mii); 1395 } 1396 1397 /* 1398 * Issue software reset. This unloads any microcode that 1399 * might already be loaded. 1400 */ 1401 sc->sc_flags &= ~FXPF_UCODE_LOADED; 1402 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1403 DELAY(50); 1404 1405 /* 1406 * Release any xmit buffers. 1407 */ 1408 for (i = 0; i < FXP_NTXCB; i++) { 1409 txs = FXP_DSTX(sc, i); 1410 if (txs->txs_mbuf != NULL) { 1411 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1412 m_freem(txs->txs_mbuf); 1413 txs->txs_mbuf = NULL; 1414 } 1415 } 1416 sc->sc_txpending = 0; 1417 1418 if (disable) { 1419 fxp_rxdrain(sc); 1420 fxp_disable(sc); 1421 } 1422 1423} 1424 1425/* 1426 * Watchdog/transmission transmit timeout handler. Called when a 1427 * transmission is started on the interface, but no interrupt is 1428 * received before the timeout. This usually indicates that the 1429 * card has wedged for some reason. 1430 */ 1431void 1432fxp_watchdog(struct ifnet *ifp) 1433{ 1434 struct fxp_softc *sc = ifp->if_softc; 1435 1436 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1437 ifp->if_oerrors++; 1438 1439 (void) fxp_init(ifp); 1440} 1441 1442/* 1443 * Initialize the interface. Must be called at splnet(). 1444 */ 1445int 1446fxp_init(struct ifnet *ifp) 1447{ 1448 struct fxp_softc *sc = ifp->if_softc; 1449 struct fxp_cb_config *cbp; 1450 struct fxp_cb_ias *cb_ias; 1451 struct fxp_txdesc *txd; 1452 bus_dmamap_t rxmap; 1453 int i, prm, save_bf, lrxen, allm, error = 0; 1454 1455 if ((error = fxp_enable(sc)) != 0) 1456 goto out; 1457 1458 /* 1459 * Cancel any pending I/O 1460 */ 1461 fxp_stop(ifp, 0); 1462 1463 /* 1464 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1465 * flag, and this prevents the MII from detaching resulting in 1466 * a panic. The flags field should perhaps be split in runtime 1467 * flags and more static information. For now, just clear the 1468 * only other flag set. 1469 */ 1470 1471 sc->sc_flags &= ~FXPF_WANTINIT; 1472 1473 /* 1474 * Initialize base of CBL and RFA memory. Loading with zero 1475 * sets it up for regular linear addressing. 1476 */ 1477 fxp_scb_wait(sc); 1478 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1479 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1480 1481 fxp_scb_wait(sc); 1482 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1483 1484 /* 1485 * Initialize the multicast filter. Do this now, since we might 1486 * have to setup the config block differently. 1487 */ 1488 fxp_mc_setup(sc); 1489 1490 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1491 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1492 1493 /* 1494 * In order to support receiving 802.1Q VLAN frames, we have to 1495 * enable "save bad frames", since they are 4 bytes larger than 1496 * the normal Ethernet maximum frame length. On i82558 and later, 1497 * we have a better mechanism for this. 1498 */ 1499 save_bf = 0; 1500 lrxen = 0; 1501 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1502 if (sc->sc_rev < FXP_REV_82558_A4) 1503 save_bf = 1; 1504 else 1505 lrxen = 1; 1506 } 1507 1508 /* 1509 * Initialize base of dump-stats buffer. 1510 */ 1511 fxp_scb_wait(sc); 1512 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1513 sc->sc_cddma + FXP_CDSTATSOFF); 1514 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1515 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1516 1517 cbp = &sc->sc_control_data->fcd_configcb; 1518 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1519 1520 /* 1521 * Load microcode for this controller. 1522 */ 1523 fxp_load_ucode(sc); 1524 1525 /* 1526 * This copy is kind of disgusting, but there are a bunch of must be 1527 * zero and must be one bits in this structure and this is the easiest 1528 * way to initialize them all to proper values. 1529 */ 1530 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1531 1532 /* BIG_ENDIAN: no need to swap to store 0 */ 1533 cbp->cb_status = 0; 1534 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1535 FXP_CB_COMMAND_EL); 1536 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1537 cbp->link_addr = 0xffffffff; /* (no) next command */ 1538 /* bytes in config block */ 1539 cbp->byte_count = FXP_CONFIG_LEN; 1540 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1541 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1542 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1543 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1544 cbp->type_enable = 0; /* actually reserved */ 1545 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1546 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1547 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1548 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1549 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1550 cbp->late_scb = 0; /* (don't) defer SCB update */ 1551 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1552 cbp->ci_int = 1; /* interrupt on CU idle */ 1553 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1554 cbp->ext_stats_dis = 1; /* disable extended counters */ 1555 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1556 cbp->save_bf = save_bf;/* save bad frames */ 1557 cbp->disc_short_rx = !prm; /* discard short packets */ 1558 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1559 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1560 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1561 /* interface mode */ 1562 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1563 cbp->csma_dis = 0; /* (don't) disable link */ 1564 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1565 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1566 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1567 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1568 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1569 cbp->nsai = 1; /* (don't) disable source addr insert */ 1570 cbp->preamble_length = 2; /* (7 byte) preamble */ 1571 cbp->loopback = 0; /* (don't) loopback */ 1572 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1573 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1574 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1575 cbp->promiscuous = prm; /* promiscuous mode */ 1576 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1577 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1578 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1579 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1580 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1581 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1582 cbp->padding = 1; /* (do) pad short tx packets */ 1583 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1584 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1585 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1586 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1587 /* must set wake_en in PMCSR also */ 1588 cbp->force_fdx = 0; /* (don't) force full duplex */ 1589 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1590 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1591 cbp->mc_all = allm; /* accept all multicasts */ 1592 1593 if (sc->sc_rev < FXP_REV_82558_A4) { 1594 /* 1595 * The i82557 has no hardware flow control, the values 1596 * here are the defaults for the chip. 1597 */ 1598 cbp->fc_delay_lsb = 0; 1599 cbp->fc_delay_msb = 0x40; 1600 cbp->pri_fc_thresh = 3; 1601 cbp->tx_fc_dis = 0; 1602 cbp->rx_fc_restop = 0; 1603 cbp->rx_fc_restart = 0; 1604 cbp->fc_filter = 0; 1605 cbp->pri_fc_loc = 1; 1606 } else { 1607 cbp->fc_delay_lsb = 0x1f; 1608 cbp->fc_delay_msb = 0x01; 1609 cbp->pri_fc_thresh = 3; 1610 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1611 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1612 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1613 cbp->fc_filter = !prm; /* drop FC frames to host */ 1614 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1615 } 1616 1617 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1618 1619 /* 1620 * Start the config command/DMA. 1621 */ 1622 fxp_scb_wait(sc); 1623 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1624 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1625 /* ...and wait for it to complete. */ 1626 i = 1000; 1627 do { 1628 FXP_CDCONFIGSYNC(sc, 1629 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1630 DELAY(1); 1631 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1632 if (i == 0) { 1633 printf("%s at line %d: dmasync timeout\n", 1634 sc->sc_dev.dv_xname, __LINE__); 1635 return ETIMEDOUT; 1636 } 1637 1638 /* 1639 * Initialize the station address. 1640 */ 1641 cb_ias = &sc->sc_control_data->fcd_iascb; 1642 /* BIG_ENDIAN: no need to swap to store 0 */ 1643 cb_ias->cb_status = 0; 1644 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1645 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1646 cb_ias->link_addr = 0xffffffff; 1647 memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1648 1649 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1650 1651 /* 1652 * Start the IAS (Individual Address Setup) command/DMA. 1653 */ 1654 fxp_scb_wait(sc); 1655 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1656 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1657 /* ...and wait for it to complete. */ 1658 i = 1000; 1659 do { 1660 FXP_CDIASSYNC(sc, 1661 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1662 DELAY(1); 1663 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1664 if (i == 0) { 1665 printf("%s at line %d: dmasync timeout\n", 1666 sc->sc_dev.dv_xname, __LINE__); 1667 return ETIMEDOUT; 1668 } 1669 1670 /* 1671 * Initialize the transmit descriptor ring. txlast is initialized 1672 * to the end of the list so that it will wrap around to the first 1673 * descriptor when the first packet is transmitted. 1674 */ 1675 for (i = 0; i < FXP_NTXCB; i++) { 1676 txd = FXP_CDTX(sc, i); 1677 memset(txd, 0, sizeof(*txd)); 1678 txd->txd_txcb.cb_command = 1679 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1680 txd->txd_txcb.link_addr = 1681 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1682 if (sc->sc_flags & FXPF_EXT_TXCB) 1683 txd->txd_txcb.tbd_array_addr = 1684 htole32(FXP_CDTBDADDR(sc, i) + 1685 (2 * sizeof(struct fxp_tbd))); 1686 else 1687 txd->txd_txcb.tbd_array_addr = 1688 htole32(FXP_CDTBDADDR(sc, i)); 1689 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1690 } 1691 sc->sc_txpending = 0; 1692 sc->sc_txdirty = 0; 1693 sc->sc_txlast = FXP_NTXCB - 1; 1694 1695 /* 1696 * Initialize the receive buffer list. 1697 */ 1698 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1699 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1700 rxmap = FXP_RXMAP_GET(sc); 1701 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1702 printf("%s: unable to allocate or map rx " 1703 "buffer %d, error = %d\n", 1704 sc->sc_dev.dv_xname, 1705 sc->sc_rxq.ifq_len, error); 1706 /* 1707 * XXX Should attempt to run with fewer receive 1708 * XXX buffers instead of just failing. 1709 */ 1710 FXP_RXMAP_PUT(sc, rxmap); 1711 fxp_rxdrain(sc); 1712 goto out; 1713 } 1714 } 1715 sc->sc_rxidle = 0; 1716 1717 /* 1718 * Give the transmit ring to the chip. We do this by pointing 1719 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1720 * issuing a start command. It will execute the NOP and then 1721 * suspend, pointing at the first descriptor. 1722 */ 1723 fxp_scb_wait(sc); 1724 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1725 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1726 1727 /* 1728 * Initialize receiver buffer area - RFA. 1729 */ 1730 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1731 fxp_scb_wait(sc); 1732 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1733 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1734 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1735 1736 if (sc->sc_flags & FXPF_MII) { 1737 /* 1738 * Set current media. 1739 */ 1740 mii_mediachg(&sc->sc_mii); 1741 } 1742 1743 /* 1744 * ...all done! 1745 */ 1746 ifp->if_flags |= IFF_RUNNING; 1747 ifp->if_flags &= ~IFF_OACTIVE; 1748 1749 /* 1750 * Start the one second timer. 1751 */ 1752 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1753 1754 /* 1755 * Attempt to start output on the interface. 1756 */ 1757 fxp_start(ifp); 1758 1759 out: 1760 if (error) { 1761 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1762 ifp->if_timer = 0; 1763 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1764 } 1765 return (error); 1766} 1767 1768/* 1769 * Change media according to request. 1770 */ 1771int 1772fxp_mii_mediachange(struct ifnet *ifp) 1773{ 1774 struct fxp_softc *sc = ifp->if_softc; 1775 1776 if (ifp->if_flags & IFF_UP) 1777 mii_mediachg(&sc->sc_mii); 1778 return (0); 1779} 1780 1781/* 1782 * Notify the world which media we're using. 1783 */ 1784void 1785fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1786{ 1787 struct fxp_softc *sc = ifp->if_softc; 1788 1789 if(sc->sc_enabled == 0) { 1790 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1791 ifmr->ifm_status = 0; 1792 return; 1793 } 1794 1795 mii_pollstat(&sc->sc_mii); 1796 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1797 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1798} 1799 1800int 1801fxp_80c24_mediachange(struct ifnet *ifp) 1802{ 1803 1804 /* Nothing to do here. */ 1805 return (0); 1806} 1807 1808void 1809fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1810{ 1811 struct fxp_softc *sc = ifp->if_softc; 1812 1813 /* 1814 * Media is currently-selected media. We cannot determine 1815 * the link status. 1816 */ 1817 ifmr->ifm_status = 0; 1818 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1819} 1820 1821/* 1822 * Add a buffer to the end of the RFA buffer list. 1823 * Return 0 if successful, error code on failure. 1824 * 1825 * The RFA struct is stuck at the beginning of mbuf cluster and the 1826 * data pointer is fixed up to point just past it. 1827 */ 1828int 1829fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 1830{ 1831 struct mbuf *m; 1832 int error; 1833 1834 MGETHDR(m, M_DONTWAIT, MT_DATA); 1835 if (m == NULL) 1836 return (ENOBUFS); 1837 1838 MCLGET(m, M_DONTWAIT); 1839 if ((m->m_flags & M_EXT) == 0) { 1840 m_freem(m); 1841 return (ENOBUFS); 1842 } 1843 1844 if (unload) 1845 bus_dmamap_unload(sc->sc_dmat, rxmap); 1846 1847 M_SETCTX(m, rxmap); 1848 1849 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1850 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1851 BUS_DMA_READ|BUS_DMA_NOWAIT); 1852 if (error) { 1853 printf("%s: can't load rx DMA map %d, error = %d\n", 1854 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 1855 panic("fxp_add_rfabuf"); /* XXX */ 1856 } 1857 1858 FXP_INIT_RFABUF(sc, m); 1859 1860 return (0); 1861} 1862 1863int 1864fxp_mdi_read(struct device *self, int phy, int reg) 1865{ 1866 struct fxp_softc *sc = (struct fxp_softc *)self; 1867 int count = 10000; 1868 int value; 1869 1870 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1871 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1872 1873 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1874 && count--) 1875 DELAY(10); 1876 1877 if (count <= 0) 1878 printf("%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 1879 1880 return (value & 0xffff); 1881} 1882 1883void 1884fxp_statchg(struct device *self) 1885{ 1886 struct fxp_softc *sc = (void *) self; 1887 1888 /* 1889 * Determine whether or not we have to work-around the 1890 * Resume Bug. 1891 */ 1892 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 1893 if (IFM_TYPE(sc->sc_mii.mii_media_active) == IFM_10_T) 1894 sc->sc_flags |= FXPF_FIX_RESUME_BUG; 1895 else 1896 sc->sc_flags &= ~FXPF_FIX_RESUME_BUG; 1897 } 1898} 1899 1900void 1901fxp_mdi_write(struct device *self, int phy, int reg, int value) 1902{ 1903 struct fxp_softc *sc = (struct fxp_softc *)self; 1904 int count = 10000; 1905 1906 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1907 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1908 (value & 0xffff)); 1909 1910 while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1911 count--) 1912 DELAY(10); 1913 1914 if (count <= 0) 1915 printf("%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 1916} 1917 1918int 1919fxp_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1920{ 1921 struct fxp_softc *sc = ifp->if_softc; 1922 struct ifreq *ifr = (struct ifreq *)data; 1923 int s, error; 1924 1925 s = splnet(); 1926 1927 switch (cmd) { 1928 case SIOCSIFMEDIA: 1929 case SIOCGIFMEDIA: 1930 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1931 break; 1932 1933 default: 1934 error = ether_ioctl(ifp, cmd, data); 1935 if (error == ENETRESET) { 1936 if (sc->sc_enabled) { 1937 /* 1938 * Multicast list has changed; set the 1939 * hardware filter accordingly. 1940 */ 1941 if (sc->sc_txpending) { 1942 sc->sc_flags |= FXPF_WANTINIT; 1943 error = 0; 1944 } else 1945 error = fxp_init(ifp); 1946 } else 1947 error = 0; 1948 } 1949 break; 1950 } 1951 1952 /* Try to get more packets going. */ 1953 if (sc->sc_enabled) 1954 fxp_start(ifp); 1955 1956 splx(s); 1957 return (error); 1958} 1959 1960/* 1961 * Program the multicast filter. 1962 * 1963 * This function must be called at splnet(). 1964 */ 1965void 1966fxp_mc_setup(struct fxp_softc *sc) 1967{ 1968 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 1969 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1970 struct ethercom *ec = &sc->sc_ethercom; 1971 struct ether_multi *enm; 1972 struct ether_multistep step; 1973 int count, nmcasts; 1974 1975#ifdef DIAGNOSTIC 1976 if (sc->sc_txpending) 1977 panic("fxp_mc_setup: pending transmissions"); 1978#endif 1979 1980 ifp->if_flags &= ~IFF_ALLMULTI; 1981 1982 /* 1983 * Initialize multicast setup descriptor. 1984 */ 1985 nmcasts = 0; 1986 ETHER_FIRST_MULTI(step, ec, enm); 1987 while (enm != NULL) { 1988 /* 1989 * Check for too many multicast addresses or if we're 1990 * listening to a range. Either way, we simply have 1991 * to accept all multicasts. 1992 */ 1993 if (nmcasts >= MAXMCADDR || 1994 memcmp(enm->enm_addrlo, enm->enm_addrhi, 1995 ETHER_ADDR_LEN) != 0) { 1996 /* 1997 * Callers of this function must do the 1998 * right thing with this. If we're called 1999 * from outside fxp_init(), the caller must 2000 * detect if the state if IFF_ALLMULTI changes. 2001 * If it does, the caller must then call 2002 * fxp_init(), since allmulti is handled by 2003 * the config block. 2004 */ 2005 ifp->if_flags |= IFF_ALLMULTI; 2006 return; 2007 } 2008 memcpy((void *)&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 2009 ETHER_ADDR_LEN); 2010 nmcasts++; 2011 ETHER_NEXT_MULTI(step, enm); 2012 } 2013 2014 /* BIG_ENDIAN: no need to swap to store 0 */ 2015 mcsp->cb_status = 0; 2016 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2017 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 2018 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2019 2020 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2021 2022 /* 2023 * Wait until the command unit is not active. This should never 2024 * happen since nothing is queued, but make sure anyway. 2025 */ 2026 count = 100; 2027 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2028 FXP_SCB_CUS_ACTIVE && --count) 2029 DELAY(1); 2030 if (count == 0) { 2031 printf("%s at line %d: command queue timeout\n", 2032 sc->sc_dev.dv_xname, __LINE__); 2033 return; 2034 } 2035 2036 /* 2037 * Start the multicast setup command/DMA. 2038 */ 2039 fxp_scb_wait(sc); 2040 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2041 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2042 2043 /* ...and wait for it to complete. */ 2044 count = 1000; 2045 do { 2046 FXP_CDMCSSYNC(sc, 2047 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2048 DELAY(1); 2049 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2050 if (count == 0) { 2051 printf("%s at line %d: dmasync timeout\n", 2052 sc->sc_dev.dv_xname, __LINE__); 2053 return; 2054 } 2055} 2056 2057static const uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2058static const uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2059static const uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2060static const uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2061static const uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2062static const uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2063 2064#define UCODE(x) x, sizeof(x) 2065 2066static const struct ucode { 2067 uint32_t revision; 2068 const uint32_t *ucode; 2069 size_t length; 2070 uint16_t int_delay_offset; 2071 uint16_t bundle_max_offset; 2072} ucode_table[] = { 2073 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), 2074 D101_CPUSAVER_DWORD, 0 }, 2075 2076 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), 2077 D101_CPUSAVER_DWORD, 0 }, 2078 2079 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2080 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2081 2082 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2083 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2084 2085 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2086 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2087 2088 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2089 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2090 2091 { 0, NULL, 0, 0, 0 } 2092}; 2093 2094void 2095fxp_load_ucode(struct fxp_softc *sc) 2096{ 2097 const struct ucode *uc; 2098 struct fxp_cb_ucode *cbp = &sc->sc_control_data->fcd_ucode; 2099 int count; 2100 2101 if (sc->sc_flags & FXPF_UCODE_LOADED) 2102 return; 2103 2104 /* 2105 * Only load the uCode if the user has requested that 2106 * we do so. 2107 */ 2108 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK0) == 0) { 2109 sc->sc_int_delay = 0; 2110 sc->sc_bundle_max = 0; 2111 return; 2112 } 2113 2114 for (uc = ucode_table; uc->ucode != NULL; uc++) { 2115 if (sc->sc_rev == uc->revision) 2116 break; 2117 } 2118 if (uc->ucode == NULL) 2119 return; 2120 2121 /* BIG ENDIAN: no need to swap to store 0 */ 2122 cbp->cb_status = 0; 2123 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2124 cbp->link_addr = 0xffffffff; /* (no) next command */ 2125 memcpy((void *) cbp->ucode, uc->ucode, uc->length); 2126 2127 if (uc->int_delay_offset) 2128 *(uint16_t *) &cbp->ucode[uc->int_delay_offset] = 2129 htole16(fxp_int_delay + (fxp_int_delay / 2)); 2130 2131 if (uc->bundle_max_offset) 2132 *(uint16_t *) &cbp->ucode[uc->bundle_max_offset] = 2133 htole16(fxp_bundle_max); 2134 2135 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2136 2137 /* 2138 * Download the uCode to the chip. 2139 */ 2140 fxp_scb_wait(sc); 2141 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDUCODEOFF); 2142 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2143 2144 /* ...and wait for it to complete. */ 2145 count = 10000; 2146 do { 2147 FXP_CDUCODESYNC(sc, 2148 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2149 DELAY(2); 2150 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2151 if (count == 0) { 2152 sc->sc_int_delay = 0; 2153 sc->sc_bundle_max = 0; 2154 printf("%s: timeout loading microcode\n", 2155 sc->sc_dev.dv_xname); 2156 return; 2157 } 2158 2159 if (sc->sc_int_delay != fxp_int_delay || 2160 sc->sc_bundle_max != fxp_bundle_max) { 2161 sc->sc_int_delay = fxp_int_delay; 2162 sc->sc_bundle_max = fxp_bundle_max; 2163 printf("%s: Microcode loaded: int delay: %d usec, " 2164 "max bundle: %d\n", sc->sc_dev.dv_xname, 2165 sc->sc_int_delay, 2166 uc->bundle_max_offset == 0 ? 0 : sc->sc_bundle_max); 2167 } 2168 2169 sc->sc_flags |= FXPF_UCODE_LOADED; 2170} 2171 2172int 2173fxp_enable(struct fxp_softc *sc) 2174{ 2175 2176 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2177 if ((*sc->sc_enable)(sc) != 0) { 2178 printf("%s: device enable failed\n", 2179 sc->sc_dev.dv_xname); 2180 return (EIO); 2181 } 2182 } 2183 2184 sc->sc_enabled = 1; 2185 return (0); 2186} 2187 2188void 2189fxp_disable(struct fxp_softc *sc) 2190{ 2191 2192 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2193 (*sc->sc_disable)(sc); 2194 sc->sc_enabled = 0; 2195 } 2196} 2197 2198/* 2199 * fxp_activate: 2200 * 2201 * Handle device activation/deactivation requests. 2202 */ 2203int 2204fxp_activate(struct device *self, enum devact act) 2205{ 2206 struct fxp_softc *sc = (void *) self; 2207 int s, error = 0; 2208 2209 s = splnet(); 2210 switch (act) { 2211 case DVACT_ACTIVATE: 2212 error = EOPNOTSUPP; 2213 break; 2214 2215 case DVACT_DEACTIVATE: 2216 if (sc->sc_flags & FXPF_MII) 2217 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 2218 MII_OFFSET_ANY); 2219 if_deactivate(&sc->sc_ethercom.ec_if); 2220 break; 2221 } 2222 splx(s); 2223 2224 return (error); 2225} 2226 2227/* 2228 * fxp_detach: 2229 * 2230 * Detach an i82557 interface. 2231 */ 2232int 2233fxp_detach(struct fxp_softc *sc) 2234{ 2235 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2236 int i; 2237 2238 /* Succeed now if there's no work to do. */ 2239 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2240 return (0); 2241 2242 /* Unhook our tick handler. */ 2243 callout_stop(&sc->sc_callout); 2244 2245 if (sc->sc_flags & FXPF_MII) { 2246 /* Detach all PHYs */ 2247 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2248 } 2249 2250 /* Delete all remaining media. */ 2251 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2252 2253#if NRND > 0 2254 rnd_detach_source(&sc->rnd_source); 2255#endif 2256 ether_ifdetach(ifp); 2257 if_detach(ifp); 2258 2259 for (i = 0; i < FXP_NRFABUFS; i++) { 2260 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2261 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2262 } 2263 2264 for (i = 0; i < FXP_NTXCB; i++) { 2265 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2266 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2267 } 2268 2269 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2270 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2271 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2272 sizeof(struct fxp_control_data)); 2273 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2274 2275 shutdownhook_disestablish(sc->sc_sdhook); 2276 powerhook_disestablish(sc->sc_powerhook); 2277 2278 return (0); 2279} 2280