i82557.c revision 1.53
1/* $NetBSD: i82557.c,v 1.53 2001/06/02 01:04:01 thorpej Exp $ */ 2 3/*- 4 * Copyright (c) 1997, 1998, 1999, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40/* 41 * Copyright (c) 1995, David Greenman 42 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice unmodified, this list of conditions, and the following 50 * disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 68 */ 69 70/* 71 * Device driver for the Intel i82557 fast Ethernet controller, 72 * and its successors, the i82558 and i82559. 73 */ 74 75#include "opt_inet.h" 76#include "opt_ns.h" 77#include "bpfilter.h" 78#include "rnd.h" 79 80#include <sys/param.h> 81#include <sys/systm.h> 82#include <sys/callout.h> 83#include <sys/mbuf.h> 84#include <sys/malloc.h> 85#include <sys/kernel.h> 86#include <sys/socket.h> 87#include <sys/ioctl.h> 88#include <sys/errno.h> 89#include <sys/device.h> 90 91#include <machine/endian.h> 92 93#include <uvm/uvm_extern.h> 94 95#if NRND > 0 96#include <sys/rnd.h> 97#endif 98 99#include <net/if.h> 100#include <net/if_dl.h> 101#include <net/if_media.h> 102#include <net/if_ether.h> 103 104#if NBPFILTER > 0 105#include <net/bpf.h> 106#endif 107 108#ifdef INET 109#include <netinet/in.h> 110#include <netinet/if_inarp.h> 111#endif 112 113#ifdef NS 114#include <netns/ns.h> 115#include <netns/ns_if.h> 116#endif 117 118#include <machine/bus.h> 119#include <machine/intr.h> 120 121#include <dev/mii/miivar.h> 122 123#include <dev/ic/i82557reg.h> 124#include <dev/ic/i82557var.h> 125 126/* 127 * NOTE! On the Alpha, we have an alignment constraint. The 128 * card DMAs the packet immediately following the RFA. However, 129 * the first thing in the packet is a 14-byte Ethernet header. 130 * This means that the packet is misaligned. To compensate, 131 * we actually offset the RFA 2 bytes into the cluster. This 132 * alignes the packet after the Ethernet header at a 32-bit 133 * boundary. HOWEVER! This means that the RFA is misaligned! 134 */ 135#define RFA_ALIGNMENT_FUDGE 2 136 137/* 138 * The configuration byte map has several undefined fields which 139 * must be one or must be zero. Set up a template for these bits 140 * only (assuming an i82557 chip), leaving the actual configuration 141 * for fxp_init(). 142 * 143 * See the definition of struct fxp_cb_config for the bit definitions. 144 */ 145const u_int8_t fxp_cb_config_template[] = { 146 0x0, 0x0, /* cb_status */ 147 0x0, 0x0, /* cb_command */ 148 0x0, 0x0, 0x0, 0x0, /* link_addr */ 149 0x0, /* 0 */ 150 0x0, /* 1 */ 151 0x0, /* 2 */ 152 0x0, /* 3 */ 153 0x0, /* 4 */ 154 0x0, /* 5 */ 155 0x32, /* 6 */ 156 0x0, /* 7 */ 157 0x0, /* 8 */ 158 0x0, /* 9 */ 159 0x6, /* 10 */ 160 0x0, /* 11 */ 161 0x0, /* 12 */ 162 0x0, /* 13 */ 163 0xf2, /* 14 */ 164 0x48, /* 15 */ 165 0x0, /* 16 */ 166 0x40, /* 17 */ 167 0xf0, /* 18 */ 168 0x0, /* 19 */ 169 0x3f, /* 20 */ 170 0x5, /* 21 */ 171 0x0, /* 22 */ 172 0x0, /* 23 */ 173 0x0, /* 24 */ 174 0x0, /* 25 */ 175 0x0, /* 26 */ 176 0x0, /* 27 */ 177 0x0, /* 28 */ 178 0x0, /* 29 */ 179 0x0, /* 30 */ 180 0x0, /* 31 */ 181}; 182 183void fxp_mii_initmedia(struct fxp_softc *); 184int fxp_mii_mediachange(struct ifnet *); 185void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 186 187void fxp_80c24_initmedia(struct fxp_softc *); 188int fxp_80c24_mediachange(struct ifnet *); 189void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 190 191void fxp_start(struct ifnet *); 192int fxp_ioctl(struct ifnet *, u_long, caddr_t); 193void fxp_watchdog(struct ifnet *); 194int fxp_init(struct ifnet *); 195void fxp_stop(struct ifnet *, int); 196 197void fxp_rxdrain(struct fxp_softc *); 198int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 199int fxp_mdi_read(struct device *, int, int); 200void fxp_statchg(struct device *); 201void fxp_mdi_write(struct device *, int, int, int); 202void fxp_autosize_eeprom(struct fxp_softc*); 203void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 204void fxp_get_info(struct fxp_softc *, u_int8_t *); 205void fxp_tick(void *); 206void fxp_mc_setup(struct fxp_softc *); 207 208void fxp_shutdown(void *); 209void fxp_power(int, void *); 210 211int fxp_copy_small = 0; 212 213struct fxp_phytype { 214 int fp_phy; /* type of PHY, -1 for MII at the end. */ 215 void (*fp_init)(struct fxp_softc *); 216} fxp_phytype_table[] = { 217 { FXP_PHY_80C24, fxp_80c24_initmedia }, 218 { -1, fxp_mii_initmedia }, 219}; 220 221/* 222 * Set initial transmit threshold at 64 (512 bytes). This is 223 * increased by 64 (512 bytes) at a time, to maximum of 192 224 * (1536 bytes), if an underrun occurs. 225 */ 226static int tx_threshold = 64; 227 228/* 229 * Wait for the previous command to be accepted (but not necessarily 230 * completed). 231 */ 232static __inline void 233fxp_scb_wait(struct fxp_softc *sc) 234{ 235 int i = 10000; 236 237 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 238 delay(2); 239 if (i == 0) 240 printf("%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 241} 242 243/* 244 * Submit a command to the i82557. 245 */ 246static __inline void 247fxp_scb_cmd(struct fxp_softc *sc, u_int8_t cmd) 248{ 249 250 if (cmd == FXP_SCB_COMMAND_CU_RESUME && 251 (sc->sc_flags & FXPF_FIX_RESUME_BUG) != 0) { 252 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_NOP); 253 fxp_scb_wait(sc); 254 } 255 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 256} 257 258/* 259 * Finish attaching an i82557 interface. Called by bus-specific front-end. 260 */ 261void 262fxp_attach(struct fxp_softc *sc) 263{ 264 u_int8_t enaddr[ETHER_ADDR_LEN]; 265 struct ifnet *ifp; 266 bus_dma_segment_t seg; 267 int rseg, i, error; 268 struct fxp_phytype *fp; 269 270 callout_init(&sc->sc_callout); 271 272 /* Start out using the standard RFA. */ 273 sc->sc_rfa_size = RFA_SIZE; 274 275 /* 276 * Enable some good stuff on i82558 and later. 277 */ 278 if (sc->sc_rev >= FXP_REV_82558_A4) { 279 /* Enable the extended TxCB. */ 280 sc->sc_flags |= FXPF_EXT_TXCB; 281 } 282 283 /* 284 * Allocate the control data structures, and create and load the 285 * DMA map for it. 286 */ 287 if ((error = bus_dmamem_alloc(sc->sc_dmat, 288 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 289 0)) != 0) { 290 printf("%s: unable to allocate control data, error = %d\n", 291 sc->sc_dev.dv_xname, error); 292 goto fail_0; 293 } 294 295 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 296 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 297 BUS_DMA_COHERENT)) != 0) { 298 printf("%s: unable to map control data, error = %d\n", 299 sc->sc_dev.dv_xname, error); 300 goto fail_1; 301 } 302 sc->sc_cdseg = seg; 303 sc->sc_cdnseg = rseg; 304 305 bzero(sc->sc_control_data, sizeof(struct fxp_control_data)); 306 307 if ((error = bus_dmamap_create(sc->sc_dmat, 308 sizeof(struct fxp_control_data), 1, 309 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 310 printf("%s: unable to create control data DMA map, " 311 "error = %d\n", sc->sc_dev.dv_xname, error); 312 goto fail_2; 313 } 314 315 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 316 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 317 0)) != 0) { 318 printf("%s: can't load control data DMA map, error = %d\n", 319 sc->sc_dev.dv_xname, error); 320 goto fail_3; 321 } 322 323 /* 324 * Create the transmit buffer DMA maps. 325 */ 326 for (i = 0; i < FXP_NTXCB; i++) { 327 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 328 FXP_NTXSEG, MCLBYTES, 0, 0, 329 &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 330 printf("%s: unable to create tx DMA map %d, " 331 "error = %d\n", sc->sc_dev.dv_xname, i, error); 332 goto fail_4; 333 } 334 } 335 336 /* 337 * Create the receive buffer DMA maps. 338 */ 339 for (i = 0; i < FXP_NRFABUFS; i++) { 340 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 341 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 342 printf("%s: unable to create rx DMA map %d, " 343 "error = %d\n", sc->sc_dev.dv_xname, i, error); 344 goto fail_5; 345 } 346 } 347 348 /* Initialize MAC address and media structures. */ 349 fxp_get_info(sc, enaddr); 350 351 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 352 ether_sprintf(enaddr)); 353 354 ifp = &sc->sc_ethercom.ec_if; 355 356 /* 357 * Get info about our media interface, and initialize it. Note 358 * the table terminates itself with a phy of -1, indicating 359 * that we're using MII. 360 */ 361 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 362 if (fp->fp_phy == sc->phy_primary_device) 363 break; 364 (*fp->fp_init)(sc); 365 366 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 367 ifp->if_softc = sc; 368 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 369 ifp->if_ioctl = fxp_ioctl; 370 ifp->if_start = fxp_start; 371 ifp->if_watchdog = fxp_watchdog; 372 ifp->if_init = fxp_init; 373 ifp->if_stop = fxp_stop; 374 IFQ_SET_READY(&ifp->if_snd); 375 376 /* 377 * We can support 802.1Q VLAN-sized frames. 378 */ 379 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 380 381 /* 382 * Attach the interface. 383 */ 384 if_attach(ifp); 385 ether_ifattach(ifp, enaddr); 386#if NRND > 0 387 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 388 RND_TYPE_NET, 0); 389#endif 390 391 /* 392 * Add shutdown hook so that DMA is disabled prior to reboot. Not 393 * doing do could allow DMA to corrupt kernel memory during the 394 * reboot before the driver initializes. 395 */ 396 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 397 if (sc->sc_sdhook == NULL) 398 printf("%s: WARNING: unable to establish shutdown hook\n", 399 sc->sc_dev.dv_xname); 400 /* 401 * Add suspend hook, for similar reasons.. 402 */ 403 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 404 if (sc->sc_powerhook == NULL) 405 printf("%s: WARNING: unable to establish power hook\n", 406 sc->sc_dev.dv_xname); 407 408 /* The attach is successful. */ 409 sc->sc_flags |= FXPF_ATTACHED; 410 411 return; 412 413 /* 414 * Free any resources we've allocated during the failed attach 415 * attempt. Do this in reverse order and fall though. 416 */ 417 fail_5: 418 for (i = 0; i < FXP_NRFABUFS; i++) { 419 if (sc->sc_rxmaps[i] != NULL) 420 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 421 } 422 fail_4: 423 for (i = 0; i < FXP_NTXCB; i++) { 424 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 425 bus_dmamap_destroy(sc->sc_dmat, 426 FXP_DSTX(sc, i)->txs_dmamap); 427 } 428 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 429 fail_3: 430 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 431 fail_2: 432 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 433 sizeof(struct fxp_control_data)); 434 fail_1: 435 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 436 fail_0: 437 return; 438} 439 440void 441fxp_mii_initmedia(struct fxp_softc *sc) 442{ 443 444 sc->sc_flags |= FXPF_MII; 445 446 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 447 sc->sc_mii.mii_readreg = fxp_mdi_read; 448 sc->sc_mii.mii_writereg = fxp_mdi_write; 449 sc->sc_mii.mii_statchg = fxp_statchg; 450 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_mii_mediachange, 451 fxp_mii_mediastatus); 452 /* 453 * The i82557 wedges if all of its PHYs are isolated! 454 */ 455 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 456 MII_OFFSET_ANY, MIIF_NOISOLATE); 457 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 458 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 459 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 460 } else 461 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 462} 463 464void 465fxp_80c24_initmedia(struct fxp_softc *sc) 466{ 467 468 /* 469 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 470 * doesn't have a programming interface of any sort. The 471 * media is sensed automatically based on how the link partner 472 * is configured. This is, in essence, manual configuration. 473 */ 474 printf("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 475 sc->sc_dev.dv_xname); 476 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 477 fxp_80c24_mediastatus); 478 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 479 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 480} 481 482/* 483 * Device shutdown routine. Called at system shutdown after sync. The 484 * main purpose of this routine is to shut off receiver DMA so that 485 * kernel memory doesn't get clobbered during warmboot. 486 */ 487void 488fxp_shutdown(void *arg) 489{ 490 struct fxp_softc *sc = arg; 491 492 /* 493 * Since the system's going to halt shortly, don't bother 494 * freeing mbufs. 495 */ 496 fxp_stop(&sc->sc_ethercom.ec_if, 0); 497} 498/* 499 * Power handler routine. Called when the system is transitioning 500 * into/out of power save modes. As with fxp_shutdown, the main 501 * purpose of this routine is to shut off receiver DMA so it doesn't 502 * clobber kernel memory at the wrong time. 503 */ 504void 505fxp_power(int why, void *arg) 506{ 507 struct fxp_softc *sc = arg; 508 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 509 int s; 510 511 s = splnet(); 512 switch (why) { 513 case PWR_SUSPEND: 514 case PWR_STANDBY: 515 fxp_stop(ifp, 0); 516 break; 517 case PWR_RESUME: 518 if (ifp->if_flags & IFF_UP) 519 fxp_init(ifp); 520 break; 521 case PWR_SOFTSUSPEND: 522 case PWR_SOFTSTANDBY: 523 case PWR_SOFTRESUME: 524 break; 525 } 526 splx(s); 527} 528 529/* 530 * Initialize the interface media. 531 */ 532void 533fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 534{ 535 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 536 537 /* 538 * Reset to a stable state. 539 */ 540 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 541 DELAY(10); 542 543 sc->sc_eeprom_size = 0; 544 fxp_autosize_eeprom(sc); 545 if(sc->sc_eeprom_size == 0) { 546 printf("%s: failed to detect EEPROM size\n", sc->sc_dev.dv_xname); 547 sc->sc_eeprom_size = 6; /* XXX panic here? */ 548 } 549#ifdef DEBUG 550 printf("%s: detected %d word EEPROM\n", 551 sc->sc_dev.dv_xname, 552 1 << sc->sc_eeprom_size); 553#endif 554 555 /* 556 * Get info about the primary PHY 557 */ 558 fxp_read_eeprom(sc, &data, 6, 1); 559 sc->phy_primary_device = 560 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 561 562 /* 563 * Read MAC address. 564 */ 565 fxp_read_eeprom(sc, myea, 0, 3); 566 enaddr[0] = myea[0] & 0xff; 567 enaddr[1] = myea[0] >> 8; 568 enaddr[2] = myea[1] & 0xff; 569 enaddr[3] = myea[1] >> 8; 570 enaddr[4] = myea[2] & 0xff; 571 enaddr[5] = myea[2] >> 8; 572} 573 574/* 575 * Figure out EEPROM size. 576 * 577 * 559's can have either 64-word or 256-word EEPROMs, the 558 578 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 579 * talks about the existance of 16 to 256 word EEPROMs. 580 * 581 * The only known sizes are 64 and 256, where the 256 version is used 582 * by CardBus cards to store CIS information. 583 * 584 * The address is shifted in msb-to-lsb, and after the last 585 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 586 * after which follows the actual data. We try to detect this zero, by 587 * probing the data-out bit in the EEPROM control register just after 588 * having shifted in a bit. If the bit is zero, we assume we've 589 * shifted enough address bits. The data-out should be tri-state, 590 * before this, which should translate to a logical one. 591 * 592 * Other ways to do this would be to try to read a register with known 593 * contents with a varying number of address bits, but no such 594 * register seem to be available. The high bits of register 10 are 01 595 * on the 558 and 559, but apparently not on the 557. 596 * 597 * The Linux driver computes a checksum on the EEPROM data, but the 598 * value of this checksum is not very well documented. 599 */ 600 601void 602fxp_autosize_eeprom(struct fxp_softc *sc) 603{ 604 u_int16_t reg; 605 int x; 606 607 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 608 /* 609 * Shift in read opcode. 610 */ 611 for (x = 3; x > 0; x--) { 612 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 613 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 614 } else { 615 reg = FXP_EEPROM_EECS; 616 } 617 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 618 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 619 reg | FXP_EEPROM_EESK); 620 DELAY(4); 621 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 622 DELAY(4); 623 } 624 /* 625 * Shift in address, wait for the dummy zero following a correct 626 * address shift. 627 */ 628 for (x = 1; x <= 8; x++) { 629 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 630 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 631 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 632 DELAY(4); 633 if((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 634 FXP_EEPROM_EEDO) == 0) 635 break; 636 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 637 DELAY(4); 638 } 639 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 640 DELAY(4); 641 if(x != 6 && x != 8) { 642#ifdef DEBUG 643 printf("%s: strange EEPROM size (%d)\n", 644 sc->sc_dev.dv_xname, 1 << x); 645#endif 646 } else 647 sc->sc_eeprom_size = x; 648} 649 650/* 651 * Read from the serial EEPROM. Basically, you manually shift in 652 * the read opcode (one bit at a time) and then shift in the address, 653 * and then you shift out the data (all of this one bit at a time). 654 * The word size is 16 bits, so you have to provide the address for 655 * every 16 bits of data. 656 */ 657void 658fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 659{ 660 u_int16_t reg; 661 int i, x; 662 663 for (i = 0; i < words; i++) { 664 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 665 /* 666 * Shift in read opcode. 667 */ 668 for (x = 3; x > 0; x--) { 669 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 670 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 671 } else { 672 reg = FXP_EEPROM_EECS; 673 } 674 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 675 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 676 reg | FXP_EEPROM_EESK); 677 DELAY(4); 678 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 679 DELAY(4); 680 } 681 /* 682 * Shift in address. 683 */ 684 for (x = sc->sc_eeprom_size; x > 0; x--) { 685 if ((i + offset) & (1 << (x - 1))) { 686 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 687 } else { 688 reg = FXP_EEPROM_EECS; 689 } 690 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 691 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 692 reg | FXP_EEPROM_EESK); 693 DELAY(4); 694 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 695 DELAY(4); 696 } 697 reg = FXP_EEPROM_EECS; 698 data[i] = 0; 699 /* 700 * Shift out data. 701 */ 702 for (x = 16; x > 0; x--) { 703 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 704 reg | FXP_EEPROM_EESK); 705 DELAY(4); 706 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 707 FXP_EEPROM_EEDO) 708 data[i] |= (1 << (x - 1)); 709 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 710 DELAY(4); 711 } 712 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 713 DELAY(4); 714 } 715} 716 717/* 718 * Start packet transmission on the interface. 719 */ 720void 721fxp_start(struct ifnet *ifp) 722{ 723 struct fxp_softc *sc = ifp->if_softc; 724 struct mbuf *m0, *m; 725 struct fxp_txdesc *txd; 726 struct fxp_txsoft *txs; 727 bus_dmamap_t dmamap; 728 int error, lasttx, nexttx, opending, seg; 729 730 /* 731 * If we want a re-init, bail out now. 732 */ 733 if (sc->sc_flags & FXPF_WANTINIT) { 734 ifp->if_flags |= IFF_OACTIVE; 735 return; 736 } 737 738 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 739 return; 740 741 /* 742 * Remember the previous txpending and the current lasttx. 743 */ 744 opending = sc->sc_txpending; 745 lasttx = sc->sc_txlast; 746 747 /* 748 * Loop through the send queue, setting up transmit descriptors 749 * until we drain the queue, or use up all available transmit 750 * descriptors. 751 */ 752 while (sc->sc_txpending < FXP_NTXCB) { 753 /* 754 * Grab a packet off the queue. 755 */ 756 IFQ_POLL(&ifp->if_snd, m0); 757 if (m0 == NULL) 758 break; 759 m = NULL; 760 761 /* 762 * Get the next available transmit descriptor. 763 */ 764 nexttx = FXP_NEXTTX(sc->sc_txlast); 765 txd = FXP_CDTX(sc, nexttx); 766 txs = FXP_DSTX(sc, nexttx); 767 dmamap = txs->txs_dmamap; 768 769 /* 770 * Load the DMA map. If this fails, the packet either 771 * didn't fit in the allotted number of frags, or we were 772 * short on resources. In this case, we'll copy and try 773 * again. 774 */ 775 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 776 BUS_DMA_NOWAIT) != 0) { 777 MGETHDR(m, M_DONTWAIT, MT_DATA); 778 if (m == NULL) { 779 printf("%s: unable to allocate Tx mbuf\n", 780 sc->sc_dev.dv_xname); 781 break; 782 } 783 if (m0->m_pkthdr.len > MHLEN) { 784 MCLGET(m, M_DONTWAIT); 785 if ((m->m_flags & M_EXT) == 0) { 786 printf("%s: unable to allocate Tx " 787 "cluster\n", sc->sc_dev.dv_xname); 788 m_freem(m); 789 break; 790 } 791 } 792 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 793 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 794 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 795 m, BUS_DMA_NOWAIT); 796 if (error) { 797 printf("%s: unable to load Tx buffer, " 798 "error = %d\n", sc->sc_dev.dv_xname, error); 799 break; 800 } 801 } 802 803 IFQ_DEQUEUE(&ifp->if_snd, m0); 804 if (m != NULL) { 805 m_freem(m0); 806 m0 = m; 807 } 808 809 /* Initialize the fraglist. */ 810 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 811 txd->txd_tbd[seg].tb_addr = 812 htole32(dmamap->dm_segs[seg].ds_addr); 813 txd->txd_tbd[seg].tb_size = 814 htole32(dmamap->dm_segs[seg].ds_len); 815 } 816 817 /* Sync the DMA map. */ 818 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 819 BUS_DMASYNC_PREWRITE); 820 821 /* 822 * Store a pointer to the packet so we can free it later. 823 */ 824 txs->txs_mbuf = m0; 825 826 /* 827 * Initialize the transmit descriptor. 828 */ 829 /* BIG_ENDIAN: no need to swap to store 0 */ 830 txd->txd_txcb.cb_status = 0; 831 txd->txd_txcb.cb_command = 832 htole16(FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF); 833 txd->txd_txcb.tx_threshold = tx_threshold; 834 txd->txd_txcb.tbd_number = dmamap->dm_nsegs; 835 836 FXP_CDTXSYNC(sc, nexttx, 837 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 838 839 /* Advance the tx pointer. */ 840 sc->sc_txpending++; 841 sc->sc_txlast = nexttx; 842 843#if NBPFILTER > 0 844 /* 845 * Pass packet to bpf if there is a listener. 846 */ 847 if (ifp->if_bpf) 848 bpf_mtap(ifp->if_bpf, m0); 849#endif 850 } 851 852 if (sc->sc_txpending == FXP_NTXCB) { 853 /* No more slots; notify upper layer. */ 854 ifp->if_flags |= IFF_OACTIVE; 855 } 856 857 if (sc->sc_txpending != opending) { 858 /* 859 * We enqueued packets. If the transmitter was idle, 860 * reset the txdirty pointer. 861 */ 862 if (opending == 0) 863 sc->sc_txdirty = FXP_NEXTTX(lasttx); 864 865 /* 866 * Cause the chip to interrupt and suspend command 867 * processing once the last packet we've enqueued 868 * has been transmitted. 869 */ 870 FXP_CDTX(sc, sc->sc_txlast)->txd_txcb.cb_command |= 871 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 872 FXP_CDTXSYNC(sc, sc->sc_txlast, 873 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 874 875 /* 876 * The entire packet chain is set up. Clear the suspend bit 877 * on the command prior to the first packet we set up. 878 */ 879 FXP_CDTXSYNC(sc, lasttx, 880 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 881 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 882 htole16(~FXP_CB_COMMAND_S); 883 FXP_CDTXSYNC(sc, lasttx, 884 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 885 886 /* 887 * Issue a Resume command in case the chip was suspended. 888 */ 889 fxp_scb_wait(sc); 890 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 891 892 /* Set a watchdog timer in case the chip flakes out. */ 893 ifp->if_timer = 5; 894 } 895} 896 897/* 898 * Process interface interrupts. 899 */ 900int 901fxp_intr(void *arg) 902{ 903 struct fxp_softc *sc = arg; 904 struct ethercom *ec = &sc->sc_ethercom; 905 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 906 struct fxp_txdesc *txd; 907 struct fxp_txsoft *txs; 908 struct mbuf *m, *m0; 909 bus_dmamap_t rxmap; 910 struct fxp_rfa *rfa; 911 int i, claimed = 0; 912 u_int16_t len, rxstat, txstat; 913 u_int8_t statack; 914 915 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 916 return (0); 917 /* 918 * If the interface isn't running, don't try to 919 * service the interrupt.. just ack it and bail. 920 */ 921 if ((ifp->if_flags & IFF_RUNNING) == 0) { 922 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 923 if (statack) { 924 claimed = 1; 925 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 926 } 927 return (claimed); 928 } 929 930 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 931 claimed = 1; 932 933 /* 934 * First ACK all the interrupts in this pass. 935 */ 936 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 937 938 /* 939 * Process receiver interrupts. If a no-resource (RNR) 940 * condition exists, get whatever packets we can and 941 * re-start the receiver. 942 */ 943 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 944 rcvloop: 945 m = sc->sc_rxq.ifq_head; 946 rfa = FXP_MTORFA(m); 947 rxmap = M_GETCTX(m, bus_dmamap_t); 948 949 FXP_RFASYNC(sc, m, 950 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 951 952 rxstat = le16toh(rfa->rfa_status); 953 954 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 955 /* 956 * We have processed all of the 957 * receive buffers. 958 */ 959 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 960 goto do_transmit; 961 } 962 963 IF_DEQUEUE(&sc->sc_rxq, m); 964 965 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 966 967 len = le16toh(rfa->actual_size) & 968 (m->m_ext.ext_size - 1); 969 970 if (len < sizeof(struct ether_header)) { 971 /* 972 * Runt packet; drop it now. 973 */ 974 FXP_INIT_RFABUF(sc, m); 975 goto rcvloop; 976 } 977 978 /* 979 * If support for 802.1Q VLAN sized frames is 980 * enabled, we need to do some additional error 981 * checking (as we are saving bad frames, in 982 * order to receive the larger ones). 983 */ 984 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 985 (rxstat & (FXP_RFA_STATUS_OVERRUN| 986 FXP_RFA_STATUS_RNR| 987 FXP_RFA_STATUS_ALIGN| 988 FXP_RFA_STATUS_CRC)) != 0) { 989 FXP_INIT_RFABUF(sc, m); 990 goto rcvloop; 991 } 992 993 /* 994 * If the packet is small enough to fit in a 995 * single header mbuf, allocate one and copy 996 * the data into it. This greatly reduces 997 * memory consumption when we receive lots 998 * of small packets. 999 * 1000 * Otherwise, we add a new buffer to the receive 1001 * chain. If this fails, we drop the packet and 1002 * recycle the old buffer. 1003 */ 1004 if (fxp_copy_small != 0 && len <= MHLEN) { 1005 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1006 if (m == NULL) 1007 goto dropit; 1008 memcpy(mtod(m0, caddr_t), 1009 mtod(m, caddr_t), len); 1010 FXP_INIT_RFABUF(sc, m); 1011 m = m0; 1012 } else { 1013 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1014 dropit: 1015 ifp->if_ierrors++; 1016 FXP_INIT_RFABUF(sc, m); 1017 goto rcvloop; 1018 } 1019 } 1020 1021 m->m_pkthdr.rcvif = ifp; 1022 m->m_pkthdr.len = m->m_len = len; 1023 1024#if NBPFILTER > 0 1025 /* 1026 * Pass this up to any BPF listeners, but only 1027 * pass it up the stack it its for us. 1028 */ 1029 if (ifp->if_bpf) 1030 bpf_mtap(ifp->if_bpf, m); 1031#endif 1032 1033 /* Pass it on. */ 1034 (*ifp->if_input)(ifp, m); 1035 goto rcvloop; 1036 } 1037 1038 do_transmit: 1039 if (statack & FXP_SCB_STATACK_RNR) { 1040 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1041 fxp_scb_wait(sc); 1042 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1043 rxmap->dm_segs[0].ds_addr + 1044 RFA_ALIGNMENT_FUDGE); 1045 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1046 } 1047 1048 /* 1049 * Free any finished transmit mbuf chains. 1050 */ 1051 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1052 ifp->if_flags &= ~IFF_OACTIVE; 1053 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1054 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1055 txd = FXP_CDTX(sc, i); 1056 txs = FXP_DSTX(sc, i); 1057 1058 FXP_CDTXSYNC(sc, i, 1059 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1060 1061 txstat = le16toh(txd->txd_txcb.cb_status); 1062 1063 if ((txstat & FXP_CB_STATUS_C) == 0) 1064 break; 1065 1066 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1067 0, txs->txs_dmamap->dm_mapsize, 1068 BUS_DMASYNC_POSTWRITE); 1069 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1070 m_freem(txs->txs_mbuf); 1071 txs->txs_mbuf = NULL; 1072 } 1073 1074 /* Update the dirty transmit buffer pointer. */ 1075 sc->sc_txdirty = i; 1076 1077 /* 1078 * Cancel the watchdog timer if there are no pending 1079 * transmissions. 1080 */ 1081 if (sc->sc_txpending == 0) { 1082 ifp->if_timer = 0; 1083 1084 /* 1085 * If we want a re-init, do that now. 1086 */ 1087 if (sc->sc_flags & FXPF_WANTINIT) 1088 (void) fxp_init(ifp); 1089 } 1090 1091 /* 1092 * Try to get more packets going. 1093 */ 1094 fxp_start(ifp); 1095 } 1096 } 1097 1098#if NRND > 0 1099 if (claimed) 1100 rnd_add_uint32(&sc->rnd_source, statack); 1101#endif 1102 return (claimed); 1103} 1104 1105/* 1106 * Update packet in/out/collision statistics. The i82557 doesn't 1107 * allow you to access these counters without doing a fairly 1108 * expensive DMA to get _all_ of the statistics it maintains, so 1109 * we do this operation here only once per second. The statistics 1110 * counters in the kernel are updated from the previous dump-stats 1111 * DMA and then a new dump-stats DMA is started. The on-chip 1112 * counters are zeroed when the DMA completes. If we can't start 1113 * the DMA immediately, we don't wait - we just prepare to read 1114 * them again next time. 1115 */ 1116void 1117fxp_tick(void *arg) 1118{ 1119 struct fxp_softc *sc = arg; 1120 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1121 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1122 int s; 1123 1124 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1125 return; 1126 1127 s = splnet(); 1128 1129 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1130 1131 ifp->if_opackets += le32toh(sp->tx_good); 1132 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1133 if (sp->rx_good) { 1134 ifp->if_ipackets += le32toh(sp->rx_good); 1135 sc->sc_rxidle = 0; 1136 } else { 1137 sc->sc_rxidle++; 1138 } 1139 ifp->if_ierrors += 1140 le32toh(sp->rx_crc_errors) + 1141 le32toh(sp->rx_alignment_errors) + 1142 le32toh(sp->rx_rnr_errors) + 1143 le32toh(sp->rx_overrun_errors); 1144 /* 1145 * If any transmit underruns occured, bump up the transmit 1146 * threshold by another 512 bytes (64 * 8). 1147 */ 1148 if (sp->tx_underruns) { 1149 ifp->if_oerrors += le32toh(sp->tx_underruns); 1150 if (tx_threshold < 192) 1151 tx_threshold += 64; 1152 } 1153 1154 /* 1155 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1156 * then assume the receiver has locked up and attempt to clear 1157 * the condition by reprogramming the multicast filter (actually, 1158 * resetting the interface). This is a work-around for a bug in 1159 * the 82557 where the receiver locks up if it gets certain types 1160 * of garbage in the syncronization bits prior to the packet header. 1161 * This bug is supposed to only occur in 10Mbps mode, but has been 1162 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1163 * speed transition). 1164 */ 1165 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1166 (void) fxp_init(ifp); 1167 splx(s); 1168 return; 1169 } 1170 /* 1171 * If there is no pending command, start another stats 1172 * dump. Otherwise punt for now. 1173 */ 1174 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1175 /* 1176 * Start another stats dump. 1177 */ 1178 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1179 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1180 } else { 1181 /* 1182 * A previous command is still waiting to be accepted. 1183 * Just zero our copy of the stats and wait for the 1184 * next timer event to update them. 1185 */ 1186 /* BIG_ENDIAN: no swap required to store 0 */ 1187 sp->tx_good = 0; 1188 sp->tx_underruns = 0; 1189 sp->tx_total_collisions = 0; 1190 1191 sp->rx_good = 0; 1192 sp->rx_crc_errors = 0; 1193 sp->rx_alignment_errors = 0; 1194 sp->rx_rnr_errors = 0; 1195 sp->rx_overrun_errors = 0; 1196 } 1197 1198 if (sc->sc_flags & FXPF_MII) { 1199 /* Tick the MII clock. */ 1200 mii_tick(&sc->sc_mii); 1201 } 1202 1203 splx(s); 1204 1205 /* 1206 * Schedule another timeout one second from now. 1207 */ 1208 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1209} 1210 1211/* 1212 * Drain the receive queue. 1213 */ 1214void 1215fxp_rxdrain(struct fxp_softc *sc) 1216{ 1217 bus_dmamap_t rxmap; 1218 struct mbuf *m; 1219 1220 for (;;) { 1221 IF_DEQUEUE(&sc->sc_rxq, m); 1222 if (m == NULL) 1223 break; 1224 rxmap = M_GETCTX(m, bus_dmamap_t); 1225 bus_dmamap_unload(sc->sc_dmat, rxmap); 1226 FXP_RXMAP_PUT(sc, rxmap); 1227 m_freem(m); 1228 } 1229} 1230 1231/* 1232 * Stop the interface. Cancels the statistics updater and resets 1233 * the interface. 1234 */ 1235void 1236fxp_stop(struct ifnet *ifp, int disable) 1237{ 1238 struct fxp_softc *sc = ifp->if_softc; 1239 struct fxp_txsoft *txs; 1240 int i; 1241 1242 /* 1243 * Turn down interface (done early to avoid bad interactions 1244 * between panics, shutdown hooks, and the watchdog timer) 1245 */ 1246 ifp->if_timer = 0; 1247 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1248 1249 /* 1250 * Cancel stats updater. 1251 */ 1252 callout_stop(&sc->sc_callout); 1253 if (sc->sc_flags & FXPF_MII) { 1254 /* Down the MII. */ 1255 mii_down(&sc->sc_mii); 1256 } 1257 1258 /* 1259 * Issue software reset 1260 */ 1261 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1262 DELAY(10); 1263 1264 /* 1265 * Release any xmit buffers. 1266 */ 1267 for (i = 0; i < FXP_NTXCB; i++) { 1268 txs = FXP_DSTX(sc, i); 1269 if (txs->txs_mbuf != NULL) { 1270 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1271 m_freem(txs->txs_mbuf); 1272 txs->txs_mbuf = NULL; 1273 } 1274 } 1275 sc->sc_txpending = 0; 1276 1277 if (disable) { 1278 fxp_rxdrain(sc); 1279 fxp_disable(sc); 1280 } 1281 1282} 1283 1284/* 1285 * Watchdog/transmission transmit timeout handler. Called when a 1286 * transmission is started on the interface, but no interrupt is 1287 * received before the timeout. This usually indicates that the 1288 * card has wedged for some reason. 1289 */ 1290void 1291fxp_watchdog(struct ifnet *ifp) 1292{ 1293 struct fxp_softc *sc = ifp->if_softc; 1294 1295 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1296 ifp->if_oerrors++; 1297 1298 (void) fxp_init(ifp); 1299} 1300 1301/* 1302 * Initialize the interface. Must be called at splnet(). 1303 */ 1304int 1305fxp_init(struct ifnet *ifp) 1306{ 1307 struct fxp_softc *sc = ifp->if_softc; 1308 struct fxp_cb_config *cbp; 1309 struct fxp_cb_ias *cb_ias; 1310 struct fxp_txdesc *txd; 1311 bus_dmamap_t rxmap; 1312 int i, prm, save_bf, lrxen, allm, error = 0; 1313 1314 if ((error = fxp_enable(sc)) != 0) 1315 goto out; 1316 1317 /* 1318 * Cancel any pending I/O 1319 */ 1320 fxp_stop(ifp, 0); 1321 1322 /* 1323 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1324 * flag, and this prevents the MII from detaching resulting in 1325 * a panic. The flags field should perhaps be split in runtime 1326 * flags and more static information. For now, just clear the 1327 * only other flag set. 1328 */ 1329 1330 sc->sc_flags &= ~FXPF_WANTINIT; 1331 1332 /* 1333 * Initialize base of CBL and RFA memory. Loading with zero 1334 * sets it up for regular linear addressing. 1335 */ 1336 fxp_scb_wait(sc); 1337 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1338 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1339 1340 fxp_scb_wait(sc); 1341 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1342 1343 /* 1344 * Initialize the multicast filter. Do this now, since we might 1345 * have to setup the config block differently. 1346 */ 1347 fxp_mc_setup(sc); 1348 1349 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1350 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1351 1352 /* 1353 * In order to support receiving 802.1Q VLAN frames, we have to 1354 * enable "save bad frames", since they are 4 bytes larger than 1355 * the normal Ethernet maximum frame length. On i82558 and later, 1356 * we have a better mechanism for this. 1357 */ 1358 save_bf = 0; 1359 lrxen = 0; 1360 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1361 if (sc->sc_rev < FXP_REV_82558_A4) 1362 save_bf = 1; 1363 else 1364 lrxen = 1; 1365 } 1366 1367 /* 1368 * Initialize base of dump-stats buffer. 1369 */ 1370 fxp_scb_wait(sc); 1371 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1372 sc->sc_cddma + FXP_CDSTATSOFF); 1373 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1374 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1375 1376 cbp = &sc->sc_control_data->fcd_configcb; 1377 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1378 1379 /* 1380 * This copy is kind of disgusting, but there are a bunch of must be 1381 * zero and must be one bits in this structure and this is the easiest 1382 * way to initialize them all to proper values. 1383 */ 1384 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1385 1386 /* BIG_ENDIAN: no need to swap to store 0 */ 1387 cbp->cb_status = 0; 1388 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1389 FXP_CB_COMMAND_EL); 1390 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1391 cbp->link_addr = 0xffffffff; /* (no) next command */ 1392 /* bytes in config block */ 1393 cbp->byte_count = FXP_CONFIG_LEN; 1394 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1395 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1396 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1397 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1398 cbp->type_enable = 0; /* actually reserved */ 1399 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1400 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1401 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1402 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1403 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1404 cbp->late_scb = 0; /* (don't) defer SCB update */ 1405 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1406 cbp->ci_int = 1; /* interrupt on CU idle */ 1407 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1408 cbp->ext_stats_dis = 1; /* disable extended counters */ 1409 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1410 cbp->save_bf = save_bf;/* save bad frames */ 1411 cbp->disc_short_rx = !prm; /* discard short packets */ 1412 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1413 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1414 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1415 /* interface mode */ 1416 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1417 cbp->csma_dis = 0; /* (don't) disable link */ 1418 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1419 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1420 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1421 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1422 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1423 cbp->nsai = 1; /* (don't) disable source addr insert */ 1424 cbp->preamble_length = 2; /* (7 byte) preamble */ 1425 cbp->loopback = 0; /* (don't) loopback */ 1426 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1427 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1428 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1429 cbp->promiscuous = prm; /* promiscuous mode */ 1430 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1431 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1432 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1433 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1434 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1435 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1436 cbp->padding = 1; /* (do) pad short tx packets */ 1437 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1438 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1439 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1440 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1441 /* must set wake_en in PMCSR also */ 1442 cbp->force_fdx = 0; /* (don't) force full duplex */ 1443 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1444 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1445 cbp->mc_all = allm; /* accept all multicasts */ 1446 1447 if (sc->sc_rev < FXP_REV_82558_A4) { 1448 /* 1449 * The i82557 has no hardware flow control, the values 1450 * here are the defaults for the chip. 1451 */ 1452 cbp->fc_delay_lsb = 0; 1453 cbp->fc_delay_msb = 0x40; 1454 cbp->pri_fc_thresh = 3; 1455 cbp->tx_fc_dis = 0; 1456 cbp->rx_fc_restop = 0; 1457 cbp->rx_fc_restart = 0; 1458 cbp->fc_filter = 0; 1459 cbp->pri_fc_loc = 1; 1460 } else { 1461 cbp->fc_delay_lsb = 0x1f; 1462 cbp->fc_delay_msb = 0x01; 1463 cbp->pri_fc_thresh = 3; 1464 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1465 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1466 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1467 cbp->fc_filter = !prm; /* drop FC frames to host */ 1468 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1469 } 1470 1471 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1472 1473 /* 1474 * Start the config command/DMA. 1475 */ 1476 fxp_scb_wait(sc); 1477 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1478 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1479 /* ...and wait for it to complete. */ 1480 i = 1000; 1481 do { 1482 FXP_CDCONFIGSYNC(sc, 1483 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1484 DELAY(1); 1485 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1486 if (i == 0) { 1487 printf("%s at line %d: dmasync timeout\n", 1488 sc->sc_dev.dv_xname, __LINE__); 1489 return ETIMEDOUT; 1490 } 1491 1492 /* 1493 * Initialize the station address. 1494 */ 1495 cb_ias = &sc->sc_control_data->fcd_iascb; 1496 /* BIG_ENDIAN: no need to swap to store 0 */ 1497 cb_ias->cb_status = 0; 1498 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1499 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1500 cb_ias->link_addr = 0xffffffff; 1501 memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1502 1503 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1504 1505 /* 1506 * Start the IAS (Individual Address Setup) command/DMA. 1507 */ 1508 fxp_scb_wait(sc); 1509 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1510 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1511 /* ...and wait for it to complete. */ 1512 i = 1000; 1513 do { 1514 FXP_CDIASSYNC(sc, 1515 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1516 DELAY(1); 1517 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1518 if (i == 0) { 1519 printf("%s at line %d: dmasync timeout\n", 1520 sc->sc_dev.dv_xname, __LINE__); 1521 return ETIMEDOUT; 1522 } 1523 1524 /* 1525 * Initialize the transmit descriptor ring. txlast is initialized 1526 * to the end of the list so that it will wrap around to the first 1527 * descriptor when the first packet is transmitted. 1528 */ 1529 for (i = 0; i < FXP_NTXCB; i++) { 1530 txd = FXP_CDTX(sc, i); 1531 memset(txd, 0, sizeof(*txd)); 1532 txd->txd_txcb.cb_command = 1533 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1534 txd->txd_txcb.link_addr = 1535 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1536 if (sc->sc_flags & FXPF_EXT_TXCB) 1537 txd->txd_txcb.tbd_array_addr = 1538 htole32(FXP_CDTBDADDR(sc, i) + 1539 (2 * sizeof(struct fxp_tbd))); 1540 else 1541 txd->txd_txcb.tbd_array_addr = 1542 htole32(FXP_CDTBDADDR(sc, i)); 1543 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1544 } 1545 sc->sc_txpending = 0; 1546 sc->sc_txdirty = 0; 1547 sc->sc_txlast = FXP_NTXCB - 1; 1548 1549 /* 1550 * Initialize the receive buffer list. 1551 */ 1552 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1553 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1554 rxmap = FXP_RXMAP_GET(sc); 1555 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1556 printf("%s: unable to allocate or map rx " 1557 "buffer %d, error = %d\n", 1558 sc->sc_dev.dv_xname, 1559 sc->sc_rxq.ifq_len, error); 1560 /* 1561 * XXX Should attempt to run with fewer receive 1562 * XXX buffers instead of just failing. 1563 */ 1564 FXP_RXMAP_PUT(sc, rxmap); 1565 fxp_rxdrain(sc); 1566 goto out; 1567 } 1568 } 1569 sc->sc_rxidle = 0; 1570 1571 /* 1572 * Give the transmit ring to the chip. We do this by pointing 1573 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1574 * issuing a start command. It will execute the NOP and then 1575 * suspend, pointing at the first descriptor. 1576 */ 1577 fxp_scb_wait(sc); 1578 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1579 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1580 1581 /* 1582 * Initialize receiver buffer area - RFA. 1583 */ 1584 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1585 fxp_scb_wait(sc); 1586 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1587 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1588 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1589 1590 if (sc->sc_flags & FXPF_MII) { 1591 /* 1592 * Set current media. 1593 */ 1594 mii_mediachg(&sc->sc_mii); 1595 } 1596 1597 /* 1598 * ...all done! 1599 */ 1600 ifp->if_flags |= IFF_RUNNING; 1601 ifp->if_flags &= ~IFF_OACTIVE; 1602 1603 /* 1604 * Start the one second timer. 1605 */ 1606 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1607 1608 /* 1609 * Attempt to start output on the interface. 1610 */ 1611 fxp_start(ifp); 1612 1613 out: 1614 if (error) { 1615 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1616 ifp->if_timer = 0; 1617 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1618 } 1619 return (error); 1620} 1621 1622/* 1623 * Change media according to request. 1624 */ 1625int 1626fxp_mii_mediachange(struct ifnet *ifp) 1627{ 1628 struct fxp_softc *sc = ifp->if_softc; 1629 1630 if (ifp->if_flags & IFF_UP) 1631 mii_mediachg(&sc->sc_mii); 1632 return (0); 1633} 1634 1635/* 1636 * Notify the world which media we're using. 1637 */ 1638void 1639fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1640{ 1641 struct fxp_softc *sc = ifp->if_softc; 1642 1643 if(sc->sc_enabled == 0) { 1644 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1645 ifmr->ifm_status = 0; 1646 return; 1647 } 1648 1649 mii_pollstat(&sc->sc_mii); 1650 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1651 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1652} 1653 1654int 1655fxp_80c24_mediachange(struct ifnet *ifp) 1656{ 1657 1658 /* Nothing to do here. */ 1659 return (0); 1660} 1661 1662void 1663fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1664{ 1665 struct fxp_softc *sc = ifp->if_softc; 1666 1667 /* 1668 * Media is currently-selected media. We cannot determine 1669 * the link status. 1670 */ 1671 ifmr->ifm_status = 0; 1672 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1673} 1674 1675/* 1676 * Add a buffer to the end of the RFA buffer list. 1677 * Return 0 if successful, error code on failure. 1678 * 1679 * The RFA struct is stuck at the beginning of mbuf cluster and the 1680 * data pointer is fixed up to point just past it. 1681 */ 1682int 1683fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 1684{ 1685 struct mbuf *m; 1686 int error; 1687 1688 MGETHDR(m, M_DONTWAIT, MT_DATA); 1689 if (m == NULL) 1690 return (ENOBUFS); 1691 1692 MCLGET(m, M_DONTWAIT); 1693 if ((m->m_flags & M_EXT) == 0) { 1694 m_freem(m); 1695 return (ENOBUFS); 1696 } 1697 1698 if (unload) 1699 bus_dmamap_unload(sc->sc_dmat, rxmap); 1700 1701 M_SETCTX(m, rxmap); 1702 1703 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1704 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1705 if (error) { 1706 printf("%s: can't load rx DMA map %d, error = %d\n", 1707 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 1708 panic("fxp_add_rfabuf"); /* XXX */ 1709 } 1710 1711 FXP_INIT_RFABUF(sc, m); 1712 1713 return (0); 1714} 1715 1716int 1717fxp_mdi_read(struct device *self, int phy, int reg) 1718{ 1719 struct fxp_softc *sc = (struct fxp_softc *)self; 1720 int count = 10000; 1721 int value; 1722 1723 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1724 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1725 1726 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1727 && count--) 1728 DELAY(10); 1729 1730 if (count <= 0) 1731 printf("%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 1732 1733 return (value & 0xffff); 1734} 1735 1736void 1737fxp_statchg(struct device *self) 1738{ 1739 struct fxp_softc *sc = (void *) self; 1740 1741 /* 1742 * Determine whether or not we have to work-around the 1743 * Resume Bug. 1744 */ 1745 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 1746 if (IFM_TYPE(sc->sc_mii.mii_media_active) == IFM_10_T) 1747 sc->sc_flags |= FXPF_FIX_RESUME_BUG; 1748 else 1749 sc->sc_flags &= ~FXPF_FIX_RESUME_BUG; 1750 } 1751} 1752 1753void 1754fxp_mdi_write(struct device *self, int phy, int reg, int value) 1755{ 1756 struct fxp_softc *sc = (struct fxp_softc *)self; 1757 int count = 10000; 1758 1759 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1760 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1761 (value & 0xffff)); 1762 1763 while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1764 count--) 1765 DELAY(10); 1766 1767 if (count <= 0) 1768 printf("%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 1769} 1770 1771int 1772fxp_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1773{ 1774 struct fxp_softc *sc = ifp->if_softc; 1775 struct ifreq *ifr = (struct ifreq *)data; 1776 int s, error; 1777 1778 s = splnet(); 1779 1780 switch (cmd) { 1781 case SIOCSIFMEDIA: 1782 case SIOCGIFMEDIA: 1783 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1784 break; 1785 1786 default: 1787 error = ether_ioctl(ifp, cmd, data); 1788 if (error == ENETRESET) { 1789 if (sc->sc_enabled) { 1790 /* 1791 * Multicast list has changed; set the 1792 * hardware filter accordingly. 1793 */ 1794 if (sc->sc_txpending) { 1795 sc->sc_flags |= FXPF_WANTINIT; 1796 error = 0; 1797 } else 1798 error = fxp_init(ifp); 1799 } else 1800 error = 0; 1801 } 1802 break; 1803 } 1804 1805 /* Try to get more packets going. */ 1806 if (sc->sc_enabled) 1807 fxp_start(ifp); 1808 1809 splx(s); 1810 return (error); 1811} 1812 1813/* 1814 * Program the multicast filter. 1815 * 1816 * This function must be called at splnet(). 1817 */ 1818void 1819fxp_mc_setup(struct fxp_softc *sc) 1820{ 1821 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 1822 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1823 struct ethercom *ec = &sc->sc_ethercom; 1824 struct ether_multi *enm; 1825 struct ether_multistep step; 1826 int count, nmcasts; 1827 1828#ifdef DIAGNOSTIC 1829 if (sc->sc_txpending) 1830 panic("fxp_mc_setup: pending transmissions"); 1831#endif 1832 1833 ifp->if_flags &= ~IFF_ALLMULTI; 1834 1835 /* 1836 * Initialize multicast setup descriptor. 1837 */ 1838 nmcasts = 0; 1839 ETHER_FIRST_MULTI(step, ec, enm); 1840 while (enm != NULL) { 1841 /* 1842 * Check for too many multicast addresses or if we're 1843 * listening to a range. Either way, we simply have 1844 * to accept all multicasts. 1845 */ 1846 if (nmcasts >= MAXMCADDR || 1847 memcmp(enm->enm_addrlo, enm->enm_addrhi, 1848 ETHER_ADDR_LEN) != 0) { 1849 /* 1850 * Callers of this function must do the 1851 * right thing with this. If we're called 1852 * from outside fxp_init(), the caller must 1853 * detect if the state if IFF_ALLMULTI changes. 1854 * If it does, the caller must then call 1855 * fxp_init(), since allmulti is handled by 1856 * the config block. 1857 */ 1858 ifp->if_flags |= IFF_ALLMULTI; 1859 return; 1860 } 1861 memcpy((void *)&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 1862 ETHER_ADDR_LEN); 1863 nmcasts++; 1864 ETHER_NEXT_MULTI(step, enm); 1865 } 1866 1867 /* BIG_ENDIAN: no need to swap to store 0 */ 1868 mcsp->cb_status = 0; 1869 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1870 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 1871 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 1872 1873 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1874 1875 /* 1876 * Wait until the command unit is not active. This should never 1877 * happen since nothing is queued, but make sure anyway. 1878 */ 1879 count = 100; 1880 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 1881 FXP_SCB_CUS_ACTIVE && --count) 1882 DELAY(1); 1883 if (count == 0) { 1884 printf("%s at line %d: command queue timeout\n", 1885 sc->sc_dev.dv_xname, __LINE__); 1886 return; 1887 } 1888 1889 /* 1890 * Start the multicast setup command/DMA. 1891 */ 1892 fxp_scb_wait(sc); 1893 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 1894 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1895 1896 /* ...and wait for it to complete. */ 1897 count = 1000; 1898 do { 1899 FXP_CDMCSSYNC(sc, 1900 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1901 DELAY(1); 1902 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 1903 if (count == 0) { 1904 printf("%s at line %d: dmasync timeout\n", 1905 sc->sc_dev.dv_xname, __LINE__); 1906 return; 1907 } 1908} 1909 1910int 1911fxp_enable(struct fxp_softc *sc) 1912{ 1913 1914 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 1915 if ((*sc->sc_enable)(sc) != 0) { 1916 printf("%s: device enable failed\n", 1917 sc->sc_dev.dv_xname); 1918 return (EIO); 1919 } 1920 } 1921 1922 sc->sc_enabled = 1; 1923 return (0); 1924} 1925 1926void 1927fxp_disable(struct fxp_softc *sc) 1928{ 1929 1930 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 1931 (*sc->sc_disable)(sc); 1932 sc->sc_enabled = 0; 1933 } 1934} 1935 1936/* 1937 * fxp_activate: 1938 * 1939 * Handle device activation/deactivation requests. 1940 */ 1941int 1942fxp_activate(struct device *self, enum devact act) 1943{ 1944 struct fxp_softc *sc = (void *) self; 1945 int s, error = 0; 1946 1947 s = splnet(); 1948 switch (act) { 1949 case DVACT_ACTIVATE: 1950 error = EOPNOTSUPP; 1951 break; 1952 1953 case DVACT_DEACTIVATE: 1954 if (sc->sc_flags & FXPF_MII) 1955 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 1956 MII_OFFSET_ANY); 1957 if_deactivate(&sc->sc_ethercom.ec_if); 1958 break; 1959 } 1960 splx(s); 1961 1962 return (error); 1963} 1964 1965/* 1966 * fxp_detach: 1967 * 1968 * Detach an i82557 interface. 1969 */ 1970int 1971fxp_detach(struct fxp_softc *sc) 1972{ 1973 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1974 int i; 1975 1976 /* Succeed now if there's no work to do. */ 1977 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 1978 return (0); 1979 1980 /* Unhook our tick handler. */ 1981 callout_stop(&sc->sc_callout); 1982 1983 if (sc->sc_flags & FXPF_MII) { 1984 /* Detach all PHYs */ 1985 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1986 } 1987 1988 /* Delete all remaining media. */ 1989 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 1990 1991#if NRND > 0 1992 rnd_detach_source(&sc->rnd_source); 1993#endif 1994 ether_ifdetach(ifp); 1995 if_detach(ifp); 1996 1997 for (i = 0; i < FXP_NRFABUFS; i++) { 1998 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 1999 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2000 } 2001 2002 for (i = 0; i < FXP_NTXCB; i++) { 2003 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2004 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2005 } 2006 2007 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2008 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2009 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2010 sizeof(struct fxp_control_data)); 2011 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2012 2013 shutdownhook_disestablish(sc->sc_sdhook); 2014 powerhook_disestablish(sc->sc_powerhook); 2015 2016 return (0); 2017} 2018