i82557.c revision 1.47
1/* $NetBSD: i82557.c,v 1.47 2001/05/21 21:47:52 thorpej Exp $ */ 2 3/*- 4 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40/* 41 * Copyright (c) 1995, David Greenman 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice unmodified, this list of conditions, and the following 49 * disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 55 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 57 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 60 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 62 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 63 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 * Id: if_fxp.c,v 1.47 1998/01/08 23:42:29 eivind Exp 67 */ 68 69/* 70 * Device driver for the Intel i82557 fast Ethernet controller, 71 * and its successors, the i82558 and i82559. 72 */ 73 74#include "opt_inet.h" 75#include "opt_ns.h" 76#include "bpfilter.h" 77#include "rnd.h" 78 79#include <sys/param.h> 80#include <sys/systm.h> 81#include <sys/callout.h> 82#include <sys/mbuf.h> 83#include <sys/malloc.h> 84#include <sys/kernel.h> 85#include <sys/socket.h> 86#include <sys/ioctl.h> 87#include <sys/errno.h> 88#include <sys/device.h> 89 90#include <machine/endian.h> 91 92#include <uvm/uvm_extern.h> 93 94#if NRND > 0 95#include <sys/rnd.h> 96#endif 97 98#include <net/if.h> 99#include <net/if_dl.h> 100#include <net/if_media.h> 101#include <net/if_ether.h> 102 103#if NBPFILTER > 0 104#include <net/bpf.h> 105#endif 106 107#ifdef INET 108#include <netinet/in.h> 109#include <netinet/if_inarp.h> 110#endif 111 112#ifdef NS 113#include <netns/ns.h> 114#include <netns/ns_if.h> 115#endif 116 117#include <machine/bus.h> 118#include <machine/intr.h> 119 120#include <dev/mii/miivar.h> 121 122#include <dev/ic/i82557reg.h> 123#include <dev/ic/i82557var.h> 124 125/* 126 * NOTE! On the Alpha, we have an alignment constraint. The 127 * card DMAs the packet immediately following the RFA. However, 128 * the first thing in the packet is a 14-byte Ethernet header. 129 * This means that the packet is misaligned. To compensate, 130 * we actually offset the RFA 2 bytes into the cluster. This 131 * alignes the packet after the Ethernet header at a 32-bit 132 * boundary. HOWEVER! This means that the RFA is misaligned! 133 */ 134#define RFA_ALIGNMENT_FUDGE 2 135 136/* 137 * Template for default configuration parameters. 138 * See struct fxp_cb_config for the bit definitions. 139 */ 140u_int8_t fxp_cb_config_template[] = { 141 0x0, 0x0, /* cb_status */ 142 0x80, 0x2, /* cb_command */ 143 0xff, 0xff, 0xff, 0xff, /* link_addr */ 144 0x16, /* 0 */ 145 0x8, /* 1 */ 146 0x0, /* 2 */ 147 0x0, /* 3 */ 148 0x0, /* 4 */ 149 0x80, /* 5 */ 150 0xb2, /* 6 */ 151 0x3, /* 7 */ 152 0x1, /* 8 */ 153 0x0, /* 9 */ 154 0x26, /* 10 */ 155 0x0, /* 11 */ 156 0x60, /* 12 */ 157 0x0, /* 13 */ 158 0xf2, /* 14 */ 159 0x48, /* 15 */ 160 0x0, /* 16 */ 161 0x40, /* 17 */ 162 0xf3, /* 18 */ 163 0x0, /* 19 */ 164 0x3f, /* 20 */ 165 0x5 /* 21 */ 166}; 167 168void fxp_mii_initmedia(struct fxp_softc *); 169int fxp_mii_mediachange(struct ifnet *); 170void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 171 172void fxp_80c24_initmedia(struct fxp_softc *); 173int fxp_80c24_mediachange(struct ifnet *); 174void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 175 176void fxp_start(struct ifnet *); 177int fxp_ioctl(struct ifnet *, u_long, caddr_t); 178void fxp_watchdog(struct ifnet *); 179int fxp_init(struct ifnet *); 180void fxp_stop(struct ifnet *, int); 181 182void fxp_rxdrain(struct fxp_softc *); 183int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 184int fxp_mdi_read(struct device *, int, int); 185void fxp_statchg(struct device *); 186void fxp_mdi_write(struct device *, int, int, int); 187void fxp_autosize_eeprom(struct fxp_softc*); 188void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 189void fxp_get_info(struct fxp_softc *, u_int8_t *); 190void fxp_tick(void *); 191void fxp_mc_setup(struct fxp_softc *); 192 193void fxp_shutdown(void *); 194void fxp_power(int, void *); 195 196int fxp_copy_small = 0; 197 198struct fxp_phytype { 199 int fp_phy; /* type of PHY, -1 for MII at the end. */ 200 void (*fp_init)(struct fxp_softc *); 201} fxp_phytype_table[] = { 202 { FXP_PHY_80C24, fxp_80c24_initmedia }, 203 { -1, fxp_mii_initmedia }, 204}; 205 206/* 207 * Set initial transmit threshold at 64 (512 bytes). This is 208 * increased by 64 (512 bytes) at a time, to maximum of 192 209 * (1536 bytes), if an underrun occurs. 210 */ 211static int tx_threshold = 64; 212 213/* 214 * Wait for the previous command to be accepted (but not necessarily 215 * completed). 216 */ 217static __inline void 218fxp_scb_wait(struct fxp_softc *sc) 219{ 220 int i = 10000; 221 222 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 223 delay(2); 224 if (i == 0) 225 printf("%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 226} 227 228/* 229 * Submit a command to the i82557. 230 */ 231static __inline void 232fxp_scb_cmd(struct fxp_softc *sc, u_int8_t cmd) 233{ 234 235 if (cmd == FXP_SCB_COMMAND_CU_RESUME && 236 (sc->sc_flags & FXPF_FIX_RESUME_BUG) != 0) { 237 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 238 fxp_scb_wait(sc); 239 } 240 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 241} 242 243/* 244 * Finish attaching an i82557 interface. Called by bus-specific front-end. 245 */ 246void 247fxp_attach(struct fxp_softc *sc) 248{ 249 u_int8_t enaddr[ETHER_ADDR_LEN]; 250 struct ifnet *ifp; 251 bus_dma_segment_t seg; 252 int rseg, i, error; 253 struct fxp_phytype *fp; 254 255 callout_init(&sc->sc_callout); 256 257 /* 258 * Allocate the control data structures, and create and load the 259 * DMA map for it. 260 */ 261 if ((error = bus_dmamem_alloc(sc->sc_dmat, 262 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 263 0)) != 0) { 264 printf("%s: unable to allocate control data, error = %d\n", 265 sc->sc_dev.dv_xname, error); 266 goto fail_0; 267 } 268 269 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 270 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 271 BUS_DMA_COHERENT)) != 0) { 272 printf("%s: unable to map control data, error = %d\n", 273 sc->sc_dev.dv_xname, error); 274 goto fail_1; 275 } 276 sc->sc_cdseg = seg; 277 sc->sc_cdnseg = rseg; 278 279 bzero(sc->sc_control_data, sizeof(struct fxp_control_data)); 280 281 if ((error = bus_dmamap_create(sc->sc_dmat, 282 sizeof(struct fxp_control_data), 1, 283 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 284 printf("%s: unable to create control data DMA map, " 285 "error = %d\n", sc->sc_dev.dv_xname, error); 286 goto fail_2; 287 } 288 289 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 290 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 291 0)) != 0) { 292 printf("%s: can't load control data DMA map, error = %d\n", 293 sc->sc_dev.dv_xname, error); 294 goto fail_3; 295 } 296 297 /* 298 * Create the transmit buffer DMA maps. 299 */ 300 for (i = 0; i < FXP_NTXCB; i++) { 301 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 302 FXP_NTXSEG, MCLBYTES, 0, 0, 303 &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 304 printf("%s: unable to create tx DMA map %d, " 305 "error = %d\n", sc->sc_dev.dv_xname, i, error); 306 goto fail_4; 307 } 308 } 309 310 /* 311 * Create the receive buffer DMA maps. 312 */ 313 for (i = 0; i < FXP_NRFABUFS; i++) { 314 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 315 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 316 printf("%s: unable to create rx DMA map %d, " 317 "error = %d\n", sc->sc_dev.dv_xname, i, error); 318 goto fail_5; 319 } 320 } 321 322 /* Initialize MAC address and media structures. */ 323 fxp_get_info(sc, enaddr); 324 325 printf("%s: Ethernet address %s, %s Mb/s\n", sc->sc_dev.dv_xname, 326 ether_sprintf(enaddr), sc->phy_10Mbps_only ? "10" : "10/100"); 327 328 ifp = &sc->sc_ethercom.ec_if; 329 330 /* 331 * Get info about our media interface, and initialize it. Note 332 * the table terminates itself with a phy of -1, indicating 333 * that we're using MII. 334 */ 335 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 336 if (fp->fp_phy == sc->phy_primary_device) 337 break; 338 (*fp->fp_init)(sc); 339 340 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 341 ifp->if_softc = sc; 342 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 343 ifp->if_ioctl = fxp_ioctl; 344 ifp->if_start = fxp_start; 345 ifp->if_watchdog = fxp_watchdog; 346 ifp->if_init = fxp_init; 347 ifp->if_stop = fxp_stop; 348 IFQ_SET_READY(&ifp->if_snd); 349 350 /* 351 * We can support 802.1Q VLAN-sized frames. 352 */ 353 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 354 355 /* 356 * Attach the interface. 357 */ 358 if_attach(ifp); 359 ether_ifattach(ifp, enaddr); 360#if NRND > 0 361 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 362 RND_TYPE_NET, 0); 363#endif 364 365 /* 366 * Add shutdown hook so that DMA is disabled prior to reboot. Not 367 * doing do could allow DMA to corrupt kernel memory during the 368 * reboot before the driver initializes. 369 */ 370 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 371 if (sc->sc_sdhook == NULL) 372 printf("%s: WARNING: unable to establish shutdown hook\n", 373 sc->sc_dev.dv_xname); 374 /* 375 * Add suspend hook, for similar reasons.. 376 */ 377 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 378 if (sc->sc_powerhook == NULL) 379 printf("%s: WARNING: unable to establish power hook\n", 380 sc->sc_dev.dv_xname); 381 382 /* The attach is successful. */ 383 sc->sc_flags |= FXPF_ATTACHED; 384 385 return; 386 387 /* 388 * Free any resources we've allocated during the failed attach 389 * attempt. Do this in reverse order and fall though. 390 */ 391 fail_5: 392 for (i = 0; i < FXP_NRFABUFS; i++) { 393 if (sc->sc_rxmaps[i] != NULL) 394 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 395 } 396 fail_4: 397 for (i = 0; i < FXP_NTXCB; i++) { 398 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 399 bus_dmamap_destroy(sc->sc_dmat, 400 FXP_DSTX(sc, i)->txs_dmamap); 401 } 402 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 403 fail_3: 404 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 405 fail_2: 406 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 407 sizeof(struct fxp_control_data)); 408 fail_1: 409 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 410 fail_0: 411 return; 412} 413 414void 415fxp_mii_initmedia(struct fxp_softc *sc) 416{ 417 418 sc->sc_flags |= FXPF_MII; 419 420 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 421 sc->sc_mii.mii_readreg = fxp_mdi_read; 422 sc->sc_mii.mii_writereg = fxp_mdi_write; 423 sc->sc_mii.mii_statchg = fxp_statchg; 424 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_mii_mediachange, 425 fxp_mii_mediastatus); 426 /* 427 * The i82557 wedges if all of its PHYs are isolated! 428 */ 429 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 430 MII_OFFSET_ANY, MIIF_NOISOLATE); 431 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 432 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 433 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 434 } else 435 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 436} 437 438void 439fxp_80c24_initmedia(struct fxp_softc *sc) 440{ 441 442 /* 443 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 444 * doesn't have a programming interface of any sort. The 445 * media is sensed automatically based on how the link partner 446 * is configured. This is, in essence, manual configuration. 447 */ 448 printf("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 449 sc->sc_dev.dv_xname); 450 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 451 fxp_80c24_mediastatus); 452 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 453 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 454} 455 456/* 457 * Device shutdown routine. Called at system shutdown after sync. The 458 * main purpose of this routine is to shut off receiver DMA so that 459 * kernel memory doesn't get clobbered during warmboot. 460 */ 461void 462fxp_shutdown(void *arg) 463{ 464 struct fxp_softc *sc = arg; 465 466 /* 467 * Since the system's going to halt shortly, don't bother 468 * freeing mbufs. 469 */ 470 fxp_stop(&sc->sc_ethercom.ec_if, 0); 471} 472/* 473 * Power handler routine. Called when the system is transitioning 474 * into/out of power save modes. As with fxp_shutdown, the main 475 * purpose of this routine is to shut off receiver DMA so it doesn't 476 * clobber kernel memory at the wrong time. 477 */ 478void 479fxp_power(int why, void *arg) 480{ 481 struct fxp_softc *sc = arg; 482 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 483 int s; 484 485 s = splnet(); 486 switch (why) { 487 case PWR_SUSPEND: 488 case PWR_STANDBY: 489 fxp_stop(ifp, 0); 490 break; 491 case PWR_RESUME: 492 if (ifp->if_flags & IFF_UP) 493 fxp_init(ifp); 494 break; 495 case PWR_SOFTSUSPEND: 496 case PWR_SOFTSTANDBY: 497 case PWR_SOFTRESUME: 498 break; 499 } 500 splx(s); 501} 502 503/* 504 * Initialize the interface media. 505 */ 506void 507fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 508{ 509 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 510 511 /* 512 * Reset to a stable state. 513 */ 514 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 515 DELAY(10); 516 517 sc->sc_eeprom_size = 0; 518 fxp_autosize_eeprom(sc); 519 if(sc->sc_eeprom_size == 0) { 520 printf("%s: failed to detect EEPROM size\n", sc->sc_dev.dv_xname); 521 sc->sc_eeprom_size = 6; /* XXX panic here? */ 522 } 523#ifdef DEBUG 524 printf("%s: detected %d word EEPROM\n", 525 sc->sc_dev.dv_xname, 526 1 << sc->sc_eeprom_size); 527#endif 528 529 /* 530 * Get info about the primary PHY 531 */ 532 fxp_read_eeprom(sc, &data, 6, 1); 533 sc->phy_primary_addr = data & 0xff; 534 sc->phy_primary_device = (data >> 8) & 0x3f; 535 sc->phy_10Mbps_only = data >> 15; 536 537 /* 538 * Read MAC address. 539 */ 540 fxp_read_eeprom(sc, myea, 0, 3); 541 enaddr[0] = myea[0] & 0xff; 542 enaddr[1] = myea[0] >> 8; 543 enaddr[2] = myea[1] & 0xff; 544 enaddr[3] = myea[1] >> 8; 545 enaddr[4] = myea[2] & 0xff; 546 enaddr[5] = myea[2] >> 8; 547} 548 549/* 550 * Figure out EEPROM size. 551 * 552 * 559's can have either 64-word or 256-word EEPROMs, the 558 553 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 554 * talks about the existance of 16 to 256 word EEPROMs. 555 * 556 * The only known sizes are 64 and 256, where the 256 version is used 557 * by CardBus cards to store CIS information. 558 * 559 * The address is shifted in msb-to-lsb, and after the last 560 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 561 * after which follows the actual data. We try to detect this zero, by 562 * probing the data-out bit in the EEPROM control register just after 563 * having shifted in a bit. If the bit is zero, we assume we've 564 * shifted enough address bits. The data-out should be tri-state, 565 * before this, which should translate to a logical one. 566 * 567 * Other ways to do this would be to try to read a register with known 568 * contents with a varying number of address bits, but no such 569 * register seem to be available. The high bits of register 10 are 01 570 * on the 558 and 559, but apparently not on the 557. 571 * 572 * The Linux driver computes a checksum on the EEPROM data, but the 573 * value of this checksum is not very well documented. 574 */ 575 576void 577fxp_autosize_eeprom(struct fxp_softc *sc) 578{ 579 u_int16_t reg; 580 int x; 581 582 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 583 /* 584 * Shift in read opcode. 585 */ 586 for (x = 3; x > 0; x--) { 587 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 588 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 589 } else { 590 reg = FXP_EEPROM_EECS; 591 } 592 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 593 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 594 reg | FXP_EEPROM_EESK); 595 DELAY(4); 596 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 597 DELAY(4); 598 } 599 /* 600 * Shift in address, wait for the dummy zero following a correct 601 * address shift. 602 */ 603 for (x = 1; x <= 8; x++) { 604 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 605 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 606 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 607 DELAY(4); 608 if((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 609 FXP_EEPROM_EEDO) == 0) 610 break; 611 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 612 DELAY(4); 613 } 614 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 615 DELAY(4); 616 if(x != 6 && x != 8) { 617#ifdef DEBUG 618 printf("%s: strange EEPROM size (%d)\n", 619 sc->sc_dev.dv_xname, 1 << x); 620#endif 621 } else 622 sc->sc_eeprom_size = x; 623} 624 625/* 626 * Read from the serial EEPROM. Basically, you manually shift in 627 * the read opcode (one bit at a time) and then shift in the address, 628 * and then you shift out the data (all of this one bit at a time). 629 * The word size is 16 bits, so you have to provide the address for 630 * every 16 bits of data. 631 */ 632void 633fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 634{ 635 u_int16_t reg; 636 int i, x; 637 638 for (i = 0; i < words; i++) { 639 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 640 /* 641 * Shift in read opcode. 642 */ 643 for (x = 3; x > 0; x--) { 644 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 645 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 646 } else { 647 reg = FXP_EEPROM_EECS; 648 } 649 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 650 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 651 reg | FXP_EEPROM_EESK); 652 DELAY(4); 653 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 654 DELAY(4); 655 } 656 /* 657 * Shift in address. 658 */ 659 for (x = sc->sc_eeprom_size; x > 0; x--) { 660 if ((i + offset) & (1 << (x - 1))) { 661 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 662 } else { 663 reg = FXP_EEPROM_EECS; 664 } 665 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 666 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 667 reg | FXP_EEPROM_EESK); 668 DELAY(4); 669 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 670 DELAY(4); 671 } 672 reg = FXP_EEPROM_EECS; 673 data[i] = 0; 674 /* 675 * Shift out data. 676 */ 677 for (x = 16; x > 0; x--) { 678 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 679 reg | FXP_EEPROM_EESK); 680 DELAY(4); 681 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 682 FXP_EEPROM_EEDO) 683 data[i] |= (1 << (x - 1)); 684 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 685 DELAY(4); 686 } 687 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 688 DELAY(4); 689 } 690} 691 692/* 693 * Start packet transmission on the interface. 694 */ 695void 696fxp_start(struct ifnet *ifp) 697{ 698 struct fxp_softc *sc = ifp->if_softc; 699 struct mbuf *m0, *m; 700 struct fxp_cb_tx *txd; 701 struct fxp_txsoft *txs; 702 struct fxp_tbdlist *tbd; 703 bus_dmamap_t dmamap; 704 int error, lasttx, nexttx, opending, seg; 705 706 /* 707 * If we want a re-init, bail out now. 708 */ 709 if (sc->sc_flags & FXPF_WANTINIT) { 710 ifp->if_flags |= IFF_OACTIVE; 711 return; 712 } 713 714 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 715 return; 716 717 /* 718 * Remember the previous txpending and the current lasttx. 719 */ 720 opending = sc->sc_txpending; 721 lasttx = sc->sc_txlast; 722 723 /* 724 * Loop through the send queue, setting up transmit descriptors 725 * until we drain the queue, or use up all available transmit 726 * descriptors. 727 */ 728 while (sc->sc_txpending < FXP_NTXCB) { 729 /* 730 * Grab a packet off the queue. 731 */ 732 IFQ_POLL(&ifp->if_snd, m0); 733 if (m0 == NULL) 734 break; 735 m = NULL; 736 737 /* 738 * Get the next available transmit descriptor. 739 */ 740 nexttx = FXP_NEXTTX(sc->sc_txlast); 741 txd = FXP_CDTX(sc, nexttx); 742 tbd = FXP_CDTBD(sc, nexttx); 743 txs = FXP_DSTX(sc, nexttx); 744 dmamap = txs->txs_dmamap; 745 746 /* 747 * Load the DMA map. If this fails, the packet either 748 * didn't fit in the allotted number of frags, or we were 749 * short on resources. In this case, we'll copy and try 750 * again. 751 */ 752 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 753 BUS_DMA_NOWAIT) != 0) { 754 MGETHDR(m, M_DONTWAIT, MT_DATA); 755 if (m == NULL) { 756 printf("%s: unable to allocate Tx mbuf\n", 757 sc->sc_dev.dv_xname); 758 break; 759 } 760 if (m0->m_pkthdr.len > MHLEN) { 761 MCLGET(m, M_DONTWAIT); 762 if ((m->m_flags & M_EXT) == 0) { 763 printf("%s: unable to allocate Tx " 764 "cluster\n", sc->sc_dev.dv_xname); 765 m_freem(m); 766 break; 767 } 768 } 769 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 770 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 771 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 772 m, BUS_DMA_NOWAIT); 773 if (error) { 774 printf("%s: unable to load Tx buffer, " 775 "error = %d\n", sc->sc_dev.dv_xname, error); 776 break; 777 } 778 } 779 780 IFQ_DEQUEUE(&ifp->if_snd, m0); 781 if (m != NULL) { 782 m_freem(m0); 783 m0 = m; 784 } 785 786 /* Initialize the fraglist. */ 787 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 788 tbd->tbd_d[seg].tb_addr = 789 htole32(dmamap->dm_segs[seg].ds_addr); 790 tbd->tbd_d[seg].tb_size = 791 htole32(dmamap->dm_segs[seg].ds_len); 792 } 793 794 FXP_CDTBDSYNC(sc, nexttx, BUS_DMASYNC_PREWRITE); 795 796 /* Sync the DMA map. */ 797 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 798 BUS_DMASYNC_PREWRITE); 799 800 /* 801 * Store a pointer to the packet so we can free it later. 802 */ 803 txs->txs_mbuf = m0; 804 805 /* 806 * Initialize the transmit descriptor. 807 */ 808 /* BIG_ENDIAN: no need to swap to store 0 */ 809 txd->cb_status = 0; 810 txd->cb_command = 811 htole16(FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF); 812 txd->tx_threshold = tx_threshold; 813 txd->tbd_number = dmamap->dm_nsegs; 814 815 FXP_CDTXSYNC(sc, nexttx, 816 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 817 818 /* Advance the tx pointer. */ 819 sc->sc_txpending++; 820 sc->sc_txlast = nexttx; 821 822#if NBPFILTER > 0 823 /* 824 * Pass packet to bpf if there is a listener. 825 */ 826 if (ifp->if_bpf) 827 bpf_mtap(ifp->if_bpf, m0); 828#endif 829 } 830 831 if (sc->sc_txpending == FXP_NTXCB) { 832 /* No more slots; notify upper layer. */ 833 ifp->if_flags |= IFF_OACTIVE; 834 } 835 836 if (sc->sc_txpending != opending) { 837 /* 838 * We enqueued packets. If the transmitter was idle, 839 * reset the txdirty pointer. 840 */ 841 if (opending == 0) 842 sc->sc_txdirty = FXP_NEXTTX(lasttx); 843 844 /* 845 * Cause the chip to interrupt and suspend command 846 * processing once the last packet we've enqueued 847 * has been transmitted. 848 */ 849 FXP_CDTX(sc, sc->sc_txlast)->cb_command |= 850 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 851 FXP_CDTXSYNC(sc, sc->sc_txlast, 852 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 853 854 /* 855 * The entire packet chain is set up. Clear the suspend bit 856 * on the command prior to the first packet we set up. 857 */ 858 FXP_CDTXSYNC(sc, lasttx, 859 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 860 FXP_CDTX(sc, lasttx)->cb_command &= htole16(~FXP_CB_COMMAND_S); 861 FXP_CDTXSYNC(sc, lasttx, 862 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 863 864 /* 865 * Issue a Resume command in case the chip was suspended. 866 */ 867 fxp_scb_wait(sc); 868 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 869 870 /* Set a watchdog timer in case the chip flakes out. */ 871 ifp->if_timer = 5; 872 } 873} 874 875/* 876 * Process interface interrupts. 877 */ 878int 879fxp_intr(void *arg) 880{ 881 struct fxp_softc *sc = arg; 882 struct ethercom *ec = &sc->sc_ethercom; 883 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 884 struct fxp_cb_tx *txd; 885 struct fxp_txsoft *txs; 886 struct mbuf *m, *m0; 887 bus_dmamap_t rxmap; 888 struct fxp_rfa *rfa; 889 int i, claimed = 0; 890 u_int16_t len, rxstat, txstat; 891 u_int8_t statack; 892 893 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 894 return (0); 895 /* 896 * If the interface isn't running, don't try to 897 * service the interrupt.. just ack it and bail. 898 */ 899 if ((ifp->if_flags & IFF_RUNNING) == 0) { 900 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 901 if (statack) { 902 claimed = 1; 903 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 904 } 905 return (claimed); 906 } 907 908 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 909 claimed = 1; 910 911 /* 912 * First ACK all the interrupts in this pass. 913 */ 914 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 915 916 /* 917 * Process receiver interrupts. If a no-resource (RNR) 918 * condition exists, get whatever packets we can and 919 * re-start the receiver. 920 */ 921 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 922 rcvloop: 923 m = sc->sc_rxq.ifq_head; 924 rfa = FXP_MTORFA(m); 925 rxmap = M_GETCTX(m, bus_dmamap_t); 926 927 FXP_RFASYNC(sc, m, 928 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 929 930 rxstat = le16toh(rfa->rfa_status); 931 932 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 933 /* 934 * We have processed all of the 935 * receive buffers. 936 */ 937 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 938 goto do_transmit; 939 } 940 941 IF_DEQUEUE(&sc->sc_rxq, m); 942 943 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 944 945 len = le16toh(rfa->actual_size) & 946 (m->m_ext.ext_size - 1); 947 948 if (len < sizeof(struct ether_header)) { 949 /* 950 * Runt packet; drop it now. 951 */ 952 FXP_INIT_RFABUF(sc, m); 953 goto rcvloop; 954 } 955 956 /* 957 * If support for 802.1Q VLAN sized frames is 958 * enabled, we need to do some additional error 959 * checking (as we are saving bad frames, in 960 * order to receive the larger ones). 961 */ 962 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 963 (rxstat & (FXP_RFA_STATUS_OVERRUN| 964 FXP_RFA_STATUS_RNR| 965 FXP_RFA_STATUS_ALIGN| 966 FXP_RFA_STATUS_CRC)) != 0) { 967 FXP_INIT_RFABUF(sc, m); 968 goto rcvloop; 969 } 970 971 /* 972 * If the packet is small enough to fit in a 973 * single header mbuf, allocate one and copy 974 * the data into it. This greatly reduces 975 * memory consumption when we receive lots 976 * of small packets. 977 * 978 * Otherwise, we add a new buffer to the receive 979 * chain. If this fails, we drop the packet and 980 * recycle the old buffer. 981 */ 982 if (fxp_copy_small != 0 && len <= MHLEN) { 983 MGETHDR(m0, M_DONTWAIT, MT_DATA); 984 if (m == NULL) 985 goto dropit; 986 memcpy(mtod(m0, caddr_t), 987 mtod(m, caddr_t), len); 988 FXP_INIT_RFABUF(sc, m); 989 m = m0; 990 } else { 991 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 992 dropit: 993 ifp->if_ierrors++; 994 FXP_INIT_RFABUF(sc, m); 995 goto rcvloop; 996 } 997 } 998 999 m->m_pkthdr.rcvif = ifp; 1000 m->m_pkthdr.len = m->m_len = len; 1001 1002#if NBPFILTER > 0 1003 /* 1004 * Pass this up to any BPF listeners, but only 1005 * pass it up the stack it its for us. 1006 */ 1007 if (ifp->if_bpf) 1008 bpf_mtap(ifp->if_bpf, m); 1009#endif 1010 1011 /* Pass it on. */ 1012 (*ifp->if_input)(ifp, m); 1013 goto rcvloop; 1014 } 1015 1016 do_transmit: 1017 if (statack & FXP_SCB_STATACK_RNR) { 1018 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1019 fxp_scb_wait(sc); 1020 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1021 rxmap->dm_segs[0].ds_addr + 1022 RFA_ALIGNMENT_FUDGE); 1023 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1024 } 1025 1026 /* 1027 * Free any finished transmit mbuf chains. 1028 */ 1029 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1030 ifp->if_flags &= ~IFF_OACTIVE; 1031 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1032 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1033 txd = FXP_CDTX(sc, i); 1034 txs = FXP_DSTX(sc, i); 1035 1036 FXP_CDTXSYNC(sc, i, 1037 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1038 1039 txstat = le16toh(txd->cb_status); 1040 1041 if ((txstat & FXP_CB_STATUS_C) == 0) 1042 break; 1043 1044 FXP_CDTBDSYNC(sc, i, BUS_DMASYNC_POSTWRITE); 1045 1046 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1047 0, txs->txs_dmamap->dm_mapsize, 1048 BUS_DMASYNC_POSTWRITE); 1049 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1050 m_freem(txs->txs_mbuf); 1051 txs->txs_mbuf = NULL; 1052 } 1053 1054 /* Update the dirty transmit buffer pointer. */ 1055 sc->sc_txdirty = i; 1056 1057 /* 1058 * Cancel the watchdog timer if there are no pending 1059 * transmissions. 1060 */ 1061 if (sc->sc_txpending == 0) { 1062 ifp->if_timer = 0; 1063 1064 /* 1065 * If we want a re-init, do that now. 1066 */ 1067 if (sc->sc_flags & FXPF_WANTINIT) 1068 (void) fxp_init(ifp); 1069 } 1070 1071 /* 1072 * Try to get more packets going. 1073 */ 1074 fxp_start(ifp); 1075 } 1076 } 1077 1078#if NRND > 0 1079 if (claimed) 1080 rnd_add_uint32(&sc->rnd_source, statack); 1081#endif 1082 return (claimed); 1083} 1084 1085/* 1086 * Update packet in/out/collision statistics. The i82557 doesn't 1087 * allow you to access these counters without doing a fairly 1088 * expensive DMA to get _all_ of the statistics it maintains, so 1089 * we do this operation here only once per second. The statistics 1090 * counters in the kernel are updated from the previous dump-stats 1091 * DMA and then a new dump-stats DMA is started. The on-chip 1092 * counters are zeroed when the DMA completes. If we can't start 1093 * the DMA immediately, we don't wait - we just prepare to read 1094 * them again next time. 1095 */ 1096void 1097fxp_tick(void *arg) 1098{ 1099 struct fxp_softc *sc = arg; 1100 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1101 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1102 int s; 1103 1104 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1105 return; 1106 1107 s = splnet(); 1108 1109 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1110 1111 ifp->if_opackets += le32toh(sp->tx_good); 1112 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1113 if (sp->rx_good) { 1114 ifp->if_ipackets += le32toh(sp->rx_good); 1115 sc->sc_rxidle = 0; 1116 } else { 1117 sc->sc_rxidle++; 1118 } 1119 ifp->if_ierrors += 1120 le32toh(sp->rx_crc_errors) + 1121 le32toh(sp->rx_alignment_errors) + 1122 le32toh(sp->rx_rnr_errors) + 1123 le32toh(sp->rx_overrun_errors); 1124 /* 1125 * If any transmit underruns occured, bump up the transmit 1126 * threshold by another 512 bytes (64 * 8). 1127 */ 1128 if (sp->tx_underruns) { 1129 ifp->if_oerrors += le32toh(sp->tx_underruns); 1130 if (tx_threshold < 192) 1131 tx_threshold += 64; 1132 } 1133 1134 /* 1135 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1136 * then assume the receiver has locked up and attempt to clear 1137 * the condition by reprogramming the multicast filter (actually, 1138 * resetting the interface). This is a work-around for a bug in 1139 * the 82557 where the receiver locks up if it gets certain types 1140 * of garbage in the syncronization bits prior to the packet header. 1141 * This bug is supposed to only occur in 10Mbps mode, but has been 1142 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1143 * speed transition). 1144 */ 1145 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1146 (void) fxp_init(ifp); 1147 splx(s); 1148 return; 1149 } 1150 /* 1151 * If there is no pending command, start another stats 1152 * dump. Otherwise punt for now. 1153 */ 1154 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1155 /* 1156 * Start another stats dump. 1157 */ 1158 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1159 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1160 } else { 1161 /* 1162 * A previous command is still waiting to be accepted. 1163 * Just zero our copy of the stats and wait for the 1164 * next timer event to update them. 1165 */ 1166 /* BIG_ENDIAN: no swap required to store 0 */ 1167 sp->tx_good = 0; 1168 sp->tx_underruns = 0; 1169 sp->tx_total_collisions = 0; 1170 1171 sp->rx_good = 0; 1172 sp->rx_crc_errors = 0; 1173 sp->rx_alignment_errors = 0; 1174 sp->rx_rnr_errors = 0; 1175 sp->rx_overrun_errors = 0; 1176 } 1177 1178 if (sc->sc_flags & FXPF_MII) { 1179 /* Tick the MII clock. */ 1180 mii_tick(&sc->sc_mii); 1181 } 1182 1183 splx(s); 1184 1185 /* 1186 * Schedule another timeout one second from now. 1187 */ 1188 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1189} 1190 1191/* 1192 * Drain the receive queue. 1193 */ 1194void 1195fxp_rxdrain(struct fxp_softc *sc) 1196{ 1197 bus_dmamap_t rxmap; 1198 struct mbuf *m; 1199 1200 for (;;) { 1201 IF_DEQUEUE(&sc->sc_rxq, m); 1202 if (m == NULL) 1203 break; 1204 rxmap = M_GETCTX(m, bus_dmamap_t); 1205 bus_dmamap_unload(sc->sc_dmat, rxmap); 1206 FXP_RXMAP_PUT(sc, rxmap); 1207 m_freem(m); 1208 } 1209} 1210 1211/* 1212 * Stop the interface. Cancels the statistics updater and resets 1213 * the interface. 1214 */ 1215void 1216fxp_stop(struct ifnet *ifp, int disable) 1217{ 1218 struct fxp_softc *sc = ifp->if_softc; 1219 struct fxp_txsoft *txs; 1220 int i; 1221 1222 /* 1223 * Turn down interface (done early to avoid bad interactions 1224 * between panics, shutdown hooks, and the watchdog timer) 1225 */ 1226 ifp->if_timer = 0; 1227 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1228 1229 /* 1230 * Cancel stats updater. 1231 */ 1232 callout_stop(&sc->sc_callout); 1233 if (sc->sc_flags & FXPF_MII) { 1234 /* Down the MII. */ 1235 mii_down(&sc->sc_mii); 1236 } 1237 1238 /* 1239 * Issue software reset 1240 */ 1241 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1242 DELAY(10); 1243 1244 /* 1245 * Release any xmit buffers. 1246 */ 1247 for (i = 0; i < FXP_NTXCB; i++) { 1248 txs = FXP_DSTX(sc, i); 1249 if (txs->txs_mbuf != NULL) { 1250 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1251 m_freem(txs->txs_mbuf); 1252 txs->txs_mbuf = NULL; 1253 } 1254 } 1255 sc->sc_txpending = 0; 1256 1257 if (disable) { 1258 fxp_rxdrain(sc); 1259 fxp_disable(sc); 1260 } 1261 1262} 1263 1264/* 1265 * Watchdog/transmission transmit timeout handler. Called when a 1266 * transmission is started on the interface, but no interrupt is 1267 * received before the timeout. This usually indicates that the 1268 * card has wedged for some reason. 1269 */ 1270void 1271fxp_watchdog(struct ifnet *ifp) 1272{ 1273 struct fxp_softc *sc = ifp->if_softc; 1274 1275 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1276 ifp->if_oerrors++; 1277 1278 (void) fxp_init(ifp); 1279} 1280 1281/* 1282 * Initialize the interface. Must be called at splnet(). 1283 */ 1284int 1285fxp_init(struct ifnet *ifp) 1286{ 1287 struct fxp_softc *sc = ifp->if_softc; 1288 struct fxp_cb_config *cbp; 1289 struct fxp_cb_ias *cb_ias; 1290 struct fxp_cb_tx *txd; 1291 bus_dmamap_t rxmap; 1292 int i, prm, save_bf, allm, error = 0; 1293 1294 if ((error = fxp_enable(sc)) != 0) 1295 goto out; 1296 1297 /* 1298 * Cancel any pending I/O 1299 */ 1300 fxp_stop(ifp, 0); 1301 1302 /* 1303 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1304 * flag, and this prevents the MII from detaching resulting in 1305 * a panic. The flags field should perhaps be split in runtime 1306 * flags and more static information. For now, just clear the 1307 * only other flag set. 1308 */ 1309 1310 sc->sc_flags &= ~FXPF_WANTINIT; 1311 1312 /* 1313 * Initialize base of CBL and RFA memory. Loading with zero 1314 * sets it up for regular linear addressing. 1315 */ 1316 fxp_scb_wait(sc); 1317 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1318 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1319 1320 fxp_scb_wait(sc); 1321 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1322 1323 /* 1324 * Initialize the multicast filter. Do this now, since we might 1325 * have to setup the config block differently. 1326 */ 1327 fxp_mc_setup(sc); 1328 1329 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1330 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1331 1332 /* 1333 * In order to support receiving 802.1Q VLAN frames, we have to 1334 * enable "save bad frames", since they are 4 bytes larger than 1335 * the normal Ethernet maximum frame length. 1336 */ 1337 save_bf = (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 1 : 0; 1338 1339 /* 1340 * Initialize base of dump-stats buffer. 1341 */ 1342 fxp_scb_wait(sc); 1343 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1344 sc->sc_cddma + FXP_CDSTATSOFF); 1345 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1346 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1347 1348 cbp = &sc->sc_control_data->fcd_configcb; 1349 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1350 1351 /* 1352 * This copy is kind of disgusting, but there are a bunch of must be 1353 * zero and must be one bits in this structure and this is the easiest 1354 * way to initialize them all to proper values. 1355 */ 1356 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1357 1358 /* BIG_ENDIAN: no need to swap to store 0 */ 1359 cbp->cb_status = 0; 1360 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1361 FXP_CB_COMMAND_EL); 1362 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1363 cbp->link_addr = 0xffffffff; /* (no) next command */ 1364 cbp->byte_count = 22; /* (22) bytes to config */ 1365 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1366 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1367 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1368 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1369 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1370 cbp->dma_bce = 0; /* (disable) dma max counters */ 1371 cbp->late_scb = 0; /* (don't) defer SCB update */ 1372 cbp->tno_int = 0; /* (disable) tx not okay interrupt */ 1373 cbp->ci_int = 1; /* interrupt on CU idle */ 1374 cbp->save_bf = save_bf;/* save bad frames */ 1375 cbp->disc_short_rx = !prm; /* discard short packets */ 1376 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1377 cbp->mediatype = !sc->phy_10Mbps_only; /* interface mode */ 1378 cbp->nsai = 1; /* (don't) disable source addr insert */ 1379 cbp->preamble_length = 2; /* (7 byte) preamble */ 1380 cbp->loopback = 0; /* (don't) loopback */ 1381 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1382 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1383 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1384 cbp->promiscuous = prm; /* promiscuous mode */ 1385 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1386 cbp->crscdt = 0; /* (CRS only) */ 1387 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1388 cbp->padding = 1; /* (do) pad short tx packets */ 1389 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1390 cbp->force_fdx = 0; /* (don't) force full duplex */ 1391 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1392 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1393 cbp->mc_all = allm; /* accept all multicasts */ 1394 1395 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1396 1397 /* 1398 * Start the config command/DMA. 1399 */ 1400 fxp_scb_wait(sc); 1401 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1402 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1403 /* ...and wait for it to complete. */ 1404 i = 1000; 1405 do { 1406 FXP_CDCONFIGSYNC(sc, 1407 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1408 DELAY(1); 1409 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1410 if (i == 0) { 1411 printf("%s at line %d: dmasync timeout\n", 1412 sc->sc_dev.dv_xname, __LINE__); 1413 return ETIMEDOUT; 1414 } 1415 1416 /* 1417 * Initialize the station address. 1418 */ 1419 cb_ias = &sc->sc_control_data->fcd_iascb; 1420 /* BIG_ENDIAN: no need to swap to store 0 */ 1421 cb_ias->cb_status = 0; 1422 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1423 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1424 cb_ias->link_addr = 0xffffffff; 1425 memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1426 1427 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1428 1429 /* 1430 * Start the IAS (Individual Address Setup) command/DMA. 1431 */ 1432 fxp_scb_wait(sc); 1433 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1434 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1435 /* ...and wait for it to complete. */ 1436 i = 1000; 1437 do { 1438 FXP_CDIASSYNC(sc, 1439 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1440 DELAY(1); 1441 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1442 if (i == 0) { 1443 printf("%s at line %d: dmasync timeout\n", 1444 sc->sc_dev.dv_xname, __LINE__); 1445 return ETIMEDOUT; 1446 } 1447 1448 /* 1449 * Initialize the transmit descriptor ring. txlast is initialized 1450 * to the end of the list so that it will wrap around to the first 1451 * descriptor when the first packet is transmitted. 1452 */ 1453 for (i = 0; i < FXP_NTXCB; i++) { 1454 txd = FXP_CDTX(sc, i); 1455 memset(txd, 0, sizeof(struct fxp_cb_tx)); 1456 txd->cb_command = 1457 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1458 txd->tbd_array_addr = htole32(FXP_CDTBDADDR(sc, i)); 1459 txd->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1460 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1461 } 1462 sc->sc_txpending = 0; 1463 sc->sc_txdirty = 0; 1464 sc->sc_txlast = FXP_NTXCB - 1; 1465 1466 /* 1467 * Initialize the receive buffer list. 1468 */ 1469 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1470 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1471 rxmap = FXP_RXMAP_GET(sc); 1472 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1473 printf("%s: unable to allocate or map rx " 1474 "buffer %d, error = %d\n", 1475 sc->sc_dev.dv_xname, 1476 sc->sc_rxq.ifq_len, error); 1477 /* 1478 * XXX Should attempt to run with fewer receive 1479 * XXX buffers instead of just failing. 1480 */ 1481 FXP_RXMAP_PUT(sc, rxmap); 1482 fxp_rxdrain(sc); 1483 goto out; 1484 } 1485 } 1486 sc->sc_rxidle = 0; 1487 1488 /* 1489 * Give the transmit ring to the chip. We do this by pointing 1490 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1491 * issuing a start command. It will execute the NOP and then 1492 * suspend, pointing at the first descriptor. 1493 */ 1494 fxp_scb_wait(sc); 1495 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1496 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1497 1498 /* 1499 * Initialize receiver buffer area - RFA. 1500 */ 1501 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1502 fxp_scb_wait(sc); 1503 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1504 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1505 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1506 1507 if (sc->sc_flags & FXPF_MII) { 1508 /* 1509 * Set current media. 1510 */ 1511 mii_mediachg(&sc->sc_mii); 1512 } 1513 1514 /* 1515 * ...all done! 1516 */ 1517 ifp->if_flags |= IFF_RUNNING; 1518 ifp->if_flags &= ~IFF_OACTIVE; 1519 1520 /* 1521 * Start the one second timer. 1522 */ 1523 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1524 1525 /* 1526 * Attempt to start output on the interface. 1527 */ 1528 fxp_start(ifp); 1529 1530 out: 1531 if (error) { 1532 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1533 ifp->if_timer = 0; 1534 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1535 } 1536 return (error); 1537} 1538 1539/* 1540 * Change media according to request. 1541 */ 1542int 1543fxp_mii_mediachange(struct ifnet *ifp) 1544{ 1545 struct fxp_softc *sc = ifp->if_softc; 1546 1547 if (ifp->if_flags & IFF_UP) 1548 mii_mediachg(&sc->sc_mii); 1549 return (0); 1550} 1551 1552/* 1553 * Notify the world which media we're using. 1554 */ 1555void 1556fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1557{ 1558 struct fxp_softc *sc = ifp->if_softc; 1559 1560 if(sc->sc_enabled == 0) { 1561 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1562 ifmr->ifm_status = 0; 1563 return; 1564 } 1565 1566 mii_pollstat(&sc->sc_mii); 1567 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1568 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1569} 1570 1571int 1572fxp_80c24_mediachange(struct ifnet *ifp) 1573{ 1574 1575 /* Nothing to do here. */ 1576 return (0); 1577} 1578 1579void 1580fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1581{ 1582 struct fxp_softc *sc = ifp->if_softc; 1583 1584 /* 1585 * Media is currently-selected media. We cannot determine 1586 * the link status. 1587 */ 1588 ifmr->ifm_status = 0; 1589 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1590} 1591 1592/* 1593 * Add a buffer to the end of the RFA buffer list. 1594 * Return 0 if successful, error code on failure. 1595 * 1596 * The RFA struct is stuck at the beginning of mbuf cluster and the 1597 * data pointer is fixed up to point just past it. 1598 */ 1599int 1600fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 1601{ 1602 struct mbuf *m; 1603 int error; 1604 1605 MGETHDR(m, M_DONTWAIT, MT_DATA); 1606 if (m == NULL) 1607 return (ENOBUFS); 1608 1609 MCLGET(m, M_DONTWAIT); 1610 if ((m->m_flags & M_EXT) == 0) { 1611 m_freem(m); 1612 return (ENOBUFS); 1613 } 1614 1615 if (unload) 1616 bus_dmamap_unload(sc->sc_dmat, rxmap); 1617 1618 M_SETCTX(m, rxmap); 1619 1620 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1621 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1622 if (error) { 1623 printf("%s: can't load rx DMA map %d, error = %d\n", 1624 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 1625 panic("fxp_add_rfabuf"); /* XXX */ 1626 } 1627 1628 FXP_INIT_RFABUF(sc, m); 1629 1630 return (0); 1631} 1632 1633int 1634fxp_mdi_read(struct device *self, int phy, int reg) 1635{ 1636 struct fxp_softc *sc = (struct fxp_softc *)self; 1637 int count = 10000; 1638 int value; 1639 1640 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1641 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1642 1643 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1644 && count--) 1645 DELAY(10); 1646 1647 if (count <= 0) 1648 printf("%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 1649 1650 return (value & 0xffff); 1651} 1652 1653void 1654fxp_statchg(struct device *self) 1655{ 1656 struct fxp_softc *sc = (void *) self; 1657 1658 /* 1659 * Determine whether or not we have to work-around the 1660 * Resume Bug. 1661 */ 1662 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 1663 if (IFM_TYPE(sc->sc_mii.mii_media_active) == IFM_10_T) 1664 sc->sc_flags |= FXPF_FIX_RESUME_BUG; 1665 else 1666 sc->sc_flags &= ~FXPF_FIX_RESUME_BUG; 1667 } 1668} 1669 1670void 1671fxp_mdi_write(struct device *self, int phy, int reg, int value) 1672{ 1673 struct fxp_softc *sc = (struct fxp_softc *)self; 1674 int count = 10000; 1675 1676 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1677 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1678 (value & 0xffff)); 1679 1680 while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1681 count--) 1682 DELAY(10); 1683 1684 if (count <= 0) 1685 printf("%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 1686} 1687 1688int 1689fxp_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1690{ 1691 struct fxp_softc *sc = ifp->if_softc; 1692 struct ifreq *ifr = (struct ifreq *)data; 1693 int s, error; 1694 1695 s = splnet(); 1696 1697 switch (cmd) { 1698 case SIOCSIFMEDIA: 1699 case SIOCGIFMEDIA: 1700 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1701 break; 1702 1703 default: 1704 error = ether_ioctl(ifp, cmd, data); 1705 if (error == ENETRESET) { 1706 if (sc->sc_enabled) { 1707 /* 1708 * Multicast list has changed; set the 1709 * hardware filter accordingly. 1710 */ 1711 if (sc->sc_txpending) { 1712 sc->sc_flags |= FXPF_WANTINIT; 1713 error = 0; 1714 } else 1715 error = fxp_init(ifp); 1716 } else 1717 error = 0; 1718 } 1719 break; 1720 } 1721 1722 /* Try to get more packets going. */ 1723 if (sc->sc_enabled) 1724 fxp_start(ifp); 1725 1726 splx(s); 1727 return (error); 1728} 1729 1730/* 1731 * Program the multicast filter. 1732 * 1733 * This function must be called at splnet(). 1734 */ 1735void 1736fxp_mc_setup(struct fxp_softc *sc) 1737{ 1738 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 1739 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1740 struct ethercom *ec = &sc->sc_ethercom; 1741 struct ether_multi *enm; 1742 struct ether_multistep step; 1743 int count, nmcasts; 1744 1745#ifdef DIAGNOSTIC 1746 if (sc->sc_txpending) 1747 panic("fxp_mc_setup: pending transmissions"); 1748#endif 1749 1750 ifp->if_flags &= ~IFF_ALLMULTI; 1751 1752 /* 1753 * Initialize multicast setup descriptor. 1754 */ 1755 nmcasts = 0; 1756 ETHER_FIRST_MULTI(step, ec, enm); 1757 while (enm != NULL) { 1758 /* 1759 * Check for too many multicast addresses or if we're 1760 * listening to a range. Either way, we simply have 1761 * to accept all multicasts. 1762 */ 1763 if (nmcasts >= MAXMCADDR || 1764 memcmp(enm->enm_addrlo, enm->enm_addrhi, 1765 ETHER_ADDR_LEN) != 0) { 1766 /* 1767 * Callers of this function must do the 1768 * right thing with this. If we're called 1769 * from outside fxp_init(), the caller must 1770 * detect if the state if IFF_ALLMULTI changes. 1771 * If it does, the caller must then call 1772 * fxp_init(), since allmulti is handled by 1773 * the config block. 1774 */ 1775 ifp->if_flags |= IFF_ALLMULTI; 1776 return; 1777 } 1778 memcpy((void *)&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 1779 ETHER_ADDR_LEN); 1780 nmcasts++; 1781 ETHER_NEXT_MULTI(step, enm); 1782 } 1783 1784 /* BIG_ENDIAN: no need to swap to store 0 */ 1785 mcsp->cb_status = 0; 1786 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1787 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 1788 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 1789 1790 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1791 1792 /* 1793 * Wait until the command unit is not active. This should never 1794 * happen since nothing is queued, but make sure anyway. 1795 */ 1796 count = 100; 1797 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 1798 FXP_SCB_CUS_ACTIVE && --count) 1799 DELAY(1); 1800 if (count == 0) { 1801 printf("%s at line %d: command queue timeout\n", 1802 sc->sc_dev.dv_xname, __LINE__); 1803 return; 1804 } 1805 1806 /* 1807 * Start the multicast setup command/DMA. 1808 */ 1809 fxp_scb_wait(sc); 1810 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 1811 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1812 1813 /* ...and wait for it to complete. */ 1814 count = 1000; 1815 do { 1816 FXP_CDMCSSYNC(sc, 1817 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1818 DELAY(1); 1819 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 1820 if (count == 0) { 1821 printf("%s at line %d: dmasync timeout\n", 1822 sc->sc_dev.dv_xname, __LINE__); 1823 return; 1824 } 1825} 1826 1827int 1828fxp_enable(struct fxp_softc *sc) 1829{ 1830 1831 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 1832 if ((*sc->sc_enable)(sc) != 0) { 1833 printf("%s: device enable failed\n", 1834 sc->sc_dev.dv_xname); 1835 return (EIO); 1836 } 1837 } 1838 1839 sc->sc_enabled = 1; 1840 return (0); 1841} 1842 1843void 1844fxp_disable(struct fxp_softc *sc) 1845{ 1846 1847 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 1848 (*sc->sc_disable)(sc); 1849 sc->sc_enabled = 0; 1850 } 1851} 1852 1853/* 1854 * fxp_activate: 1855 * 1856 * Handle device activation/deactivation requests. 1857 */ 1858int 1859fxp_activate(struct device *self, enum devact act) 1860{ 1861 struct fxp_softc *sc = (void *) self; 1862 int s, error = 0; 1863 1864 s = splnet(); 1865 switch (act) { 1866 case DVACT_ACTIVATE: 1867 error = EOPNOTSUPP; 1868 break; 1869 1870 case DVACT_DEACTIVATE: 1871 if (sc->sc_flags & FXPF_MII) 1872 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 1873 MII_OFFSET_ANY); 1874 if_deactivate(&sc->sc_ethercom.ec_if); 1875 break; 1876 } 1877 splx(s); 1878 1879 return (error); 1880} 1881 1882/* 1883 * fxp_detach: 1884 * 1885 * Detach an i82557 interface. 1886 */ 1887int 1888fxp_detach(struct fxp_softc *sc) 1889{ 1890 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1891 int i; 1892 1893 /* Succeed now if there's no work to do. */ 1894 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 1895 return (0); 1896 1897 /* Unhook our tick handler. */ 1898 callout_stop(&sc->sc_callout); 1899 1900 if (sc->sc_flags & FXPF_MII) { 1901 /* Detach all PHYs */ 1902 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1903 } 1904 1905 /* Delete all remaining media. */ 1906 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 1907 1908#if NRND > 0 1909 rnd_detach_source(&sc->rnd_source); 1910#endif 1911 ether_ifdetach(ifp); 1912 if_detach(ifp); 1913 1914 for (i = 0; i < FXP_NRFABUFS; i++) { 1915 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 1916 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 1917 } 1918 1919 for (i = 0; i < FXP_NTXCB; i++) { 1920 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 1921 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 1922 } 1923 1924 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 1925 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 1926 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1927 sizeof(struct fxp_control_data)); 1928 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 1929 1930 shutdownhook_disestablish(sc->sc_sdhook); 1931 powerhook_disestablish(sc->sc_powerhook); 1932 1933 return (0); 1934} 1935