i82557.c revision 1.45
1/* $NetBSD: i82557.c,v 1.45 2001/05/16 04:20:55 lukem Exp $ */ 2 3/*- 4 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40/* 41 * Copyright (c) 1995, David Greenman 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice unmodified, this list of conditions, and the following 49 * disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 55 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 57 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 60 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 62 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 63 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 * Id: if_fxp.c,v 1.47 1998/01/08 23:42:29 eivind Exp 67 */ 68 69/* 70 * Device driver for the Intel i82557 fast Ethernet controller, 71 * and its successors, the i82558 and i82559. 72 */ 73 74#include "opt_inet.h" 75#include "opt_ns.h" 76#include "bpfilter.h" 77#include "rnd.h" 78 79#include <sys/param.h> 80#include <sys/systm.h> 81#include <sys/callout.h> 82#include <sys/mbuf.h> 83#include <sys/malloc.h> 84#include <sys/kernel.h> 85#include <sys/socket.h> 86#include <sys/ioctl.h> 87#include <sys/errno.h> 88#include <sys/device.h> 89 90#include <machine/endian.h> 91 92#include <uvm/uvm_extern.h> 93 94#if NRND > 0 95#include <sys/rnd.h> 96#endif 97 98#include <net/if.h> 99#include <net/if_dl.h> 100#include <net/if_media.h> 101#include <net/if_ether.h> 102 103#if NBPFILTER > 0 104#include <net/bpf.h> 105#endif 106 107#ifdef INET 108#include <netinet/in.h> 109#include <netinet/if_inarp.h> 110#endif 111 112#ifdef NS 113#include <netns/ns.h> 114#include <netns/ns_if.h> 115#endif 116 117#include <machine/bus.h> 118#include <machine/intr.h> 119 120#include <dev/mii/miivar.h> 121 122#include <dev/ic/i82557reg.h> 123#include <dev/ic/i82557var.h> 124 125/* 126 * NOTE! On the Alpha, we have an alignment constraint. The 127 * card DMAs the packet immediately following the RFA. However, 128 * the first thing in the packet is a 14-byte Ethernet header. 129 * This means that the packet is misaligned. To compensate, 130 * we actually offset the RFA 2 bytes into the cluster. This 131 * alignes the packet after the Ethernet header at a 32-bit 132 * boundary. HOWEVER! This means that the RFA is misaligned! 133 */ 134#define RFA_ALIGNMENT_FUDGE 2 135 136/* 137 * Template for default configuration parameters. 138 * See struct fxp_cb_config for the bit definitions. 139 */ 140u_int8_t fxp_cb_config_template[] = { 141 0x0, 0x0, /* cb_status */ 142 0x80, 0x2, /* cb_command */ 143 0xff, 0xff, 0xff, 0xff, /* link_addr */ 144 0x16, /* 0 */ 145 0x8, /* 1 */ 146 0x0, /* 2 */ 147 0x0, /* 3 */ 148 0x0, /* 4 */ 149 0x80, /* 5 */ 150 0xb2, /* 6 */ 151 0x3, /* 7 */ 152 0x1, /* 8 */ 153 0x0, /* 9 */ 154 0x26, /* 10 */ 155 0x0, /* 11 */ 156 0x60, /* 12 */ 157 0x0, /* 13 */ 158 0xf2, /* 14 */ 159 0x48, /* 15 */ 160 0x0, /* 16 */ 161 0x40, /* 17 */ 162 0xf3, /* 18 */ 163 0x0, /* 19 */ 164 0x3f, /* 20 */ 165 0x5 /* 21 */ 166}; 167 168void fxp_mii_initmedia __P((struct fxp_softc *)); 169int fxp_mii_mediachange __P((struct ifnet *)); 170void fxp_mii_mediastatus __P((struct ifnet *, struct ifmediareq *)); 171 172void fxp_80c24_initmedia __P((struct fxp_softc *)); 173int fxp_80c24_mediachange __P((struct ifnet *)); 174void fxp_80c24_mediastatus __P((struct ifnet *, struct ifmediareq *)); 175 176inline void fxp_scb_wait __P((struct fxp_softc *)); 177 178void fxp_start __P((struct ifnet *)); 179int fxp_ioctl __P((struct ifnet *, u_long, caddr_t)); 180void fxp_watchdog __P((struct ifnet *)); 181int fxp_init __P((struct ifnet *)); 182void fxp_stop __P((struct ifnet *, int)); 183 184void fxp_rxdrain __P((struct fxp_softc *)); 185int fxp_add_rfabuf __P((struct fxp_softc *, bus_dmamap_t, int)); 186int fxp_mdi_read __P((struct device *, int, int)); 187void fxp_statchg __P((struct device *)); 188void fxp_mdi_write __P((struct device *, int, int, int)); 189void fxp_autosize_eeprom __P((struct fxp_softc*)); 190void fxp_read_eeprom __P((struct fxp_softc *, u_int16_t *, int, int)); 191void fxp_get_info __P((struct fxp_softc *, u_int8_t *)); 192void fxp_tick __P((void *)); 193void fxp_mc_setup __P((struct fxp_softc *)); 194 195void fxp_shutdown __P((void *)); 196void fxp_power __P((int, void *)); 197 198int fxp_copy_small = 0; 199 200struct fxp_phytype { 201 int fp_phy; /* type of PHY, -1 for MII at the end. */ 202 void (*fp_init) __P((struct fxp_softc *)); 203} fxp_phytype_table[] = { 204 { FXP_PHY_80C24, fxp_80c24_initmedia }, 205 { -1, fxp_mii_initmedia }, 206}; 207 208/* 209 * Set initial transmit threshold at 64 (512 bytes). This is 210 * increased by 64 (512 bytes) at a time, to maximum of 192 211 * (1536 bytes), if an underrun occurs. 212 */ 213static int tx_threshold = 64; 214 215/* 216 * Wait for the previous command to be accepted (but not necessarily 217 * completed). 218 */ 219inline void 220fxp_scb_wait(sc) 221 struct fxp_softc *sc; 222{ 223 int i = 10000; 224 225 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 226 delay(2); 227 if (i == 0) 228 printf("%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 229} 230 231/* 232 * Finish attaching an i82557 interface. Called by bus-specific front-end. 233 */ 234void 235fxp_attach(sc) 236 struct fxp_softc *sc; 237{ 238 u_int8_t enaddr[ETHER_ADDR_LEN]; 239 struct ifnet *ifp; 240 bus_dma_segment_t seg; 241 int rseg, i, error; 242 struct fxp_phytype *fp; 243 244 callout_init(&sc->sc_callout); 245 246 /* 247 * Allocate the control data structures, and create and load the 248 * DMA map for it. 249 */ 250 if ((error = bus_dmamem_alloc(sc->sc_dmat, 251 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 252 0)) != 0) { 253 printf("%s: unable to allocate control data, error = %d\n", 254 sc->sc_dev.dv_xname, error); 255 goto fail_0; 256 } 257 258 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 259 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 260 BUS_DMA_COHERENT)) != 0) { 261 printf("%s: unable to map control data, error = %d\n", 262 sc->sc_dev.dv_xname, error); 263 goto fail_1; 264 } 265 sc->sc_cdseg = seg; 266 sc->sc_cdnseg = rseg; 267 268 bzero(sc->sc_control_data, sizeof(struct fxp_control_data)); 269 270 if ((error = bus_dmamap_create(sc->sc_dmat, 271 sizeof(struct fxp_control_data), 1, 272 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 273 printf("%s: unable to create control data DMA map, " 274 "error = %d\n", sc->sc_dev.dv_xname, error); 275 goto fail_2; 276 } 277 278 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 279 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 280 0)) != 0) { 281 printf("%s: can't load control data DMA map, error = %d\n", 282 sc->sc_dev.dv_xname, error); 283 goto fail_3; 284 } 285 286 /* 287 * Create the transmit buffer DMA maps. 288 */ 289 for (i = 0; i < FXP_NTXCB; i++) { 290 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 291 FXP_NTXSEG, MCLBYTES, 0, 0, 292 &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 293 printf("%s: unable to create tx DMA map %d, " 294 "error = %d\n", sc->sc_dev.dv_xname, i, error); 295 goto fail_4; 296 } 297 } 298 299 /* 300 * Create the receive buffer DMA maps. 301 */ 302 for (i = 0; i < FXP_NRFABUFS; i++) { 303 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 304 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 305 printf("%s: unable to create rx DMA map %d, " 306 "error = %d\n", sc->sc_dev.dv_xname, i, error); 307 goto fail_5; 308 } 309 } 310 311 /* Initialize MAC address and media structures. */ 312 fxp_get_info(sc, enaddr); 313 314 printf("%s: Ethernet address %s, %s Mb/s\n", sc->sc_dev.dv_xname, 315 ether_sprintf(enaddr), sc->phy_10Mbps_only ? "10" : "10/100"); 316 317 ifp = &sc->sc_ethercom.ec_if; 318 319 /* 320 * Get info about our media interface, and initialize it. Note 321 * the table terminates itself with a phy of -1, indicating 322 * that we're using MII. 323 */ 324 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 325 if (fp->fp_phy == sc->phy_primary_device) 326 break; 327 (*fp->fp_init)(sc); 328 329 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 330 ifp->if_softc = sc; 331 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 332 ifp->if_ioctl = fxp_ioctl; 333 ifp->if_start = fxp_start; 334 ifp->if_watchdog = fxp_watchdog; 335 ifp->if_init = fxp_init; 336 ifp->if_stop = fxp_stop; 337 IFQ_SET_READY(&ifp->if_snd); 338 339 /* 340 * We can support 802.1Q VLAN-sized frames. 341 */ 342 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 343 344 /* 345 * Attach the interface. 346 */ 347 if_attach(ifp); 348 ether_ifattach(ifp, enaddr); 349#if NRND > 0 350 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 351 RND_TYPE_NET, 0); 352#endif 353 354 /* 355 * Add shutdown hook so that DMA is disabled prior to reboot. Not 356 * doing do could allow DMA to corrupt kernel memory during the 357 * reboot before the driver initializes. 358 */ 359 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 360 if (sc->sc_sdhook == NULL) 361 printf("%s: WARNING: unable to establish shutdown hook\n", 362 sc->sc_dev.dv_xname); 363 /* 364 * Add suspend hook, for similar reasons.. 365 */ 366 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 367 if (sc->sc_powerhook == NULL) 368 printf("%s: WARNING: unable to establish power hook\n", 369 sc->sc_dev.dv_xname); 370 371 /* The attach is successful. */ 372 sc->sc_flags |= FXPF_ATTACHED; 373 374 return; 375 376 /* 377 * Free any resources we've allocated during the failed attach 378 * attempt. Do this in reverse order and fall though. 379 */ 380 fail_5: 381 for (i = 0; i < FXP_NRFABUFS; i++) { 382 if (sc->sc_rxmaps[i] != NULL) 383 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 384 } 385 fail_4: 386 for (i = 0; i < FXP_NTXCB; i++) { 387 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 388 bus_dmamap_destroy(sc->sc_dmat, 389 FXP_DSTX(sc, i)->txs_dmamap); 390 } 391 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 392 fail_3: 393 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 394 fail_2: 395 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 396 sizeof(struct fxp_control_data)); 397 fail_1: 398 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 399 fail_0: 400 return; 401} 402 403void 404fxp_mii_initmedia(sc) 405 struct fxp_softc *sc; 406{ 407 408 sc->sc_flags |= FXPF_MII; 409 410 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 411 sc->sc_mii.mii_readreg = fxp_mdi_read; 412 sc->sc_mii.mii_writereg = fxp_mdi_write; 413 sc->sc_mii.mii_statchg = fxp_statchg; 414 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_mii_mediachange, 415 fxp_mii_mediastatus); 416 /* 417 * The i82557 wedges if all of its PHYs are isolated! 418 */ 419 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 420 MII_OFFSET_ANY, MIIF_NOISOLATE); 421 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 422 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 423 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 424 } else 425 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 426} 427 428void 429fxp_80c24_initmedia(sc) 430 struct fxp_softc *sc; 431{ 432 433 /* 434 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 435 * doesn't have a programming interface of any sort. The 436 * media is sensed automatically based on how the link partner 437 * is configured. This is, in essence, manual configuration. 438 */ 439 printf("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 440 sc->sc_dev.dv_xname); 441 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 442 fxp_80c24_mediastatus); 443 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 444 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 445} 446 447/* 448 * Device shutdown routine. Called at system shutdown after sync. The 449 * main purpose of this routine is to shut off receiver DMA so that 450 * kernel memory doesn't get clobbered during warmboot. 451 */ 452void 453fxp_shutdown(arg) 454 void *arg; 455{ 456 struct fxp_softc *sc = arg; 457 458 /* 459 * Since the system's going to halt shortly, don't bother 460 * freeing mbufs. 461 */ 462 fxp_stop(&sc->sc_ethercom.ec_if, 0); 463} 464/* 465 * Power handler routine. Called when the system is transitioning 466 * into/out of power save modes. As with fxp_shutdown, the main 467 * purpose of this routine is to shut off receiver DMA so it doesn't 468 * clobber kernel memory at the wrong time. 469 */ 470void 471fxp_power(why, arg) 472 int why; 473 void *arg; 474{ 475 struct fxp_softc *sc = arg; 476 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 477 int s; 478 479 s = splnet(); 480 switch (why) { 481 case PWR_SUSPEND: 482 case PWR_STANDBY: 483 fxp_stop(ifp, 0); 484 break; 485 case PWR_RESUME: 486 if (ifp->if_flags & IFF_UP) 487 fxp_init(ifp); 488 break; 489 case PWR_SOFTSUSPEND: 490 case PWR_SOFTSTANDBY: 491 case PWR_SOFTRESUME: 492 break; 493 } 494 splx(s); 495} 496 497/* 498 * Initialize the interface media. 499 */ 500void 501fxp_get_info(sc, enaddr) 502 struct fxp_softc *sc; 503 u_int8_t *enaddr; 504{ 505 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 506 507 /* 508 * Reset to a stable state. 509 */ 510 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 511 DELAY(10); 512 513 sc->sc_eeprom_size = 0; 514 fxp_autosize_eeprom(sc); 515 if(sc->sc_eeprom_size == 0) { 516 printf("%s: failed to detect EEPROM size\n", sc->sc_dev.dv_xname); 517 sc->sc_eeprom_size = 6; /* XXX panic here? */ 518 } 519#ifdef DEBUG 520 printf("%s: detected %d word EEPROM\n", 521 sc->sc_dev.dv_xname, 522 1 << sc->sc_eeprom_size); 523#endif 524 525 /* 526 * Get info about the primary PHY 527 */ 528 fxp_read_eeprom(sc, &data, 6, 1); 529 sc->phy_primary_addr = data & 0xff; 530 sc->phy_primary_device = (data >> 8) & 0x3f; 531 sc->phy_10Mbps_only = data >> 15; 532 533 /* 534 * Read MAC address. 535 */ 536 fxp_read_eeprom(sc, myea, 0, 3); 537 enaddr[0] = myea[0] & 0xff; 538 enaddr[1] = myea[0] >> 8; 539 enaddr[2] = myea[1] & 0xff; 540 enaddr[3] = myea[1] >> 8; 541 enaddr[4] = myea[2] & 0xff; 542 enaddr[5] = myea[2] >> 8; 543} 544 545/* 546 * Figure out EEPROM size. 547 * 548 * 559's can have either 64-word or 256-word EEPROMs, the 558 549 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 550 * talks about the existance of 16 to 256 word EEPROMs. 551 * 552 * The only known sizes are 64 and 256, where the 256 version is used 553 * by CardBus cards to store CIS information. 554 * 555 * The address is shifted in msb-to-lsb, and after the last 556 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 557 * after which follows the actual data. We try to detect this zero, by 558 * probing the data-out bit in the EEPROM control register just after 559 * having shifted in a bit. If the bit is zero, we assume we've 560 * shifted enough address bits. The data-out should be tri-state, 561 * before this, which should translate to a logical one. 562 * 563 * Other ways to do this would be to try to read a register with known 564 * contents with a varying number of address bits, but no such 565 * register seem to be available. The high bits of register 10 are 01 566 * on the 558 and 559, but apparently not on the 557. 567 * 568 * The Linux driver computes a checksum on the EEPROM data, but the 569 * value of this checksum is not very well documented. 570 */ 571 572void 573fxp_autosize_eeprom(sc) 574 struct fxp_softc *sc; 575{ 576 u_int16_t reg; 577 int x; 578 579 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 580 /* 581 * Shift in read opcode. 582 */ 583 for (x = 3; x > 0; x--) { 584 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 585 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 586 } else { 587 reg = FXP_EEPROM_EECS; 588 } 589 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 590 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 591 reg | FXP_EEPROM_EESK); 592 DELAY(4); 593 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 594 DELAY(4); 595 } 596 /* 597 * Shift in address, wait for the dummy zero following a correct 598 * address shift. 599 */ 600 for (x = 1; x <= 8; x++) { 601 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 602 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 603 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 604 DELAY(4); 605 if((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 606 FXP_EEPROM_EEDO) == 0) 607 break; 608 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 609 DELAY(4); 610 } 611 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 612 DELAY(4); 613 if(x != 6 && x != 8) { 614#ifdef DEBUG 615 printf("%s: strange EEPROM size (%d)\n", 616 sc->sc_dev.dv_xname, 1 << x); 617#endif 618 } else 619 sc->sc_eeprom_size = x; 620} 621 622/* 623 * Read from the serial EEPROM. Basically, you manually shift in 624 * the read opcode (one bit at a time) and then shift in the address, 625 * and then you shift out the data (all of this one bit at a time). 626 * The word size is 16 bits, so you have to provide the address for 627 * every 16 bits of data. 628 */ 629void 630fxp_read_eeprom(sc, data, offset, words) 631 struct fxp_softc *sc; 632 u_int16_t *data; 633 int offset; 634 int words; 635{ 636 u_int16_t reg; 637 int i, x; 638 639 for (i = 0; i < words; i++) { 640 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 641 /* 642 * Shift in read opcode. 643 */ 644 for (x = 3; x > 0; x--) { 645 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 646 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 647 } else { 648 reg = FXP_EEPROM_EECS; 649 } 650 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 651 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 652 reg | FXP_EEPROM_EESK); 653 DELAY(4); 654 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 655 DELAY(4); 656 } 657 /* 658 * Shift in address. 659 */ 660 for (x = sc->sc_eeprom_size; x > 0; x--) { 661 if ((i + offset) & (1 << (x - 1))) { 662 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 663 } else { 664 reg = FXP_EEPROM_EECS; 665 } 666 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 667 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 668 reg | FXP_EEPROM_EESK); 669 DELAY(4); 670 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 671 DELAY(4); 672 } 673 reg = FXP_EEPROM_EECS; 674 data[i] = 0; 675 /* 676 * Shift out data. 677 */ 678 for (x = 16; x > 0; x--) { 679 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 680 reg | FXP_EEPROM_EESK); 681 DELAY(4); 682 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 683 FXP_EEPROM_EEDO) 684 data[i] |= (1 << (x - 1)); 685 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 686 DELAY(4); 687 } 688 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 689 DELAY(4); 690 } 691} 692 693/* 694 * Start packet transmission on the interface. 695 */ 696void 697fxp_start(ifp) 698 struct ifnet *ifp; 699{ 700 struct fxp_softc *sc = ifp->if_softc; 701 struct mbuf *m0, *m; 702 struct fxp_cb_tx *txd; 703 struct fxp_txsoft *txs; 704 struct fxp_tbdlist *tbd; 705 bus_dmamap_t dmamap; 706 int error, lasttx, nexttx, opending, seg; 707 708 /* 709 * If we want a re-init, bail out now. 710 */ 711 if (sc->sc_flags & FXPF_WANTINIT) { 712 ifp->if_flags |= IFF_OACTIVE; 713 return; 714 } 715 716 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 717 return; 718 719 /* 720 * Remember the previous txpending and the current lasttx. 721 */ 722 opending = sc->sc_txpending; 723 lasttx = sc->sc_txlast; 724 725 /* 726 * Loop through the send queue, setting up transmit descriptors 727 * until we drain the queue, or use up all available transmit 728 * descriptors. 729 */ 730 while (sc->sc_txpending < FXP_NTXCB) { 731 /* 732 * Grab a packet off the queue. 733 */ 734 IFQ_POLL(&ifp->if_snd, m0); 735 if (m0 == NULL) 736 break; 737 m = NULL; 738 739 /* 740 * Get the next available transmit descriptor. 741 */ 742 nexttx = FXP_NEXTTX(sc->sc_txlast); 743 txd = FXP_CDTX(sc, nexttx); 744 tbd = FXP_CDTBD(sc, nexttx); 745 txs = FXP_DSTX(sc, nexttx); 746 dmamap = txs->txs_dmamap; 747 748 /* 749 * Load the DMA map. If this fails, the packet either 750 * didn't fit in the allotted number of frags, or we were 751 * short on resources. In this case, we'll copy and try 752 * again. 753 */ 754 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 755 BUS_DMA_NOWAIT) != 0) { 756 MGETHDR(m, M_DONTWAIT, MT_DATA); 757 if (m == NULL) { 758 printf("%s: unable to allocate Tx mbuf\n", 759 sc->sc_dev.dv_xname); 760 break; 761 } 762 if (m0->m_pkthdr.len > MHLEN) { 763 MCLGET(m, M_DONTWAIT); 764 if ((m->m_flags & M_EXT) == 0) { 765 printf("%s: unable to allocate Tx " 766 "cluster\n", sc->sc_dev.dv_xname); 767 m_freem(m); 768 break; 769 } 770 } 771 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 772 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 773 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 774 m, BUS_DMA_NOWAIT); 775 if (error) { 776 printf("%s: unable to load Tx buffer, " 777 "error = %d\n", sc->sc_dev.dv_xname, error); 778 break; 779 } 780 } 781 782 IFQ_DEQUEUE(&ifp->if_snd, m0); 783 if (m != NULL) { 784 m_freem(m0); 785 m0 = m; 786 } 787 788 /* Initialize the fraglist. */ 789 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 790 tbd->tbd_d[seg].tb_addr = 791 htole32(dmamap->dm_segs[seg].ds_addr); 792 tbd->tbd_d[seg].tb_size = 793 htole32(dmamap->dm_segs[seg].ds_len); 794 } 795 796 FXP_CDTBDSYNC(sc, nexttx, BUS_DMASYNC_PREWRITE); 797 798 /* Sync the DMA map. */ 799 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 800 BUS_DMASYNC_PREWRITE); 801 802 /* 803 * Store a pointer to the packet so we can free it later. 804 */ 805 txs->txs_mbuf = m0; 806 807 /* 808 * Initialize the transmit descriptor. 809 */ 810 /* BIG_ENDIAN: no need to swap to store 0 */ 811 txd->cb_status = 0; 812 txd->cb_command = 813 htole16(FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF); 814 txd->tx_threshold = tx_threshold; 815 txd->tbd_number = dmamap->dm_nsegs; 816 817 FXP_CDTXSYNC(sc, nexttx, 818 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 819 820 /* Advance the tx pointer. */ 821 sc->sc_txpending++; 822 sc->sc_txlast = nexttx; 823 824#if NBPFILTER > 0 825 /* 826 * Pass packet to bpf if there is a listener. 827 */ 828 if (ifp->if_bpf) 829 bpf_mtap(ifp->if_bpf, m0); 830#endif 831 } 832 833 if (sc->sc_txpending == FXP_NTXCB) { 834 /* No more slots; notify upper layer. */ 835 ifp->if_flags |= IFF_OACTIVE; 836 } 837 838 if (sc->sc_txpending != opending) { 839 /* 840 * We enqueued packets. If the transmitter was idle, 841 * reset the txdirty pointer. 842 */ 843 if (opending == 0) 844 sc->sc_txdirty = FXP_NEXTTX(lasttx); 845 846 /* 847 * Cause the chip to interrupt and suspend command 848 * processing once the last packet we've enqueued 849 * has been transmitted. 850 */ 851 FXP_CDTX(sc, sc->sc_txlast)->cb_command |= 852 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 853 FXP_CDTXSYNC(sc, sc->sc_txlast, 854 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 855 856 /* 857 * The entire packet chain is set up. Clear the suspend bit 858 * on the command prior to the first packet we set up. 859 */ 860 FXP_CDTXSYNC(sc, lasttx, 861 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 862 FXP_CDTX(sc, lasttx)->cb_command &= htole16(~FXP_CB_COMMAND_S); 863 FXP_CDTXSYNC(sc, lasttx, 864 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 865 866 /* 867 * Issue a Resume command in case the chip was suspended. 868 */ 869 fxp_scb_wait(sc); 870 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME); 871 872 /* Set a watchdog timer in case the chip flakes out. */ 873 ifp->if_timer = 5; 874 } 875} 876 877/* 878 * Process interface interrupts. 879 */ 880int 881fxp_intr(arg) 882 void *arg; 883{ 884 struct fxp_softc *sc = arg; 885 struct ethercom *ec = &sc->sc_ethercom; 886 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 887 struct fxp_cb_tx *txd; 888 struct fxp_txsoft *txs; 889 struct mbuf *m, *m0; 890 bus_dmamap_t rxmap; 891 struct fxp_rfa *rfa; 892 int i, claimed = 0; 893 u_int16_t len, rxstat, txstat; 894 u_int8_t statack; 895 896 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 897 return (0); 898 /* 899 * If the interface isn't running, don't try to 900 * service the interrupt.. just ack it and bail. 901 */ 902 if ((ifp->if_flags & IFF_RUNNING) == 0) { 903 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 904 if (statack) { 905 claimed = 1; 906 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 907 } 908 return (claimed); 909 } 910 911 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 912 claimed = 1; 913 914 /* 915 * First ACK all the interrupts in this pass. 916 */ 917 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 918 919 /* 920 * Process receiver interrupts. If a no-resource (RNR) 921 * condition exists, get whatever packets we can and 922 * re-start the receiver. 923 */ 924 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 925 rcvloop: 926 m = sc->sc_rxq.ifq_head; 927 rfa = FXP_MTORFA(m); 928 rxmap = M_GETCTX(m, bus_dmamap_t); 929 930 FXP_RFASYNC(sc, m, 931 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 932 933 rxstat = le16toh(rfa->rfa_status); 934 935 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 936 /* 937 * We have processed all of the 938 * receive buffers. 939 */ 940 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 941 goto do_transmit; 942 } 943 944 IF_DEQUEUE(&sc->sc_rxq, m); 945 946 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 947 948 len = le16toh(rfa->actual_size) & 949 (m->m_ext.ext_size - 1); 950 951 if (len < sizeof(struct ether_header)) { 952 /* 953 * Runt packet; drop it now. 954 */ 955 FXP_INIT_RFABUF(sc, m); 956 goto rcvloop; 957 } 958 959 /* 960 * If support for 802.1Q VLAN sized frames is 961 * enabled, we need to do some additional error 962 * checking (as we are saving bad frames, in 963 * order to receive the larger ones). 964 */ 965 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 966 (rxstat & (FXP_RFA_STATUS_OVERRUN| 967 FXP_RFA_STATUS_RNR| 968 FXP_RFA_STATUS_ALIGN| 969 FXP_RFA_STATUS_CRC)) != 0) { 970 FXP_INIT_RFABUF(sc, m); 971 goto rcvloop; 972 } 973 974 /* 975 * If the packet is small enough to fit in a 976 * single header mbuf, allocate one and copy 977 * the data into it. This greatly reduces 978 * memory consumption when we receive lots 979 * of small packets. 980 * 981 * Otherwise, we add a new buffer to the receive 982 * chain. If this fails, we drop the packet and 983 * recycle the old buffer. 984 */ 985 if (fxp_copy_small != 0 && len <= MHLEN) { 986 MGETHDR(m0, M_DONTWAIT, MT_DATA); 987 if (m == NULL) 988 goto dropit; 989 memcpy(mtod(m0, caddr_t), 990 mtod(m, caddr_t), len); 991 FXP_INIT_RFABUF(sc, m); 992 m = m0; 993 } else { 994 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 995 dropit: 996 ifp->if_ierrors++; 997 FXP_INIT_RFABUF(sc, m); 998 goto rcvloop; 999 } 1000 } 1001 1002 m->m_pkthdr.rcvif = ifp; 1003 m->m_pkthdr.len = m->m_len = len; 1004 1005#if NBPFILTER > 0 1006 /* 1007 * Pass this up to any BPF listeners, but only 1008 * pass it up the stack it its for us. 1009 */ 1010 if (ifp->if_bpf) 1011 bpf_mtap(ifp->if_bpf, m); 1012#endif 1013 1014 /* Pass it on. */ 1015 (*ifp->if_input)(ifp, m); 1016 goto rcvloop; 1017 } 1018 1019 do_transmit: 1020 if (statack & FXP_SCB_STATACK_RNR) { 1021 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1022 fxp_scb_wait(sc); 1023 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1024 rxmap->dm_segs[0].ds_addr + 1025 RFA_ALIGNMENT_FUDGE); 1026 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1027 FXP_SCB_COMMAND_RU_START); 1028 } 1029 1030 /* 1031 * Free any finished transmit mbuf chains. 1032 */ 1033 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1034 ifp->if_flags &= ~IFF_OACTIVE; 1035 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1036 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1037 txd = FXP_CDTX(sc, i); 1038 txs = FXP_DSTX(sc, i); 1039 1040 FXP_CDTXSYNC(sc, i, 1041 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1042 1043 txstat = le16toh(txd->cb_status); 1044 1045 if ((txstat & FXP_CB_STATUS_C) == 0) 1046 break; 1047 1048 FXP_CDTBDSYNC(sc, i, BUS_DMASYNC_POSTWRITE); 1049 1050 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1051 0, txs->txs_dmamap->dm_mapsize, 1052 BUS_DMASYNC_POSTWRITE); 1053 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1054 m_freem(txs->txs_mbuf); 1055 txs->txs_mbuf = NULL; 1056 } 1057 1058 /* Update the dirty transmit buffer pointer. */ 1059 sc->sc_txdirty = i; 1060 1061 /* 1062 * Cancel the watchdog timer if there are no pending 1063 * transmissions. 1064 */ 1065 if (sc->sc_txpending == 0) { 1066 ifp->if_timer = 0; 1067 1068 /* 1069 * If we want a re-init, do that now. 1070 */ 1071 if (sc->sc_flags & FXPF_WANTINIT) 1072 (void) fxp_init(ifp); 1073 } 1074 1075 /* 1076 * Try to get more packets going. 1077 */ 1078 fxp_start(ifp); 1079 } 1080 } 1081 1082#if NRND > 0 1083 if (claimed) 1084 rnd_add_uint32(&sc->rnd_source, statack); 1085#endif 1086 return (claimed); 1087} 1088 1089/* 1090 * Update packet in/out/collision statistics. The i82557 doesn't 1091 * allow you to access these counters without doing a fairly 1092 * expensive DMA to get _all_ of the statistics it maintains, so 1093 * we do this operation here only once per second. The statistics 1094 * counters in the kernel are updated from the previous dump-stats 1095 * DMA and then a new dump-stats DMA is started. The on-chip 1096 * counters are zeroed when the DMA completes. If we can't start 1097 * the DMA immediately, we don't wait - we just prepare to read 1098 * them again next time. 1099 */ 1100void 1101fxp_tick(arg) 1102 void *arg; 1103{ 1104 struct fxp_softc *sc = arg; 1105 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1106 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1107 int s; 1108 1109 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1110 return; 1111 1112 s = splnet(); 1113 1114 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1115 1116 ifp->if_opackets += le32toh(sp->tx_good); 1117 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1118 if (sp->rx_good) { 1119 ifp->if_ipackets += le32toh(sp->rx_good); 1120 sc->sc_rxidle = 0; 1121 } else { 1122 sc->sc_rxidle++; 1123 } 1124 ifp->if_ierrors += 1125 le32toh(sp->rx_crc_errors) + 1126 le32toh(sp->rx_alignment_errors) + 1127 le32toh(sp->rx_rnr_errors) + 1128 le32toh(sp->rx_overrun_errors); 1129 /* 1130 * If any transmit underruns occured, bump up the transmit 1131 * threshold by another 512 bytes (64 * 8). 1132 */ 1133 if (sp->tx_underruns) { 1134 ifp->if_oerrors += le32toh(sp->tx_underruns); 1135 if (tx_threshold < 192) 1136 tx_threshold += 64; 1137 } 1138 1139 /* 1140 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1141 * then assume the receiver has locked up and attempt to clear 1142 * the condition by reprogramming the multicast filter (actually, 1143 * resetting the interface). This is a work-around for a bug in 1144 * the 82557 where the receiver locks up if it gets certain types 1145 * of garbage in the syncronization bits prior to the packet header. 1146 * This bug is supposed to only occur in 10Mbps mode, but has been 1147 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1148 * speed transition). 1149 */ 1150 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1151 (void) fxp_init(ifp); 1152 splx(s); 1153 return; 1154 } 1155 /* 1156 * If there is no pending command, start another stats 1157 * dump. Otherwise punt for now. 1158 */ 1159 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1160 /* 1161 * Start another stats dump. 1162 */ 1163 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1164 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1165 FXP_SCB_COMMAND_CU_DUMPRESET); 1166 } else { 1167 /* 1168 * A previous command is still waiting to be accepted. 1169 * Just zero our copy of the stats and wait for the 1170 * next timer event to update them. 1171 */ 1172 /* BIG_ENDIAN: no swap required to store 0 */ 1173 sp->tx_good = 0; 1174 sp->tx_underruns = 0; 1175 sp->tx_total_collisions = 0; 1176 1177 sp->rx_good = 0; 1178 sp->rx_crc_errors = 0; 1179 sp->rx_alignment_errors = 0; 1180 sp->rx_rnr_errors = 0; 1181 sp->rx_overrun_errors = 0; 1182 } 1183 1184 if (sc->sc_flags & FXPF_MII) { 1185 /* Tick the MII clock. */ 1186 mii_tick(&sc->sc_mii); 1187 } 1188 1189 splx(s); 1190 1191 /* 1192 * Schedule another timeout one second from now. 1193 */ 1194 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1195} 1196 1197/* 1198 * Drain the receive queue. 1199 */ 1200void 1201fxp_rxdrain(sc) 1202 struct fxp_softc *sc; 1203{ 1204 bus_dmamap_t rxmap; 1205 struct mbuf *m; 1206 1207 for (;;) { 1208 IF_DEQUEUE(&sc->sc_rxq, m); 1209 if (m == NULL) 1210 break; 1211 rxmap = M_GETCTX(m, bus_dmamap_t); 1212 bus_dmamap_unload(sc->sc_dmat, rxmap); 1213 FXP_RXMAP_PUT(sc, rxmap); 1214 m_freem(m); 1215 } 1216} 1217 1218/* 1219 * Stop the interface. Cancels the statistics updater and resets 1220 * the interface. 1221 */ 1222void 1223fxp_stop(ifp, disable) 1224 struct ifnet *ifp; 1225 int disable; 1226{ 1227 struct fxp_softc *sc = ifp->if_softc; 1228 struct fxp_txsoft *txs; 1229 int i; 1230 1231 /* 1232 * Turn down interface (done early to avoid bad interactions 1233 * between panics, shutdown hooks, and the watchdog timer) 1234 */ 1235 ifp->if_timer = 0; 1236 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1237 1238 /* 1239 * Cancel stats updater. 1240 */ 1241 callout_stop(&sc->sc_callout); 1242 if (sc->sc_flags & FXPF_MII) { 1243 /* Down the MII. */ 1244 mii_down(&sc->sc_mii); 1245 } 1246 1247 /* 1248 * Issue software reset 1249 */ 1250 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1251 DELAY(10); 1252 1253 /* 1254 * Release any xmit buffers. 1255 */ 1256 for (i = 0; i < FXP_NTXCB; i++) { 1257 txs = FXP_DSTX(sc, i); 1258 if (txs->txs_mbuf != NULL) { 1259 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1260 m_freem(txs->txs_mbuf); 1261 txs->txs_mbuf = NULL; 1262 } 1263 } 1264 sc->sc_txpending = 0; 1265 1266 if (disable) { 1267 fxp_rxdrain(sc); 1268 fxp_disable(sc); 1269 } 1270 1271} 1272 1273/* 1274 * Watchdog/transmission transmit timeout handler. Called when a 1275 * transmission is started on the interface, but no interrupt is 1276 * received before the timeout. This usually indicates that the 1277 * card has wedged for some reason. 1278 */ 1279void 1280fxp_watchdog(ifp) 1281 struct ifnet *ifp; 1282{ 1283 struct fxp_softc *sc = ifp->if_softc; 1284 1285 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1286 ifp->if_oerrors++; 1287 1288 (void) fxp_init(ifp); 1289} 1290 1291/* 1292 * Initialize the interface. Must be called at splnet(). 1293 */ 1294int 1295fxp_init(ifp) 1296 struct ifnet *ifp; 1297{ 1298 struct fxp_softc *sc = ifp->if_softc; 1299 struct fxp_cb_config *cbp; 1300 struct fxp_cb_ias *cb_ias; 1301 struct fxp_cb_tx *txd; 1302 bus_dmamap_t rxmap; 1303 int i, prm, save_bf, allm, error = 0; 1304 1305 if ((error = fxp_enable(sc)) != 0) 1306 goto out; 1307 1308 /* 1309 * Cancel any pending I/O 1310 */ 1311 fxp_stop(ifp, 0); 1312 1313 /* 1314 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1315 * flag, and this prevents the MII from detaching resulting in 1316 * a panic. The flags field should perhaps be split in runtime 1317 * flags and more static information. For now, just clear the 1318 * only other flag set. 1319 */ 1320 1321 sc->sc_flags &= ~FXPF_WANTINIT; 1322 1323 /* 1324 * Initialize base of CBL and RFA memory. Loading with zero 1325 * sets it up for regular linear addressing. 1326 */ 1327 fxp_scb_wait(sc); 1328 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1329 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_BASE); 1330 1331 fxp_scb_wait(sc); 1332 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_BASE); 1333 1334 /* 1335 * Initialize the multicast filter. Do this now, since we might 1336 * have to setup the config block differently. 1337 */ 1338 fxp_mc_setup(sc); 1339 1340 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1341 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1342 1343 /* 1344 * In order to support receiving 802.1Q VLAN frames, we have to 1345 * enable "save bad frames", since they are 4 bytes larger than 1346 * the normal Ethernet maximum frame length. 1347 */ 1348 save_bf = (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 1 : 0; 1349 1350 /* 1351 * Initialize base of dump-stats buffer. 1352 */ 1353 fxp_scb_wait(sc); 1354 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1355 sc->sc_cddma + FXP_CDSTATSOFF); 1356 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1357 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_DUMP_ADR); 1358 1359 cbp = &sc->sc_control_data->fcd_configcb; 1360 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1361 1362 /* 1363 * This copy is kind of disgusting, but there are a bunch of must be 1364 * zero and must be one bits in this structure and this is the easiest 1365 * way to initialize them all to proper values. 1366 */ 1367 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1368 1369 /* BIG_ENDIAN: no need to swap to store 0 */ 1370 cbp->cb_status = 0; 1371 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1372 FXP_CB_COMMAND_EL); 1373 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1374 cbp->link_addr = 0xffffffff; /* (no) next command */ 1375 cbp->byte_count = 22; /* (22) bytes to config */ 1376 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1377 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1378 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1379 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1380 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1381 cbp->dma_bce = 0; /* (disable) dma max counters */ 1382 cbp->late_scb = 0; /* (don't) defer SCB update */ 1383 cbp->tno_int = 0; /* (disable) tx not okay interrupt */ 1384 cbp->ci_int = 1; /* interrupt on CU idle */ 1385 cbp->save_bf = save_bf;/* save bad frames */ 1386 cbp->disc_short_rx = !prm; /* discard short packets */ 1387 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1388 cbp->mediatype = !sc->phy_10Mbps_only; /* interface mode */ 1389 cbp->nsai = 1; /* (don't) disable source addr insert */ 1390 cbp->preamble_length = 2; /* (7 byte) preamble */ 1391 cbp->loopback = 0; /* (don't) loopback */ 1392 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1393 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1394 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1395 cbp->promiscuous = prm; /* promiscuous mode */ 1396 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1397 cbp->crscdt = 0; /* (CRS only) */ 1398 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1399 cbp->padding = 1; /* (do) pad short tx packets */ 1400 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1401 cbp->force_fdx = 0; /* (don't) force full duplex */ 1402 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1403 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1404 cbp->mc_all = allm; /* accept all multicasts */ 1405 1406 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1407 1408 /* 1409 * Start the config command/DMA. 1410 */ 1411 fxp_scb_wait(sc); 1412 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1413 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1414 /* ...and wait for it to complete. */ 1415 i = 1000; 1416 do { 1417 FXP_CDCONFIGSYNC(sc, 1418 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1419 DELAY(1); 1420 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1421 if (i == 0) { 1422 printf("%s at line %d: dmasync timeout\n", 1423 sc->sc_dev.dv_xname, __LINE__); 1424 return ETIMEDOUT; 1425 } 1426 1427 /* 1428 * Initialize the station address. 1429 */ 1430 cb_ias = &sc->sc_control_data->fcd_iascb; 1431 /* BIG_ENDIAN: no need to swap to store 0 */ 1432 cb_ias->cb_status = 0; 1433 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1434 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1435 cb_ias->link_addr = 0xffffffff; 1436 memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1437 1438 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1439 1440 /* 1441 * Start the IAS (Individual Address Setup) command/DMA. 1442 */ 1443 fxp_scb_wait(sc); 1444 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1445 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1446 /* ...and wait for it to complete. */ 1447 i = 1000; 1448 do { 1449 FXP_CDIASSYNC(sc, 1450 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1451 DELAY(1); 1452 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1453 if (i == 0) { 1454 printf("%s at line %d: dmasync timeout\n", 1455 sc->sc_dev.dv_xname, __LINE__); 1456 return ETIMEDOUT; 1457 } 1458 1459 /* 1460 * Initialize the transmit descriptor ring. txlast is initialized 1461 * to the end of the list so that it will wrap around to the first 1462 * descriptor when the first packet is transmitted. 1463 */ 1464 for (i = 0; i < FXP_NTXCB; i++) { 1465 txd = FXP_CDTX(sc, i); 1466 memset(txd, 0, sizeof(struct fxp_cb_tx)); 1467 txd->cb_command = 1468 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1469 txd->tbd_array_addr = htole32(FXP_CDTBDADDR(sc, i)); 1470 txd->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1471 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1472 } 1473 sc->sc_txpending = 0; 1474 sc->sc_txdirty = 0; 1475 sc->sc_txlast = FXP_NTXCB - 1; 1476 1477 /* 1478 * Initialize the receive buffer list. 1479 */ 1480 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1481 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1482 rxmap = FXP_RXMAP_GET(sc); 1483 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1484 printf("%s: unable to allocate or map rx " 1485 "buffer %d, error = %d\n", 1486 sc->sc_dev.dv_xname, 1487 sc->sc_rxq.ifq_len, error); 1488 /* 1489 * XXX Should attempt to run with fewer receive 1490 * XXX buffers instead of just failing. 1491 */ 1492 FXP_RXMAP_PUT(sc, rxmap); 1493 fxp_rxdrain(sc); 1494 goto out; 1495 } 1496 } 1497 sc->sc_rxidle = 0; 1498 1499 /* 1500 * Give the transmit ring to the chip. We do this by pointing 1501 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1502 * issuing a start command. It will execute the NOP and then 1503 * suspend, pointing at the first descriptor. 1504 */ 1505 fxp_scb_wait(sc); 1506 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1507 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1508 1509 /* 1510 * Initialize receiver buffer area - RFA. 1511 */ 1512 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1513 fxp_scb_wait(sc); 1514 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1515 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1516 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_START); 1517 1518 if (sc->sc_flags & FXPF_MII) { 1519 /* 1520 * Set current media. 1521 */ 1522 mii_mediachg(&sc->sc_mii); 1523 } 1524 1525 /* 1526 * ...all done! 1527 */ 1528 ifp->if_flags |= IFF_RUNNING; 1529 ifp->if_flags &= ~IFF_OACTIVE; 1530 1531 /* 1532 * Start the one second timer. 1533 */ 1534 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1535 1536 /* 1537 * Attempt to start output on the interface. 1538 */ 1539 fxp_start(ifp); 1540 1541 out: 1542 if (error) { 1543 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1544 ifp->if_timer = 0; 1545 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1546 } 1547 return (error); 1548} 1549 1550/* 1551 * Change media according to request. 1552 */ 1553int 1554fxp_mii_mediachange(ifp) 1555 struct ifnet *ifp; 1556{ 1557 struct fxp_softc *sc = ifp->if_softc; 1558 1559 if (ifp->if_flags & IFF_UP) 1560 mii_mediachg(&sc->sc_mii); 1561 return (0); 1562} 1563 1564/* 1565 * Notify the world which media we're using. 1566 */ 1567void 1568fxp_mii_mediastatus(ifp, ifmr) 1569 struct ifnet *ifp; 1570 struct ifmediareq *ifmr; 1571{ 1572 struct fxp_softc *sc = ifp->if_softc; 1573 1574 if(sc->sc_enabled == 0) { 1575 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1576 ifmr->ifm_status = 0; 1577 return; 1578 } 1579 1580 mii_pollstat(&sc->sc_mii); 1581 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1582 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1583} 1584 1585int 1586fxp_80c24_mediachange(ifp) 1587 struct ifnet *ifp; 1588{ 1589 1590 /* Nothing to do here. */ 1591 return (0); 1592} 1593 1594void 1595fxp_80c24_mediastatus(ifp, ifmr) 1596 struct ifnet *ifp; 1597 struct ifmediareq *ifmr; 1598{ 1599 struct fxp_softc *sc = ifp->if_softc; 1600 1601 /* 1602 * Media is currently-selected media. We cannot determine 1603 * the link status. 1604 */ 1605 ifmr->ifm_status = 0; 1606 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1607} 1608 1609/* 1610 * Add a buffer to the end of the RFA buffer list. 1611 * Return 0 if successful, error code on failure. 1612 * 1613 * The RFA struct is stuck at the beginning of mbuf cluster and the 1614 * data pointer is fixed up to point just past it. 1615 */ 1616int 1617fxp_add_rfabuf(sc, rxmap, unload) 1618 struct fxp_softc *sc; 1619 bus_dmamap_t rxmap; 1620 int unload; 1621{ 1622 struct mbuf *m; 1623 int error; 1624 1625 MGETHDR(m, M_DONTWAIT, MT_DATA); 1626 if (m == NULL) 1627 return (ENOBUFS); 1628 1629 MCLGET(m, M_DONTWAIT); 1630 if ((m->m_flags & M_EXT) == 0) { 1631 m_freem(m); 1632 return (ENOBUFS); 1633 } 1634 1635 if (unload) 1636 bus_dmamap_unload(sc->sc_dmat, rxmap); 1637 1638 M_SETCTX(m, rxmap); 1639 1640 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1641 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1642 if (error) { 1643 printf("%s: can't load rx DMA map %d, error = %d\n", 1644 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 1645 panic("fxp_add_rfabuf"); /* XXX */ 1646 } 1647 1648 FXP_INIT_RFABUF(sc, m); 1649 1650 return (0); 1651} 1652 1653int 1654fxp_mdi_read(self, phy, reg) 1655 struct device *self; 1656 int phy; 1657 int reg; 1658{ 1659 struct fxp_softc *sc = (struct fxp_softc *)self; 1660 int count = 10000; 1661 int value; 1662 1663 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1664 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1665 1666 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1667 && count--) 1668 DELAY(10); 1669 1670 if (count <= 0) 1671 printf("%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 1672 1673 return (value & 0xffff); 1674} 1675 1676void 1677fxp_statchg(self) 1678 struct device *self; 1679{ 1680 1681 /* Nothing to do. */ 1682} 1683 1684void 1685fxp_mdi_write(self, phy, reg, value) 1686 struct device *self; 1687 int phy; 1688 int reg; 1689 int value; 1690{ 1691 struct fxp_softc *sc = (struct fxp_softc *)self; 1692 int count = 10000; 1693 1694 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1695 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1696 (value & 0xffff)); 1697 1698 while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1699 count--) 1700 DELAY(10); 1701 1702 if (count <= 0) 1703 printf("%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 1704} 1705 1706int 1707fxp_ioctl(ifp, cmd, data) 1708 struct ifnet *ifp; 1709 u_long cmd; 1710 caddr_t data; 1711{ 1712 struct fxp_softc *sc = ifp->if_softc; 1713 struct ifreq *ifr = (struct ifreq *)data; 1714 int s, error; 1715 1716 s = splnet(); 1717 1718 switch (cmd) { 1719 case SIOCSIFMEDIA: 1720 case SIOCGIFMEDIA: 1721 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1722 break; 1723 1724 default: 1725 error = ether_ioctl(ifp, cmd, data); 1726 if (error == ENETRESET) { 1727 if (sc->sc_enabled) { 1728 /* 1729 * Multicast list has changed; set the 1730 * hardware filter accordingly. 1731 */ 1732 if (sc->sc_txpending) { 1733 sc->sc_flags |= FXPF_WANTINIT; 1734 error = 0; 1735 } else 1736 error = fxp_init(ifp); 1737 } else 1738 error = 0; 1739 } 1740 break; 1741 } 1742 1743 /* Try to get more packets going. */ 1744 if (sc->sc_enabled) 1745 fxp_start(ifp); 1746 1747 splx(s); 1748 return (error); 1749} 1750 1751/* 1752 * Program the multicast filter. 1753 * 1754 * This function must be called at splnet(). 1755 */ 1756void 1757fxp_mc_setup(sc) 1758 struct fxp_softc *sc; 1759{ 1760 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 1761 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1762 struct ethercom *ec = &sc->sc_ethercom; 1763 struct ether_multi *enm; 1764 struct ether_multistep step; 1765 int count, nmcasts; 1766 1767#ifdef DIAGNOSTIC 1768 if (sc->sc_txpending) 1769 panic("fxp_mc_setup: pending transmissions"); 1770#endif 1771 1772 ifp->if_flags &= ~IFF_ALLMULTI; 1773 1774 /* 1775 * Initialize multicast setup descriptor. 1776 */ 1777 nmcasts = 0; 1778 ETHER_FIRST_MULTI(step, ec, enm); 1779 while (enm != NULL) { 1780 /* 1781 * Check for too many multicast addresses or if we're 1782 * listening to a range. Either way, we simply have 1783 * to accept all multicasts. 1784 */ 1785 if (nmcasts >= MAXMCADDR || 1786 memcmp(enm->enm_addrlo, enm->enm_addrhi, 1787 ETHER_ADDR_LEN) != 0) { 1788 /* 1789 * Callers of this function must do the 1790 * right thing with this. If we're called 1791 * from outside fxp_init(), the caller must 1792 * detect if the state if IFF_ALLMULTI changes. 1793 * If it does, the caller must then call 1794 * fxp_init(), since allmulti is handled by 1795 * the config block. 1796 */ 1797 ifp->if_flags |= IFF_ALLMULTI; 1798 return; 1799 } 1800 memcpy((void *)&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 1801 ETHER_ADDR_LEN); 1802 nmcasts++; 1803 ETHER_NEXT_MULTI(step, enm); 1804 } 1805 1806 /* BIG_ENDIAN: no need to swap to store 0 */ 1807 mcsp->cb_status = 0; 1808 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1809 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 1810 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 1811 1812 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1813 1814 /* 1815 * Wait until the command unit is not active. This should never 1816 * happen since nothing is queued, but make sure anyway. 1817 */ 1818 count = 100; 1819 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 1820 FXP_SCB_CUS_ACTIVE && --count) 1821 DELAY(1); 1822 if (count == 0) { 1823 printf("%s at line %d: command queue timeout\n", 1824 sc->sc_dev.dv_xname, __LINE__); 1825 return; 1826 } 1827 1828 /* 1829 * Start the multicast setup command/DMA. 1830 */ 1831 fxp_scb_wait(sc); 1832 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 1833 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1834 1835 /* ...and wait for it to complete. */ 1836 count = 1000; 1837 do { 1838 FXP_CDMCSSYNC(sc, 1839 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1840 DELAY(1); 1841 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 1842 if (count == 0) { 1843 printf("%s at line %d: dmasync timeout\n", 1844 sc->sc_dev.dv_xname, __LINE__); 1845 return; 1846 } 1847} 1848 1849int 1850fxp_enable(sc) 1851 struct fxp_softc *sc; 1852{ 1853 1854 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 1855 if ((*sc->sc_enable)(sc) != 0) { 1856 printf("%s: device enable failed\n", 1857 sc->sc_dev.dv_xname); 1858 return (EIO); 1859 } 1860 } 1861 1862 sc->sc_enabled = 1; 1863 return (0); 1864} 1865 1866void 1867fxp_disable(sc) 1868 struct fxp_softc *sc; 1869{ 1870 1871 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 1872 (*sc->sc_disable)(sc); 1873 sc->sc_enabled = 0; 1874 } 1875} 1876 1877/* 1878 * fxp_activate: 1879 * 1880 * Handle device activation/deactivation requests. 1881 */ 1882int 1883fxp_activate(self, act) 1884 struct device *self; 1885 enum devact act; 1886{ 1887 struct fxp_softc *sc = (void *) self; 1888 int s, error = 0; 1889 1890 s = splnet(); 1891 switch (act) { 1892 case DVACT_ACTIVATE: 1893 error = EOPNOTSUPP; 1894 break; 1895 1896 case DVACT_DEACTIVATE: 1897 if (sc->sc_flags & FXPF_MII) 1898 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 1899 MII_OFFSET_ANY); 1900 if_deactivate(&sc->sc_ethercom.ec_if); 1901 break; 1902 } 1903 splx(s); 1904 1905 return (error); 1906} 1907 1908/* 1909 * fxp_detach: 1910 * 1911 * Detach an i82557 interface. 1912 */ 1913int 1914fxp_detach(sc) 1915 struct fxp_softc *sc; 1916{ 1917 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1918 int i; 1919 1920 /* Succeed now if there's no work to do. */ 1921 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 1922 return (0); 1923 1924 /* Unhook our tick handler. */ 1925 callout_stop(&sc->sc_callout); 1926 1927 if (sc->sc_flags & FXPF_MII) { 1928 /* Detach all PHYs */ 1929 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1930 } 1931 1932 /* Delete all remaining media. */ 1933 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 1934 1935#if NRND > 0 1936 rnd_detach_source(&sc->rnd_source); 1937#endif 1938 ether_ifdetach(ifp); 1939 if_detach(ifp); 1940 1941 for (i = 0; i < FXP_NRFABUFS; i++) { 1942 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 1943 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 1944 } 1945 1946 for (i = 0; i < FXP_NTXCB; i++) { 1947 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 1948 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 1949 } 1950 1951 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 1952 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 1953 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1954 sizeof(struct fxp_control_data)); 1955 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 1956 1957 shutdownhook_disestablish(sc->sc_sdhook); 1958 powerhook_disestablish(sc->sc_powerhook); 1959 1960 return (0); 1961} 1962