i82557.c revision 1.43
1/* $NetBSD: i82557.c,v 1.43 2000/12/14 06:27:25 thorpej Exp $ */ 2 3/*- 4 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40/* 41 * Copyright (c) 1995, David Greenman 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice unmodified, this list of conditions, and the following 49 * disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 55 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 57 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 60 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 62 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 63 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 * Id: if_fxp.c,v 1.47 1998/01/08 23:42:29 eivind Exp 67 */ 68 69/* 70 * Device driver for the Intel i82557 fast Ethernet controller, 71 * and its successors, the i82558 and i82559. 72 */ 73 74#include "opt_inet.h" 75#include "opt_ns.h" 76#include "bpfilter.h" 77#include "rnd.h" 78 79#include <sys/param.h> 80#include <sys/systm.h> 81#include <sys/callout.h> 82#include <sys/mbuf.h> 83#include <sys/malloc.h> 84#include <sys/kernel.h> 85#include <sys/socket.h> 86#include <sys/ioctl.h> 87#include <sys/errno.h> 88#include <sys/device.h> 89 90#include <machine/endian.h> 91 92#include <uvm/uvm_extern.h> 93 94#if NRND > 0 95#include <sys/rnd.h> 96#endif 97 98#include <net/if.h> 99#include <net/if_dl.h> 100#include <net/if_media.h> 101#include <net/if_ether.h> 102 103#if NBPFILTER > 0 104#include <net/bpf.h> 105#endif 106 107#ifdef INET 108#include <netinet/in.h> 109#include <netinet/if_inarp.h> 110#endif 111 112#ifdef NS 113#include <netns/ns.h> 114#include <netns/ns_if.h> 115#endif 116 117#include <machine/bus.h> 118#include <machine/intr.h> 119 120#include <dev/mii/miivar.h> 121 122#include <dev/ic/i82557reg.h> 123#include <dev/ic/i82557var.h> 124 125/* 126 * NOTE! On the Alpha, we have an alignment constraint. The 127 * card DMAs the packet immediately following the RFA. However, 128 * the first thing in the packet is a 14-byte Ethernet header. 129 * This means that the packet is misaligned. To compensate, 130 * we actually offset the RFA 2 bytes into the cluster. This 131 * alignes the packet after the Ethernet header at a 32-bit 132 * boundary. HOWEVER! This means that the RFA is misaligned! 133 */ 134#define RFA_ALIGNMENT_FUDGE 2 135 136/* 137 * Template for default configuration parameters. 138 * See struct fxp_cb_config for the bit definitions. 139 */ 140u_int8_t fxp_cb_config_template[] = { 141 0x0, 0x0, /* cb_status */ 142 0x80, 0x2, /* cb_command */ 143 0xff, 0xff, 0xff, 0xff, /* link_addr */ 144 0x16, /* 0 */ 145 0x8, /* 1 */ 146 0x0, /* 2 */ 147 0x0, /* 3 */ 148 0x0, /* 4 */ 149 0x80, /* 5 */ 150 0xb2, /* 6 */ 151 0x3, /* 7 */ 152 0x1, /* 8 */ 153 0x0, /* 9 */ 154 0x26, /* 10 */ 155 0x0, /* 11 */ 156 0x60, /* 12 */ 157 0x0, /* 13 */ 158 0xf2, /* 14 */ 159 0x48, /* 15 */ 160 0x0, /* 16 */ 161 0x40, /* 17 */ 162 0xf3, /* 18 */ 163 0x0, /* 19 */ 164 0x3f, /* 20 */ 165 0x5 /* 21 */ 166}; 167 168void fxp_mii_initmedia __P((struct fxp_softc *)); 169int fxp_mii_mediachange __P((struct ifnet *)); 170void fxp_mii_mediastatus __P((struct ifnet *, struct ifmediareq *)); 171 172void fxp_80c24_initmedia __P((struct fxp_softc *)); 173int fxp_80c24_mediachange __P((struct ifnet *)); 174void fxp_80c24_mediastatus __P((struct ifnet *, struct ifmediareq *)); 175 176inline void fxp_scb_wait __P((struct fxp_softc *)); 177 178void fxp_start __P((struct ifnet *)); 179int fxp_ioctl __P((struct ifnet *, u_long, caddr_t)); 180void fxp_watchdog __P((struct ifnet *)); 181int fxp_init __P((struct ifnet *)); 182void fxp_stop __P((struct ifnet *, int)); 183 184void fxp_rxdrain __P((struct fxp_softc *)); 185int fxp_add_rfabuf __P((struct fxp_softc *, bus_dmamap_t, int)); 186int fxp_mdi_read __P((struct device *, int, int)); 187void fxp_statchg __P((struct device *)); 188void fxp_mdi_write __P((struct device *, int, int, int)); 189void fxp_autosize_eeprom __P((struct fxp_softc*)); 190void fxp_read_eeprom __P((struct fxp_softc *, u_int16_t *, int, int)); 191void fxp_get_info __P((struct fxp_softc *, u_int8_t *)); 192void fxp_tick __P((void *)); 193void fxp_mc_setup __P((struct fxp_softc *)); 194 195void fxp_shutdown __P((void *)); 196void fxp_power __P((int, void *)); 197 198int fxp_copy_small = 0; 199 200struct fxp_phytype { 201 int fp_phy; /* type of PHY, -1 for MII at the end. */ 202 void (*fp_init) __P((struct fxp_softc *)); 203} fxp_phytype_table[] = { 204 { FXP_PHY_80C24, fxp_80c24_initmedia }, 205 { -1, fxp_mii_initmedia }, 206}; 207 208/* 209 * Set initial transmit threshold at 64 (512 bytes). This is 210 * increased by 64 (512 bytes) at a time, to maximum of 192 211 * (1536 bytes), if an underrun occurs. 212 */ 213static int tx_threshold = 64; 214 215/* 216 * Wait for the previous command to be accepted (but not necessarily 217 * completed). 218 */ 219inline void 220fxp_scb_wait(sc) 221 struct fxp_softc *sc; 222{ 223 int i = 10000; 224 225 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 226 delay(2); 227 if (i == 0) 228 printf("%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 229} 230 231/* 232 * Finish attaching an i82557 interface. Called by bus-specific front-end. 233 */ 234void 235fxp_attach(sc) 236 struct fxp_softc *sc; 237{ 238 u_int8_t enaddr[ETHER_ADDR_LEN]; 239 struct ifnet *ifp; 240 bus_dma_segment_t seg; 241 int rseg, i, error; 242 struct fxp_phytype *fp; 243 244 callout_init(&sc->sc_callout); 245 246 /* 247 * Allocate the control data structures, and create and load the 248 * DMA map for it. 249 */ 250 if ((error = bus_dmamem_alloc(sc->sc_dmat, 251 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 252 0)) != 0) { 253 printf("%s: unable to allocate control data, error = %d\n", 254 sc->sc_dev.dv_xname, error); 255 goto fail_0; 256 } 257 258 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 259 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 260 BUS_DMA_COHERENT)) != 0) { 261 printf("%s: unable to map control data, error = %d\n", 262 sc->sc_dev.dv_xname, error); 263 goto fail_1; 264 } 265 sc->sc_cdseg = seg; 266 sc->sc_cdnseg = rseg; 267 268 bzero(sc->sc_control_data, sizeof(struct fxp_control_data)); 269 270 if ((error = bus_dmamap_create(sc->sc_dmat, 271 sizeof(struct fxp_control_data), 1, 272 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 273 printf("%s: unable to create control data DMA map, " 274 "error = %d\n", sc->sc_dev.dv_xname, error); 275 goto fail_2; 276 } 277 278 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 279 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 280 0)) != 0) { 281 printf("%s: can't load control data DMA map, error = %d\n", 282 sc->sc_dev.dv_xname, error); 283 goto fail_3; 284 } 285 286 /* 287 * Create the transmit buffer DMA maps. 288 */ 289 for (i = 0; i < FXP_NTXCB; i++) { 290 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 291 FXP_NTXSEG, MCLBYTES, 0, 0, 292 &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 293 printf("%s: unable to create tx DMA map %d, " 294 "error = %d\n", sc->sc_dev.dv_xname, i, error); 295 goto fail_4; 296 } 297 } 298 299 /* 300 * Create the receive buffer DMA maps. 301 */ 302 for (i = 0; i < FXP_NRFABUFS; i++) { 303 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 304 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 305 printf("%s: unable to create rx DMA map %d, " 306 "error = %d\n", sc->sc_dev.dv_xname, i, error); 307 goto fail_5; 308 } 309 } 310 311 /* Initialize MAC address and media structures. */ 312 fxp_get_info(sc, enaddr); 313 314 printf("%s: Ethernet address %s, %s Mb/s\n", sc->sc_dev.dv_xname, 315 ether_sprintf(enaddr), sc->phy_10Mbps_only ? "10" : "10/100"); 316 317 ifp = &sc->sc_ethercom.ec_if; 318 319 /* 320 * Get info about our media interface, and initialize it. Note 321 * the table terminates itself with a phy of -1, indicating 322 * that we're using MII. 323 */ 324 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 325 if (fp->fp_phy == sc->phy_primary_device) 326 break; 327 (*fp->fp_init)(sc); 328 329 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 330 ifp->if_softc = sc; 331 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 332 ifp->if_ioctl = fxp_ioctl; 333 ifp->if_start = fxp_start; 334 ifp->if_watchdog = fxp_watchdog; 335 ifp->if_init = fxp_init; 336 ifp->if_stop = fxp_stop; 337 IFQ_SET_READY(&ifp->if_snd); 338 339 /* 340 * We can support 802.1Q VLAN-sized frames. 341 */ 342 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 343 344 /* 345 * Attach the interface. 346 */ 347 if_attach(ifp); 348 ether_ifattach(ifp, enaddr); 349#if NRND > 0 350 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 351 RND_TYPE_NET, 0); 352#endif 353 354 /* 355 * Add shutdown hook so that DMA is disabled prior to reboot. Not 356 * doing do could allow DMA to corrupt kernel memory during the 357 * reboot before the driver initializes. 358 */ 359 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 360 if (sc->sc_sdhook == NULL) 361 printf("%s: WARNING: unable to establish shutdown hook\n", 362 sc->sc_dev.dv_xname); 363 /* 364 * Add suspend hook, for similar reasons.. 365 */ 366 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 367 if (sc->sc_powerhook == NULL) 368 printf("%s: WARNING: unable to establish power hook\n", 369 sc->sc_dev.dv_xname); 370 371 /* The attach is successful. */ 372 sc->sc_flags |= FXPF_ATTACHED; 373 374 return; 375 376 /* 377 * Free any resources we've allocated during the failed attach 378 * attempt. Do this in reverse order and fall though. 379 */ 380 fail_5: 381 for (i = 0; i < FXP_NRFABUFS; i++) { 382 if (sc->sc_rxmaps[i] != NULL) 383 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 384 } 385 fail_4: 386 for (i = 0; i < FXP_NTXCB; i++) { 387 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 388 bus_dmamap_destroy(sc->sc_dmat, 389 FXP_DSTX(sc, i)->txs_dmamap); 390 } 391 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 392 fail_3: 393 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 394 fail_2: 395 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 396 sizeof(struct fxp_control_data)); 397 fail_1: 398 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 399 fail_0: 400 return; 401} 402 403void 404fxp_mii_initmedia(sc) 405 struct fxp_softc *sc; 406{ 407 408 sc->sc_flags |= FXPF_MII; 409 410 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 411 sc->sc_mii.mii_readreg = fxp_mdi_read; 412 sc->sc_mii.mii_writereg = fxp_mdi_write; 413 sc->sc_mii.mii_statchg = fxp_statchg; 414 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_mii_mediachange, 415 fxp_mii_mediastatus); 416 /* 417 * The i82557 wedges if all of its PHYs are isolated! 418 */ 419 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 420 MII_OFFSET_ANY, MIIF_NOISOLATE); 421 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 422 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 423 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 424 } else 425 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 426} 427 428void 429fxp_80c24_initmedia(sc) 430 struct fxp_softc *sc; 431{ 432 433 /* 434 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 435 * doesn't have a programming interface of any sort. The 436 * media is sensed automatically based on how the link partner 437 * is configured. This is, in essence, manual configuration. 438 */ 439 printf("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 440 sc->sc_dev.dv_xname); 441 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 442 fxp_80c24_mediastatus); 443 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 444 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 445} 446 447/* 448 * Device shutdown routine. Called at system shutdown after sync. The 449 * main purpose of this routine is to shut off receiver DMA so that 450 * kernel memory doesn't get clobbered during warmboot. 451 */ 452void 453fxp_shutdown(arg) 454 void *arg; 455{ 456 struct fxp_softc *sc = arg; 457 458 /* 459 * Since the system's going to halt shortly, don't bother 460 * freeing mbufs. 461 */ 462 fxp_stop(&sc->sc_ethercom.ec_if, 0); 463} 464/* 465 * Power handler routine. Called when the system is transitioning 466 * into/out of power save modes. As with fxp_shutdown, the main 467 * purpose of this routine is to shut off receiver DMA so it doesn't 468 * clobber kernel memory at the wrong time. 469 */ 470void 471fxp_power(why, arg) 472 int why; 473 void *arg; 474{ 475 struct fxp_softc *sc = arg; 476 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 477 int s; 478 479 s = splnet(); 480 switch (why) { 481 case PWR_SUSPEND: 482 case PWR_STANDBY: 483 fxp_stop(ifp, 0); 484 break; 485 case PWR_RESUME: 486 if (ifp->if_flags & IFF_UP) 487 fxp_init(ifp); 488 break; 489 case PWR_SOFTSUSPEND: 490 case PWR_SOFTSTANDBY: 491 case PWR_SOFTRESUME: 492 break; 493 } 494 splx(s); 495} 496 497/* 498 * Initialize the interface media. 499 */ 500void 501fxp_get_info(sc, enaddr) 502 struct fxp_softc *sc; 503 u_int8_t *enaddr; 504{ 505 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 506 507 /* 508 * Reset to a stable state. 509 */ 510 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 511 DELAY(10); 512 513 sc->sc_eeprom_size = 0; 514 fxp_autosize_eeprom(sc); 515 if(sc->sc_eeprom_size == 0) { 516 printf("%s: failed to detect EEPROM size\n", sc->sc_dev.dv_xname); 517 sc->sc_eeprom_size = 6; /* XXX panic here? */ 518 } 519#ifdef DEBUG 520 printf("%s: detected %d word EEPROM\n", 521 sc->sc_dev.dv_xname, 522 1 << sc->sc_eeprom_size); 523#endif 524 525 /* 526 * Get info about the primary PHY 527 */ 528 fxp_read_eeprom(sc, &data, 6, 1); 529 sc->phy_primary_addr = data & 0xff; 530 sc->phy_primary_device = (data >> 8) & 0x3f; 531 sc->phy_10Mbps_only = data >> 15; 532 533 /* 534 * Read MAC address. 535 */ 536 fxp_read_eeprom(sc, myea, 0, 3); 537 enaddr[0] = myea[0] & 0xff; 538 enaddr[1] = myea[0] >> 8; 539 enaddr[2] = myea[1] & 0xff; 540 enaddr[3] = myea[1] >> 8; 541 enaddr[4] = myea[2] & 0xff; 542 enaddr[5] = myea[2] >> 8; 543} 544 545/* 546 * Figure out EEPROM size. 547 * 548 * 559's can have either 64-word or 256-word EEPROMs, the 558 549 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 550 * talks about the existance of 16 to 256 word EEPROMs. 551 * 552 * The only known sizes are 64 and 256, where the 256 version is used 553 * by CardBus cards to store CIS information. 554 * 555 * The address is shifted in msb-to-lsb, and after the last 556 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 557 * after which follows the actual data. We try to detect this zero, by 558 * probing the data-out bit in the EEPROM control register just after 559 * having shifted in a bit. If the bit is zero, we assume we've 560 * shifted enough address bits. The data-out should be tri-state, 561 * before this, which should translate to a logical one. 562 * 563 * Other ways to do this would be to try to read a register with known 564 * contents with a varying number of address bits, but no such 565 * register seem to be available. The high bits of register 10 are 01 566 * on the 558 and 559, but apparently not on the 557. 567 * 568 * The Linux driver computes a checksum on the EEPROM data, but the 569 * value of this checksum is not very well documented. 570 */ 571 572void 573fxp_autosize_eeprom(sc) 574 struct fxp_softc *sc; 575{ 576 u_int16_t reg; 577 int x; 578 579 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 580 /* 581 * Shift in read opcode. 582 */ 583 for (x = 3; x > 0; x--) { 584 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 585 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 586 } else { 587 reg = FXP_EEPROM_EECS; 588 } 589 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 590 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 591 reg | FXP_EEPROM_EESK); 592 DELAY(4); 593 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 594 DELAY(4); 595 } 596 /* 597 * Shift in address, wait for the dummy zero following a correct 598 * address shift. 599 */ 600 for (x = 1; x <= 8; x++) { 601 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 602 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 603 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 604 DELAY(4); 605 if((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 606 FXP_EEPROM_EEDO) == 0) 607 break; 608 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 609 DELAY(4); 610 } 611 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 612 DELAY(4); 613 if(x != 6 && x != 8) { 614#ifdef DEBUG 615 printf("%s: strange EEPROM size (%d)\n", 616 sc->sc_dev.dv_xname, 1 << x); 617#endif 618 } else 619 sc->sc_eeprom_size = x; 620} 621 622/* 623 * Read from the serial EEPROM. Basically, you manually shift in 624 * the read opcode (one bit at a time) and then shift in the address, 625 * and then you shift out the data (all of this one bit at a time). 626 * The word size is 16 bits, so you have to provide the address for 627 * every 16 bits of data. 628 */ 629void 630fxp_read_eeprom(sc, data, offset, words) 631 struct fxp_softc *sc; 632 u_int16_t *data; 633 int offset; 634 int words; 635{ 636 u_int16_t reg; 637 int i, x; 638 639 for (i = 0; i < words; i++) { 640 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 641 /* 642 * Shift in read opcode. 643 */ 644 for (x = 3; x > 0; x--) { 645 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 646 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 647 } else { 648 reg = FXP_EEPROM_EECS; 649 } 650 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 651 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 652 reg | FXP_EEPROM_EESK); 653 DELAY(4); 654 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 655 DELAY(4); 656 } 657 /* 658 * Shift in address. 659 */ 660 for (x = sc->sc_eeprom_size; x > 0; x--) { 661 if ((i + offset) & (1 << (x - 1))) { 662 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 663 } else { 664 reg = FXP_EEPROM_EECS; 665 } 666 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 667 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 668 reg | FXP_EEPROM_EESK); 669 DELAY(4); 670 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 671 DELAY(4); 672 } 673 reg = FXP_EEPROM_EECS; 674 data[i] = 0; 675 /* 676 * Shift out data. 677 */ 678 for (x = 16; x > 0; x--) { 679 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 680 reg | FXP_EEPROM_EESK); 681 DELAY(4); 682 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 683 FXP_EEPROM_EEDO) 684 data[i] |= (1 << (x - 1)); 685 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 686 DELAY(4); 687 } 688 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 689 DELAY(4); 690 } 691} 692 693/* 694 * Start packet transmission on the interface. 695 */ 696void 697fxp_start(ifp) 698 struct ifnet *ifp; 699{ 700 struct fxp_softc *sc = ifp->if_softc; 701 struct mbuf *m0, *m; 702 struct fxp_cb_tx *txd; 703 struct fxp_txsoft *txs; 704 struct fxp_tbdlist *tbd; 705 bus_dmamap_t dmamap; 706 int error, lasttx, nexttx, opending, seg; 707 708 /* 709 * If we want a re-init, bail out now. 710 */ 711 if (sc->sc_flags & FXPF_WANTINIT) { 712 ifp->if_flags |= IFF_OACTIVE; 713 return; 714 } 715 716 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 717 return; 718 719 /* 720 * Remember the previous txpending and the current lasttx. 721 */ 722 opending = sc->sc_txpending; 723 lasttx = sc->sc_txlast; 724 725 /* 726 * Loop through the send queue, setting up transmit descriptors 727 * until we drain the queue, or use up all available transmit 728 * descriptors. 729 */ 730 while (sc->sc_txpending < FXP_NTXCB) { 731 /* 732 * Grab a packet off the queue. 733 */ 734 IFQ_POLL(&ifp->if_snd, m0); 735 if (m0 == NULL) 736 break; 737 738 /* 739 * Get the next available transmit descriptor. 740 */ 741 nexttx = FXP_NEXTTX(sc->sc_txlast); 742 txd = FXP_CDTX(sc, nexttx); 743 tbd = FXP_CDTBD(sc, nexttx); 744 txs = FXP_DSTX(sc, nexttx); 745 dmamap = txs->txs_dmamap; 746 747 /* 748 * Load the DMA map. If this fails, the packet either 749 * didn't fit in the allotted number of frags, or we were 750 * short on resources. In this case, we'll copy and try 751 * again. 752 */ 753 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 754 BUS_DMA_NOWAIT) != 0) { 755 MGETHDR(m, M_DONTWAIT, MT_DATA); 756 if (m == NULL) { 757 printf("%s: unable to allocate Tx mbuf\n", 758 sc->sc_dev.dv_xname); 759 break; 760 } 761 if (m0->m_pkthdr.len > MHLEN) { 762 MCLGET(m, M_DONTWAIT); 763 if ((m->m_flags & M_EXT) == 0) { 764 printf("%s: unable to allocate Tx " 765 "cluster\n", sc->sc_dev.dv_xname); 766 m_freem(m); 767 break; 768 } 769 } 770 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 771 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 772 m_freem(m0); 773 m0 = m; 774 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 775 m0, BUS_DMA_NOWAIT); 776 if (error) { 777 printf("%s: unable to load Tx buffer, " 778 "error = %d\n", sc->sc_dev.dv_xname, error); 779 break; 780 } 781 } 782 783 IFQ_DEQUEUE(&ifp->if_snd, m0); 784 785 /* Initialize the fraglist. */ 786 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 787 tbd->tbd_d[seg].tb_addr = 788 htole32(dmamap->dm_segs[seg].ds_addr); 789 tbd->tbd_d[seg].tb_size = 790 htole32(dmamap->dm_segs[seg].ds_len); 791 } 792 793 FXP_CDTBDSYNC(sc, nexttx, BUS_DMASYNC_PREWRITE); 794 795 /* Sync the DMA map. */ 796 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 797 BUS_DMASYNC_PREWRITE); 798 799 /* 800 * Store a pointer to the packet so we can free it later. 801 */ 802 txs->txs_mbuf = m0; 803 804 /* 805 * Initialize the transmit descriptor. 806 */ 807 /* BIG_ENDIAN: no need to swap to store 0 */ 808 txd->cb_status = 0; 809 txd->cb_command = 810 htole16(FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF); 811 txd->tx_threshold = tx_threshold; 812 txd->tbd_number = dmamap->dm_nsegs; 813 814 FXP_CDTXSYNC(sc, nexttx, 815 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 816 817 /* Advance the tx pointer. */ 818 sc->sc_txpending++; 819 sc->sc_txlast = nexttx; 820 821#if NBPFILTER > 0 822 /* 823 * Pass packet to bpf if there is a listener. 824 */ 825 if (ifp->if_bpf) 826 bpf_mtap(ifp->if_bpf, m0); 827#endif 828 } 829 830 if (sc->sc_txpending == FXP_NTXCB) { 831 /* No more slots; notify upper layer. */ 832 ifp->if_flags |= IFF_OACTIVE; 833 } 834 835 if (sc->sc_txpending != opending) { 836 /* 837 * We enqueued packets. If the transmitter was idle, 838 * reset the txdirty pointer. 839 */ 840 if (opending == 0) 841 sc->sc_txdirty = FXP_NEXTTX(lasttx); 842 843 /* 844 * Cause the chip to interrupt and suspend command 845 * processing once the last packet we've enqueued 846 * has been transmitted. 847 */ 848 FXP_CDTX(sc, sc->sc_txlast)->cb_command |= 849 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 850 FXP_CDTXSYNC(sc, sc->sc_txlast, 851 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 852 853 /* 854 * The entire packet chain is set up. Clear the suspend bit 855 * on the command prior to the first packet we set up. 856 */ 857 FXP_CDTXSYNC(sc, lasttx, 858 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 859 FXP_CDTX(sc, lasttx)->cb_command &= htole16(~FXP_CB_COMMAND_S); 860 FXP_CDTXSYNC(sc, lasttx, 861 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 862 863 /* 864 * Issue a Resume command in case the chip was suspended. 865 */ 866 fxp_scb_wait(sc); 867 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME); 868 869 /* Set a watchdog timer in case the chip flakes out. */ 870 ifp->if_timer = 5; 871 } 872} 873 874/* 875 * Process interface interrupts. 876 */ 877int 878fxp_intr(arg) 879 void *arg; 880{ 881 struct fxp_softc *sc = arg; 882 struct ethercom *ec = &sc->sc_ethercom; 883 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 884 struct fxp_cb_tx *txd; 885 struct fxp_txsoft *txs; 886 struct mbuf *m, *m0; 887 bus_dmamap_t rxmap; 888 struct fxp_rfa *rfa; 889 int i, claimed = 0; 890 u_int16_t len, rxstat, txstat; 891 u_int8_t statack; 892 893 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 894 return (0); 895 /* 896 * If the interface isn't running, don't try to 897 * service the interrupt.. just ack it and bail. 898 */ 899 if ((ifp->if_flags & IFF_RUNNING) == 0) { 900 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 901 if (statack) { 902 claimed = 1; 903 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 904 } 905 return (claimed); 906 } 907 908 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 909 claimed = 1; 910 911 /* 912 * First ACK all the interrupts in this pass. 913 */ 914 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 915 916 /* 917 * Process receiver interrupts. If a no-resource (RNR) 918 * condition exists, get whatever packets we can and 919 * re-start the receiver. 920 */ 921 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 922 rcvloop: 923 m = sc->sc_rxq.ifq_head; 924 rfa = FXP_MTORFA(m); 925 rxmap = M_GETCTX(m, bus_dmamap_t); 926 927 FXP_RFASYNC(sc, m, 928 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 929 930 rxstat = le16toh(rfa->rfa_status); 931 932 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 933 /* 934 * We have processed all of the 935 * receive buffers. 936 */ 937 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 938 goto do_transmit; 939 } 940 941 IF_DEQUEUE(&sc->sc_rxq, m); 942 943 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 944 945 len = le16toh(rfa->actual_size) & 946 (m->m_ext.ext_size - 1); 947 948 if (len < sizeof(struct ether_header)) { 949 /* 950 * Runt packet; drop it now. 951 */ 952 FXP_INIT_RFABUF(sc, m); 953 goto rcvloop; 954 } 955 956 /* 957 * If support for 802.1Q VLAN sized frames is 958 * enabled, we need to do some additional error 959 * checking (as we are saving bad frames, in 960 * order to receive the larger ones). 961 */ 962 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 963 (rxstat & (FXP_RFA_STATUS_OVERRUN| 964 FXP_RFA_STATUS_RNR| 965 FXP_RFA_STATUS_ALIGN| 966 FXP_RFA_STATUS_CRC)) != 0) { 967 FXP_INIT_RFABUF(sc, m); 968 goto rcvloop; 969 } 970 971 /* 972 * If the packet is small enough to fit in a 973 * single header mbuf, allocate one and copy 974 * the data into it. This greatly reduces 975 * memory consumption when we receive lots 976 * of small packets. 977 * 978 * Otherwise, we add a new buffer to the receive 979 * chain. If this fails, we drop the packet and 980 * recycle the old buffer. 981 */ 982 if (fxp_copy_small != 0 && len <= MHLEN) { 983 MGETHDR(m0, M_DONTWAIT, MT_DATA); 984 if (m == NULL) 985 goto dropit; 986 memcpy(mtod(m0, caddr_t), 987 mtod(m, caddr_t), len); 988 FXP_INIT_RFABUF(sc, m); 989 m = m0; 990 } else { 991 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 992 dropit: 993 ifp->if_ierrors++; 994 FXP_INIT_RFABUF(sc, m); 995 goto rcvloop; 996 } 997 } 998 999 m->m_pkthdr.rcvif = ifp; 1000 m->m_pkthdr.len = m->m_len = len; 1001 1002#if NBPFILTER > 0 1003 /* 1004 * Pass this up to any BPF listeners, but only 1005 * pass it up the stack it its for us. 1006 */ 1007 if (ifp->if_bpf) 1008 bpf_mtap(ifp->if_bpf, m); 1009#endif 1010 1011 /* Pass it on. */ 1012 (*ifp->if_input)(ifp, m); 1013 goto rcvloop; 1014 } 1015 1016 do_transmit: 1017 if (statack & FXP_SCB_STATACK_RNR) { 1018 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1019 fxp_scb_wait(sc); 1020 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1021 rxmap->dm_segs[0].ds_addr + 1022 RFA_ALIGNMENT_FUDGE); 1023 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1024 FXP_SCB_COMMAND_RU_START); 1025 } 1026 1027 /* 1028 * Free any finished transmit mbuf chains. 1029 */ 1030 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1031 ifp->if_flags &= ~IFF_OACTIVE; 1032 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1033 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1034 txd = FXP_CDTX(sc, i); 1035 txs = FXP_DSTX(sc, i); 1036 1037 FXP_CDTXSYNC(sc, i, 1038 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1039 1040 txstat = le16toh(txd->cb_status); 1041 1042 if ((txstat & FXP_CB_STATUS_C) == 0) 1043 break; 1044 1045 FXP_CDTBDSYNC(sc, i, BUS_DMASYNC_POSTWRITE); 1046 1047 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1048 0, txs->txs_dmamap->dm_mapsize, 1049 BUS_DMASYNC_POSTWRITE); 1050 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1051 m_freem(txs->txs_mbuf); 1052 txs->txs_mbuf = NULL; 1053 } 1054 1055 /* Update the dirty transmit buffer pointer. */ 1056 sc->sc_txdirty = i; 1057 1058 /* 1059 * Cancel the watchdog timer if there are no pending 1060 * transmissions. 1061 */ 1062 if (sc->sc_txpending == 0) { 1063 ifp->if_timer = 0; 1064 1065 /* 1066 * If we want a re-init, do that now. 1067 */ 1068 if (sc->sc_flags & FXPF_WANTINIT) 1069 (void) fxp_init(ifp); 1070 } 1071 1072 /* 1073 * Try to get more packets going. 1074 */ 1075 fxp_start(ifp); 1076 } 1077 } 1078 1079#if NRND > 0 1080 if (claimed) 1081 rnd_add_uint32(&sc->rnd_source, statack); 1082#endif 1083 return (claimed); 1084} 1085 1086/* 1087 * Update packet in/out/collision statistics. The i82557 doesn't 1088 * allow you to access these counters without doing a fairly 1089 * expensive DMA to get _all_ of the statistics it maintains, so 1090 * we do this operation here only once per second. The statistics 1091 * counters in the kernel are updated from the previous dump-stats 1092 * DMA and then a new dump-stats DMA is started. The on-chip 1093 * counters are zeroed when the DMA completes. If we can't start 1094 * the DMA immediately, we don't wait - we just prepare to read 1095 * them again next time. 1096 */ 1097void 1098fxp_tick(arg) 1099 void *arg; 1100{ 1101 struct fxp_softc *sc = arg; 1102 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1103 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1104 int s; 1105 1106 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1107 return; 1108 1109 s = splnet(); 1110 1111 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1112 1113 ifp->if_opackets += le32toh(sp->tx_good); 1114 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1115 if (sp->rx_good) { 1116 ifp->if_ipackets += le32toh(sp->rx_good); 1117 sc->sc_rxidle = 0; 1118 } else { 1119 sc->sc_rxidle++; 1120 } 1121 ifp->if_ierrors += 1122 le32toh(sp->rx_crc_errors) + 1123 le32toh(sp->rx_alignment_errors) + 1124 le32toh(sp->rx_rnr_errors) + 1125 le32toh(sp->rx_overrun_errors); 1126 /* 1127 * If any transmit underruns occured, bump up the transmit 1128 * threshold by another 512 bytes (64 * 8). 1129 */ 1130 if (sp->tx_underruns) { 1131 ifp->if_oerrors += le32toh(sp->tx_underruns); 1132 if (tx_threshold < 192) 1133 tx_threshold += 64; 1134 } 1135 1136 /* 1137 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1138 * then assume the receiver has locked up and attempt to clear 1139 * the condition by reprogramming the multicast filter (actually, 1140 * resetting the interface). This is a work-around for a bug in 1141 * the 82557 where the receiver locks up if it gets certain types 1142 * of garbage in the syncronization bits prior to the packet header. 1143 * This bug is supposed to only occur in 10Mbps mode, but has been 1144 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1145 * speed transition). 1146 */ 1147 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1148 (void) fxp_init(ifp); 1149 splx(s); 1150 return; 1151 } 1152 /* 1153 * If there is no pending command, start another stats 1154 * dump. Otherwise punt for now. 1155 */ 1156 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1157 /* 1158 * Start another stats dump. 1159 */ 1160 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1161 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1162 FXP_SCB_COMMAND_CU_DUMPRESET); 1163 } else { 1164 /* 1165 * A previous command is still waiting to be accepted. 1166 * Just zero our copy of the stats and wait for the 1167 * next timer event to update them. 1168 */ 1169 /* BIG_ENDIAN: no swap required to store 0 */ 1170 sp->tx_good = 0; 1171 sp->tx_underruns = 0; 1172 sp->tx_total_collisions = 0; 1173 1174 sp->rx_good = 0; 1175 sp->rx_crc_errors = 0; 1176 sp->rx_alignment_errors = 0; 1177 sp->rx_rnr_errors = 0; 1178 sp->rx_overrun_errors = 0; 1179 } 1180 1181 if (sc->sc_flags & FXPF_MII) { 1182 /* Tick the MII clock. */ 1183 mii_tick(&sc->sc_mii); 1184 } 1185 1186 splx(s); 1187 1188 /* 1189 * Schedule another timeout one second from now. 1190 */ 1191 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1192} 1193 1194/* 1195 * Drain the receive queue. 1196 */ 1197void 1198fxp_rxdrain(sc) 1199 struct fxp_softc *sc; 1200{ 1201 bus_dmamap_t rxmap; 1202 struct mbuf *m; 1203 1204 for (;;) { 1205 IF_DEQUEUE(&sc->sc_rxq, m); 1206 if (m == NULL) 1207 break; 1208 rxmap = M_GETCTX(m, bus_dmamap_t); 1209 bus_dmamap_unload(sc->sc_dmat, rxmap); 1210 FXP_RXMAP_PUT(sc, rxmap); 1211 m_freem(m); 1212 } 1213} 1214 1215/* 1216 * Stop the interface. Cancels the statistics updater and resets 1217 * the interface. 1218 */ 1219void 1220fxp_stop(ifp, disable) 1221 struct ifnet *ifp; 1222 int disable; 1223{ 1224 struct fxp_softc *sc = ifp->if_softc; 1225 struct fxp_txsoft *txs; 1226 int i; 1227 1228 /* 1229 * Turn down interface (done early to avoid bad interactions 1230 * between panics, shutdown hooks, and the watchdog timer) 1231 */ 1232 ifp->if_timer = 0; 1233 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1234 1235 /* 1236 * Cancel stats updater. 1237 */ 1238 callout_stop(&sc->sc_callout); 1239 if (sc->sc_flags & FXPF_MII) { 1240 /* Down the MII. */ 1241 mii_down(&sc->sc_mii); 1242 } 1243 1244 /* 1245 * Issue software reset 1246 */ 1247 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1248 DELAY(10); 1249 1250 /* 1251 * Release any xmit buffers. 1252 */ 1253 for (i = 0; i < FXP_NTXCB; i++) { 1254 txs = FXP_DSTX(sc, i); 1255 if (txs->txs_mbuf != NULL) { 1256 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1257 m_freem(txs->txs_mbuf); 1258 txs->txs_mbuf = NULL; 1259 } 1260 } 1261 sc->sc_txpending = 0; 1262 1263 if (disable) { 1264 fxp_rxdrain(sc); 1265 fxp_disable(sc); 1266 } 1267 1268} 1269 1270/* 1271 * Watchdog/transmission transmit timeout handler. Called when a 1272 * transmission is started on the interface, but no interrupt is 1273 * received before the timeout. This usually indicates that the 1274 * card has wedged for some reason. 1275 */ 1276void 1277fxp_watchdog(ifp) 1278 struct ifnet *ifp; 1279{ 1280 struct fxp_softc *sc = ifp->if_softc; 1281 1282 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1283 ifp->if_oerrors++; 1284 1285 (void) fxp_init(ifp); 1286} 1287 1288/* 1289 * Initialize the interface. Must be called at splnet(). 1290 */ 1291int 1292fxp_init(ifp) 1293 struct ifnet *ifp; 1294{ 1295 struct fxp_softc *sc = ifp->if_softc; 1296 struct fxp_cb_config *cbp; 1297 struct fxp_cb_ias *cb_ias; 1298 struct fxp_cb_tx *txd; 1299 bus_dmamap_t rxmap; 1300 int i, prm, save_bf, allm, error = 0; 1301 1302 if ((error = fxp_enable(sc)) != 0) 1303 goto out; 1304 1305 /* 1306 * Cancel any pending I/O 1307 */ 1308 fxp_stop(ifp, 0); 1309 1310 /* 1311 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1312 * flag, and this prevents the MII from detaching resulting in 1313 * a panic. The flags field should perhaps be split in runtime 1314 * flags and more static information. For now, just clear the 1315 * only other flag set. 1316 */ 1317 1318 sc->sc_flags &= ~FXPF_WANTINIT; 1319 1320 /* 1321 * Initialize base of CBL and RFA memory. Loading with zero 1322 * sets it up for regular linear addressing. 1323 */ 1324 fxp_scb_wait(sc); 1325 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1326 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_BASE); 1327 1328 fxp_scb_wait(sc); 1329 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_BASE); 1330 1331 /* 1332 * Initialize the multicast filter. Do this now, since we might 1333 * have to setup the config block differently. 1334 */ 1335 fxp_mc_setup(sc); 1336 1337 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1338 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1339 1340 /* 1341 * In order to support receiving 802.1Q VLAN frames, we have to 1342 * enable "save bad frames", since they are 4 bytes larger than 1343 * the normal Ethernet maximum frame length. 1344 */ 1345 save_bf = (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 1 : 0; 1346 1347 /* 1348 * Initialize base of dump-stats buffer. 1349 */ 1350 fxp_scb_wait(sc); 1351 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1352 sc->sc_cddma + FXP_CDSTATSOFF); 1353 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1354 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_DUMP_ADR); 1355 1356 cbp = &sc->sc_control_data->fcd_configcb; 1357 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1358 1359 /* 1360 * This copy is kind of disgusting, but there are a bunch of must be 1361 * zero and must be one bits in this structure and this is the easiest 1362 * way to initialize them all to proper values. 1363 */ 1364 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1365 1366 /* BIG_ENDIAN: no need to swap to store 0 */ 1367 cbp->cb_status = 0; 1368 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1369 FXP_CB_COMMAND_EL); 1370 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1371 cbp->link_addr = 0xffffffff; /* (no) next command */ 1372 cbp->byte_count = 22; /* (22) bytes to config */ 1373 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1374 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1375 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1376 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1377 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1378 cbp->dma_bce = 0; /* (disable) dma max counters */ 1379 cbp->late_scb = 0; /* (don't) defer SCB update */ 1380 cbp->tno_int = 0; /* (disable) tx not okay interrupt */ 1381 cbp->ci_int = 1; /* interrupt on CU idle */ 1382 cbp->save_bf = save_bf;/* save bad frames */ 1383 cbp->disc_short_rx = !prm; /* discard short packets */ 1384 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1385 cbp->mediatype = !sc->phy_10Mbps_only; /* interface mode */ 1386 cbp->nsai = 1; /* (don't) disable source addr insert */ 1387 cbp->preamble_length = 2; /* (7 byte) preamble */ 1388 cbp->loopback = 0; /* (don't) loopback */ 1389 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1390 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1391 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1392 cbp->promiscuous = prm; /* promiscuous mode */ 1393 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1394 cbp->crscdt = 0; /* (CRS only) */ 1395 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1396 cbp->padding = 1; /* (do) pad short tx packets */ 1397 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1398 cbp->force_fdx = 0; /* (don't) force full duplex */ 1399 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1400 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1401 cbp->mc_all = allm; /* accept all multicasts */ 1402 1403 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1404 1405 /* 1406 * Start the config command/DMA. 1407 */ 1408 fxp_scb_wait(sc); 1409 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1410 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1411 /* ...and wait for it to complete. */ 1412 i = 1000; 1413 do { 1414 FXP_CDCONFIGSYNC(sc, 1415 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1416 DELAY(1); 1417 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1418 if (i == 0) { 1419 printf("%s at line %d: dmasync timeout\n", 1420 sc->sc_dev.dv_xname, __LINE__); 1421 return ETIMEDOUT; 1422 } 1423 1424 /* 1425 * Initialize the station address. 1426 */ 1427 cb_ias = &sc->sc_control_data->fcd_iascb; 1428 /* BIG_ENDIAN: no need to swap to store 0 */ 1429 cb_ias->cb_status = 0; 1430 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1431 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1432 cb_ias->link_addr = 0xffffffff; 1433 memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1434 1435 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1436 1437 /* 1438 * Start the IAS (Individual Address Setup) command/DMA. 1439 */ 1440 fxp_scb_wait(sc); 1441 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1442 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1443 /* ...and wait for it to complete. */ 1444 i = 1000; 1445 do { 1446 FXP_CDIASSYNC(sc, 1447 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1448 DELAY(1); 1449 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1450 if (i == 0) { 1451 printf("%s at line %d: dmasync timeout\n", 1452 sc->sc_dev.dv_xname, __LINE__); 1453 return ETIMEDOUT; 1454 } 1455 1456 /* 1457 * Initialize the transmit descriptor ring. txlast is initialized 1458 * to the end of the list so that it will wrap around to the first 1459 * descriptor when the first packet is transmitted. 1460 */ 1461 for (i = 0; i < FXP_NTXCB; i++) { 1462 txd = FXP_CDTX(sc, i); 1463 memset(txd, 0, sizeof(struct fxp_cb_tx)); 1464 txd->cb_command = 1465 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1466 txd->tbd_array_addr = htole32(FXP_CDTBDADDR(sc, i)); 1467 txd->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1468 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1469 } 1470 sc->sc_txpending = 0; 1471 sc->sc_txdirty = 0; 1472 sc->sc_txlast = FXP_NTXCB - 1; 1473 1474 /* 1475 * Initialize the receive buffer list. 1476 */ 1477 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1478 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1479 rxmap = FXP_RXMAP_GET(sc); 1480 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1481 printf("%s: unable to allocate or map rx " 1482 "buffer %d, error = %d\n", 1483 sc->sc_dev.dv_xname, 1484 sc->sc_rxq.ifq_len, error); 1485 /* 1486 * XXX Should attempt to run with fewer receive 1487 * XXX buffers instead of just failing. 1488 */ 1489 FXP_RXMAP_PUT(sc, rxmap); 1490 fxp_rxdrain(sc); 1491 goto out; 1492 } 1493 } 1494 sc->sc_rxidle = 0; 1495 1496 /* 1497 * Give the transmit ring to the chip. We do this by pointing 1498 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1499 * issuing a start command. It will execute the NOP and then 1500 * suspend, pointing at the first descriptor. 1501 */ 1502 fxp_scb_wait(sc); 1503 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1504 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1505 1506 /* 1507 * Initialize receiver buffer area - RFA. 1508 */ 1509 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1510 fxp_scb_wait(sc); 1511 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1512 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1513 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_START); 1514 1515 if (sc->sc_flags & FXPF_MII) { 1516 /* 1517 * Set current media. 1518 */ 1519 mii_mediachg(&sc->sc_mii); 1520 } 1521 1522 /* 1523 * ...all done! 1524 */ 1525 ifp->if_flags |= IFF_RUNNING; 1526 ifp->if_flags &= ~IFF_OACTIVE; 1527 1528 /* 1529 * Start the one second timer. 1530 */ 1531 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1532 1533 /* 1534 * Attempt to start output on the interface. 1535 */ 1536 fxp_start(ifp); 1537 1538 out: 1539 if (error) { 1540 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1541 ifp->if_timer = 0; 1542 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1543 } 1544 return (error); 1545} 1546 1547/* 1548 * Change media according to request. 1549 */ 1550int 1551fxp_mii_mediachange(ifp) 1552 struct ifnet *ifp; 1553{ 1554 struct fxp_softc *sc = ifp->if_softc; 1555 1556 if (ifp->if_flags & IFF_UP) 1557 mii_mediachg(&sc->sc_mii); 1558 return (0); 1559} 1560 1561/* 1562 * Notify the world which media we're using. 1563 */ 1564void 1565fxp_mii_mediastatus(ifp, ifmr) 1566 struct ifnet *ifp; 1567 struct ifmediareq *ifmr; 1568{ 1569 struct fxp_softc *sc = ifp->if_softc; 1570 1571 if(sc->sc_enabled == 0) { 1572 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1573 ifmr->ifm_status = 0; 1574 return; 1575 } 1576 1577 mii_pollstat(&sc->sc_mii); 1578 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1579 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1580} 1581 1582int 1583fxp_80c24_mediachange(ifp) 1584 struct ifnet *ifp; 1585{ 1586 1587 /* Nothing to do here. */ 1588 return (0); 1589} 1590 1591void 1592fxp_80c24_mediastatus(ifp, ifmr) 1593 struct ifnet *ifp; 1594 struct ifmediareq *ifmr; 1595{ 1596 struct fxp_softc *sc = ifp->if_softc; 1597 1598 /* 1599 * Media is currently-selected media. We cannot determine 1600 * the link status. 1601 */ 1602 ifmr->ifm_status = 0; 1603 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1604} 1605 1606/* 1607 * Add a buffer to the end of the RFA buffer list. 1608 * Return 0 if successful, error code on failure. 1609 * 1610 * The RFA struct is stuck at the beginning of mbuf cluster and the 1611 * data pointer is fixed up to point just past it. 1612 */ 1613int 1614fxp_add_rfabuf(sc, rxmap, unload) 1615 struct fxp_softc *sc; 1616 bus_dmamap_t rxmap; 1617 int unload; 1618{ 1619 struct mbuf *m; 1620 int error; 1621 1622 MGETHDR(m, M_DONTWAIT, MT_DATA); 1623 if (m == NULL) 1624 return (ENOBUFS); 1625 1626 MCLGET(m, M_DONTWAIT); 1627 if ((m->m_flags & M_EXT) == 0) { 1628 m_freem(m); 1629 return (ENOBUFS); 1630 } 1631 1632 if (unload) 1633 bus_dmamap_unload(sc->sc_dmat, rxmap); 1634 1635 M_SETCTX(m, rxmap); 1636 1637 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1638 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1639 if (error) { 1640 printf("%s: can't load rx DMA map %d, error = %d\n", 1641 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 1642 panic("fxp_add_rfabuf"); /* XXX */ 1643 } 1644 1645 FXP_INIT_RFABUF(sc, m); 1646 1647 return (0); 1648} 1649 1650volatile int 1651fxp_mdi_read(self, phy, reg) 1652 struct device *self; 1653 int phy; 1654 int reg; 1655{ 1656 struct fxp_softc *sc = (struct fxp_softc *)self; 1657 int count = 10000; 1658 int value; 1659 1660 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1661 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1662 1663 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1664 && count--) 1665 DELAY(10); 1666 1667 if (count <= 0) 1668 printf("%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 1669 1670 return (value & 0xffff); 1671} 1672 1673void 1674fxp_statchg(self) 1675 struct device *self; 1676{ 1677 1678 /* Nothing to do. */ 1679} 1680 1681void 1682fxp_mdi_write(self, phy, reg, value) 1683 struct device *self; 1684 int phy; 1685 int reg; 1686 int value; 1687{ 1688 struct fxp_softc *sc = (struct fxp_softc *)self; 1689 int count = 10000; 1690 1691 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1692 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1693 (value & 0xffff)); 1694 1695 while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1696 count--) 1697 DELAY(10); 1698 1699 if (count <= 0) 1700 printf("%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 1701} 1702 1703int 1704fxp_ioctl(ifp, cmd, data) 1705 struct ifnet *ifp; 1706 u_long cmd; 1707 caddr_t data; 1708{ 1709 struct fxp_softc *sc = ifp->if_softc; 1710 struct ifreq *ifr = (struct ifreq *)data; 1711 int s, error; 1712 1713 s = splnet(); 1714 1715 switch (cmd) { 1716 case SIOCSIFMEDIA: 1717 case SIOCGIFMEDIA: 1718 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1719 break; 1720 1721 default: 1722 error = ether_ioctl(ifp, cmd, data); 1723 if (error == ENETRESET) { 1724 if (sc->sc_enabled) { 1725 /* 1726 * Multicast list has changed; set the 1727 * hardware filter accordingly. 1728 */ 1729 if (sc->sc_txpending) { 1730 sc->sc_flags |= FXPF_WANTINIT; 1731 error = 0; 1732 } else 1733 error = fxp_init(ifp); 1734 } else 1735 error = 0; 1736 } 1737 break; 1738 } 1739 1740 /* Try to get more packets going. */ 1741 if (sc->sc_enabled) 1742 fxp_start(ifp); 1743 1744 splx(s); 1745 return (error); 1746} 1747 1748/* 1749 * Program the multicast filter. 1750 * 1751 * This function must be called at splnet(). 1752 */ 1753void 1754fxp_mc_setup(sc) 1755 struct fxp_softc *sc; 1756{ 1757 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 1758 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1759 struct ethercom *ec = &sc->sc_ethercom; 1760 struct ether_multi *enm; 1761 struct ether_multistep step; 1762 int count, nmcasts; 1763 1764#ifdef DIAGNOSTIC 1765 if (sc->sc_txpending) 1766 panic("fxp_mc_setup: pending transmissions"); 1767#endif 1768 1769 ifp->if_flags &= ~IFF_ALLMULTI; 1770 1771 /* 1772 * Initialize multicast setup descriptor. 1773 */ 1774 nmcasts = 0; 1775 ETHER_FIRST_MULTI(step, ec, enm); 1776 while (enm != NULL) { 1777 /* 1778 * Check for too many multicast addresses or if we're 1779 * listening to a range. Either way, we simply have 1780 * to accept all multicasts. 1781 */ 1782 if (nmcasts >= MAXMCADDR || 1783 memcmp(enm->enm_addrlo, enm->enm_addrhi, 1784 ETHER_ADDR_LEN) != 0) { 1785 /* 1786 * Callers of this function must do the 1787 * right thing with this. If we're called 1788 * from outside fxp_init(), the caller must 1789 * detect if the state if IFF_ALLMULTI changes. 1790 * If it does, the caller must then call 1791 * fxp_init(), since allmulti is handled by 1792 * the config block. 1793 */ 1794 ifp->if_flags |= IFF_ALLMULTI; 1795 return; 1796 } 1797 memcpy((void *)&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 1798 ETHER_ADDR_LEN); 1799 nmcasts++; 1800 ETHER_NEXT_MULTI(step, enm); 1801 } 1802 1803 /* BIG_ENDIAN: no need to swap to store 0 */ 1804 mcsp->cb_status = 0; 1805 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1806 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 1807 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 1808 1809 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1810 1811 /* 1812 * Wait until the command unit is not active. This should never 1813 * happen since nothing is queued, but make sure anyway. 1814 */ 1815 count = 100; 1816 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 1817 FXP_SCB_CUS_ACTIVE && --count) 1818 DELAY(1); 1819 if (count == 0) { 1820 printf("%s at line %d: command queue timeout\n", 1821 sc->sc_dev.dv_xname, __LINE__); 1822 return; 1823 } 1824 1825 /* 1826 * Start the multicast setup command/DMA. 1827 */ 1828 fxp_scb_wait(sc); 1829 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 1830 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1831 1832 /* ...and wait for it to complete. */ 1833 count = 1000; 1834 do { 1835 FXP_CDMCSSYNC(sc, 1836 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1837 DELAY(1); 1838 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 1839 if (count == 0) { 1840 printf("%s at line %d: dmasync timeout\n", 1841 sc->sc_dev.dv_xname, __LINE__); 1842 return; 1843 } 1844} 1845 1846int 1847fxp_enable(sc) 1848 struct fxp_softc *sc; 1849{ 1850 1851 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 1852 if ((*sc->sc_enable)(sc) != 0) { 1853 printf("%s: device enable failed\n", 1854 sc->sc_dev.dv_xname); 1855 return (EIO); 1856 } 1857 } 1858 1859 sc->sc_enabled = 1; 1860 return (0); 1861} 1862 1863void 1864fxp_disable(sc) 1865 struct fxp_softc *sc; 1866{ 1867 1868 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 1869 (*sc->sc_disable)(sc); 1870 sc->sc_enabled = 0; 1871 } 1872} 1873 1874/* 1875 * fxp_activate: 1876 * 1877 * Handle device activation/deactivation requests. 1878 */ 1879int 1880fxp_activate(self, act) 1881 struct device *self; 1882 enum devact act; 1883{ 1884 struct fxp_softc *sc = (void *) self; 1885 int s, error = 0; 1886 1887 s = splnet(); 1888 switch (act) { 1889 case DVACT_ACTIVATE: 1890 error = EOPNOTSUPP; 1891 break; 1892 1893 case DVACT_DEACTIVATE: 1894 if (sc->sc_flags & FXPF_MII) 1895 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 1896 MII_OFFSET_ANY); 1897 if_deactivate(&sc->sc_ethercom.ec_if); 1898 break; 1899 } 1900 splx(s); 1901 1902 return (error); 1903} 1904 1905/* 1906 * fxp_detach: 1907 * 1908 * Detach an i82557 interface. 1909 */ 1910int 1911fxp_detach(sc) 1912 struct fxp_softc *sc; 1913{ 1914 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1915 int i; 1916 1917 /* Succeed now if there's no work to do. */ 1918 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 1919 return (0); 1920 1921 /* Unhook our tick handler. */ 1922 callout_stop(&sc->sc_callout); 1923 1924 if (sc->sc_flags & FXPF_MII) { 1925 /* Detach all PHYs */ 1926 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1927 } 1928 1929 /* Delete all remaining media. */ 1930 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 1931 1932#if NRND > 0 1933 rnd_detach_source(&sc->rnd_source); 1934#endif 1935 ether_ifdetach(ifp); 1936 if_detach(ifp); 1937 1938 for (i = 0; i < FXP_NRFABUFS; i++) { 1939 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 1940 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 1941 } 1942 1943 for (i = 0; i < FXP_NTXCB; i++) { 1944 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 1945 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 1946 } 1947 1948 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 1949 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 1950 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1951 sizeof(struct fxp_control_data)); 1952 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 1953 1954 shutdownhook_disestablish(sc->sc_sdhook); 1955 powerhook_disestablish(sc->sc_powerhook); 1956 1957 return (0); 1958} 1959