i82557.c revision 1.32
1/* $NetBSD: i82557.c,v 1.32 2000/05/26 19:11:24 tsutsui Exp $ */ 2 3/*- 4 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40/* 41 * Copyright (c) 1995, David Greenman 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice unmodified, this list of conditions, and the following 49 * disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 55 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 57 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 60 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 62 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 63 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 * Id: if_fxp.c,v 1.47 1998/01/08 23:42:29 eivind Exp 67 */ 68 69/* 70 * Device driver for the Intel i82557 fast Ethernet controller, 71 * and its successors, the i82558 and i82559. 72 */ 73 74#include "opt_inet.h" 75#include "opt_ns.h" 76#include "bpfilter.h" 77#include "rnd.h" 78 79#include <sys/param.h> 80#include <sys/systm.h> 81#include <sys/callout.h> 82#include <sys/mbuf.h> 83#include <sys/malloc.h> 84#include <sys/kernel.h> 85#include <sys/socket.h> 86#include <sys/ioctl.h> 87#include <sys/errno.h> 88#include <sys/device.h> 89 90#include <machine/endian.h> 91 92#include <vm/vm.h> /* for PAGE_SIZE */ 93 94#if NRND > 0 95#include <sys/rnd.h> 96#endif 97 98#include <net/if.h> 99#include <net/if_dl.h> 100#include <net/if_media.h> 101#include <net/if_ether.h> 102 103#if NBPFILTER > 0 104#include <net/bpf.h> 105#endif 106 107#ifdef INET 108#include <netinet/in.h> 109#include <netinet/if_inarp.h> 110#endif 111 112#ifdef NS 113#include <netns/ns.h> 114#include <netns/ns_if.h> 115#endif 116 117#include <machine/bus.h> 118#include <machine/intr.h> 119 120#include <dev/mii/miivar.h> 121 122#include <dev/ic/i82557reg.h> 123#include <dev/ic/i82557var.h> 124 125/* 126 * NOTE! On the Alpha, we have an alignment constraint. The 127 * card DMAs the packet immediately following the RFA. However, 128 * the first thing in the packet is a 14-byte Ethernet header. 129 * This means that the packet is misaligned. To compensate, 130 * we actually offset the RFA 2 bytes into the cluster. This 131 * alignes the packet after the Ethernet header at a 32-bit 132 * boundary. HOWEVER! This means that the RFA is misaligned! 133 */ 134#define RFA_ALIGNMENT_FUDGE 2 135 136/* 137 * Template for default configuration parameters. 138 * See struct fxp_cb_config for the bit definitions. 139 */ 140u_int8_t fxp_cb_config_template[] = { 141 0x0, 0x0, /* cb_status */ 142 0x80, 0x2, /* cb_command */ 143 0xff, 0xff, 0xff, 0xff, /* link_addr */ 144 0x16, /* 0 */ 145 0x8, /* 1 */ 146 0x0, /* 2 */ 147 0x0, /* 3 */ 148 0x0, /* 4 */ 149 0x80, /* 5 */ 150 0xb2, /* 6 */ 151 0x3, /* 7 */ 152 0x1, /* 8 */ 153 0x0, /* 9 */ 154 0x26, /* 10 */ 155 0x0, /* 11 */ 156 0x60, /* 12 */ 157 0x0, /* 13 */ 158 0xf2, /* 14 */ 159 0x48, /* 15 */ 160 0x0, /* 16 */ 161 0x40, /* 17 */ 162 0xf3, /* 18 */ 163 0x0, /* 19 */ 164 0x3f, /* 20 */ 165 0x5 /* 21 */ 166}; 167 168void fxp_mii_initmedia __P((struct fxp_softc *)); 169int fxp_mii_mediachange __P((struct ifnet *)); 170void fxp_mii_mediastatus __P((struct ifnet *, struct ifmediareq *)); 171 172void fxp_80c24_initmedia __P((struct fxp_softc *)); 173int fxp_80c24_mediachange __P((struct ifnet *)); 174void fxp_80c24_mediastatus __P((struct ifnet *, struct ifmediareq *)); 175 176inline void fxp_scb_wait __P((struct fxp_softc *)); 177 178void fxp_start __P((struct ifnet *)); 179int fxp_ioctl __P((struct ifnet *, u_long, caddr_t)); 180int fxp_init __P((struct fxp_softc *)); 181void fxp_rxdrain __P((struct fxp_softc *)); 182void fxp_stop __P((struct fxp_softc *, int)); 183void fxp_watchdog __P((struct ifnet *)); 184int fxp_add_rfabuf __P((struct fxp_softc *, bus_dmamap_t, int)); 185int fxp_mdi_read __P((struct device *, int, int)); 186void fxp_statchg __P((struct device *)); 187void fxp_mdi_write __P((struct device *, int, int, int)); 188void fxp_autosize_eeprom __P((struct fxp_softc*)); 189void fxp_read_eeprom __P((struct fxp_softc *, u_int16_t *, int, int)); 190void fxp_get_info __P((struct fxp_softc *, u_int8_t *)); 191void fxp_tick __P((void *)); 192void fxp_mc_setup __P((struct fxp_softc *)); 193 194void fxp_shutdown __P((void *)); 195void fxp_power __P((int, void *)); 196 197int fxp_copy_small = 0; 198 199struct fxp_phytype { 200 int fp_phy; /* type of PHY, -1 for MII at the end. */ 201 void (*fp_init) __P((struct fxp_softc *)); 202} fxp_phytype_table[] = { 203 { FXP_PHY_80C24, fxp_80c24_initmedia }, 204 { -1, fxp_mii_initmedia }, 205}; 206 207/* 208 * Set initial transmit threshold at 64 (512 bytes). This is 209 * increased by 64 (512 bytes) at a time, to maximum of 192 210 * (1536 bytes), if an underrun occurs. 211 */ 212static int tx_threshold = 64; 213 214/* 215 * Wait for the previous command to be accepted (but not necessarily 216 * completed). 217 */ 218inline void 219fxp_scb_wait(sc) 220 struct fxp_softc *sc; 221{ 222 int i = 10000; 223 224 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 225 delay(2); 226 if (i == 0) 227 printf("%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 228} 229 230/* 231 * Finish attaching an i82557 interface. Called by bus-specific front-end. 232 */ 233void 234fxp_attach(sc) 235 struct fxp_softc *sc; 236{ 237 u_int8_t enaddr[6]; 238 struct ifnet *ifp; 239 bus_dma_segment_t seg; 240 int rseg, i, error; 241 struct fxp_phytype *fp; 242 243 callout_init(&sc->sc_callout); 244 245 /* 246 * Allocate the control data structures, and create and load the 247 * DMA map for it. 248 */ 249 if ((error = bus_dmamem_alloc(sc->sc_dmat, 250 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 251 0)) != 0) { 252 printf("%s: unable to allocate control data, error = %d\n", 253 sc->sc_dev.dv_xname, error); 254 goto fail_0; 255 } 256 257 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 258 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 259 BUS_DMA_COHERENT)) != 0) { 260 printf("%s: unable to map control data, error = %d\n", 261 sc->sc_dev.dv_xname, error); 262 goto fail_1; 263 } 264 sc->sc_cdseg = seg; 265 sc->sc_cdnseg = rseg; 266 267 bzero(sc->sc_control_data, sizeof(struct fxp_control_data)); 268 269 if ((error = bus_dmamap_create(sc->sc_dmat, 270 sizeof(struct fxp_control_data), 1, 271 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 272 printf("%s: unable to create control data DMA map, " 273 "error = %d\n", sc->sc_dev.dv_xname, error); 274 goto fail_2; 275 } 276 277 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 278 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 279 0)) != 0) { 280 printf("%s: can't load control data DMA map, error = %d\n", 281 sc->sc_dev.dv_xname, error); 282 goto fail_3; 283 } 284 285 /* 286 * Create the transmit buffer DMA maps. 287 */ 288 for (i = 0; i < FXP_NTXCB; i++) { 289 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 290 FXP_NTXSEG, MCLBYTES, 0, 0, 291 &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 292 printf("%s: unable to create tx DMA map %d, " 293 "error = %d\n", sc->sc_dev.dv_xname, i, error); 294 goto fail_4; 295 } 296 } 297 298 /* 299 * Create the receive buffer DMA maps. 300 */ 301 for (i = 0; i < FXP_NRFABUFS; i++) { 302 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 303 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 304 printf("%s: unable to create rx DMA map %d, " 305 "error = %d\n", sc->sc_dev.dv_xname, i, error); 306 goto fail_5; 307 } 308 } 309 310 /* Initialize MAC address and media structures. */ 311 fxp_get_info(sc, enaddr); 312 313 printf("%s: Ethernet address %s, %s Mb/s\n", sc->sc_dev.dv_xname, 314 ether_sprintf(enaddr), sc->phy_10Mbps_only ? "10" : "10/100"); 315 316 ifp = &sc->sc_ethercom.ec_if; 317 318 /* 319 * Get info about our media interface, and initialize it. Note 320 * the table terminates itself with a phy of -1, indicating 321 * that we're using MII. 322 */ 323 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 324 if (fp->fp_phy == sc->phy_primary_device) 325 break; 326 (*fp->fp_init)(sc); 327 328 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 329 ifp->if_softc = sc; 330 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 331 ifp->if_ioctl = fxp_ioctl; 332 ifp->if_start = fxp_start; 333 ifp->if_watchdog = fxp_watchdog; 334 335 /* 336 * Attach the interface. 337 */ 338 if_attach(ifp); 339 ether_ifattach(ifp, enaddr); 340#if NBPFILTER > 0 341 bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 342 sizeof(struct ether_header)); 343#endif 344#if NRND > 0 345 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 346 RND_TYPE_NET, 0); 347#endif 348 349 /* 350 * Add shutdown hook so that DMA is disabled prior to reboot. Not 351 * doing do could allow DMA to corrupt kernel memory during the 352 * reboot before the driver initializes. 353 */ 354 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 355 if (sc->sc_sdhook == NULL) 356 printf("%s: WARNING: unable to establish shutdown hook\n", 357 sc->sc_dev.dv_xname); 358 /* 359 * Add suspend hook, for similar reasons.. 360 */ 361 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 362 if (sc->sc_powerhook == NULL) 363 printf("%s: WARNING: unable to establish power hook\n", 364 sc->sc_dev.dv_xname); 365 return; 366 367 /* 368 * Free any resources we've allocated during the failed attach 369 * attempt. Do this in reverse order and fall though. 370 */ 371 fail_5: 372 for (i = 0; i < FXP_NRFABUFS; i++) { 373 if (sc->sc_rxmaps[i] != NULL) 374 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 375 } 376 fail_4: 377 for (i = 0; i < FXP_NTXCB; i++) { 378 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 379 bus_dmamap_destroy(sc->sc_dmat, 380 FXP_DSTX(sc, i)->txs_dmamap); 381 } 382 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 383 fail_3: 384 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 385 fail_2: 386 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 387 sizeof(struct fxp_control_data)); 388 fail_1: 389 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 390 fail_0: 391 return; 392} 393 394void 395fxp_mii_initmedia(sc) 396 struct fxp_softc *sc; 397{ 398 399 sc->sc_flags |= FXPF_MII; 400 401 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 402 sc->sc_mii.mii_readreg = fxp_mdi_read; 403 sc->sc_mii.mii_writereg = fxp_mdi_write; 404 sc->sc_mii.mii_statchg = fxp_statchg; 405 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_mii_mediachange, 406 fxp_mii_mediastatus); 407 /* 408 * The i82557 wedges if all of its PHYs are isolated! 409 */ 410 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 411 MII_OFFSET_ANY, MIIF_NOISOLATE); 412 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 413 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 414 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 415 } else 416 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 417} 418 419void 420fxp_80c24_initmedia(sc) 421 struct fxp_softc *sc; 422{ 423 424 /* 425 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 426 * doesn't have a programming interface of any sort. The 427 * media is sensed automatically based on how the link partner 428 * is configured. This is, in essence, manual configuration. 429 */ 430 printf("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 431 sc->sc_dev.dv_xname); 432 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 433 fxp_80c24_mediastatus); 434 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 435 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 436} 437 438/* 439 * Device shutdown routine. Called at system shutdown after sync. The 440 * main purpose of this routine is to shut off receiver DMA so that 441 * kernel memory doesn't get clobbered during warmboot. 442 */ 443void 444fxp_shutdown(arg) 445 void *arg; 446{ 447 struct fxp_softc *sc = arg; 448 449 /* 450 * Since the system's going to halt shortly, don't bother 451 * freeing mbufs. 452 */ 453 fxp_stop(sc, 0); 454} 455/* 456 * Power handler routine. Called when the system is transitioning 457 * into/out of power save modes. As with fxp_shutdown, the main 458 * purpose of this routine is to shut off receiver DMA so it doesn't 459 * clobber kernel memory at the wrong time. 460 */ 461void 462fxp_power(why, arg) 463 int why; 464 void *arg; 465{ 466 struct fxp_softc *sc = arg; 467 struct ifnet *ifp; 468 int s; 469 470 s = splnet(); 471 if (why != PWR_RESUME) 472 fxp_stop(sc, 0); 473 else { 474 ifp = &sc->sc_ethercom.ec_if; 475 if (ifp->if_flags & IFF_UP) 476 fxp_init(sc); 477 } 478 splx(s); 479} 480 481/* 482 * Initialize the interface media. 483 */ 484void 485fxp_get_info(sc, enaddr) 486 struct fxp_softc *sc; 487 u_int8_t *enaddr; 488{ 489 u_int16_t data, myea[3]; 490 491 /* 492 * Reset to a stable state. 493 */ 494 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 495 DELAY(10); 496 497 sc->sc_eeprom_size = 0; 498 fxp_autosize_eeprom(sc); 499 if(sc->sc_eeprom_size == 0) { 500 printf("%s: failed to detect EEPROM size\n", sc->sc_dev.dv_xname); 501 sc->sc_eeprom_size = 6; /* XXX panic here? */ 502 } 503#ifdef DEBUG 504 printf("%s: detected %d word EEPROM\n", 505 sc->sc_dev.dv_xname, 506 1 << sc->sc_eeprom_size); 507#endif 508 509 /* 510 * Get info about the primary PHY 511 */ 512 fxp_read_eeprom(sc, &data, 6, 1); 513 sc->phy_primary_addr = data & 0xff; 514 sc->phy_primary_device = (data >> 8) & 0x3f; 515 sc->phy_10Mbps_only = data >> 15; 516 517 /* 518 * Read MAC address. 519 */ 520 fxp_read_eeprom(sc, myea, 0, 3); 521 enaddr[0] = myea[0] & 0xff; 522 enaddr[1] = myea[0] >> 8; 523 enaddr[2] = myea[1] & 0xff; 524 enaddr[3] = myea[1] >> 8; 525 enaddr[4] = myea[2] & 0xff; 526 enaddr[5] = myea[2] >> 8; 527} 528 529/* 530 * Figure out EEPROM size. 531 * 532 * 559's can have either 64-word or 256-word EEPROMs, the 558 533 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 534 * talks about the existance of 16 to 256 word EEPROMs. 535 * 536 * The only known sizes are 64 and 256, where the 256 version is used 537 * by CardBus cards to store CIS information. 538 * 539 * The address is shifted in msb-to-lsb, and after the last 540 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 541 * after which follows the actual data. We try to detect this zero, by 542 * probing the data-out bit in the EEPROM control register just after 543 * having shifted in a bit. If the bit is zero, we assume we've 544 * shifted enough address bits. The data-out should be tri-state, 545 * before this, which should translate to a logical one. 546 * 547 * Other ways to do this would be to try to read a register with known 548 * contents with a varying number of address bits, but no such 549 * register seem to be available. The high bits of register 10 are 01 550 * on the 558 and 559, but apparently not on the 557. 551 * 552 * The Linux driver computes a checksum on the EEPROM data, but the 553 * value of this checksum is not very well documented. 554 */ 555 556void 557fxp_autosize_eeprom(sc) 558 struct fxp_softc *sc; 559{ 560 u_int16_t reg; 561 int x; 562 563 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 564 /* 565 * Shift in read opcode. 566 */ 567 for (x = 3; x > 0; x--) { 568 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 569 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 570 } else { 571 reg = FXP_EEPROM_EECS; 572 } 573 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 574 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 575 reg | FXP_EEPROM_EESK); 576 DELAY(1); 577 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 578 DELAY(1); 579 } 580 /* 581 * Shift in address, wait for the dummy zero following a correct 582 * address shift. 583 */ 584 for (x = 1; x <= 8; x++) { 585 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 586 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 587 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 588 DELAY(1); 589 if((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 590 FXP_EEPROM_EEDO) == 0) 591 break; 592 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 593 DELAY(1); 594 } 595 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 596 DELAY(1); 597 if(x != 6 && x != 8) { 598#ifdef DEBUG 599 printf("%s: strange EEPROM size (%d)\n", 600 sc->sc_dev.dv_xname, 1 << x); 601#endif 602 } else 603 sc->sc_eeprom_size = x; 604} 605 606/* 607 * Read from the serial EEPROM. Basically, you manually shift in 608 * the read opcode (one bit at a time) and then shift in the address, 609 * and then you shift out the data (all of this one bit at a time). 610 * The word size is 16 bits, so you have to provide the address for 611 * every 16 bits of data. 612 */ 613void 614fxp_read_eeprom(sc, data, offset, words) 615 struct fxp_softc *sc; 616 u_int16_t *data; 617 int offset; 618 int words; 619{ 620 u_int16_t reg; 621 int i, x; 622 623 for (i = 0; i < words; i++) { 624 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 625 /* 626 * Shift in read opcode. 627 */ 628 for (x = 3; x > 0; x--) { 629 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 630 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 631 } else { 632 reg = FXP_EEPROM_EECS; 633 } 634 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 635 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 636 reg | FXP_EEPROM_EESK); 637 DELAY(1); 638 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 639 DELAY(1); 640 } 641 /* 642 * Shift in address. 643 */ 644 for (x = sc->sc_eeprom_size; x > 0; x--) { 645 if ((i + offset) & (1 << (x - 1))) { 646 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 647 } else { 648 reg = FXP_EEPROM_EECS; 649 } 650 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 651 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 652 reg | FXP_EEPROM_EESK); 653 DELAY(1); 654 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 655 DELAY(1); 656 } 657 reg = FXP_EEPROM_EECS; 658 data[i] = 0; 659 /* 660 * Shift out data. 661 */ 662 for (x = 16; x > 0; x--) { 663 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 664 reg | FXP_EEPROM_EESK); 665 DELAY(1); 666 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 667 FXP_EEPROM_EEDO) 668 data[i] |= (1 << (x - 1)); 669 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 670 DELAY(1); 671 } 672 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 673 DELAY(1); 674 } 675} 676 677/* 678 * Start packet transmission on the interface. 679 */ 680void 681fxp_start(ifp) 682 struct ifnet *ifp; 683{ 684 struct fxp_softc *sc = ifp->if_softc; 685 struct mbuf *m0, *m; 686 struct fxp_cb_tx *txd; 687 struct fxp_txsoft *txs; 688 struct fxp_tbdlist *tbd; 689 bus_dmamap_t dmamap; 690 int error, lasttx, nexttx, opending, seg; 691 692 /* 693 * If we want a re-init, bail out now. 694 */ 695 if (sc->sc_flags & FXPF_WANTINIT) { 696 ifp->if_flags |= IFF_OACTIVE; 697 return; 698 } 699 700 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 701 return; 702 703 /* 704 * Remember the previous txpending and the current lasttx. 705 */ 706 opending = sc->sc_txpending; 707 lasttx = sc->sc_txlast; 708 709 /* 710 * Loop through the send queue, setting up transmit descriptors 711 * until we drain the queue, or use up all available transmit 712 * descriptors. 713 */ 714 while (sc->sc_txpending < FXP_NTXCB) { 715 /* 716 * Grab a packet off the queue. 717 */ 718 IF_DEQUEUE(&ifp->if_snd, m0); 719 if (m0 == NULL) 720 break; 721 722 /* 723 * Get the next available transmit descriptor. 724 */ 725 nexttx = FXP_NEXTTX(sc->sc_txlast); 726 txd = FXP_CDTX(sc, nexttx); 727 tbd = FXP_CDTBD(sc, nexttx); 728 txs = FXP_DSTX(sc, nexttx); 729 dmamap = txs->txs_dmamap; 730 731 /* 732 * Load the DMA map. If this fails, the packet either 733 * didn't fit in the allotted number of frags, or we were 734 * short on resources. In this case, we'll copy and try 735 * again. 736 */ 737 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 738 BUS_DMA_NOWAIT) != 0) { 739 MGETHDR(m, M_DONTWAIT, MT_DATA); 740 if (m == NULL) { 741 printf("%s: unable to allocate Tx mbuf\n", 742 sc->sc_dev.dv_xname); 743 IF_PREPEND(&ifp->if_snd, m0); 744 break; 745 } 746 if (m0->m_pkthdr.len > MHLEN) { 747 MCLGET(m, M_DONTWAIT); 748 if ((m->m_flags & M_EXT) == 0) { 749 printf("%s: unable to allocate Tx " 750 "cluster\n", sc->sc_dev.dv_xname); 751 m_freem(m); 752 IF_PREPEND(&ifp->if_snd, m0); 753 break; 754 } 755 } 756 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 757 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 758 m_freem(m0); 759 m0 = m; 760 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 761 m0, BUS_DMA_NOWAIT); 762 if (error) { 763 printf("%s: unable to load Tx buffer, " 764 "error = %d\n", sc->sc_dev.dv_xname, error); 765 IF_PREPEND(&ifp->if_snd, m0); 766 break; 767 } 768 } 769 770 /* Initialize the fraglist. */ 771 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 772 tbd->tbd_d[seg].tb_addr = 773 htole32(dmamap->dm_segs[seg].ds_addr); 774 tbd->tbd_d[seg].tb_size = 775 htole32(dmamap->dm_segs[seg].ds_len); 776 } 777 778 FXP_CDTBDSYNC(sc, nexttx, BUS_DMASYNC_PREWRITE); 779 780 /* Sync the DMA map. */ 781 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 782 BUS_DMASYNC_PREWRITE); 783 784 /* 785 * Store a pointer to the packet so we can free it later. 786 */ 787 txs->txs_mbuf = m0; 788 789 /* 790 * Initialize the transmit descriptor. 791 */ 792 /* BIG_ENDIAN: no need to swap to store 0 */ 793 txd->cb_status = 0; 794 txd->cb_command = 795 htole16(FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF); 796 txd->tx_threshold = tx_threshold; 797 txd->tbd_number = dmamap->dm_nsegs; 798 799 FXP_CDTXSYNC(sc, nexttx, 800 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 801 802 /* Advance the tx pointer. */ 803 sc->sc_txpending++; 804 sc->sc_txlast = nexttx; 805 806#if NBPFILTER > 0 807 /* 808 * Pass packet to bpf if there is a listener. 809 */ 810 if (ifp->if_bpf) 811 bpf_mtap(ifp->if_bpf, m0); 812#endif 813 } 814 815 if (sc->sc_txpending == FXP_NTXCB) { 816 /* No more slots; notify upper layer. */ 817 ifp->if_flags |= IFF_OACTIVE; 818 } 819 820 if (sc->sc_txpending != opending) { 821 /* 822 * We enqueued packets. If the transmitter was idle, 823 * reset the txdirty pointer. 824 */ 825 if (opending == 0) 826 sc->sc_txdirty = FXP_NEXTTX(lasttx); 827 828 /* 829 * Cause the chip to interrupt and suspend command 830 * processing once the last packet we've enqueued 831 * has been transmitted. 832 */ 833 FXP_CDTX(sc, sc->sc_txlast)->cb_command |= 834 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 835 FXP_CDTXSYNC(sc, sc->sc_txlast, 836 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 837 838 /* 839 * The entire packet chain is set up. Clear the suspend bit 840 * on the command prior to the first packet we set up. 841 */ 842 FXP_CDTXSYNC(sc, lasttx, 843 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 844 FXP_CDTX(sc, lasttx)->cb_command &= htole16(~FXP_CB_COMMAND_S); 845 FXP_CDTXSYNC(sc, lasttx, 846 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 847 848 /* 849 * Issue a Resume command in case the chip was suspended. 850 */ 851 fxp_scb_wait(sc); 852 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME); 853 854 /* Set a watchdog timer in case the chip flakes out. */ 855 ifp->if_timer = 5; 856 } 857} 858 859/* 860 * Process interface interrupts. 861 */ 862int 863fxp_intr(arg) 864 void *arg; 865{ 866 struct fxp_softc *sc = arg; 867 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 868 struct fxp_cb_tx *txd; 869 struct fxp_txsoft *txs; 870 struct mbuf *m, *m0; 871 bus_dmamap_t rxmap; 872 struct fxp_rfa *rfa; 873 struct ether_header *eh; 874 int i, claimed = 0; 875 u_int16_t len, rxstat, txstat; 876 u_int8_t statack; 877 878 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 879 return (0); 880 /* 881 * If the interface isn't running, don't try to 882 * service the interrupt.. just ack it and bail. 883 */ 884 if ((ifp->if_flags & IFF_RUNNING) == 0) { 885 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 886 if (statack) { 887 claimed = 1; 888 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 889 } 890 return (claimed); 891 } 892 893 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 894 claimed = 1; 895 896 /* 897 * First ACK all the interrupts in this pass. 898 */ 899 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 900 901 /* 902 * Process receiver interrupts. If a no-resource (RNR) 903 * condition exists, get whatever packets we can and 904 * re-start the receiver. 905 */ 906 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 907 rcvloop: 908 m = sc->sc_rxq.ifq_head; 909 rfa = FXP_MTORFA(m); 910 rxmap = M_GETCTX(m, bus_dmamap_t); 911 912 FXP_RFASYNC(sc, m, 913 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 914 915 rxstat = le16toh(rfa->rfa_status); 916 917 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 918 /* 919 * We have processed all of the 920 * receive buffers. 921 */ 922 goto do_transmit; 923 } 924 925 IF_DEQUEUE(&sc->sc_rxq, m); 926 927 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 928 929 len = le16toh(rfa->actual_size) & 930 (m->m_ext.ext_size - 1); 931 932 if (len < sizeof(struct ether_header)) { 933 /* 934 * Runt packet; drop it now. 935 */ 936 FXP_INIT_RFABUF(sc, m); 937 goto rcvloop; 938 } 939 940 /* 941 * If the packet is small enough to fit in a 942 * single header mbuf, allocate one and copy 943 * the data into it. This greatly reduces 944 * memory consumption when we receive lots 945 * of small packets. 946 * 947 * Otherwise, we add a new buffer to the receive 948 * chain. If this fails, we drop the packet and 949 * recycle the old buffer. 950 */ 951 if (fxp_copy_small != 0 && len <= MHLEN) { 952 MGETHDR(m0, M_DONTWAIT, MT_DATA); 953 if (m == NULL) 954 goto dropit; 955 memcpy(mtod(m0, caddr_t), 956 mtod(m, caddr_t), len); 957 FXP_INIT_RFABUF(sc, m); 958 m = m0; 959 } else { 960 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 961 dropit: 962 ifp->if_ierrors++; 963 FXP_INIT_RFABUF(sc, m); 964 goto rcvloop; 965 } 966 } 967 968 m->m_pkthdr.rcvif = ifp; 969 m->m_pkthdr.len = m->m_len = len; 970 eh = mtod(m, struct ether_header *); 971 972#if NBPFILTER > 0 973 /* 974 * Pass this up to any BPF listeners, but only 975 * pass it up the stack it its for us. 976 */ 977 if (ifp->if_bpf) { 978 bpf_mtap(ifp->if_bpf, m); 979 980 if ((ifp->if_flags & IFF_PROMISC) != 0 && 981 (rxstat & FXP_RFA_STATUS_IAMATCH) != 0 && 982 (eh->ether_dhost[0] & 1) == 0) { 983 m_freem(m); 984 goto rcvloop; 985 } 986 } 987#endif /* NBPFILTER > 0 */ 988 989 /* Pass it on. */ 990 (*ifp->if_input)(ifp, m); 991 goto rcvloop; 992 } 993 994 do_transmit: 995 if (statack & FXP_SCB_STATACK_RNR) { 996 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 997 fxp_scb_wait(sc); 998 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 999 rxmap->dm_segs[0].ds_addr + 1000 RFA_ALIGNMENT_FUDGE); 1001 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1002 FXP_SCB_COMMAND_RU_START); 1003 } 1004 1005 /* 1006 * Free any finished transmit mbuf chains. 1007 */ 1008 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1009 ifp->if_flags &= ~IFF_OACTIVE; 1010 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1011 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1012 txd = FXP_CDTX(sc, i); 1013 txs = FXP_DSTX(sc, i); 1014 1015 FXP_CDTXSYNC(sc, i, 1016 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1017 1018 txstat = le16toh(txd->cb_status); 1019 1020 if ((txstat & FXP_CB_STATUS_C) == 0) 1021 break; 1022 1023 FXP_CDTBDSYNC(sc, i, BUS_DMASYNC_POSTWRITE); 1024 1025 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1026 0, txs->txs_dmamap->dm_mapsize, 1027 BUS_DMASYNC_POSTWRITE); 1028 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1029 m_freem(txs->txs_mbuf); 1030 txs->txs_mbuf = NULL; 1031 } 1032 1033 /* Update the dirty transmit buffer pointer. */ 1034 sc->sc_txdirty = i; 1035 1036 /* 1037 * Cancel the watchdog timer if there are no pending 1038 * transmissions. 1039 */ 1040 if (sc->sc_txpending == 0) { 1041 ifp->if_timer = 0; 1042 1043 /* 1044 * If we want a re-init, do that now. 1045 */ 1046 if (sc->sc_flags & FXPF_WANTINIT) 1047 (void) fxp_init(sc); 1048 } 1049 1050 /* 1051 * Try to get more packets going. 1052 */ 1053 fxp_start(ifp); 1054 } 1055 } 1056 1057#if NRND > 0 1058 if (claimed) 1059 rnd_add_uint32(&sc->rnd_source, statack); 1060#endif 1061 return (claimed); 1062} 1063 1064/* 1065 * Update packet in/out/collision statistics. The i82557 doesn't 1066 * allow you to access these counters without doing a fairly 1067 * expensive DMA to get _all_ of the statistics it maintains, so 1068 * we do this operation here only once per second. The statistics 1069 * counters in the kernel are updated from the previous dump-stats 1070 * DMA and then a new dump-stats DMA is started. The on-chip 1071 * counters are zeroed when the DMA completes. If we can't start 1072 * the DMA immediately, we don't wait - we just prepare to read 1073 * them again next time. 1074 */ 1075void 1076fxp_tick(arg) 1077 void *arg; 1078{ 1079 struct fxp_softc *sc = arg; 1080 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1081 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1082 int s; 1083 1084 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1085 return; 1086 1087 s = splnet(); 1088 1089 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1090 1091 ifp->if_opackets += le32toh(sp->tx_good); 1092 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1093 if (sp->rx_good) { 1094 ifp->if_ipackets += le32toh(sp->rx_good); 1095 sc->sc_rxidle = 0; 1096 } else { 1097 sc->sc_rxidle++; 1098 } 1099 ifp->if_ierrors += 1100 le32toh(sp->rx_crc_errors) + 1101 le32toh(sp->rx_alignment_errors) + 1102 le32toh(sp->rx_rnr_errors) + 1103 le32toh(sp->rx_overrun_errors); 1104 /* 1105 * If any transmit underruns occured, bump up the transmit 1106 * threshold by another 512 bytes (64 * 8). 1107 */ 1108 if (sp->tx_underruns) { 1109 ifp->if_oerrors += le32toh(sp->tx_underruns); 1110 if (tx_threshold < 192) 1111 tx_threshold += 64; 1112 } 1113 1114 /* 1115 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1116 * then assume the receiver has locked up and attempt to clear 1117 * the condition by reprogramming the multicast filter (actually, 1118 * resetting the interface). This is a work-around for a bug in 1119 * the 82557 where the receiver locks up if it gets certain types 1120 * of garbage in the syncronization bits prior to the packet header. 1121 * This bug is supposed to only occur in 10Mbps mode, but has been 1122 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1123 * speed transition). 1124 */ 1125 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1126 (void) fxp_init(sc); 1127 splx(s); 1128 return; 1129 } 1130 /* 1131 * If there is no pending command, start another stats 1132 * dump. Otherwise punt for now. 1133 */ 1134 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1135 /* 1136 * Start another stats dump. 1137 */ 1138 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1139 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1140 FXP_SCB_COMMAND_CU_DUMPRESET); 1141 } else { 1142 /* 1143 * A previous command is still waiting to be accepted. 1144 * Just zero our copy of the stats and wait for the 1145 * next timer event to update them. 1146 */ 1147 /* BIG_ENDIAN: no swap required to store 0 */ 1148 sp->tx_good = 0; 1149 sp->tx_underruns = 0; 1150 sp->tx_total_collisions = 0; 1151 1152 sp->rx_good = 0; 1153 sp->rx_crc_errors = 0; 1154 sp->rx_alignment_errors = 0; 1155 sp->rx_rnr_errors = 0; 1156 sp->rx_overrun_errors = 0; 1157 } 1158 1159 if (sc->sc_flags & FXPF_MII) { 1160 /* Tick the MII clock. */ 1161 mii_tick(&sc->sc_mii); 1162 } 1163 1164 splx(s); 1165 1166 /* 1167 * Schedule another timeout one second from now. 1168 */ 1169 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1170} 1171 1172/* 1173 * Drain the receive queue. 1174 */ 1175void 1176fxp_rxdrain(sc) 1177 struct fxp_softc *sc; 1178{ 1179 bus_dmamap_t rxmap; 1180 struct mbuf *m; 1181 1182 for (;;) { 1183 IF_DEQUEUE(&sc->sc_rxq, m); 1184 if (m == NULL) 1185 break; 1186 rxmap = M_GETCTX(m, bus_dmamap_t); 1187 bus_dmamap_unload(sc->sc_dmat, rxmap); 1188 FXP_RXMAP_PUT(sc, rxmap); 1189 m_freem(m); 1190 } 1191} 1192 1193/* 1194 * Stop the interface. Cancels the statistics updater and resets 1195 * the interface. 1196 */ 1197void 1198fxp_stop(sc, drain) 1199 struct fxp_softc *sc; 1200 int drain; 1201{ 1202 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1203 struct fxp_txsoft *txs; 1204 int i; 1205 1206 /* 1207 * Turn down interface (done early to avoid bad interactions 1208 * between panics, shutdown hooks, and the watchdog timer) 1209 */ 1210 ifp->if_timer = 0; 1211 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1212 1213 /* 1214 * Cancel stats updater. 1215 */ 1216 callout_stop(&sc->sc_callout); 1217 if (sc->sc_flags & FXPF_MII) { 1218 /* Down the MII. */ 1219 mii_down(&sc->sc_mii); 1220 } 1221 1222 /* 1223 * Issue software reset 1224 */ 1225 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1226 DELAY(10); 1227 1228 /* 1229 * Release any xmit buffers. 1230 */ 1231 for (i = 0; i < FXP_NTXCB; i++) { 1232 txs = FXP_DSTX(sc, i); 1233 if (txs->txs_mbuf != NULL) { 1234 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1235 m_freem(txs->txs_mbuf); 1236 txs->txs_mbuf = NULL; 1237 } 1238 } 1239 sc->sc_txpending = 0; 1240 1241 if (drain) { 1242 /* 1243 * Release the receive buffers. 1244 */ 1245 fxp_rxdrain(sc); 1246 } 1247 1248} 1249 1250/* 1251 * Watchdog/transmission transmit timeout handler. Called when a 1252 * transmission is started on the interface, but no interrupt is 1253 * received before the timeout. This usually indicates that the 1254 * card has wedged for some reason. 1255 */ 1256void 1257fxp_watchdog(ifp) 1258 struct ifnet *ifp; 1259{ 1260 struct fxp_softc *sc = ifp->if_softc; 1261 1262 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1263 ifp->if_oerrors++; 1264 1265 (void) fxp_init(sc); 1266} 1267 1268/* 1269 * Initialize the interface. Must be called at splnet(). 1270 */ 1271int 1272fxp_init(sc) 1273 struct fxp_softc *sc; 1274{ 1275 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1276 struct fxp_cb_config *cbp; 1277 struct fxp_cb_ias *cb_ias; 1278 struct fxp_cb_tx *txd; 1279 bus_dmamap_t rxmap; 1280 int i, prm, allm, error = 0; 1281 1282 /* 1283 * Cancel any pending I/O 1284 */ 1285 fxp_stop(sc, 0); 1286 1287 /* 1288 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1289 * flag, and this prevents the MII from detaching resulting in 1290 * a panic. The flags field should perhaps be split in runtime 1291 * flags and more static information. For now, just clear the 1292 * only other flag set. 1293 */ 1294 1295 sc->sc_flags &= ~FXPF_WANTINIT; 1296 1297 /* 1298 * Initialize base of CBL and RFA memory. Loading with zero 1299 * sets it up for regular linear addressing. 1300 */ 1301 fxp_scb_wait(sc); 1302 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1303 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_BASE); 1304 1305 fxp_scb_wait(sc); 1306 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_BASE); 1307 1308 /* 1309 * Initialize the multicast filter. Do this now, since we might 1310 * have to setup the config block differently. 1311 */ 1312 fxp_mc_setup(sc); 1313 1314 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1315 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1316 1317 /* 1318 * Initialize base of dump-stats buffer. 1319 */ 1320 fxp_scb_wait(sc); 1321 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1322 sc->sc_cddma + FXP_CDSTATSOFF); 1323 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1324 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_DUMP_ADR); 1325 1326 cbp = &sc->sc_control_data->fcd_configcb; 1327 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1328 1329 /* 1330 * This copy is kind of disgusting, but there are a bunch of must be 1331 * zero and must be one bits in this structure and this is the easiest 1332 * way to initialize them all to proper values. 1333 */ 1334 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1335 1336 /* BIG_ENDIAN: no need to swap to store 0 */ 1337 cbp->cb_status = 0; 1338 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1339 FXP_CB_COMMAND_EL); 1340 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1341 cbp->link_addr = 0xffffffff; /* (no) next command */ 1342 cbp->byte_count = 22; /* (22) bytes to config */ 1343 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1344 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1345 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1346 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1347 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1348 cbp->dma_bce = 0; /* (disable) dma max counters */ 1349 cbp->late_scb = 0; /* (don't) defer SCB update */ 1350 cbp->tno_int = 0; /* (disable) tx not okay interrupt */ 1351 cbp->ci_int = 1; /* interrupt on CU idle */ 1352 cbp->save_bf = prm; /* save bad frames */ 1353 cbp->disc_short_rx = !prm; /* discard short packets */ 1354 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1355 cbp->mediatype = !sc->phy_10Mbps_only; /* interface mode */ 1356 cbp->nsai = 1; /* (don't) disable source addr insert */ 1357 cbp->preamble_length = 2; /* (7 byte) preamble */ 1358 cbp->loopback = 0; /* (don't) loopback */ 1359 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1360 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1361 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1362 cbp->promiscuous = prm; /* promiscuous mode */ 1363 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1364 cbp->crscdt = 0; /* (CRS only) */ 1365 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1366 cbp->padding = 1; /* (do) pad short tx packets */ 1367 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1368 cbp->force_fdx = 0; /* (don't) force full duplex */ 1369 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1370 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1371 cbp->mc_all = allm; /* accept all multicasts */ 1372 1373 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1374 1375 /* 1376 * Start the config command/DMA. 1377 */ 1378 fxp_scb_wait(sc); 1379 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1380 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1381 /* ...and wait for it to complete. */ 1382 i = 1000; 1383 do { 1384 FXP_CDCONFIGSYNC(sc, 1385 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1386 DELAY(1); 1387 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1388 if (i == 0) { 1389 printf("%s at line %d: dmasync timeout\n", 1390 sc->sc_dev.dv_xname, __LINE__); 1391 return ETIMEDOUT; 1392 } 1393 1394 /* 1395 * Initialize the station address. 1396 */ 1397 cb_ias = &sc->sc_control_data->fcd_iascb; 1398 /* BIG_ENDIAN: no need to swap to store 0 */ 1399 cb_ias->cb_status = 0; 1400 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1401 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1402 cb_ias->link_addr = 0xffffffff; 1403 memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1404 1405 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1406 1407 /* 1408 * Start the IAS (Individual Address Setup) command/DMA. 1409 */ 1410 fxp_scb_wait(sc); 1411 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1412 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1413 /* ...and wait for it to complete. */ 1414 i = 1000; 1415 do { 1416 FXP_CDIASSYNC(sc, 1417 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1418 DELAY(1); 1419 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1420 if (i == 0) { 1421 printf("%s at line %d: dmasync timeout\n", 1422 sc->sc_dev.dv_xname, __LINE__); 1423 return ETIMEDOUT; 1424 } 1425 1426 /* 1427 * Initialize the transmit descriptor ring. txlast is initialized 1428 * to the end of the list so that it will wrap around to the first 1429 * descriptor when the first packet is transmitted. 1430 */ 1431 for (i = 0; i < FXP_NTXCB; i++) { 1432 txd = FXP_CDTX(sc, i); 1433 memset(txd, 0, sizeof(struct fxp_cb_tx)); 1434 txd->cb_command = 1435 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1436 txd->tbd_array_addr = htole32(FXP_CDTBDADDR(sc, i)); 1437 txd->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1438 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1439 } 1440 sc->sc_txpending = 0; 1441 sc->sc_txdirty = 0; 1442 sc->sc_txlast = FXP_NTXCB - 1; 1443 1444 /* 1445 * Initialize the receive buffer list. 1446 */ 1447 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1448 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1449 rxmap = FXP_RXMAP_GET(sc); 1450 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1451 printf("%s: unable to allocate or map rx " 1452 "buffer %d, error = %d\n", 1453 sc->sc_dev.dv_xname, 1454 sc->sc_rxq.ifq_len, error); 1455 /* 1456 * XXX Should attempt to run with fewer receive 1457 * XXX buffers instead of just failing. 1458 */ 1459 FXP_RXMAP_PUT(sc, rxmap); 1460 fxp_rxdrain(sc); 1461 goto out; 1462 } 1463 } 1464 sc->sc_rxidle = 0; 1465 1466 /* 1467 * Give the transmit ring to the chip. We do this by pointing 1468 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1469 * issuing a start command. It will execute the NOP and then 1470 * suspend, pointing at the first descriptor. 1471 */ 1472 fxp_scb_wait(sc); 1473 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1474 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1475 1476 /* 1477 * Initialize receiver buffer area - RFA. 1478 */ 1479 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1480 fxp_scb_wait(sc); 1481 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1482 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1483 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_START); 1484 1485 if (sc->sc_flags & FXPF_MII) { 1486 /* 1487 * Set current media. 1488 */ 1489 mii_mediachg(&sc->sc_mii); 1490 } 1491 1492 /* 1493 * ...all done! 1494 */ 1495 ifp->if_flags |= IFF_RUNNING; 1496 ifp->if_flags &= ~IFF_OACTIVE; 1497 1498 /* 1499 * Start the one second timer. 1500 */ 1501 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1502 1503 /* 1504 * Attempt to start output on the interface. 1505 */ 1506 fxp_start(ifp); 1507 1508 out: 1509 if (error) 1510 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1511 return (error); 1512} 1513 1514/* 1515 * Change media according to request. 1516 */ 1517int 1518fxp_mii_mediachange(ifp) 1519 struct ifnet *ifp; 1520{ 1521 struct fxp_softc *sc = ifp->if_softc; 1522 1523 if (ifp->if_flags & IFF_UP) 1524 mii_mediachg(&sc->sc_mii); 1525 return (0); 1526} 1527 1528/* 1529 * Notify the world which media we're using. 1530 */ 1531void 1532fxp_mii_mediastatus(ifp, ifmr) 1533 struct ifnet *ifp; 1534 struct ifmediareq *ifmr; 1535{ 1536 struct fxp_softc *sc = ifp->if_softc; 1537 1538 if(sc->sc_enabled == 0) { 1539 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1540 ifmr->ifm_status = 0; 1541 return; 1542 } 1543 1544 mii_pollstat(&sc->sc_mii); 1545 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1546 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1547} 1548 1549int 1550fxp_80c24_mediachange(ifp) 1551 struct ifnet *ifp; 1552{ 1553 1554 /* Nothing to do here. */ 1555 return (0); 1556} 1557 1558void 1559fxp_80c24_mediastatus(ifp, ifmr) 1560 struct ifnet *ifp; 1561 struct ifmediareq *ifmr; 1562{ 1563 struct fxp_softc *sc = ifp->if_softc; 1564 1565 /* 1566 * Media is currently-selected media. We cannot determine 1567 * the link status. 1568 */ 1569 ifmr->ifm_status = 0; 1570 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1571} 1572 1573/* 1574 * Add a buffer to the end of the RFA buffer list. 1575 * Return 0 if successful, error code on failure. 1576 * 1577 * The RFA struct is stuck at the beginning of mbuf cluster and the 1578 * data pointer is fixed up to point just past it. 1579 */ 1580int 1581fxp_add_rfabuf(sc, rxmap, unload) 1582 struct fxp_softc *sc; 1583 bus_dmamap_t rxmap; 1584 int unload; 1585{ 1586 struct mbuf *m; 1587 int error; 1588 1589 MGETHDR(m, M_DONTWAIT, MT_DATA); 1590 if (m == NULL) 1591 return (ENOBUFS); 1592 1593 MCLGET(m, M_DONTWAIT); 1594 if ((m->m_flags & M_EXT) == 0) { 1595 m_freem(m); 1596 return (ENOBUFS); 1597 } 1598 1599 if (unload) 1600 bus_dmamap_unload(sc->sc_dmat, rxmap); 1601 1602 M_SETCTX(m, rxmap); 1603 1604 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1605 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1606 if (error) { 1607 printf("%s: can't load rx DMA map %d, error = %d\n", 1608 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 1609 panic("fxp_add_rfabuf"); /* XXX */ 1610 } 1611 1612 FXP_INIT_RFABUF(sc, m); 1613 1614 return (0); 1615} 1616 1617volatile int 1618fxp_mdi_read(self, phy, reg) 1619 struct device *self; 1620 int phy; 1621 int reg; 1622{ 1623 struct fxp_softc *sc = (struct fxp_softc *)self; 1624 int count = 10000; 1625 int value; 1626 1627 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1628 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1629 1630 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1631 && count--) 1632 DELAY(10); 1633 1634 if (count <= 0) 1635 printf("%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 1636 1637 return (value & 0xffff); 1638} 1639 1640void 1641fxp_statchg(self) 1642 struct device *self; 1643{ 1644 1645 /* Nothing to do. */ 1646} 1647 1648void 1649fxp_mdi_write(self, phy, reg, value) 1650 struct device *self; 1651 int phy; 1652 int reg; 1653 int value; 1654{ 1655 struct fxp_softc *sc = (struct fxp_softc *)self; 1656 int count = 10000; 1657 1658 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1659 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1660 (value & 0xffff)); 1661 1662 while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1663 count--) 1664 DELAY(10); 1665 1666 if (count <= 0) 1667 printf("%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 1668} 1669 1670int 1671fxp_ioctl(ifp, command, data) 1672 struct ifnet *ifp; 1673 u_long command; 1674 caddr_t data; 1675{ 1676 struct fxp_softc *sc = ifp->if_softc; 1677 struct ifreq *ifr = (struct ifreq *)data; 1678 struct ifaddr *ifa = (struct ifaddr *)data; 1679 int s, error = 0; 1680 1681 s = splnet(); 1682 1683 switch (command) { 1684 case SIOCSIFADDR: 1685 if ((error = fxp_enable(sc)) != 0) 1686 break; 1687 ifp->if_flags |= IFF_UP; 1688 1689 switch (ifa->ifa_addr->sa_family) { 1690#ifdef INET 1691 case AF_INET: 1692 if ((error = fxp_init(sc)) != 0) 1693 break; 1694 arp_ifinit(ifp, ifa); 1695 break; 1696#endif /* INET */ 1697#ifdef NS 1698 case AF_NS: 1699 { 1700 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1701 1702 if (ns_nullhost(*ina)) 1703 ina->x_host = *(union ns_host *) 1704 LLADDR(ifp->if_sadl); 1705 else 1706 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1707 ifp->if_addrlen); 1708 /* Set new address. */ 1709 error = fxp_init(sc); 1710 break; 1711 } 1712#endif /* NS */ 1713 default: 1714 error = fxp_init(sc); 1715 break; 1716 } 1717 break; 1718 1719 case SIOCSIFMTU: 1720 if (ifr->ifr_mtu > ETHERMTU) 1721 error = EINVAL; 1722 else 1723 ifp->if_mtu = ifr->ifr_mtu; 1724 break; 1725 1726 case SIOCSIFFLAGS: 1727 if ((ifp->if_flags & IFF_UP) == 0 && 1728 (ifp->if_flags & IFF_RUNNING) != 0) { 1729 /* 1730 * If interface is marked down and it is running, then 1731 * stop it. 1732 */ 1733 fxp_stop(sc, 1); 1734 fxp_disable(sc); 1735 } else if ((ifp->if_flags & IFF_UP) != 0 && 1736 (ifp->if_flags & IFF_RUNNING) == 0) { 1737 /* 1738 * If interface is marked up and it is stopped, then 1739 * start it. 1740 */ 1741 if((error = fxp_enable(sc)) != 0) 1742 break; 1743 error = fxp_init(sc); 1744 } else if ((ifp->if_flags & IFF_UP) != 0) { 1745 /* 1746 * Reset the interface to pick up change in any other 1747 * flags that affect the hardware state. 1748 */ 1749 if((error = fxp_enable(sc)) != 0) 1750 break; 1751 error = fxp_init(sc); 1752 } 1753 break; 1754 1755 case SIOCADDMULTI: 1756 case SIOCDELMULTI: 1757 if(sc->sc_enabled == 0) { 1758 error = EIO; 1759 break; 1760 } 1761 error = (command == SIOCADDMULTI) ? 1762 ether_addmulti(ifr, &sc->sc_ethercom) : 1763 ether_delmulti(ifr, &sc->sc_ethercom); 1764 1765 if (error == ENETRESET) { 1766 /* 1767 * Multicast list has changed; set the hardware 1768 * filter accordingly. 1769 */ 1770 if (sc->sc_txpending) { 1771 sc->sc_flags |= FXPF_WANTINIT; 1772 error = 0; 1773 } else 1774 error = fxp_init(sc); 1775 } 1776 break; 1777 1778 case SIOCSIFMEDIA: 1779 case SIOCGIFMEDIA: 1780 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1781 break; 1782 1783 default: 1784 error = EINVAL; 1785 break; 1786 } 1787 1788 splx(s); 1789 return (error); 1790} 1791 1792/* 1793 * Program the multicast filter. 1794 * 1795 * This function must be called at splnet(). 1796 */ 1797void 1798fxp_mc_setup(sc) 1799 struct fxp_softc *sc; 1800{ 1801 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 1802 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1803 struct ethercom *ec = &sc->sc_ethercom; 1804 struct ether_multi *enm; 1805 struct ether_multistep step; 1806 int count, nmcasts; 1807 1808#ifdef DIAGNOSTIC 1809 if (sc->sc_txpending) 1810 panic("fxp_mc_setup: pending transmissions"); 1811#endif 1812 1813 ifp->if_flags &= ~IFF_ALLMULTI; 1814 1815 /* 1816 * Initialize multicast setup descriptor. 1817 */ 1818 nmcasts = 0; 1819 ETHER_FIRST_MULTI(step, ec, enm); 1820 while (enm != NULL) { 1821 /* 1822 * Check for too many multicast addresses or if we're 1823 * listening to a range. Either way, we simply have 1824 * to accept all multicasts. 1825 */ 1826 if (nmcasts >= MAXMCADDR || 1827 memcmp(enm->enm_addrlo, enm->enm_addrhi, 1828 ETHER_ADDR_LEN) != 0) { 1829 /* 1830 * Callers of this function must do the 1831 * right thing with this. If we're called 1832 * from outside fxp_init(), the caller must 1833 * detect if the state if IFF_ALLMULTI changes. 1834 * If it does, the caller must then call 1835 * fxp_init(), since allmulti is handled by 1836 * the config block. 1837 */ 1838 ifp->if_flags |= IFF_ALLMULTI; 1839 return; 1840 } 1841 memcpy((void *)&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 1842 ETHER_ADDR_LEN); 1843 nmcasts++; 1844 ETHER_NEXT_MULTI(step, enm); 1845 } 1846 1847 /* BIG_ENDIAN: no need to swap to store 0 */ 1848 mcsp->cb_status = 0; 1849 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1850 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 1851 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 1852 1853 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1854 1855 /* 1856 * Wait until the command unit is not active. This should never 1857 * happen since nothing is queued, but make sure anyway. 1858 */ 1859 count = 100; 1860 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 1861 FXP_SCB_CUS_ACTIVE && --count) 1862 DELAY(1); 1863 if (count == 0) { 1864 printf("%s at line %d: command queue timeout\n", 1865 sc->sc_dev.dv_xname, __LINE__); 1866 return; 1867 } 1868 1869 /* 1870 * Start the multicast setup command/DMA. 1871 */ 1872 fxp_scb_wait(sc); 1873 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 1874 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1875 1876 /* ...and wait for it to complete. */ 1877 count = 1000; 1878 do { 1879 FXP_CDMCSSYNC(sc, 1880 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1881 DELAY(1); 1882 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 1883 if (count == 0) { 1884 printf("%s at line %d: dmasync timeout\n", 1885 sc->sc_dev.dv_xname, __LINE__); 1886 return; 1887 } 1888} 1889 1890int 1891fxp_enable(sc) 1892 struct fxp_softc *sc; 1893{ 1894 1895 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 1896 if ((*sc->sc_enable)(sc) != 0) { 1897 printf("%s: device enable failed\n", 1898 sc->sc_dev.dv_xname); 1899 return (EIO); 1900 } 1901 } 1902 1903 sc->sc_enabled = 1; 1904 return (0); 1905} 1906 1907void 1908fxp_disable(sc) 1909 struct fxp_softc *sc; 1910{ 1911 1912 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 1913 (*sc->sc_disable)(sc); 1914 sc->sc_enabled = 0; 1915 } 1916} 1917 1918/* 1919 * fxp_activate: 1920 * 1921 * Handle device activation/deactivation requests. 1922 */ 1923int 1924fxp_activate(self, act) 1925 struct device *self; 1926 enum devact act; 1927{ 1928 struct fxp_softc *sc = (void *) self; 1929 int s, error = 0; 1930 1931 s = splnet(); 1932 switch (act) { 1933 case DVACT_ACTIVATE: 1934 error = EOPNOTSUPP; 1935 break; 1936 1937 case DVACT_DEACTIVATE: 1938 if (sc->sc_flags & FXPF_MII) 1939 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 1940 MII_OFFSET_ANY); 1941 if_deactivate(&sc->sc_ethercom.ec_if); 1942 break; 1943 } 1944 splx(s); 1945 1946 return (error); 1947} 1948 1949/* 1950 * fxp_detach: 1951 * 1952 * Detach an i82557 interface. 1953 */ 1954int 1955fxp_detach(sc) 1956 struct fxp_softc *sc; 1957{ 1958 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1959 int i; 1960 1961 /* Unhook our tick handler. */ 1962 callout_stop(&sc->sc_callout); 1963 1964 if (sc->sc_flags & FXPF_MII) { 1965 /* Detach all PHYs */ 1966 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1967 } 1968 1969 /* Delete all remaining media. */ 1970 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 1971 1972#if NRND > 0 1973 rnd_detach_source(&sc->rnd_source); 1974#endif 1975#if NBPFILTER > 0 1976 bpfdetach(ifp); 1977#endif 1978 ether_ifdetach(ifp); 1979 if_detach(ifp); 1980 1981 for (i = 0; i < FXP_NRFABUFS; i++) { 1982 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 1983 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 1984 } 1985 1986 for (i = 0; i < FXP_NTXCB; i++) { 1987 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 1988 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 1989 } 1990 1991 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 1992 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 1993 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1994 sizeof(struct fxp_control_data)); 1995 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 1996 1997 shutdownhook_disestablish(sc->sc_sdhook); 1998 powerhook_disestablish(sc->sc_powerhook); 1999 2000 return (0); 2001} 2002