i82557.c revision 1.147
1/* $NetBSD: i82557.c,v 1.147 2017/02/20 07:43:29 ozaki-r Exp $ */ 2 3/*- 4 * Copyright (c) 1997, 1998, 1999, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Copyright (c) 1995, David Greenman 35 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice unmodified, this list of conditions, and the following 43 * disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 61 */ 62 63/* 64 * Device driver for the Intel i82557 fast Ethernet controller, 65 * and its successors, the i82558 and i82559. 66 */ 67 68#include <sys/cdefs.h> 69__KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.147 2017/02/20 07:43:29 ozaki-r Exp $"); 70 71#include <sys/param.h> 72#include <sys/systm.h> 73#include <sys/callout.h> 74#include <sys/mbuf.h> 75#include <sys/malloc.h> 76#include <sys/kernel.h> 77#include <sys/socket.h> 78#include <sys/ioctl.h> 79#include <sys/errno.h> 80#include <sys/device.h> 81#include <sys/syslog.h> 82#include <sys/proc.h> 83 84#include <machine/endian.h> 85 86#include <sys/rndsource.h> 87 88#include <net/if.h> 89#include <net/if_dl.h> 90#include <net/if_media.h> 91#include <net/if_ether.h> 92 93#include <netinet/in.h> 94#include <netinet/in_systm.h> 95#include <netinet/ip.h> 96#include <netinet/tcp.h> 97#include <netinet/udp.h> 98 99#include <net/bpf.h> 100 101#include <sys/bus.h> 102#include <sys/intr.h> 103 104#include <dev/mii/miivar.h> 105 106#include <dev/ic/i82557reg.h> 107#include <dev/ic/i82557var.h> 108 109#include <dev/microcode/i8255x/rcvbundl.h> 110 111/* 112 * NOTE! On the Alpha, we have an alignment constraint. The 113 * card DMAs the packet immediately following the RFA. However, 114 * the first thing in the packet is a 14-byte Ethernet header. 115 * This means that the packet is misaligned. To compensate, 116 * we actually offset the RFA 2 bytes into the cluster. This 117 * alignes the packet after the Ethernet header at a 32-bit 118 * boundary. HOWEVER! This means that the RFA is misaligned! 119 */ 120#define RFA_ALIGNMENT_FUDGE 2 121 122/* 123 * The configuration byte map has several undefined fields which 124 * must be one or must be zero. Set up a template for these bits 125 * only (assuming an i82557 chip), leaving the actual configuration 126 * for fxp_init(). 127 * 128 * See the definition of struct fxp_cb_config for the bit definitions. 129 */ 130const uint8_t fxp_cb_config_template[] = { 131 0x0, 0x0, /* cb_status */ 132 0x0, 0x0, /* cb_command */ 133 0x0, 0x0, 0x0, 0x0, /* link_addr */ 134 0x0, /* 0 */ 135 0x0, /* 1 */ 136 0x0, /* 2 */ 137 0x0, /* 3 */ 138 0x0, /* 4 */ 139 0x0, /* 5 */ 140 0x32, /* 6 */ 141 0x0, /* 7 */ 142 0x0, /* 8 */ 143 0x0, /* 9 */ 144 0x6, /* 10 */ 145 0x0, /* 11 */ 146 0x0, /* 12 */ 147 0x0, /* 13 */ 148 0xf2, /* 14 */ 149 0x48, /* 15 */ 150 0x0, /* 16 */ 151 0x40, /* 17 */ 152 0xf0, /* 18 */ 153 0x0, /* 19 */ 154 0x3f, /* 20 */ 155 0x5, /* 21 */ 156 0x0, /* 22 */ 157 0x0, /* 23 */ 158 0x0, /* 24 */ 159 0x0, /* 25 */ 160 0x0, /* 26 */ 161 0x0, /* 27 */ 162 0x0, /* 28 */ 163 0x0, /* 29 */ 164 0x0, /* 30 */ 165 0x0, /* 31 */ 166}; 167 168void fxp_mii_initmedia(struct fxp_softc *); 169void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 170 171void fxp_80c24_initmedia(struct fxp_softc *); 172int fxp_80c24_mediachange(struct ifnet *); 173void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 174 175void fxp_start(struct ifnet *); 176int fxp_ioctl(struct ifnet *, u_long, void *); 177void fxp_watchdog(struct ifnet *); 178int fxp_init(struct ifnet *); 179void fxp_stop(struct ifnet *, int); 180 181void fxp_txintr(struct fxp_softc *); 182int fxp_rxintr(struct fxp_softc *); 183 184void fxp_rx_hwcksum(struct fxp_softc *,struct mbuf *, 185 const struct fxp_rfa *, u_int); 186 187void fxp_rxdrain(struct fxp_softc *); 188int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 189int fxp_mdi_read(device_t, int, int); 190void fxp_statchg(struct ifnet *); 191void fxp_mdi_write(device_t, int, int, int); 192void fxp_autosize_eeprom(struct fxp_softc*); 193void fxp_read_eeprom(struct fxp_softc *, uint16_t *, int, int); 194void fxp_write_eeprom(struct fxp_softc *, uint16_t *, int, int); 195void fxp_eeprom_update_cksum(struct fxp_softc *); 196void fxp_get_info(struct fxp_softc *, uint8_t *); 197void fxp_tick(void *); 198void fxp_mc_setup(struct fxp_softc *); 199void fxp_load_ucode(struct fxp_softc *); 200 201int fxp_copy_small = 0; 202 203/* 204 * Variables for interrupt mitigating microcode. 205 */ 206int fxp_int_delay = 1000; /* usec */ 207int fxp_bundle_max = 6; /* packets */ 208 209struct fxp_phytype { 210 int fp_phy; /* type of PHY, -1 for MII at the end. */ 211 void (*fp_init)(struct fxp_softc *); 212} fxp_phytype_table[] = { 213 { FXP_PHY_80C24, fxp_80c24_initmedia }, 214 { -1, fxp_mii_initmedia }, 215}; 216 217/* 218 * Set initial transmit threshold at 64 (512 bytes). This is 219 * increased by 64 (512 bytes) at a time, to maximum of 192 220 * (1536 bytes), if an underrun occurs. 221 */ 222static int tx_threshold = 64; 223 224/* 225 * Wait for the previous command to be accepted (but not necessarily 226 * completed). 227 */ 228static inline void 229fxp_scb_wait(struct fxp_softc *sc) 230{ 231 int i = 10000; 232 233 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 234 delay(2); 235 if (i == 0) 236 log(LOG_WARNING, 237 "%s: WARNING: SCB timed out!\n", device_xname(sc->sc_dev)); 238} 239 240/* 241 * Submit a command to the i82557. 242 */ 243static inline void 244fxp_scb_cmd(struct fxp_softc *sc, uint8_t cmd) 245{ 246 247 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 248} 249 250/* 251 * Finish attaching an i82557 interface. Called by bus-specific front-end. 252 */ 253void 254fxp_attach(struct fxp_softc *sc) 255{ 256 uint8_t enaddr[ETHER_ADDR_LEN]; 257 struct ifnet *ifp; 258 bus_dma_segment_t seg; 259 int rseg, i, error; 260 struct fxp_phytype *fp; 261 262 callout_init(&sc->sc_callout, 0); 263 264 /* 265 * Enable use of extended RFDs and IPCBs for 82550 and later chips. 266 * Note: to use IPCB we need extended TXCB support too, and 267 * these feature flags should be set in each bus attachment. 268 */ 269 if (sc->sc_flags & FXPF_EXT_RFA) { 270 sc->sc_txcmd = htole16(FXP_CB_COMMAND_IPCBXMIT); 271 sc->sc_rfa_size = RFA_EXT_SIZE; 272 } else { 273 sc->sc_txcmd = htole16(FXP_CB_COMMAND_XMIT); 274 sc->sc_rfa_size = RFA_SIZE; 275 } 276 277 /* 278 * Allocate the control data structures, and create and load the 279 * DMA map for it. 280 */ 281 if ((error = bus_dmamem_alloc(sc->sc_dmat, 282 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 283 0)) != 0) { 284 aprint_error_dev(sc->sc_dev, 285 "unable to allocate control data, error = %d\n", 286 error); 287 goto fail_0; 288 } 289 290 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 291 sizeof(struct fxp_control_data), (void **)&sc->sc_control_data, 292 BUS_DMA_COHERENT)) != 0) { 293 aprint_error_dev(sc->sc_dev, 294 "unable to map control data, error = %d\n", error); 295 goto fail_1; 296 } 297 sc->sc_cdseg = seg; 298 sc->sc_cdnseg = rseg; 299 300 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 301 302 if ((error = bus_dmamap_create(sc->sc_dmat, 303 sizeof(struct fxp_control_data), 1, 304 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 305 aprint_error_dev(sc->sc_dev, 306 "unable to create control data DMA map, error = %d\n", 307 error); 308 goto fail_2; 309 } 310 311 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 312 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 313 0)) != 0) { 314 aprint_error_dev(sc->sc_dev, 315 "can't load control data DMA map, error = %d\n", 316 error); 317 goto fail_3; 318 } 319 320 /* 321 * Create the transmit buffer DMA maps. 322 */ 323 for (i = 0; i < FXP_NTXCB; i++) { 324 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 325 (sc->sc_flags & FXPF_EXT_RFA) ? 326 FXP_IPCB_NTXSEG : FXP_NTXSEG, 327 MCLBYTES, 0, 0, &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 328 aprint_error_dev(sc->sc_dev, 329 "unable to create tx DMA map %d, error = %d\n", 330 i, error); 331 goto fail_4; 332 } 333 } 334 335 /* 336 * Create the receive buffer DMA maps. 337 */ 338 for (i = 0; i < FXP_NRFABUFS; i++) { 339 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 340 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 341 aprint_error_dev(sc->sc_dev, 342 "unable to create rx DMA map %d, error = %d\n", 343 i, error); 344 goto fail_5; 345 } 346 } 347 348 /* Initialize MAC address and media structures. */ 349 fxp_get_info(sc, enaddr); 350 351 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 352 ether_sprintf(enaddr)); 353 354 ifp = &sc->sc_ethercom.ec_if; 355 356 /* 357 * Get info about our media interface, and initialize it. Note 358 * the table terminates itself with a phy of -1, indicating 359 * that we're using MII. 360 */ 361 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 362 if (fp->fp_phy == sc->phy_primary_device) 363 break; 364 (*fp->fp_init)(sc); 365 366 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 367 ifp->if_softc = sc; 368 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 369 ifp->if_ioctl = fxp_ioctl; 370 ifp->if_start = fxp_start; 371 ifp->if_watchdog = fxp_watchdog; 372 ifp->if_init = fxp_init; 373 ifp->if_stop = fxp_stop; 374 IFQ_SET_READY(&ifp->if_snd); 375 376 if (sc->sc_flags & FXPF_EXT_RFA) { 377 /* 378 * Enable hardware cksum support by EXT_RFA and IPCB. 379 * 380 * IFCAP_CSUM_IPv4_Tx seems to have a problem, 381 * at least, on i82550 rev.12. 382 * specifically, it doesn't set ipv4 checksum properly 383 * when sending UDP (and probably TCP) packets with 384 * 20 byte ipv4 header + 1 or 2 byte data, 385 * though ICMP packets seem working. 386 * FreeBSD driver has related comments. 387 * We've added a workaround to handle the bug by padding 388 * such packets manually. 389 */ 390 ifp->if_capabilities = 391 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 392 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 393 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 394 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 395 } else if (sc->sc_flags & FXPF_82559_RXCSUM) { 396 ifp->if_capabilities = 397 IFCAP_CSUM_TCPv4_Rx | 398 IFCAP_CSUM_UDPv4_Rx; 399 } 400 401 /* 402 * We can support 802.1Q VLAN-sized frames. 403 */ 404 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 405 406 /* 407 * Attach the interface. 408 */ 409 if_attach(ifp); 410 if_deferred_start_init(ifp, NULL); 411 ether_ifattach(ifp, enaddr); 412 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 413 RND_TYPE_NET, RND_FLAG_DEFAULT); 414 415#ifdef FXP_EVENT_COUNTERS 416 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 417 NULL, device_xname(sc->sc_dev), "txstall"); 418 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 419 NULL, device_xname(sc->sc_dev), "txintr"); 420 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 421 NULL, device_xname(sc->sc_dev), "rxintr"); 422 if (sc->sc_flags & FXPF_FC) { 423 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 424 NULL, device_xname(sc->sc_dev), "txpause"); 425 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 426 NULL, device_xname(sc->sc_dev), "rxpause"); 427 } 428#endif /* FXP_EVENT_COUNTERS */ 429 430 /* The attach is successful. */ 431 sc->sc_flags |= FXPF_ATTACHED; 432 433 return; 434 435 /* 436 * Free any resources we've allocated during the failed attach 437 * attempt. Do this in reverse order and fall though. 438 */ 439 fail_5: 440 for (i = 0; i < FXP_NRFABUFS; i++) { 441 if (sc->sc_rxmaps[i] != NULL) 442 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 443 } 444 fail_4: 445 for (i = 0; i < FXP_NTXCB; i++) { 446 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 447 bus_dmamap_destroy(sc->sc_dmat, 448 FXP_DSTX(sc, i)->txs_dmamap); 449 } 450 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 451 fail_3: 452 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 453 fail_2: 454 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 455 sizeof(struct fxp_control_data)); 456 fail_1: 457 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 458 fail_0: 459 return; 460} 461 462void 463fxp_mii_initmedia(struct fxp_softc *sc) 464{ 465 int flags; 466 467 sc->sc_flags |= FXPF_MII; 468 469 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 470 sc->sc_mii.mii_readreg = fxp_mdi_read; 471 sc->sc_mii.mii_writereg = fxp_mdi_write; 472 sc->sc_mii.mii_statchg = fxp_statchg; 473 474 sc->sc_ethercom.ec_mii = &sc->sc_mii; 475 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 476 fxp_mii_mediastatus); 477 478 flags = MIIF_NOISOLATE; 479 if (sc->sc_flags & FXPF_FC) 480 flags |= MIIF_FORCEANEG|MIIF_DOPAUSE; 481 /* 482 * The i82557 wedges if all of its PHYs are isolated! 483 */ 484 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 485 MII_OFFSET_ANY, flags); 486 if (LIST_EMPTY(&sc->sc_mii.mii_phys)) { 487 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 488 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 489 } else 490 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 491} 492 493void 494fxp_80c24_initmedia(struct fxp_softc *sc) 495{ 496 497 /* 498 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 499 * doesn't have a programming interface of any sort. The 500 * media is sensed automatically based on how the link partner 501 * is configured. This is, in essence, manual configuration. 502 */ 503 aprint_normal_dev(sc->sc_dev, 504 "Seeq 80c24 AutoDUPLEX media interface present\n"); 505 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 506 fxp_80c24_mediastatus); 507 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 508 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 509} 510 511/* 512 * Initialize the interface media. 513 */ 514void 515fxp_get_info(struct fxp_softc *sc, uint8_t *enaddr) 516{ 517 uint16_t data, myea[ETHER_ADDR_LEN / 2]; 518 519 /* 520 * Reset to a stable state. 521 */ 522 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 523 DELAY(100); 524 525 sc->sc_eeprom_size = 0; 526 fxp_autosize_eeprom(sc); 527 if (sc->sc_eeprom_size == 0) { 528 aprint_error_dev(sc->sc_dev, "failed to detect EEPROM size\n"); 529 sc->sc_eeprom_size = 6; /* XXX panic here? */ 530 } 531#ifdef DEBUG 532 aprint_debug_dev(sc->sc_dev, "detected %d word EEPROM\n", 533 1 << sc->sc_eeprom_size); 534#endif 535 536 /* 537 * Get info about the primary PHY 538 */ 539 fxp_read_eeprom(sc, &data, 6, 1); 540 sc->phy_primary_device = 541 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 542 543 /* 544 * Read MAC address. 545 */ 546 fxp_read_eeprom(sc, myea, 0, 3); 547 enaddr[0] = myea[0] & 0xff; 548 enaddr[1] = myea[0] >> 8; 549 enaddr[2] = myea[1] & 0xff; 550 enaddr[3] = myea[1] >> 8; 551 enaddr[4] = myea[2] & 0xff; 552 enaddr[5] = myea[2] >> 8; 553 554 /* 555 * Systems based on the ICH2/ICH2-M chip from Intel, as well 556 * as some i82559 designs, have a defect where the chip can 557 * cause a PCI protocol violation if it receives a CU_RESUME 558 * command when it is entering the IDLE state. 559 * 560 * The work-around is to disable Dynamic Standby Mode, so that 561 * the chip never deasserts #CLKRUN, and always remains in the 562 * active state. 563 * 564 * Unfortunately, the only way to disable Dynamic Standby is 565 * to frob an EEPROM setting and reboot (the EEPROM setting 566 * is only consulted when the PCI bus comes out of reset). 567 * 568 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 569 */ 570 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 571 fxp_read_eeprom(sc, &data, 10, 1); 572 if (data & 0x02) { /* STB enable */ 573 aprint_error_dev(sc->sc_dev, "WARNING: " 574 "Disabling dynamic standby mode in EEPROM " 575 "to work around a\n"); 576 aprint_normal_dev(sc->sc_dev, 577 "WARNING: hardware bug. You must reset " 578 "the system before using this\n"); 579 aprint_normal_dev(sc->sc_dev, "WARNING: interface.\n"); 580 data &= ~0x02; 581 fxp_write_eeprom(sc, &data, 10, 1); 582 aprint_normal_dev(sc->sc_dev, "new EEPROM ID: 0x%04x\n", 583 data); 584 fxp_eeprom_update_cksum(sc); 585 } 586 } 587 588 /* Receiver lock-up workaround detection. (FXPF_RECV_WORKAROUND) */ 589 /* Due to false positives we make it conditional on setting link1 */ 590 fxp_read_eeprom(sc, &data, 3, 1); 591 if ((data & 0x03) != 0x03) { 592 aprint_verbose_dev(sc->sc_dev, 593 "May need receiver lock-up workaround\n"); 594 } 595} 596 597static void 598fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 599{ 600 uint16_t reg; 601 int x; 602 603 for (x = 1 << (len - 1); x != 0; x >>= 1) { 604 DELAY(40); 605 if (data & x) 606 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 607 else 608 reg = FXP_EEPROM_EECS; 609 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 610 DELAY(40); 611 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 612 reg | FXP_EEPROM_EESK); 613 DELAY(40); 614 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 615 } 616 DELAY(40); 617} 618 619/* 620 * Figure out EEPROM size. 621 * 622 * 559's can have either 64-word or 256-word EEPROMs, the 558 623 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 624 * talks about the existence of 16 to 256 word EEPROMs. 625 * 626 * The only known sizes are 64 and 256, where the 256 version is used 627 * by CardBus cards to store CIS information. 628 * 629 * The address is shifted in msb-to-lsb, and after the last 630 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 631 * after which follows the actual data. We try to detect this zero, by 632 * probing the data-out bit in the EEPROM control register just after 633 * having shifted in a bit. If the bit is zero, we assume we've 634 * shifted enough address bits. The data-out should be tri-state, 635 * before this, which should translate to a logical one. 636 * 637 * Other ways to do this would be to try to read a register with known 638 * contents with a varying number of address bits, but no such 639 * register seem to be available. The high bits of register 10 are 01 640 * on the 558 and 559, but apparently not on the 557. 641 * 642 * The Linux driver computes a checksum on the EEPROM data, but the 643 * value of this checksum is not very well documented. 644 */ 645 646void 647fxp_autosize_eeprom(struct fxp_softc *sc) 648{ 649 int x; 650 651 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 652 DELAY(40); 653 654 /* Shift in read opcode. */ 655 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 656 657 /* 658 * Shift in address, wait for the dummy zero following a correct 659 * address shift. 660 */ 661 for (x = 1; x <= 8; x++) { 662 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 663 DELAY(40); 664 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 665 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 666 DELAY(40); 667 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 668 FXP_EEPROM_EEDO) == 0) 669 break; 670 DELAY(40); 671 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 672 DELAY(40); 673 } 674 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 675 DELAY(40); 676 if (x != 6 && x != 8) { 677#ifdef DEBUG 678 printf("%s: strange EEPROM size (%d)\n", 679 device_xname(sc->sc_dev), 1 << x); 680#endif 681 } else 682 sc->sc_eeprom_size = x; 683} 684 685/* 686 * Read from the serial EEPROM. Basically, you manually shift in 687 * the read opcode (one bit at a time) and then shift in the address, 688 * and then you shift out the data (all of this one bit at a time). 689 * The word size is 16 bits, so you have to provide the address for 690 * every 16 bits of data. 691 */ 692void 693fxp_read_eeprom(struct fxp_softc *sc, uint16_t *data, int offset, int words) 694{ 695 uint16_t reg; 696 int i, x; 697 698 for (i = 0; i < words; i++) { 699 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 700 701 /* Shift in read opcode. */ 702 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 703 704 /* Shift in address. */ 705 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 706 707 reg = FXP_EEPROM_EECS; 708 data[i] = 0; 709 710 /* Shift out data. */ 711 for (x = 16; x > 0; x--) { 712 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 713 reg | FXP_EEPROM_EESK); 714 DELAY(40); 715 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 716 FXP_EEPROM_EEDO) 717 data[i] |= (1 << (x - 1)); 718 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 719 DELAY(40); 720 } 721 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 722 DELAY(40); 723 } 724} 725 726/* 727 * Write data to the serial EEPROM. 728 */ 729void 730fxp_write_eeprom(struct fxp_softc *sc, uint16_t *data, int offset, int words) 731{ 732 int i, j; 733 734 for (i = 0; i < words; i++) { 735 /* Erase/write enable. */ 736 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 737 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 738 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 739 sc->sc_eeprom_size); 740 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 741 DELAY(4); 742 743 /* Shift in write opcode, address, data. */ 744 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 745 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 746 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 747 fxp_eeprom_shiftin(sc, data[i], 16); 748 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 749 DELAY(4); 750 751 /* Wait for the EEPROM to finish up. */ 752 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 753 DELAY(4); 754 for (j = 0; j < 1000; j++) { 755 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 756 FXP_EEPROM_EEDO) 757 break; 758 DELAY(50); 759 } 760 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 761 DELAY(4); 762 763 /* Erase/write disable. */ 764 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 765 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 766 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 767 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 768 DELAY(4); 769 } 770} 771 772/* 773 * Update the checksum of the EEPROM. 774 */ 775void 776fxp_eeprom_update_cksum(struct fxp_softc *sc) 777{ 778 int i; 779 uint16_t data, cksum; 780 781 cksum = 0; 782 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 783 fxp_read_eeprom(sc, &data, i, 1); 784 cksum += data; 785 } 786 i = (1 << sc->sc_eeprom_size) - 1; 787 cksum = 0xbaba - cksum; 788 fxp_read_eeprom(sc, &data, i, 1); 789 fxp_write_eeprom(sc, &cksum, i, 1); 790 log(LOG_INFO, "%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 791 device_xname(sc->sc_dev), i, data, cksum); 792} 793 794/* 795 * Start packet transmission on the interface. 796 */ 797void 798fxp_start(struct ifnet *ifp) 799{ 800 struct fxp_softc *sc = ifp->if_softc; 801 struct mbuf *m0, *m; 802 struct fxp_txdesc *txd; 803 struct fxp_txsoft *txs; 804 bus_dmamap_t dmamap; 805 int error, lasttx, nexttx, opending, seg, nsegs, len; 806 807 /* 808 * If we want a re-init, bail out now. 809 */ 810 if (sc->sc_flags & FXPF_WANTINIT) { 811 ifp->if_flags |= IFF_OACTIVE; 812 return; 813 } 814 815 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 816 return; 817 818 /* 819 * Remember the previous txpending and the current lasttx. 820 */ 821 opending = sc->sc_txpending; 822 lasttx = sc->sc_txlast; 823 824 /* 825 * Loop through the send queue, setting up transmit descriptors 826 * until we drain the queue, or use up all available transmit 827 * descriptors. 828 */ 829 for (;;) { 830 struct fxp_tbd *tbdp; 831 int csum_flags; 832 833 /* 834 * Grab a packet off the queue. 835 */ 836 IFQ_POLL(&ifp->if_snd, m0); 837 if (m0 == NULL) 838 break; 839 m = NULL; 840 841 if (sc->sc_txpending == FXP_NTXCB - 1) { 842 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 843 break; 844 } 845 846 /* 847 * Get the next available transmit descriptor. 848 */ 849 nexttx = FXP_NEXTTX(sc->sc_txlast); 850 txd = FXP_CDTX(sc, nexttx); 851 txs = FXP_DSTX(sc, nexttx); 852 dmamap = txs->txs_dmamap; 853 854 /* 855 * Load the DMA map. If this fails, the packet either 856 * didn't fit in the allotted number of frags, or we were 857 * short on resources. In this case, we'll copy and try 858 * again. 859 */ 860 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 861 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 862 MGETHDR(m, M_DONTWAIT, MT_DATA); 863 if (m == NULL) { 864 log(LOG_ERR, "%s: unable to allocate Tx mbuf\n", 865 device_xname(sc->sc_dev)); 866 break; 867 } 868 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 869 if (m0->m_pkthdr.len > MHLEN) { 870 MCLGET(m, M_DONTWAIT); 871 if ((m->m_flags & M_EXT) == 0) { 872 log(LOG_ERR, "%s: unable to allocate " 873 "Tx cluster\n", 874 device_xname(sc->sc_dev)); 875 m_freem(m); 876 break; 877 } 878 } 879 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 880 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 881 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 882 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 883 if (error) { 884 log(LOG_ERR, "%s: unable to load Tx buffer, " 885 "error = %d\n", 886 device_xname(sc->sc_dev), error); 887 break; 888 } 889 } 890 891 IFQ_DEQUEUE(&ifp->if_snd, m0); 892 csum_flags = m0->m_pkthdr.csum_flags; 893 if (m != NULL) { 894 m_freem(m0); 895 m0 = m; 896 } 897 898 /* Initialize the fraglist. */ 899 tbdp = txd->txd_tbd; 900 len = m0->m_pkthdr.len; 901 nsegs = dmamap->dm_nsegs; 902 if (sc->sc_flags & FXPF_EXT_RFA) 903 tbdp++; 904 for (seg = 0; seg < nsegs; seg++) { 905 tbdp[seg].tb_addr = 906 htole32(dmamap->dm_segs[seg].ds_addr); 907 tbdp[seg].tb_size = 908 htole32(dmamap->dm_segs[seg].ds_len); 909 } 910 if (__predict_false(len <= FXP_IP4CSUMTX_PADLEN && 911 (csum_flags & M_CSUM_IPv4) != 0)) { 912 /* 913 * Pad short packets to avoid ip4csum-tx bug. 914 * 915 * XXX Should we still consider if such short 916 * (36 bytes or less) packets might already 917 * occupy FXP_IPCB_NTXSEG (15) fragments here? 918 */ 919 KASSERT(nsegs < FXP_IPCB_NTXSEG); 920 nsegs++; 921 tbdp[seg].tb_addr = htole32(FXP_CDTXPADADDR(sc)); 922 tbdp[seg].tb_size = 923 htole32(FXP_IP4CSUMTX_PADLEN + 1 - len); 924 } 925 926 /* Sync the DMA map. */ 927 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 928 BUS_DMASYNC_PREWRITE); 929 930 /* 931 * Store a pointer to the packet so we can free it later. 932 */ 933 txs->txs_mbuf = m0; 934 935 /* 936 * Initialize the transmit descriptor. 937 */ 938 /* BIG_ENDIAN: no need to swap to store 0 */ 939 txd->txd_txcb.cb_status = 0; 940 txd->txd_txcb.cb_command = 941 sc->sc_txcmd | htole16(FXP_CB_COMMAND_SF); 942 txd->txd_txcb.tx_threshold = tx_threshold; 943 txd->txd_txcb.tbd_number = nsegs; 944 945 KASSERT((csum_flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) == 0); 946 if (sc->sc_flags & FXPF_EXT_RFA) { 947 struct m_tag *vtag; 948 struct fxp_ipcb *ipcb; 949 /* 950 * Deal with TCP/IP checksum offload. Note that 951 * in order for TCP checksum offload to work, 952 * the pseudo header checksum must have already 953 * been computed and stored in the checksum field 954 * in the TCP header. The stack should have 955 * already done this for us. 956 */ 957 ipcb = &txd->txd_u.txdu_ipcb; 958 memset(ipcb, 0, sizeof(*ipcb)); 959 /* 960 * always do hardware parsing. 961 */ 962 ipcb->ipcb_ip_activation_high = 963 FXP_IPCB_HARDWAREPARSING_ENABLE; 964 /* 965 * ip checksum offloading. 966 */ 967 if (csum_flags & M_CSUM_IPv4) { 968 ipcb->ipcb_ip_schedule |= 969 FXP_IPCB_IP_CHECKSUM_ENABLE; 970 } 971 /* 972 * TCP/UDP checksum offloading. 973 */ 974 if (csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 975 ipcb->ipcb_ip_schedule |= 976 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 977 } 978 979 /* 980 * request VLAN tag insertion if needed. 981 */ 982 vtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0); 983 if (vtag) { 984 ipcb->ipcb_vlan_id = 985 htobe16(*(u_int *)(vtag + 1)); 986 ipcb->ipcb_ip_activation_high |= 987 FXP_IPCB_INSERTVLAN_ENABLE; 988 } 989 } else { 990 KASSERT((csum_flags & 991 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) == 0); 992 } 993 994 FXP_CDTXSYNC(sc, nexttx, 995 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 996 997 /* Advance the tx pointer. */ 998 sc->sc_txpending++; 999 sc->sc_txlast = nexttx; 1000 1001 /* 1002 * Pass packet to bpf if there is a listener. 1003 */ 1004 bpf_mtap(ifp, m0); 1005 } 1006 1007 if (sc->sc_txpending == FXP_NTXCB - 1) { 1008 /* No more slots; notify upper layer. */ 1009 ifp->if_flags |= IFF_OACTIVE; 1010 } 1011 1012 if (sc->sc_txpending != opending) { 1013 /* 1014 * We enqueued packets. If the transmitter was idle, 1015 * reset the txdirty pointer. 1016 */ 1017 if (opending == 0) 1018 sc->sc_txdirty = FXP_NEXTTX(lasttx); 1019 1020 /* 1021 * Cause the chip to interrupt and suspend command 1022 * processing once the last packet we've enqueued 1023 * has been transmitted. 1024 * 1025 * To avoid a race between updating status bits 1026 * by the fxp chip and clearing command bits 1027 * by this function on machines which don't have 1028 * atomic methods to clear/set bits in memory 1029 * smaller than 32bits (both cb_status and cb_command 1030 * members are uint16_t and in the same 32bit word), 1031 * we have to prepare a dummy TX descriptor which has 1032 * NOP command and just causes a TX completion interrupt. 1033 */ 1034 sc->sc_txpending++; 1035 sc->sc_txlast = FXP_NEXTTX(sc->sc_txlast); 1036 txd = FXP_CDTX(sc, sc->sc_txlast); 1037 /* BIG_ENDIAN: no need to swap to store 0 */ 1038 txd->txd_txcb.cb_status = 0; 1039 txd->txd_txcb.cb_command = htole16(FXP_CB_COMMAND_NOP | 1040 FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 1041 FXP_CDTXSYNC(sc, sc->sc_txlast, 1042 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1043 1044 /* 1045 * The entire packet chain is set up. Clear the suspend bit 1046 * on the command prior to the first packet we set up. 1047 */ 1048 FXP_CDTXSYNC(sc, lasttx, 1049 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1050 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 1051 htole16(~FXP_CB_COMMAND_S); 1052 FXP_CDTXSYNC(sc, lasttx, 1053 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1054 1055 /* 1056 * Issue a Resume command in case the chip was suspended. 1057 */ 1058 fxp_scb_wait(sc); 1059 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1060 1061 /* Set a watchdog timer in case the chip flakes out. */ 1062 ifp->if_timer = 5; 1063 } 1064} 1065 1066/* 1067 * Process interface interrupts. 1068 */ 1069int 1070fxp_intr(void *arg) 1071{ 1072 struct fxp_softc *sc = arg; 1073 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1074 bus_dmamap_t rxmap; 1075 int claimed = 0, rnr; 1076 uint8_t statack; 1077 1078 if (!device_is_active(sc->sc_dev) || sc->sc_enabled == 0) 1079 return (0); 1080 /* 1081 * If the interface isn't running, don't try to 1082 * service the interrupt.. just ack it and bail. 1083 */ 1084 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1085 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1086 if (statack) { 1087 claimed = 1; 1088 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1089 } 1090 return (claimed); 1091 } 1092 1093 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1094 claimed = 1; 1095 1096 /* 1097 * First ACK all the interrupts in this pass. 1098 */ 1099 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1100 1101 /* 1102 * Process receiver interrupts. If a no-resource (RNR) 1103 * condition exists, get whatever packets we can and 1104 * re-start the receiver. 1105 */ 1106 rnr = (statack & (FXP_SCB_STATACK_RNR | FXP_SCB_STATACK_SWI)) ? 1107 1 : 0; 1108 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR | 1109 FXP_SCB_STATACK_SWI)) { 1110 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1111 rnr |= fxp_rxintr(sc); 1112 } 1113 1114 /* 1115 * Free any finished transmit mbuf chains. 1116 */ 1117 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1118 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1119 fxp_txintr(sc); 1120 1121 /* 1122 * Try to get more packets going. 1123 */ 1124 if_schedule_deferred_start(ifp); 1125 1126 if (sc->sc_txpending == 0) { 1127 /* 1128 * Tell them that they can re-init now. 1129 */ 1130 if (sc->sc_flags & FXPF_WANTINIT) 1131 wakeup(sc); 1132 } 1133 } 1134 1135 if (rnr) { 1136 fxp_scb_wait(sc); 1137 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_ABORT); 1138 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1139 fxp_scb_wait(sc); 1140 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1141 rxmap->dm_segs[0].ds_addr + 1142 RFA_ALIGNMENT_FUDGE); 1143 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1144 } 1145 } 1146 1147 if (claimed) 1148 rnd_add_uint32(&sc->rnd_source, statack); 1149 return (claimed); 1150} 1151 1152/* 1153 * Handle transmit completion interrupts. 1154 */ 1155void 1156fxp_txintr(struct fxp_softc *sc) 1157{ 1158 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1159 struct fxp_txdesc *txd; 1160 struct fxp_txsoft *txs; 1161 int i; 1162 uint16_t txstat; 1163 1164 ifp->if_flags &= ~IFF_OACTIVE; 1165 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1166 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1167 txd = FXP_CDTX(sc, i); 1168 txs = FXP_DSTX(sc, i); 1169 1170 FXP_CDTXSYNC(sc, i, 1171 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1172 1173 /* skip dummy NOP TX descriptor */ 1174 if ((le16toh(txd->txd_txcb.cb_command) & FXP_CB_COMMAND_CMD) 1175 == FXP_CB_COMMAND_NOP) 1176 continue; 1177 1178 txstat = le16toh(txd->txd_txcb.cb_status); 1179 1180 if ((txstat & FXP_CB_STATUS_C) == 0) 1181 break; 1182 1183 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1184 0, txs->txs_dmamap->dm_mapsize, 1185 BUS_DMASYNC_POSTWRITE); 1186 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1187 m_freem(txs->txs_mbuf); 1188 txs->txs_mbuf = NULL; 1189 } 1190 1191 /* Update the dirty transmit buffer pointer. */ 1192 sc->sc_txdirty = i; 1193 1194 /* 1195 * Cancel the watchdog timer if there are no pending 1196 * transmissions. 1197 */ 1198 if (sc->sc_txpending == 0) 1199 ifp->if_timer = 0; 1200} 1201 1202/* 1203 * fxp_rx_hwcksum: check status of H/W offloading for received packets. 1204 */ 1205 1206void 1207fxp_rx_hwcksum(struct fxp_softc *sc, struct mbuf *m, const struct fxp_rfa *rfa, 1208 u_int len) 1209{ 1210 uint32_t csum_data; 1211 int csum_flags; 1212 1213 /* 1214 * check H/W Checksumming. 1215 */ 1216 1217 csum_flags = 0; 1218 csum_data = 0; 1219 1220 if ((sc->sc_flags & FXPF_EXT_RFA) != 0) { 1221 uint8_t csum_stat; 1222 1223 csum_stat = rfa->cksum_stat; 1224 if ((rfa->rfa_status & htole16(FXP_RFA_STATUS_PARSE)) == 0) 1225 goto out; 1226 1227 if (csum_stat & FXP_RFDX_CS_IP_CSUM_BIT_VALID) { 1228 csum_flags = M_CSUM_IPv4; 1229 if ((csum_stat & FXP_RFDX_CS_IP_CSUM_VALID) == 0) 1230 csum_flags |= M_CSUM_IPv4_BAD; 1231 } 1232 1233 if (csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) { 1234 csum_flags |= (M_CSUM_TCPv4|M_CSUM_UDPv4); /* XXX */ 1235 if ((csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_VALID) == 0) 1236 csum_flags |= M_CSUM_TCP_UDP_BAD; 1237 } 1238 1239 } else if ((sc->sc_flags & FXPF_82559_RXCSUM) != 0) { 1240 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1241 struct ether_header *eh; 1242 struct ip *ip; 1243 struct udphdr *uh; 1244 u_int hlen, pktlen; 1245 1246 if (len < ETHER_HDR_LEN + sizeof(struct ip)) 1247 goto out; 1248 pktlen = len - ETHER_HDR_LEN; 1249 eh = mtod(m, struct ether_header *); 1250 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1251 goto out; 1252 ip = (struct ip *)((uint8_t *)eh + ETHER_HDR_LEN); 1253 if (ip->ip_v != IPVERSION) 1254 goto out; 1255 1256 hlen = ip->ip_hl << 2; 1257 if (hlen < sizeof(struct ip)) 1258 goto out; 1259 1260 /* 1261 * Bail if too short, has random trailing garbage, truncated, 1262 * fragment, or has ethernet pad. 1263 */ 1264 if (ntohs(ip->ip_len) < hlen || 1265 ntohs(ip->ip_len) != pktlen || 1266 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK)) != 0) 1267 goto out; 1268 1269 switch (ip->ip_p) { 1270 case IPPROTO_TCP: 1271 if ((ifp->if_csum_flags_rx & M_CSUM_TCPv4) == 0 || 1272 pktlen < (hlen + sizeof(struct tcphdr))) 1273 goto out; 1274 csum_flags = 1275 M_CSUM_TCPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 1276 break; 1277 case IPPROTO_UDP: 1278 if ((ifp->if_csum_flags_rx & M_CSUM_UDPv4) == 0 || 1279 pktlen < (hlen + sizeof(struct udphdr))) 1280 goto out; 1281 uh = (struct udphdr *)((uint8_t *)ip + hlen); 1282 if (uh->uh_sum == 0) 1283 goto out; /* no checksum */ 1284 csum_flags = 1285 M_CSUM_UDPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 1286 break; 1287 default: 1288 goto out; 1289 } 1290 1291 /* Extract computed checksum. */ 1292 csum_data = be16dec(mtod(m, uint8_t *) + len); 1293 1294 /* 1295 * The computed checksum includes IP headers, 1296 * so we have to deduct them. 1297 */ 1298#if 0 1299 /* 1300 * But in TCP/UDP layer we can assume the IP header is valid, 1301 * i.e. a sum of the whole IP header should be 0xffff, 1302 * so we don't have to bother to deduct it. 1303 */ 1304 if (hlen > 0) { 1305 uint32_t hsum; 1306 const uint16_t *iphdr; 1307 hsum = 0; 1308 iphdr = (uint16_t *)ip; 1309 1310 while (hlen > 1) { 1311 hsum += ntohs(*iphdr++); 1312 hlen -= sizeof(uint16_t); 1313 } 1314 while (hsum >> 16) 1315 hsum = (hsum >> 16) + (hsum & 0xffff); 1316 1317 csum_data += (uint16_t)~hsum; 1318 1319 while (csum_data >> 16) 1320 csum_data = 1321 (csum_data >> 16) + (csum_data & 0xffff); 1322 } 1323#endif 1324 } 1325 out: 1326 m->m_pkthdr.csum_flags = csum_flags; 1327 m->m_pkthdr.csum_data = csum_data; 1328} 1329 1330/* 1331 * Handle receive interrupts. 1332 */ 1333int 1334fxp_rxintr(struct fxp_softc *sc) 1335{ 1336 struct ethercom *ec = &sc->sc_ethercom; 1337 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1338 struct mbuf *m, *m0; 1339 bus_dmamap_t rxmap; 1340 struct fxp_rfa *rfa; 1341 int rnr; 1342 uint16_t len, rxstat; 1343 1344 rnr = 0; 1345 1346 for (;;) { 1347 m = sc->sc_rxq.ifq_head; 1348 rfa = FXP_MTORFA(m); 1349 rxmap = M_GETCTX(m, bus_dmamap_t); 1350 1351 FXP_RFASYNC(sc, m, 1352 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1353 1354 rxstat = le16toh(rfa->rfa_status); 1355 1356 if ((rxstat & FXP_RFA_STATUS_RNR) != 0) 1357 rnr = 1; 1358 1359 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1360 /* 1361 * We have processed all of the 1362 * receive buffers. 1363 */ 1364 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1365 return rnr; 1366 } 1367 1368 IF_DEQUEUE(&sc->sc_rxq, m); 1369 1370 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1371 1372 len = le16toh(rfa->actual_size) & 1373 (m->m_ext.ext_size - 1); 1374 if ((sc->sc_flags & FXPF_82559_RXCSUM) != 0) { 1375 /* Adjust for appended checksum bytes. */ 1376 len -= sizeof(uint16_t); 1377 } 1378 1379 if (len < sizeof(struct ether_header)) { 1380 /* 1381 * Runt packet; drop it now. 1382 */ 1383 FXP_INIT_RFABUF(sc, m); 1384 continue; 1385 } 1386 1387 /* 1388 * If support for 802.1Q VLAN sized frames is 1389 * enabled, we need to do some additional error 1390 * checking (as we are saving bad frames, in 1391 * order to receive the larger ones). 1392 */ 1393 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1394 (rxstat & (FXP_RFA_STATUS_OVERRUN| 1395 FXP_RFA_STATUS_RNR| 1396 FXP_RFA_STATUS_ALIGN| 1397 FXP_RFA_STATUS_CRC)) != 0) { 1398 FXP_INIT_RFABUF(sc, m); 1399 continue; 1400 } 1401 1402 /* 1403 * check VLAN tag stripping. 1404 */ 1405 if ((sc->sc_flags & FXPF_EXT_RFA) != 0 && 1406 (rfa->rfa_status & htole16(FXP_RFA_STATUS_VLAN)) != 0) { 1407 struct m_tag *vtag; 1408 1409 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), 1410 M_NOWAIT); 1411 if (vtag == NULL) 1412 goto dropit; 1413 *(u_int *)(vtag + 1) = be16toh(rfa->vlan_id); 1414 m_tag_prepend(m, vtag); 1415 } 1416 1417 /* Do checksum checking. */ 1418 if ((ifp->if_csum_flags_rx & (M_CSUM_TCPv4|M_CSUM_UDPv4)) != 0) 1419 fxp_rx_hwcksum(sc, m, rfa, len); 1420 1421 /* 1422 * If the packet is small enough to fit in a 1423 * single header mbuf, allocate one and copy 1424 * the data into it. This greatly reduces 1425 * memory consumption when we receive lots 1426 * of small packets. 1427 * 1428 * Otherwise, we add a new buffer to the receive 1429 * chain. If this fails, we drop the packet and 1430 * recycle the old buffer. 1431 */ 1432 if (fxp_copy_small != 0 && len <= MHLEN) { 1433 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1434 if (m0 == NULL) 1435 goto dropit; 1436 MCLAIM(m0, &sc->sc_ethercom.ec_rx_mowner); 1437 memcpy(mtod(m0, void *), 1438 mtod(m, void *), len); 1439 m0->m_pkthdr.csum_flags = m->m_pkthdr.csum_flags; 1440 m0->m_pkthdr.csum_data = m->m_pkthdr.csum_data; 1441 FXP_INIT_RFABUF(sc, m); 1442 m = m0; 1443 } else { 1444 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1445 dropit: 1446 ifp->if_ierrors++; 1447 FXP_INIT_RFABUF(sc, m); 1448 continue; 1449 } 1450 } 1451 1452 m_set_rcvif(m, ifp); 1453 m->m_pkthdr.len = m->m_len = len; 1454 1455 /* Pass it on. */ 1456 if_percpuq_enqueue(ifp->if_percpuq, m); 1457 } 1458} 1459 1460/* 1461 * Update packet in/out/collision statistics. The i82557 doesn't 1462 * allow you to access these counters without doing a fairly 1463 * expensive DMA to get _all_ of the statistics it maintains, so 1464 * we do this operation here only once per second. The statistics 1465 * counters in the kernel are updated from the previous dump-stats 1466 * DMA and then a new dump-stats DMA is started. The on-chip 1467 * counters are zeroed when the DMA completes. If we can't start 1468 * the DMA immediately, we don't wait - we just prepare to read 1469 * them again next time. 1470 */ 1471void 1472fxp_tick(void *arg) 1473{ 1474 struct fxp_softc *sc = arg; 1475 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1476 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1477 int s; 1478 1479 if (!device_is_active(sc->sc_dev)) 1480 return; 1481 1482 s = splnet(); 1483 1484 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1485 1486 ifp->if_opackets += le32toh(sp->tx_good); 1487 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1488 if (sp->rx_good) { 1489 ifp->if_ipackets += le32toh(sp->rx_good); 1490 sc->sc_rxidle = 0; 1491 } else if (sc->sc_flags & FXPF_RECV_WORKAROUND) { 1492 sc->sc_rxidle++; 1493 } 1494 ifp->if_ierrors += 1495 le32toh(sp->rx_crc_errors) + 1496 le32toh(sp->rx_alignment_errors) + 1497 le32toh(sp->rx_rnr_errors) + 1498 le32toh(sp->rx_overrun_errors); 1499 /* 1500 * If any transmit underruns occurred, bump up the transmit 1501 * threshold by another 512 bytes (64 * 8). 1502 */ 1503 if (sp->tx_underruns) { 1504 ifp->if_oerrors += le32toh(sp->tx_underruns); 1505 if (tx_threshold < 192) 1506 tx_threshold += 64; 1507 } 1508#ifdef FXP_EVENT_COUNTERS 1509 if (sc->sc_flags & FXPF_FC) { 1510 sc->sc_ev_txpause.ev_count += sp->tx_pauseframes; 1511 sc->sc_ev_rxpause.ev_count += sp->rx_pauseframes; 1512 } 1513#endif 1514 1515 /* 1516 * If we haven't received any packets in FXP_MAX_RX_IDLE seconds, 1517 * then assume the receiver has locked up and attempt to clear 1518 * the condition by reprogramming the multicast filter (actually, 1519 * resetting the interface). This is a work-around for a bug in 1520 * the 82557 where the receiver locks up if it gets certain types 1521 * of garbage in the synchronization bits prior to the packet header. 1522 * This bug is supposed to only occur in 10Mbps mode, but has been 1523 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1524 * speed transition). 1525 */ 1526 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1527 (void) fxp_init(ifp); 1528 splx(s); 1529 return; 1530 } 1531 /* 1532 * If there is no pending command, start another stats 1533 * dump. Otherwise punt for now. 1534 */ 1535 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1536 /* 1537 * Start another stats dump. 1538 */ 1539 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1540 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1541 } else { 1542 /* 1543 * A previous command is still waiting to be accepted. 1544 * Just zero our copy of the stats and wait for the 1545 * next timer event to update them. 1546 */ 1547 /* BIG_ENDIAN: no swap required to store 0 */ 1548 sp->tx_good = 0; 1549 sp->tx_underruns = 0; 1550 sp->tx_total_collisions = 0; 1551 1552 sp->rx_good = 0; 1553 sp->rx_crc_errors = 0; 1554 sp->rx_alignment_errors = 0; 1555 sp->rx_rnr_errors = 0; 1556 sp->rx_overrun_errors = 0; 1557 if (sc->sc_flags & FXPF_FC) { 1558 sp->tx_pauseframes = 0; 1559 sp->rx_pauseframes = 0; 1560 } 1561 } 1562 1563 if (sc->sc_flags & FXPF_MII) { 1564 /* Tick the MII clock. */ 1565 mii_tick(&sc->sc_mii); 1566 } 1567 1568 splx(s); 1569 1570 /* 1571 * Schedule another timeout one second from now. 1572 */ 1573 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1574} 1575 1576/* 1577 * Drain the receive queue. 1578 */ 1579void 1580fxp_rxdrain(struct fxp_softc *sc) 1581{ 1582 bus_dmamap_t rxmap; 1583 struct mbuf *m; 1584 1585 for (;;) { 1586 IF_DEQUEUE(&sc->sc_rxq, m); 1587 if (m == NULL) 1588 break; 1589 rxmap = M_GETCTX(m, bus_dmamap_t); 1590 bus_dmamap_unload(sc->sc_dmat, rxmap); 1591 FXP_RXMAP_PUT(sc, rxmap); 1592 m_freem(m); 1593 } 1594} 1595 1596/* 1597 * Stop the interface. Cancels the statistics updater and resets 1598 * the interface. 1599 */ 1600void 1601fxp_stop(struct ifnet *ifp, int disable) 1602{ 1603 struct fxp_softc *sc = ifp->if_softc; 1604 struct fxp_txsoft *txs; 1605 int i; 1606 1607 /* 1608 * Turn down interface (done early to avoid bad interactions 1609 * between panics, shutdown hooks, and the watchdog timer) 1610 */ 1611 ifp->if_timer = 0; 1612 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1613 1614 /* 1615 * Cancel stats updater. 1616 */ 1617 callout_stop(&sc->sc_callout); 1618 if (sc->sc_flags & FXPF_MII) { 1619 /* Down the MII. */ 1620 mii_down(&sc->sc_mii); 1621 } 1622 1623 /* 1624 * Issue software reset. This unloads any microcode that 1625 * might already be loaded. 1626 */ 1627 sc->sc_flags &= ~FXPF_UCODE_LOADED; 1628 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1629 DELAY(50); 1630 1631 /* 1632 * Release any xmit buffers. 1633 */ 1634 for (i = 0; i < FXP_NTXCB; i++) { 1635 txs = FXP_DSTX(sc, i); 1636 if (txs->txs_mbuf != NULL) { 1637 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1638 m_freem(txs->txs_mbuf); 1639 txs->txs_mbuf = NULL; 1640 } 1641 } 1642 sc->sc_txpending = 0; 1643 1644 if (disable) { 1645 fxp_rxdrain(sc); 1646 fxp_disable(sc); 1647 } 1648 1649} 1650 1651/* 1652 * Watchdog/transmission transmit timeout handler. Called when a 1653 * transmission is started on the interface, but no interrupt is 1654 * received before the timeout. This usually indicates that the 1655 * card has wedged for some reason. 1656 */ 1657void 1658fxp_watchdog(struct ifnet *ifp) 1659{ 1660 struct fxp_softc *sc = ifp->if_softc; 1661 1662 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1663 ifp->if_oerrors++; 1664 1665 (void) fxp_init(ifp); 1666} 1667 1668/* 1669 * Initialize the interface. Must be called at splnet(). 1670 */ 1671int 1672fxp_init(struct ifnet *ifp) 1673{ 1674 struct fxp_softc *sc = ifp->if_softc; 1675 struct fxp_cb_config *cbp; 1676 struct fxp_cb_ias *cb_ias; 1677 struct fxp_txdesc *txd; 1678 bus_dmamap_t rxmap; 1679 int i, prm, save_bf, lrxen, vlan_drop, allm, error = 0; 1680 uint16_t status; 1681 1682 if ((error = fxp_enable(sc)) != 0) 1683 goto out; 1684 1685 /* 1686 * Cancel any pending I/O 1687 */ 1688 fxp_stop(ifp, 0); 1689 1690 /* 1691 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1692 * flag, and this prevents the MII from detaching resulting in 1693 * a panic. The flags field should perhaps be split in runtime 1694 * flags and more static information. For now, just clear the 1695 * only other flag set. 1696 */ 1697 1698 sc->sc_flags &= ~FXPF_WANTINIT; 1699 1700 /* 1701 * Initialize base of CBL and RFA memory. Loading with zero 1702 * sets it up for regular linear addressing. 1703 */ 1704 fxp_scb_wait(sc); 1705 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1706 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1707 1708 fxp_scb_wait(sc); 1709 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1710 1711 /* 1712 * Initialize the multicast filter. Do this now, since we might 1713 * have to setup the config block differently. 1714 */ 1715 fxp_mc_setup(sc); 1716 1717 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1718 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1719 1720 /* 1721 * In order to support receiving 802.1Q VLAN frames, we have to 1722 * enable "save bad frames", since they are 4 bytes larger than 1723 * the normal Ethernet maximum frame length. On i82558 and later, 1724 * we have a better mechanism for this. 1725 */ 1726 save_bf = 0; 1727 lrxen = 0; 1728 vlan_drop = 0; 1729 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1730 if (sc->sc_rev < FXP_REV_82558_A4) 1731 save_bf = 1; 1732 else 1733 lrxen = 1; 1734 if (sc->sc_rev >= FXP_REV_82550) 1735 vlan_drop = 1; 1736 } 1737 1738 /* 1739 * Initialize base of dump-stats buffer. 1740 */ 1741 fxp_scb_wait(sc); 1742 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1743 sc->sc_cddma + FXP_CDSTATSOFF); 1744 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1745 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1746 1747 cbp = &sc->sc_control_data->fcd_configcb; 1748 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1749 1750 /* 1751 * Load microcode for this controller. 1752 */ 1753 fxp_load_ucode(sc); 1754 1755 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK1)) 1756 sc->sc_flags |= FXPF_RECV_WORKAROUND; 1757 else 1758 sc->sc_flags &= ~FXPF_RECV_WORKAROUND; 1759 1760 /* 1761 * This copy is kind of disgusting, but there are a bunch of must be 1762 * zero and must be one bits in this structure and this is the easiest 1763 * way to initialize them all to proper values. 1764 */ 1765 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1766 1767 /* BIG_ENDIAN: no need to swap to store 0 */ 1768 cbp->cb_status = 0; 1769 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1770 FXP_CB_COMMAND_EL); 1771 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1772 cbp->link_addr = 0xffffffff; /* (no) next command */ 1773 /* bytes in config block */ 1774 cbp->byte_count = (sc->sc_flags & FXPF_EXT_RFA) ? 1775 FXP_EXT_CONFIG_LEN : FXP_CONFIG_LEN; 1776 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1777 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1778 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1779 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1780 cbp->type_enable = 0; /* actually reserved */ 1781 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1782 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1783 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1784 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1785 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1786 cbp->late_scb = 0; /* (don't) defer SCB update */ 1787 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1788 cbp->ci_int = 1; /* interrupt on CU idle */ 1789 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1790 cbp->ext_stats_dis = 1; /* disable extended counters */ 1791 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1792 cbp->save_bf = save_bf;/* save bad frames */ 1793 cbp->disc_short_rx = !prm; /* discard short packets */ 1794 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1795 cbp->ext_rfa = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1796 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1797 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1798 /* interface mode */ 1799 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1800 cbp->csma_dis = 0; /* (don't) disable link */ 1801 cbp->tcp_udp_cksum = (sc->sc_flags & FXPF_82559_RXCSUM) ? 1 : 0; 1802 /* (don't) enable RX checksum */ 1803 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1804 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1805 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1806 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1807 cbp->nsai = 1; /* (don't) disable source addr insert */ 1808 cbp->preamble_length = 2; /* (7 byte) preamble */ 1809 cbp->loopback = 0; /* (don't) loopback */ 1810 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1811 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1812 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1813 cbp->promiscuous = prm; /* promiscuous mode */ 1814 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1815 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1816 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1817 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1818 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1819 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1820 cbp->padding = 1; /* (do) pad short tx packets */ 1821 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1822 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1823 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1824 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1825 /* must set wake_en in PMCSR also */ 1826 cbp->force_fdx = 0; /* (don't) force full duplex */ 1827 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1828 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1829 cbp->mc_all = allm; /* accept all multicasts */ 1830 cbp->ext_rx_mode = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1831 cbp->vlan_drop_en = vlan_drop; 1832 1833 if (!(sc->sc_flags & FXPF_FC)) { 1834 /* 1835 * The i82557 has no hardware flow control, the values 1836 * here are the defaults for the chip. 1837 */ 1838 cbp->fc_delay_lsb = 0; 1839 cbp->fc_delay_msb = 0x40; 1840 cbp->pri_fc_thresh = 3; 1841 cbp->tx_fc_dis = 0; 1842 cbp->rx_fc_restop = 0; 1843 cbp->rx_fc_restart = 0; 1844 cbp->fc_filter = 0; 1845 cbp->pri_fc_loc = 1; 1846 } else { 1847 cbp->fc_delay_lsb = 0x1f; 1848 cbp->fc_delay_msb = 0x01; 1849 cbp->pri_fc_thresh = 3; 1850 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1851 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1852 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1853 cbp->fc_filter = !prm; /* drop FC frames to host */ 1854 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1855 cbp->ext_stats_dis = 0; /* enable extended stats */ 1856 } 1857 1858 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1859 1860 /* 1861 * Start the config command/DMA. 1862 */ 1863 fxp_scb_wait(sc); 1864 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1865 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1866 /* ...and wait for it to complete. */ 1867 for (i = 1000; i > 0; i--) { 1868 FXP_CDCONFIGSYNC(sc, 1869 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1870 status = le16toh(cbp->cb_status); 1871 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD); 1872 if ((status & FXP_CB_STATUS_C) != 0) 1873 break; 1874 DELAY(1); 1875 } 1876 if (i == 0) { 1877 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1878 device_xname(sc->sc_dev), __LINE__); 1879 return (ETIMEDOUT); 1880 } 1881 1882 /* 1883 * Initialize the station address. 1884 */ 1885 cb_ias = &sc->sc_control_data->fcd_iascb; 1886 /* BIG_ENDIAN: no need to swap to store 0 */ 1887 cb_ias->cb_status = 0; 1888 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1889 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1890 cb_ias->link_addr = 0xffffffff; 1891 memcpy(cb_ias->macaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1892 1893 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1894 1895 /* 1896 * Start the IAS (Individual Address Setup) command/DMA. 1897 */ 1898 fxp_scb_wait(sc); 1899 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1900 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1901 /* ...and wait for it to complete. */ 1902 for (i = 1000; i > 0; i++) { 1903 FXP_CDIASSYNC(sc, 1904 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1905 status = le16toh(cb_ias->cb_status); 1906 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD); 1907 if ((status & FXP_CB_STATUS_C) != 0) 1908 break; 1909 DELAY(1); 1910 } 1911 if (i == 0) { 1912 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1913 device_xname(sc->sc_dev), __LINE__); 1914 return (ETIMEDOUT); 1915 } 1916 1917 /* 1918 * Initialize the transmit descriptor ring. txlast is initialized 1919 * to the end of the list so that it will wrap around to the first 1920 * descriptor when the first packet is transmitted. 1921 */ 1922 for (i = 0; i < FXP_NTXCB; i++) { 1923 txd = FXP_CDTX(sc, i); 1924 memset(txd, 0, sizeof(*txd)); 1925 txd->txd_txcb.cb_command = 1926 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1927 txd->txd_txcb.link_addr = 1928 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1929 if (sc->sc_flags & FXPF_EXT_TXCB) 1930 txd->txd_txcb.tbd_array_addr = 1931 htole32(FXP_CDTBDADDR(sc, i) + 1932 (2 * sizeof(struct fxp_tbd))); 1933 else 1934 txd->txd_txcb.tbd_array_addr = 1935 htole32(FXP_CDTBDADDR(sc, i)); 1936 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1937 } 1938 sc->sc_txpending = 0; 1939 sc->sc_txdirty = 0; 1940 sc->sc_txlast = FXP_NTXCB - 1; 1941 1942 /* 1943 * Initialize the receive buffer list. 1944 */ 1945 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1946 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1947 rxmap = FXP_RXMAP_GET(sc); 1948 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1949 log(LOG_ERR, "%s: unable to allocate or map rx " 1950 "buffer %d, error = %d\n", 1951 device_xname(sc->sc_dev), 1952 sc->sc_rxq.ifq_len, error); 1953 /* 1954 * XXX Should attempt to run with fewer receive 1955 * XXX buffers instead of just failing. 1956 */ 1957 FXP_RXMAP_PUT(sc, rxmap); 1958 fxp_rxdrain(sc); 1959 goto out; 1960 } 1961 } 1962 sc->sc_rxidle = 0; 1963 1964 /* 1965 * Give the transmit ring to the chip. We do this by pointing 1966 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1967 * issuing a start command. It will execute the NOP and then 1968 * suspend, pointing at the first descriptor. 1969 */ 1970 fxp_scb_wait(sc); 1971 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1972 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1973 1974 /* 1975 * Initialize receiver buffer area - RFA. 1976 */ 1977#if 0 /* initialization will be done by FXP_SCB_INTRCNTL_REQUEST_SWI later */ 1978 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1979 fxp_scb_wait(sc); 1980 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1981 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1982 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1983#endif 1984 1985 if (sc->sc_flags & FXPF_MII) { 1986 /* 1987 * Set current media. 1988 */ 1989 if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0) 1990 goto out; 1991 } 1992 1993 /* 1994 * ...all done! 1995 */ 1996 ifp->if_flags |= IFF_RUNNING; 1997 ifp->if_flags &= ~IFF_OACTIVE; 1998 1999 /* 2000 * Request a software generated interrupt that will be used to 2001 * (re)start the RU processing. If we direct the chip to start 2002 * receiving from the start of queue now, instead of letting the 2003 * interrupt handler first process all received packets, we run 2004 * the risk of having it overwrite mbuf clusters while they are 2005 * being processed or after they have been returned to the pool. 2006 */ 2007 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTRCNTL_REQUEST_SWI); 2008 2009 /* 2010 * Start the one second timer. 2011 */ 2012 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 2013 2014 /* 2015 * Attempt to start output on the interface. 2016 */ 2017 fxp_start(ifp); 2018 2019 out: 2020 if (error) { 2021 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2022 ifp->if_timer = 0; 2023 log(LOG_ERR, "%s: interface not running\n", 2024 device_xname(sc->sc_dev)); 2025 } 2026 return (error); 2027} 2028 2029/* 2030 * Notify the world which media we're using. 2031 */ 2032void 2033fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2034{ 2035 struct fxp_softc *sc = ifp->if_softc; 2036 2037 if (sc->sc_enabled == 0) { 2038 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 2039 ifmr->ifm_status = 0; 2040 return; 2041 } 2042 2043 ether_mediastatus(ifp, ifmr); 2044} 2045 2046int 2047fxp_80c24_mediachange(struct ifnet *ifp) 2048{ 2049 2050 /* Nothing to do here. */ 2051 return (0); 2052} 2053 2054void 2055fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2056{ 2057 struct fxp_softc *sc = ifp->if_softc; 2058 2059 /* 2060 * Media is currently-selected media. We cannot determine 2061 * the link status. 2062 */ 2063 ifmr->ifm_status = 0; 2064 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 2065} 2066 2067/* 2068 * Add a buffer to the end of the RFA buffer list. 2069 * Return 0 if successful, error code on failure. 2070 * 2071 * The RFA struct is stuck at the beginning of mbuf cluster and the 2072 * data pointer is fixed up to point just past it. 2073 */ 2074int 2075fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 2076{ 2077 struct mbuf *m; 2078 int error; 2079 2080 MGETHDR(m, M_DONTWAIT, MT_DATA); 2081 if (m == NULL) 2082 return (ENOBUFS); 2083 2084 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2085 MCLGET(m, M_DONTWAIT); 2086 if ((m->m_flags & M_EXT) == 0) { 2087 m_freem(m); 2088 return (ENOBUFS); 2089 } 2090 2091 if (unload) 2092 bus_dmamap_unload(sc->sc_dmat, rxmap); 2093 2094 M_SETCTX(m, rxmap); 2095 2096 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2097 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, 2098 BUS_DMA_READ|BUS_DMA_NOWAIT); 2099 if (error) { 2100 /* XXX XXX XXX */ 2101 aprint_error_dev(sc->sc_dev, 2102 "can't load rx DMA map %d, error = %d\n", 2103 sc->sc_rxq.ifq_len, error); 2104 panic("fxp_add_rfabuf"); 2105 } 2106 2107 FXP_INIT_RFABUF(sc, m); 2108 2109 return (0); 2110} 2111 2112int 2113fxp_mdi_read(device_t self, int phy, int reg) 2114{ 2115 struct fxp_softc *sc = device_private(self); 2116 int count = 10000; 2117 int value; 2118 2119 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2120 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2121 2122 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 2123 0x10000000) == 0 && count--) 2124 DELAY(10); 2125 2126 if (count <= 0) 2127 log(LOG_WARNING, 2128 "%s: fxp_mdi_read: timed out\n", device_xname(self)); 2129 2130 return (value & 0xffff); 2131} 2132 2133void 2134fxp_statchg(struct ifnet *ifp) 2135{ 2136 2137 /* Nothing to do. */ 2138} 2139 2140void 2141fxp_mdi_write(device_t self, int phy, int reg, int value) 2142{ 2143 struct fxp_softc *sc = device_private(self); 2144 int count = 10000; 2145 2146 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2147 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2148 (value & 0xffff)); 2149 2150 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2151 count--) 2152 DELAY(10); 2153 2154 if (count <= 0) 2155 log(LOG_WARNING, 2156 "%s: fxp_mdi_write: timed out\n", device_xname(self)); 2157} 2158 2159int 2160fxp_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2161{ 2162 struct fxp_softc *sc = ifp->if_softc; 2163 struct ifreq *ifr = (struct ifreq *)data; 2164 int s, error; 2165 2166 s = splnet(); 2167 2168 switch (cmd) { 2169 case SIOCSIFMEDIA: 2170 case SIOCGIFMEDIA: 2171 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2172 break; 2173 2174 default: 2175 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 2176 break; 2177 2178 error = 0; 2179 2180 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2181 ; 2182 else if (ifp->if_flags & IFF_RUNNING) { 2183 /* 2184 * Multicast list has changed; set the 2185 * hardware filter accordingly. 2186 */ 2187 while (sc->sc_txpending) { 2188 sc->sc_flags |= FXPF_WANTINIT; 2189 tsleep(sc, PSOCK, "fxp_init", 0); 2190 } 2191 error = fxp_init(ifp); 2192 } 2193 break; 2194 } 2195 2196 /* Try to get more packets going. */ 2197 if (sc->sc_enabled) 2198 fxp_start(ifp); 2199 2200 splx(s); 2201 return (error); 2202} 2203 2204/* 2205 * Program the multicast filter. 2206 * 2207 * This function must be called at splnet(). 2208 */ 2209void 2210fxp_mc_setup(struct fxp_softc *sc) 2211{ 2212 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 2213 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2214 struct ethercom *ec = &sc->sc_ethercom; 2215 struct ether_multi *enm; 2216 struct ether_multistep step; 2217 int count, nmcasts; 2218 uint16_t status; 2219 2220#ifdef DIAGNOSTIC 2221 if (sc->sc_txpending) 2222 panic("fxp_mc_setup: pending transmissions"); 2223#endif 2224 2225 2226 if (ifp->if_flags & IFF_PROMISC) { 2227 ifp->if_flags |= IFF_ALLMULTI; 2228 return; 2229 } else { 2230 ifp->if_flags &= ~IFF_ALLMULTI; 2231 } 2232 2233 /* 2234 * Initialize multicast setup descriptor. 2235 */ 2236 nmcasts = 0; 2237 ETHER_FIRST_MULTI(step, ec, enm); 2238 while (enm != NULL) { 2239 /* 2240 * Check for too many multicast addresses or if we're 2241 * listening to a range. Either way, we simply have 2242 * to accept all multicasts. 2243 */ 2244 if (nmcasts >= MAXMCADDR || 2245 memcmp(enm->enm_addrlo, enm->enm_addrhi, 2246 ETHER_ADDR_LEN) != 0) { 2247 /* 2248 * Callers of this function must do the 2249 * right thing with this. If we're called 2250 * from outside fxp_init(), the caller must 2251 * detect if the state if IFF_ALLMULTI changes. 2252 * If it does, the caller must then call 2253 * fxp_init(), since allmulti is handled by 2254 * the config block. 2255 */ 2256 ifp->if_flags |= IFF_ALLMULTI; 2257 return; 2258 } 2259 memcpy(&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 2260 ETHER_ADDR_LEN); 2261 nmcasts++; 2262 ETHER_NEXT_MULTI(step, enm); 2263 } 2264 2265 /* BIG_ENDIAN: no need to swap to store 0 */ 2266 mcsp->cb_status = 0; 2267 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2268 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 2269 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2270 2271 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2272 2273 /* 2274 * Wait until the command unit is not active. This should never 2275 * happen since nothing is queued, but make sure anyway. 2276 */ 2277 count = 100; 2278 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2279 FXP_SCB_CUS_ACTIVE && --count) 2280 DELAY(1); 2281 if (count == 0) { 2282 log(LOG_WARNING, "%s: line %d: command queue timeout\n", 2283 device_xname(sc->sc_dev), __LINE__); 2284 return; 2285 } 2286 2287 /* 2288 * Start the multicast setup command/DMA. 2289 */ 2290 fxp_scb_wait(sc); 2291 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2292 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2293 2294 /* ...and wait for it to complete. */ 2295 for (count = 1000; count > 0; count--) { 2296 FXP_CDMCSSYNC(sc, 2297 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2298 status = le16toh(mcsp->cb_status); 2299 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD); 2300 if ((status & FXP_CB_STATUS_C) != 0) 2301 break; 2302 DELAY(1); 2303 } 2304 if (count == 0) { 2305 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 2306 device_xname(sc->sc_dev), __LINE__); 2307 return; 2308 } 2309} 2310 2311static const uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2312static const uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2313static const uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2314static const uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2315static const uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2316static const uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2317static const uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE; 2318 2319#define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2320 2321static const struct ucode { 2322 int32_t revision; 2323 const uint32_t *ucode; 2324 size_t length; 2325 uint16_t int_delay_offset; 2326 uint16_t bundle_max_offset; 2327} ucode_table[] = { 2328 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), 2329 D101_CPUSAVER_DWORD, 0 }, 2330 2331 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), 2332 D101_CPUSAVER_DWORD, 0 }, 2333 2334 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2335 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2336 2337 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2338 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2339 2340 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2341 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2342 2343 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2344 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2345 2346 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e), 2347 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 2348 2349 { FXP_REV_82551_10, UCODE(fxp_ucode_d102e), 2350 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 2351 2352 { 0, NULL, 0, 0, 0 } 2353}; 2354 2355void 2356fxp_load_ucode(struct fxp_softc *sc) 2357{ 2358 const struct ucode *uc; 2359 struct fxp_cb_ucode *cbp = &sc->sc_control_data->fcd_ucode; 2360 int count, i; 2361 uint16_t status; 2362 2363 if (sc->sc_flags & FXPF_UCODE_LOADED) 2364 return; 2365 2366 /* 2367 * Only load the uCode if the user has requested that 2368 * we do so. 2369 */ 2370 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK0) == 0) { 2371 sc->sc_int_delay = 0; 2372 sc->sc_bundle_max = 0; 2373 return; 2374 } 2375 2376 for (uc = ucode_table; uc->ucode != NULL; uc++) { 2377 if (sc->sc_rev == uc->revision) 2378 break; 2379 } 2380 if (uc->ucode == NULL) 2381 return; 2382 2383 /* BIG ENDIAN: no need to swap to store 0 */ 2384 cbp->cb_status = 0; 2385 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2386 cbp->link_addr = 0xffffffff; /* (no) next command */ 2387 for (i = 0; i < uc->length; i++) 2388 cbp->ucode[i] = htole32(uc->ucode[i]); 2389 2390 if (uc->int_delay_offset) 2391 *(volatile uint16_t *) &cbp->ucode[uc->int_delay_offset] = 2392 htole16(fxp_int_delay + (fxp_int_delay / 2)); 2393 2394 if (uc->bundle_max_offset) 2395 *(volatile uint16_t *) &cbp->ucode[uc->bundle_max_offset] = 2396 htole16(fxp_bundle_max); 2397 2398 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2399 2400 /* 2401 * Download the uCode to the chip. 2402 */ 2403 fxp_scb_wait(sc); 2404 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDUCODEOFF); 2405 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2406 2407 /* ...and wait for it to complete. */ 2408 for (count = 10000; count > 0; count--) { 2409 FXP_CDUCODESYNC(sc, 2410 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2411 status = le16toh(cbp->cb_status); 2412 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD); 2413 if ((status & FXP_CB_STATUS_C) != 0) 2414 break; 2415 DELAY(2); 2416 } 2417 if (count == 0) { 2418 sc->sc_int_delay = 0; 2419 sc->sc_bundle_max = 0; 2420 log(LOG_WARNING, "%s: timeout loading microcode\n", 2421 device_xname(sc->sc_dev)); 2422 return; 2423 } 2424 2425 if (sc->sc_int_delay != fxp_int_delay || 2426 sc->sc_bundle_max != fxp_bundle_max) { 2427 sc->sc_int_delay = fxp_int_delay; 2428 sc->sc_bundle_max = fxp_bundle_max; 2429 log(LOG_INFO, "%s: Microcode loaded: int delay: %d usec, " 2430 "max bundle: %d\n", device_xname(sc->sc_dev), 2431 sc->sc_int_delay, 2432 uc->bundle_max_offset == 0 ? 0 : sc->sc_bundle_max); 2433 } 2434 2435 sc->sc_flags |= FXPF_UCODE_LOADED; 2436} 2437 2438int 2439fxp_enable(struct fxp_softc *sc) 2440{ 2441 2442 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2443 if ((*sc->sc_enable)(sc) != 0) { 2444 log(LOG_ERR, "%s: device enable failed\n", 2445 device_xname(sc->sc_dev)); 2446 return (EIO); 2447 } 2448 } 2449 2450 sc->sc_enabled = 1; 2451 return (0); 2452} 2453 2454void 2455fxp_disable(struct fxp_softc *sc) 2456{ 2457 2458 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2459 (*sc->sc_disable)(sc); 2460 sc->sc_enabled = 0; 2461 } 2462} 2463 2464/* 2465 * fxp_activate: 2466 * 2467 * Handle device activation/deactivation requests. 2468 */ 2469int 2470fxp_activate(device_t self, enum devact act) 2471{ 2472 struct fxp_softc *sc = device_private(self); 2473 2474 switch (act) { 2475 case DVACT_DEACTIVATE: 2476 if_deactivate(&sc->sc_ethercom.ec_if); 2477 return 0; 2478 default: 2479 return EOPNOTSUPP; 2480 } 2481} 2482 2483/* 2484 * fxp_detach: 2485 * 2486 * Detach an i82557 interface. 2487 */ 2488int 2489fxp_detach(struct fxp_softc *sc, int flags) 2490{ 2491 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2492 int i, s; 2493 2494 /* Succeed now if there's no work to do. */ 2495 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2496 return (0); 2497 2498 s = splnet(); 2499 /* Stop the interface. Callouts are stopped in it. */ 2500 fxp_stop(ifp, 1); 2501 splx(s); 2502 2503 /* Destroy our callout. */ 2504 callout_destroy(&sc->sc_callout); 2505 2506 if (sc->sc_flags & FXPF_MII) { 2507 /* Detach all PHYs */ 2508 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2509 } 2510 2511 /* Delete all remaining media. */ 2512 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2513 2514 rnd_detach_source(&sc->rnd_source); 2515 ether_ifdetach(ifp); 2516 if_detach(ifp); 2517 2518 for (i = 0; i < FXP_NRFABUFS; i++) { 2519 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2520 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2521 } 2522 2523 for (i = 0; i < FXP_NTXCB; i++) { 2524 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2525 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2526 } 2527 2528 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2529 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2530 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 2531 sizeof(struct fxp_control_data)); 2532 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2533 2534 return (0); 2535} 2536