i82557.c revision 1.126
1/* $NetBSD: i82557.c,v 1.126 2009/03/09 10:33:33 tsutsui Exp $ */ 2 3/*- 4 * Copyright (c) 1997, 1998, 1999, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Copyright (c) 1995, David Greenman 35 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice unmodified, this list of conditions, and the following 43 * disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 61 */ 62 63/* 64 * Device driver for the Intel i82557 fast Ethernet controller, 65 * and its successors, the i82558 and i82559. 66 */ 67 68#include <sys/cdefs.h> 69__KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.126 2009/03/09 10:33:33 tsutsui Exp $"); 70 71#include "bpfilter.h" 72#include "rnd.h" 73 74#include <sys/param.h> 75#include <sys/systm.h> 76#include <sys/callout.h> 77#include <sys/mbuf.h> 78#include <sys/malloc.h> 79#include <sys/kernel.h> 80#include <sys/socket.h> 81#include <sys/ioctl.h> 82#include <sys/errno.h> 83#include <sys/device.h> 84#include <sys/syslog.h> 85 86#include <machine/endian.h> 87 88#include <uvm/uvm_extern.h> 89 90#if NRND > 0 91#include <sys/rnd.h> 92#endif 93 94#include <net/if.h> 95#include <net/if_dl.h> 96#include <net/if_media.h> 97#include <net/if_ether.h> 98 99#include <netinet/in.h> 100#include <netinet/in_systm.h> 101#include <netinet/ip.h> 102#include <netinet/tcp.h> 103#include <netinet/udp.h> 104 105#if NBPFILTER > 0 106#include <net/bpf.h> 107#endif 108 109#include <sys/bus.h> 110#include <sys/intr.h> 111 112#include <dev/mii/miivar.h> 113 114#include <dev/ic/i82557reg.h> 115#include <dev/ic/i82557var.h> 116 117#include <dev/microcode/i8255x/rcvbundl.h> 118 119/* 120 * NOTE! On the Alpha, we have an alignment constraint. The 121 * card DMAs the packet immediately following the RFA. However, 122 * the first thing in the packet is a 14-byte Ethernet header. 123 * This means that the packet is misaligned. To compensate, 124 * we actually offset the RFA 2 bytes into the cluster. This 125 * alignes the packet after the Ethernet header at a 32-bit 126 * boundary. HOWEVER! This means that the RFA is misaligned! 127 */ 128#define RFA_ALIGNMENT_FUDGE 2 129 130/* 131 * The configuration byte map has several undefined fields which 132 * must be one or must be zero. Set up a template for these bits 133 * only (assuming an i82557 chip), leaving the actual configuration 134 * for fxp_init(). 135 * 136 * See the definition of struct fxp_cb_config for the bit definitions. 137 */ 138const u_int8_t fxp_cb_config_template[] = { 139 0x0, 0x0, /* cb_status */ 140 0x0, 0x0, /* cb_command */ 141 0x0, 0x0, 0x0, 0x0, /* link_addr */ 142 0x0, /* 0 */ 143 0x0, /* 1 */ 144 0x0, /* 2 */ 145 0x0, /* 3 */ 146 0x0, /* 4 */ 147 0x0, /* 5 */ 148 0x32, /* 6 */ 149 0x0, /* 7 */ 150 0x0, /* 8 */ 151 0x0, /* 9 */ 152 0x6, /* 10 */ 153 0x0, /* 11 */ 154 0x0, /* 12 */ 155 0x0, /* 13 */ 156 0xf2, /* 14 */ 157 0x48, /* 15 */ 158 0x0, /* 16 */ 159 0x40, /* 17 */ 160 0xf0, /* 18 */ 161 0x0, /* 19 */ 162 0x3f, /* 20 */ 163 0x5, /* 21 */ 164 0x0, /* 22 */ 165 0x0, /* 23 */ 166 0x0, /* 24 */ 167 0x0, /* 25 */ 168 0x0, /* 26 */ 169 0x0, /* 27 */ 170 0x0, /* 28 */ 171 0x0, /* 29 */ 172 0x0, /* 30 */ 173 0x0, /* 31 */ 174}; 175 176void fxp_mii_initmedia(struct fxp_softc *); 177void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 178 179void fxp_80c24_initmedia(struct fxp_softc *); 180int fxp_80c24_mediachange(struct ifnet *); 181void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 182 183void fxp_start(struct ifnet *); 184int fxp_ioctl(struct ifnet *, u_long, void *); 185void fxp_watchdog(struct ifnet *); 186int fxp_init(struct ifnet *); 187void fxp_stop(struct ifnet *, int); 188 189void fxp_txintr(struct fxp_softc *); 190int fxp_rxintr(struct fxp_softc *); 191 192void fxp_rx_hwcksum(struct fxp_softc *,struct mbuf *, 193 const struct fxp_rfa *, u_int); 194 195void fxp_rxdrain(struct fxp_softc *); 196int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 197int fxp_mdi_read(device_t, int, int); 198void fxp_statchg(device_t); 199void fxp_mdi_write(device_t, int, int, int); 200void fxp_autosize_eeprom(struct fxp_softc*); 201void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 202void fxp_write_eeprom(struct fxp_softc *, u_int16_t *, int, int); 203void fxp_eeprom_update_cksum(struct fxp_softc *); 204void fxp_get_info(struct fxp_softc *, u_int8_t *); 205void fxp_tick(void *); 206void fxp_mc_setup(struct fxp_softc *); 207void fxp_load_ucode(struct fxp_softc *); 208 209int fxp_copy_small = 0; 210 211/* 212 * Variables for interrupt mitigating microcode. 213 */ 214int fxp_int_delay = 1000; /* usec */ 215int fxp_bundle_max = 6; /* packets */ 216 217struct fxp_phytype { 218 int fp_phy; /* type of PHY, -1 for MII at the end. */ 219 void (*fp_init)(struct fxp_softc *); 220} fxp_phytype_table[] = { 221 { FXP_PHY_80C24, fxp_80c24_initmedia }, 222 { -1, fxp_mii_initmedia }, 223}; 224 225/* 226 * Set initial transmit threshold at 64 (512 bytes). This is 227 * increased by 64 (512 bytes) at a time, to maximum of 192 228 * (1536 bytes), if an underrun occurs. 229 */ 230static int tx_threshold = 64; 231 232/* 233 * Wait for the previous command to be accepted (but not necessarily 234 * completed). 235 */ 236static inline void 237fxp_scb_wait(struct fxp_softc *sc) 238{ 239 int i = 10000; 240 241 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 242 delay(2); 243 if (i == 0) 244 log(LOG_WARNING, 245 "%s: WARNING: SCB timed out!\n", device_xname(sc->sc_dev)); 246} 247 248/* 249 * Submit a command to the i82557. 250 */ 251static inline void 252fxp_scb_cmd(struct fxp_softc *sc, u_int8_t cmd) 253{ 254 255 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 256} 257 258/* 259 * Finish attaching an i82557 interface. Called by bus-specific front-end. 260 */ 261void 262fxp_attach(struct fxp_softc *sc) 263{ 264 u_int8_t enaddr[ETHER_ADDR_LEN]; 265 struct ifnet *ifp; 266 bus_dma_segment_t seg; 267 int rseg, i, error; 268 struct fxp_phytype *fp; 269 270 callout_init(&sc->sc_callout, 0); 271 272 /* 273 * Enable use of extended RFDs and TCBs for 82550 274 * and later chips. Note: we need extended TXCB support 275 * too, but that's already enabled by the code above. 276 * Be careful to do this only on the right devices. 277 */ 278 if (sc->sc_flags & FXPF_EXT_RFA) 279 sc->sc_txcmd = htole16(FXP_CB_COMMAND_IPCBXMIT); 280 else 281 sc->sc_txcmd = htole16(FXP_CB_COMMAND_XMIT); 282 283 sc->sc_rfa_size = 284 (sc->sc_flags & FXPF_EXT_RFA) ? RFA_EXT_SIZE : RFA_SIZE; 285 286 /* 287 * Allocate the control data structures, and create and load the 288 * DMA map for it. 289 */ 290 if ((error = bus_dmamem_alloc(sc->sc_dmat, 291 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 292 0)) != 0) { 293 aprint_error_dev(sc->sc_dev, 294 "unable to allocate control data, error = %d\n", 295 error); 296 goto fail_0; 297 } 298 299 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 300 sizeof(struct fxp_control_data), (void **)&sc->sc_control_data, 301 BUS_DMA_COHERENT)) != 0) { 302 aprint_error_dev(sc->sc_dev, 303 "unable to map control data, error = %d\n", error); 304 goto fail_1; 305 } 306 sc->sc_cdseg = seg; 307 sc->sc_cdnseg = rseg; 308 309 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 310 311 if ((error = bus_dmamap_create(sc->sc_dmat, 312 sizeof(struct fxp_control_data), 1, 313 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 314 aprint_error_dev(sc->sc_dev, 315 "unable to create control data DMA map, error = %d\n", 316 error); 317 goto fail_2; 318 } 319 320 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 321 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 322 0)) != 0) { 323 aprint_error_dev(sc->sc_dev, 324 "can't load control data DMA map, error = %d\n", 325 error); 326 goto fail_3; 327 } 328 329 /* 330 * Create the transmit buffer DMA maps. 331 */ 332 for (i = 0; i < FXP_NTXCB; i++) { 333 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 334 (sc->sc_flags & FXPF_EXT_RFA) ? 335 FXP_IPCB_NTXSEG : FXP_NTXSEG, 336 MCLBYTES, 0, 0, &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 337 aprint_error_dev(sc->sc_dev, 338 "unable to create tx DMA map %d, error = %d\n", 339 i, error); 340 goto fail_4; 341 } 342 } 343 344 /* 345 * Create the receive buffer DMA maps. 346 */ 347 for (i = 0; i < FXP_NRFABUFS; i++) { 348 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 349 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 350 aprint_error_dev(sc->sc_dev, 351 "unable to create rx DMA map %d, error = %d\n", 352 i, error); 353 goto fail_5; 354 } 355 } 356 357 /* Initialize MAC address and media structures. */ 358 fxp_get_info(sc, enaddr); 359 360 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 361 ether_sprintf(enaddr)); 362 363 ifp = &sc->sc_ethercom.ec_if; 364 365 /* 366 * Get info about our media interface, and initialize it. Note 367 * the table terminates itself with a phy of -1, indicating 368 * that we're using MII. 369 */ 370 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 371 if (fp->fp_phy == sc->phy_primary_device) 372 break; 373 (*fp->fp_init)(sc); 374 375 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 376 ifp->if_softc = sc; 377 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 378 ifp->if_ioctl = fxp_ioctl; 379 ifp->if_start = fxp_start; 380 ifp->if_watchdog = fxp_watchdog; 381 ifp->if_init = fxp_init; 382 ifp->if_stop = fxp_stop; 383 IFQ_SET_READY(&ifp->if_snd); 384 385 if (sc->sc_flags & FXPF_EXT_RFA) { 386 /* 387 * IFCAP_CSUM_IPv4_Tx seems to have a problem, 388 * at least, on i82550 rev.12. 389 * specifically, it doesn't set ipv4 checksum properly 390 * when sending UDP (and probably TCP) packets with 391 * 20 byte ipv4 header + 1 or 2 byte data, 392 * though ICMP packets seem working. 393 * FreeBSD driver has related comments. 394 * We've added a workaround to handle the bug by padding 395 * such packets manually. 396 */ 397 ifp->if_capabilities = 398 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 399 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 400 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 401 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 402 } else if (sc->sc_flags & FXPF_82559_RXCSUM) { 403 ifp->if_capabilities = 404 IFCAP_CSUM_TCPv4_Rx | 405 IFCAP_CSUM_UDPv4_Rx; 406 } 407 408 /* 409 * We can support 802.1Q VLAN-sized frames. 410 */ 411 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 412 413 /* 414 * Attach the interface. 415 */ 416 if_attach(ifp); 417 ether_ifattach(ifp, enaddr); 418#if NRND > 0 419 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 420 RND_TYPE_NET, 0); 421#endif 422 423#ifdef FXP_EVENT_COUNTERS 424 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 425 NULL, device_xname(sc->sc_dev), "txstall"); 426 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 427 NULL, device_xname(sc->sc_dev), "txintr"); 428 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 429 NULL, device_xname(sc->sc_dev), "rxintr"); 430 if (sc->sc_flags & FXPF_FC) { 431 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 432 NULL, device_xname(sc->sc_dev), "txpause"); 433 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 434 NULL, device_xname(sc->sc_dev), "rxpause"); 435 } 436#endif /* FXP_EVENT_COUNTERS */ 437 438 /* The attach is successful. */ 439 sc->sc_flags |= FXPF_ATTACHED; 440 441 return; 442 443 /* 444 * Free any resources we've allocated during the failed attach 445 * attempt. Do this in reverse order and fall though. 446 */ 447 fail_5: 448 for (i = 0; i < FXP_NRFABUFS; i++) { 449 if (sc->sc_rxmaps[i] != NULL) 450 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 451 } 452 fail_4: 453 for (i = 0; i < FXP_NTXCB; i++) { 454 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 455 bus_dmamap_destroy(sc->sc_dmat, 456 FXP_DSTX(sc, i)->txs_dmamap); 457 } 458 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 459 fail_3: 460 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 461 fail_2: 462 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 463 sizeof(struct fxp_control_data)); 464 fail_1: 465 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 466 fail_0: 467 return; 468} 469 470void 471fxp_mii_initmedia(struct fxp_softc *sc) 472{ 473 int flags; 474 475 sc->sc_flags |= FXPF_MII; 476 477 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 478 sc->sc_mii.mii_readreg = fxp_mdi_read; 479 sc->sc_mii.mii_writereg = fxp_mdi_write; 480 sc->sc_mii.mii_statchg = fxp_statchg; 481 482 sc->sc_ethercom.ec_mii = &sc->sc_mii; 483 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 484 fxp_mii_mediastatus); 485 486 flags = MIIF_NOISOLATE; 487 if (sc->sc_flags & FXPF_FC) 488 flags |= MIIF_FORCEANEG|MIIF_DOPAUSE; 489 /* 490 * The i82557 wedges if all of its PHYs are isolated! 491 */ 492 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 493 MII_OFFSET_ANY, flags); 494 if (LIST_EMPTY(&sc->sc_mii.mii_phys)) { 495 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 496 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 497 } else 498 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 499} 500 501void 502fxp_80c24_initmedia(struct fxp_softc *sc) 503{ 504 505 /* 506 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 507 * doesn't have a programming interface of any sort. The 508 * media is sensed automatically based on how the link partner 509 * is configured. This is, in essence, manual configuration. 510 */ 511 aprint_normal_dev(sc->sc_dev, 512 "Seeq 80c24 AutoDUPLEX media interface present\n"); 513 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 514 fxp_80c24_mediastatus); 515 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 516 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 517} 518 519/* 520 * Initialize the interface media. 521 */ 522void 523fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 524{ 525 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 526 527 /* 528 * Reset to a stable state. 529 */ 530 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 531 DELAY(100); 532 533 sc->sc_eeprom_size = 0; 534 fxp_autosize_eeprom(sc); 535 if (sc->sc_eeprom_size == 0) { 536 aprint_error_dev(sc->sc_dev, "failed to detect EEPROM size\n"); 537 sc->sc_eeprom_size = 6; /* XXX panic here? */ 538 } 539#ifdef DEBUG 540 aprint_debug_dev(sc->sc_dev, "detected %d word EEPROM\n", 541 1 << sc->sc_eeprom_size); 542#endif 543 544 /* 545 * Get info about the primary PHY 546 */ 547 fxp_read_eeprom(sc, &data, 6, 1); 548 sc->phy_primary_device = 549 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 550 551 /* 552 * Read MAC address. 553 */ 554 fxp_read_eeprom(sc, myea, 0, 3); 555 enaddr[0] = myea[0] & 0xff; 556 enaddr[1] = myea[0] >> 8; 557 enaddr[2] = myea[1] & 0xff; 558 enaddr[3] = myea[1] >> 8; 559 enaddr[4] = myea[2] & 0xff; 560 enaddr[5] = myea[2] >> 8; 561 562 /* 563 * Systems based on the ICH2/ICH2-M chip from Intel, as well 564 * as some i82559 designs, have a defect where the chip can 565 * cause a PCI protocol violation if it receives a CU_RESUME 566 * command when it is entering the IDLE state. 567 * 568 * The work-around is to disable Dynamic Standby Mode, so that 569 * the chip never deasserts #CLKRUN, and always remains in the 570 * active state. 571 * 572 * Unfortunately, the only way to disable Dynamic Standby is 573 * to frob an EEPROM setting and reboot (the EEPROM setting 574 * is only consulted when the PCI bus comes out of reset). 575 * 576 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 577 */ 578 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 579 fxp_read_eeprom(sc, &data, 10, 1); 580 if (data & 0x02) { /* STB enable */ 581 aprint_error_dev(sc->sc_dev, "WARNING: " 582 "Disabling dynamic standby mode in EEPROM " 583 "to work around a\n"); 584 aprint_normal_dev(sc->sc_dev, 585 "WARNING: hardware bug. You must reset " 586 "the system before using this\n"); 587 aprint_normal_dev(sc->sc_dev, "WARNING: interface.\n"); 588 data &= ~0x02; 589 fxp_write_eeprom(sc, &data, 10, 1); 590 aprint_normal_dev(sc->sc_dev, "new EEPROM ID: 0x%04x\n", 591 data); 592 fxp_eeprom_update_cksum(sc); 593 } 594 } 595 596 /* Receiver lock-up workaround detection. (FXPF_RECV_WORKAROUND) */ 597 /* Due to false positives we make it conditional on setting link1 */ 598 fxp_read_eeprom(sc, &data, 3, 1); 599 if ((data & 0x03) != 0x03) { 600 aprint_verbose_dev(sc->sc_dev, 601 "May need receiver lock-up workaround\n"); 602 } 603} 604 605static void 606fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 607{ 608 uint16_t reg; 609 int x; 610 611 for (x = 1 << (len - 1); x != 0; x >>= 1) { 612 DELAY(40); 613 if (data & x) 614 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 615 else 616 reg = FXP_EEPROM_EECS; 617 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 618 DELAY(40); 619 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 620 reg | FXP_EEPROM_EESK); 621 DELAY(40); 622 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 623 } 624 DELAY(40); 625} 626 627/* 628 * Figure out EEPROM size. 629 * 630 * 559's can have either 64-word or 256-word EEPROMs, the 558 631 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 632 * talks about the existence of 16 to 256 word EEPROMs. 633 * 634 * The only known sizes are 64 and 256, where the 256 version is used 635 * by CardBus cards to store CIS information. 636 * 637 * The address is shifted in msb-to-lsb, and after the last 638 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 639 * after which follows the actual data. We try to detect this zero, by 640 * probing the data-out bit in the EEPROM control register just after 641 * having shifted in a bit. If the bit is zero, we assume we've 642 * shifted enough address bits. The data-out should be tri-state, 643 * before this, which should translate to a logical one. 644 * 645 * Other ways to do this would be to try to read a register with known 646 * contents with a varying number of address bits, but no such 647 * register seem to be available. The high bits of register 10 are 01 648 * on the 558 and 559, but apparently not on the 557. 649 * 650 * The Linux driver computes a checksum on the EEPROM data, but the 651 * value of this checksum is not very well documented. 652 */ 653 654void 655fxp_autosize_eeprom(struct fxp_softc *sc) 656{ 657 int x; 658 659 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 660 DELAY(40); 661 662 /* Shift in read opcode. */ 663 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 664 665 /* 666 * Shift in address, wait for the dummy zero following a correct 667 * address shift. 668 */ 669 for (x = 1; x <= 8; x++) { 670 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 671 DELAY(40); 672 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 673 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 674 DELAY(40); 675 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 676 FXP_EEPROM_EEDO) == 0) 677 break; 678 DELAY(40); 679 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 680 DELAY(40); 681 } 682 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 683 DELAY(40); 684 if (x != 6 && x != 8) { 685#ifdef DEBUG 686 printf("%s: strange EEPROM size (%d)\n", 687 device_xname(sc->sc_dev), 1 << x); 688#endif 689 } else 690 sc->sc_eeprom_size = x; 691} 692 693/* 694 * Read from the serial EEPROM. Basically, you manually shift in 695 * the read opcode (one bit at a time) and then shift in the address, 696 * and then you shift out the data (all of this one bit at a time). 697 * The word size is 16 bits, so you have to provide the address for 698 * every 16 bits of data. 699 */ 700void 701fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 702{ 703 u_int16_t reg; 704 int i, x; 705 706 for (i = 0; i < words; i++) { 707 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 708 709 /* Shift in read opcode. */ 710 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 711 712 /* Shift in address. */ 713 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 714 715 reg = FXP_EEPROM_EECS; 716 data[i] = 0; 717 718 /* Shift out data. */ 719 for (x = 16; x > 0; x--) { 720 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 721 reg | FXP_EEPROM_EESK); 722 DELAY(40); 723 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 724 FXP_EEPROM_EEDO) 725 data[i] |= (1 << (x - 1)); 726 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 727 DELAY(40); 728 } 729 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 730 DELAY(40); 731 } 732} 733 734/* 735 * Write data to the serial EEPROM. 736 */ 737void 738fxp_write_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 739{ 740 int i, j; 741 742 for (i = 0; i < words; i++) { 743 /* Erase/write enable. */ 744 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 745 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 746 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 747 sc->sc_eeprom_size); 748 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 749 DELAY(4); 750 751 /* Shift in write opcode, address, data. */ 752 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 753 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 754 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 755 fxp_eeprom_shiftin(sc, data[i], 16); 756 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 757 DELAY(4); 758 759 /* Wait for the EEPROM to finish up. */ 760 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 761 DELAY(4); 762 for (j = 0; j < 1000; j++) { 763 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 764 FXP_EEPROM_EEDO) 765 break; 766 DELAY(50); 767 } 768 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 769 DELAY(4); 770 771 /* Erase/write disable. */ 772 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 773 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 774 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 775 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 776 DELAY(4); 777 } 778} 779 780/* 781 * Update the checksum of the EEPROM. 782 */ 783void 784fxp_eeprom_update_cksum(struct fxp_softc *sc) 785{ 786 int i; 787 uint16_t data, cksum; 788 789 cksum = 0; 790 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 791 fxp_read_eeprom(sc, &data, i, 1); 792 cksum += data; 793 } 794 i = (1 << sc->sc_eeprom_size) - 1; 795 cksum = 0xbaba - cksum; 796 fxp_read_eeprom(sc, &data, i, 1); 797 fxp_write_eeprom(sc, &cksum, i, 1); 798 log(LOG_INFO, "%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 799 device_xname(sc->sc_dev), i, data, cksum); 800} 801 802/* 803 * Start packet transmission on the interface. 804 */ 805void 806fxp_start(struct ifnet *ifp) 807{ 808 struct fxp_softc *sc = ifp->if_softc; 809 struct mbuf *m0, *m; 810 struct fxp_txdesc *txd; 811 struct fxp_txsoft *txs; 812 bus_dmamap_t dmamap; 813 int error, lasttx, nexttx, opending, seg, nsegs, len; 814 815 /* 816 * If we want a re-init, bail out now. 817 */ 818 if (sc->sc_flags & FXPF_WANTINIT) { 819 ifp->if_flags |= IFF_OACTIVE; 820 return; 821 } 822 823 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 824 return; 825 826 /* 827 * Remember the previous txpending and the current lasttx. 828 */ 829 opending = sc->sc_txpending; 830 lasttx = sc->sc_txlast; 831 832 /* 833 * Loop through the send queue, setting up transmit descriptors 834 * until we drain the queue, or use up all available transmit 835 * descriptors. 836 */ 837 for (;;) { 838 struct fxp_tbd *tbdp; 839 int csum_flags; 840 841 /* 842 * Grab a packet off the queue. 843 */ 844 IFQ_POLL(&ifp->if_snd, m0); 845 if (m0 == NULL) 846 break; 847 m = NULL; 848 849 if (sc->sc_txpending == FXP_NTXCB - 1) { 850 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 851 break; 852 } 853 854 /* 855 * Get the next available transmit descriptor. 856 */ 857 nexttx = FXP_NEXTTX(sc->sc_txlast); 858 txd = FXP_CDTX(sc, nexttx); 859 txs = FXP_DSTX(sc, nexttx); 860 dmamap = txs->txs_dmamap; 861 862 /* 863 * Load the DMA map. If this fails, the packet either 864 * didn't fit in the allotted number of frags, or we were 865 * short on resources. In this case, we'll copy and try 866 * again. 867 */ 868 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 869 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 870 MGETHDR(m, M_DONTWAIT, MT_DATA); 871 if (m == NULL) { 872 log(LOG_ERR, "%s: unable to allocate Tx mbuf\n", 873 device_xname(sc->sc_dev)); 874 break; 875 } 876 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 877 if (m0->m_pkthdr.len > MHLEN) { 878 MCLGET(m, M_DONTWAIT); 879 if ((m->m_flags & M_EXT) == 0) { 880 log(LOG_ERR, "%s: unable to allocate " 881 "Tx cluster\n", 882 device_xname(sc->sc_dev)); 883 m_freem(m); 884 break; 885 } 886 } 887 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 888 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 889 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 890 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 891 if (error) { 892 log(LOG_ERR, "%s: unable to load Tx buffer, " 893 "error = %d\n", 894 device_xname(sc->sc_dev), error); 895 break; 896 } 897 } 898 899 IFQ_DEQUEUE(&ifp->if_snd, m0); 900 csum_flags = m0->m_pkthdr.csum_flags; 901 if (m != NULL) { 902 m_freem(m0); 903 m0 = m; 904 } 905 906 /* Initialize the fraglist. */ 907 tbdp = txd->txd_tbd; 908 len = m0->m_pkthdr.len; 909 nsegs = dmamap->dm_nsegs; 910 if (sc->sc_flags & FXPF_EXT_RFA) 911 tbdp++; 912 for (seg = 0; seg < nsegs; seg++) { 913 tbdp[seg].tb_addr = 914 htole32(dmamap->dm_segs[seg].ds_addr); 915 tbdp[seg].tb_size = 916 htole32(dmamap->dm_segs[seg].ds_len); 917 } 918 if (__predict_false(len <= FXP_IP4CSUMTX_PADLEN && 919 (csum_flags & M_CSUM_IPv4) != 0)) { 920 /* 921 * Pad short packets to avoid ip4csum-tx bug. 922 * 923 * XXX Should we still consider if such short 924 * (36 bytes or less) packets might already 925 * occupy FXP_IPCB_NTXSEG (15) fragments here? 926 */ 927 KASSERT(nsegs < FXP_IPCB_NTXSEG); 928 nsegs++; 929 tbdp[seg].tb_addr = htole32(FXP_CDTXPADADDR(sc)); 930 tbdp[seg].tb_size = 931 htole32(FXP_IP4CSUMTX_PADLEN + 1 - len); 932 } 933 934 /* Sync the DMA map. */ 935 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 936 BUS_DMASYNC_PREWRITE); 937 938 /* 939 * Store a pointer to the packet so we can free it later. 940 */ 941 txs->txs_mbuf = m0; 942 943 /* 944 * Initialize the transmit descriptor. 945 */ 946 /* BIG_ENDIAN: no need to swap to store 0 */ 947 txd->txd_txcb.cb_status = 0; 948 txd->txd_txcb.cb_command = 949 sc->sc_txcmd | htole16(FXP_CB_COMMAND_SF); 950 txd->txd_txcb.tx_threshold = tx_threshold; 951 txd->txd_txcb.tbd_number = nsegs; 952 953 KASSERT((csum_flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) == 0); 954 if (sc->sc_flags & FXPF_EXT_RFA) { 955 struct m_tag *vtag; 956 struct fxp_ipcb *ipcb; 957 /* 958 * Deal with TCP/IP checksum offload. Note that 959 * in order for TCP checksum offload to work, 960 * the pseudo header checksum must have already 961 * been computed and stored in the checksum field 962 * in the TCP header. The stack should have 963 * already done this for us. 964 */ 965 ipcb = &txd->txd_u.txdu_ipcb; 966 memset(ipcb, 0, sizeof(*ipcb)); 967 /* 968 * always do hardware parsing. 969 */ 970 ipcb->ipcb_ip_activation_high = 971 FXP_IPCB_HARDWAREPARSING_ENABLE; 972 /* 973 * ip checksum offloading. 974 */ 975 if (csum_flags & M_CSUM_IPv4) { 976 ipcb->ipcb_ip_schedule |= 977 FXP_IPCB_IP_CHECKSUM_ENABLE; 978 } 979 /* 980 * TCP/UDP checksum offloading. 981 */ 982 if (csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 983 ipcb->ipcb_ip_schedule |= 984 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 985 } 986 987 /* 988 * request VLAN tag insertion if needed. 989 */ 990 vtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0); 991 if (vtag) { 992 ipcb->ipcb_vlan_id = 993 htobe16(*(u_int *)(vtag + 1)); 994 ipcb->ipcb_ip_activation_high |= 995 FXP_IPCB_INSERTVLAN_ENABLE; 996 } 997 } else { 998 KASSERT((csum_flags & 999 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) == 0); 1000 } 1001 1002 FXP_CDTXSYNC(sc, nexttx, 1003 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1004 1005 /* Advance the tx pointer. */ 1006 sc->sc_txpending++; 1007 sc->sc_txlast = nexttx; 1008 1009#if NBPFILTER > 0 1010 /* 1011 * Pass packet to bpf if there is a listener. 1012 */ 1013 if (ifp->if_bpf) 1014 bpf_mtap(ifp->if_bpf, m0); 1015#endif 1016 } 1017 1018 if (sc->sc_txpending == FXP_NTXCB - 1) { 1019 /* No more slots; notify upper layer. */ 1020 ifp->if_flags |= IFF_OACTIVE; 1021 } 1022 1023 if (sc->sc_txpending != opending) { 1024 /* 1025 * We enqueued packets. If the transmitter was idle, 1026 * reset the txdirty pointer. 1027 */ 1028 if (opending == 0) 1029 sc->sc_txdirty = FXP_NEXTTX(lasttx); 1030 1031 /* 1032 * Cause the chip to interrupt and suspend command 1033 * processing once the last packet we've enqueued 1034 * has been transmitted. 1035 * 1036 * To avoid a race between updating status bits 1037 * by the fxp chip and clearing command bits 1038 * by this function on machines which don't have 1039 * atomic methods to clear/set bits in memory 1040 * smaller than 32bits (both cb_status and cb_command 1041 * members are uint16_t and in the same 32bit word), 1042 * we have to prepare a dummy TX descriptor which has 1043 * NOP command and just causes a TX completion interrupt. 1044 */ 1045 sc->sc_txpending++; 1046 sc->sc_txlast = FXP_NEXTTX(sc->sc_txlast); 1047 txd = FXP_CDTX(sc, sc->sc_txlast); 1048 /* BIG_ENDIAN: no need to swap to store 0 */ 1049 txd->txd_txcb.cb_status = 0; 1050 txd->txd_txcb.cb_command = htole16(FXP_CB_COMMAND_NOP | 1051 FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 1052 FXP_CDTXSYNC(sc, sc->sc_txlast, 1053 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1054 1055 /* 1056 * The entire packet chain is set up. Clear the suspend bit 1057 * on the command prior to the first packet we set up. 1058 */ 1059 FXP_CDTXSYNC(sc, lasttx, 1060 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1061 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 1062 htole16(~FXP_CB_COMMAND_S); 1063 FXP_CDTXSYNC(sc, lasttx, 1064 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1065 1066 /* 1067 * Issue a Resume command in case the chip was suspended. 1068 */ 1069 fxp_scb_wait(sc); 1070 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1071 1072 /* Set a watchdog timer in case the chip flakes out. */ 1073 ifp->if_timer = 5; 1074 } 1075} 1076 1077/* 1078 * Process interface interrupts. 1079 */ 1080int 1081fxp_intr(void *arg) 1082{ 1083 struct fxp_softc *sc = arg; 1084 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1085 bus_dmamap_t rxmap; 1086 int claimed = 0, rnr; 1087 u_int8_t statack; 1088 1089 if (!device_is_active(sc->sc_dev) || sc->sc_enabled == 0) 1090 return (0); 1091 /* 1092 * If the interface isn't running, don't try to 1093 * service the interrupt.. just ack it and bail. 1094 */ 1095 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1096 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1097 if (statack) { 1098 claimed = 1; 1099 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1100 } 1101 return (claimed); 1102 } 1103 1104 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1105 claimed = 1; 1106 1107 /* 1108 * First ACK all the interrupts in this pass. 1109 */ 1110 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1111 1112 /* 1113 * Process receiver interrupts. If a no-resource (RNR) 1114 * condition exists, get whatever packets we can and 1115 * re-start the receiver. 1116 */ 1117 rnr = (statack & (FXP_SCB_STATACK_RNR | FXP_SCB_STATACK_SWI)) ? 1118 1 : 0; 1119 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR | 1120 FXP_SCB_STATACK_SWI)) { 1121 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1122 rnr |= fxp_rxintr(sc); 1123 } 1124 1125 /* 1126 * Free any finished transmit mbuf chains. 1127 */ 1128 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1129 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1130 fxp_txintr(sc); 1131 1132 /* 1133 * Try to get more packets going. 1134 */ 1135 fxp_start(ifp); 1136 1137 if (sc->sc_txpending == 0) { 1138 /* 1139 * Tell them that they can re-init now. 1140 */ 1141 if (sc->sc_flags & FXPF_WANTINIT) 1142 wakeup(sc); 1143 } 1144 } 1145 1146 if (rnr) { 1147 fxp_scb_wait(sc); 1148 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_ABORT); 1149 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1150 fxp_scb_wait(sc); 1151 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1152 rxmap->dm_segs[0].ds_addr + 1153 RFA_ALIGNMENT_FUDGE); 1154 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1155 } 1156 } 1157 1158#if NRND > 0 1159 if (claimed) 1160 rnd_add_uint32(&sc->rnd_source, statack); 1161#endif 1162 return (claimed); 1163} 1164 1165/* 1166 * Handle transmit completion interrupts. 1167 */ 1168void 1169fxp_txintr(struct fxp_softc *sc) 1170{ 1171 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1172 struct fxp_txdesc *txd; 1173 struct fxp_txsoft *txs; 1174 int i; 1175 u_int16_t txstat; 1176 1177 ifp->if_flags &= ~IFF_OACTIVE; 1178 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1179 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1180 txd = FXP_CDTX(sc, i); 1181 txs = FXP_DSTX(sc, i); 1182 1183 FXP_CDTXSYNC(sc, i, 1184 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1185 1186 /* skip dummy NOP TX descriptor */ 1187 if ((le16toh(txd->txd_txcb.cb_command) & FXP_CB_COMMAND_CMD) 1188 == FXP_CB_COMMAND_NOP) 1189 continue; 1190 1191 txstat = le16toh(txd->txd_txcb.cb_status); 1192 1193 if ((txstat & FXP_CB_STATUS_C) == 0) 1194 break; 1195 1196 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1197 0, txs->txs_dmamap->dm_mapsize, 1198 BUS_DMASYNC_POSTWRITE); 1199 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1200 m_freem(txs->txs_mbuf); 1201 txs->txs_mbuf = NULL; 1202 } 1203 1204 /* Update the dirty transmit buffer pointer. */ 1205 sc->sc_txdirty = i; 1206 1207 /* 1208 * Cancel the watchdog timer if there are no pending 1209 * transmissions. 1210 */ 1211 if (sc->sc_txpending == 0) 1212 ifp->if_timer = 0; 1213} 1214 1215/* 1216 * fxp_rx_hwcksum: check status of H/W offloading for received packets. 1217 */ 1218 1219void 1220fxp_rx_hwcksum(struct fxp_softc *sc, struct mbuf *m, const struct fxp_rfa *rfa, 1221 u_int len) 1222{ 1223 uint32_t csum_data; 1224 int csum_flags; 1225 1226 /* 1227 * check H/W Checksumming. 1228 */ 1229 1230 csum_flags = 0; 1231 csum_data = 0; 1232 1233 if ((sc->sc_flags & FXPF_EXT_RFA) != 0) { 1234 uint8_t rxparsestat; 1235 uint8_t csum_stat; 1236 1237 csum_stat = rfa->cksum_stat; 1238 rxparsestat = rfa->rx_parse_stat; 1239 if ((rfa->rfa_status & htole16(FXP_RFA_STATUS_PARSE)) == 0) 1240 goto out; 1241 1242 if (csum_stat & FXP_RFDX_CS_IP_CSUM_BIT_VALID) { 1243 csum_flags = M_CSUM_IPv4; 1244 if ((csum_stat & FXP_RFDX_CS_IP_CSUM_VALID) == 0) 1245 csum_flags |= M_CSUM_IPv4_BAD; 1246 } 1247 1248 if (csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) { 1249 csum_flags |= (M_CSUM_TCPv4|M_CSUM_UDPv4); /* XXX */ 1250 if ((csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_VALID) == 0) 1251 csum_flags |= M_CSUM_TCP_UDP_BAD; 1252 } 1253 1254 } else if ((sc->sc_flags & FXPF_82559_RXCSUM) != 0) { 1255 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1256 struct ether_header *eh; 1257 struct ip *ip; 1258 struct udphdr *uh; 1259 u_int hlen, pktlen; 1260 1261 if (len < ETHER_HDR_LEN + sizeof(struct ip)) 1262 goto out; 1263 pktlen = len - ETHER_HDR_LEN; 1264 eh = mtod(m, struct ether_header *); 1265 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1266 goto out; 1267 ip = (struct ip *)((uint8_t *)eh + ETHER_HDR_LEN); 1268 if (ip->ip_v != IPVERSION) 1269 goto out; 1270 1271 hlen = ip->ip_hl << 2; 1272 if (hlen < sizeof(struct ip)) 1273 goto out; 1274 1275 /* 1276 * Bail if too short, has random trailing garbage, truncated, 1277 * fragment, or has ethernet pad. 1278 */ 1279 if (ntohs(ip->ip_len) < hlen || 1280 ntohs(ip->ip_len) != pktlen || 1281 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK)) != 0) 1282 goto out; 1283 1284 switch (ip->ip_p) { 1285 case IPPROTO_TCP: 1286 if ((ifp->if_csum_flags_rx & M_CSUM_TCPv4) == 0 || 1287 pktlen < (hlen + sizeof(struct tcphdr))) 1288 goto out; 1289 csum_flags = 1290 M_CSUM_TCPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 1291 break; 1292 case IPPROTO_UDP: 1293 if ((ifp->if_csum_flags_rx & M_CSUM_UDPv4) == 0 || 1294 pktlen < (hlen + sizeof(struct udphdr))) 1295 goto out; 1296 uh = (struct udphdr *)((uint8_t *)ip + hlen); 1297 if (uh->uh_sum == 0) 1298 goto out; /* no checksum */ 1299 csum_flags = 1300 M_CSUM_UDPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 1301 break; 1302 default: 1303 goto out; 1304 } 1305 1306 /* Extract computed checksum. */ 1307 csum_data = be16dec(mtod(m, uint8_t *) + len); 1308 1309 /* 1310 * The computed checksum includes IP headers, 1311 * so we have to deduct them. 1312 */ 1313#if 0 1314 /* 1315 * But in TCP/UDP layer we can assume the IP header is valid, 1316 * i.e. a sum of the whole IP header should be 0xffff, 1317 * so we don't have to bother to deduct it. 1318 */ 1319 if (hlen > 0) { 1320 uint32_t hsum; 1321 const uint16_t *iphdr; 1322 hsum = 0; 1323 iphdr = (uint16_t *)ip; 1324 1325 while (hlen > 1) { 1326 hsum += ntohs(*iphdr++); 1327 hlen -= sizeof(uint16_t); 1328 } 1329 while (hsum >> 16) 1330 hsum = (hsum >> 16) + (hsum & 0xffff); 1331 1332 csum_data = ~(~csum_data - ~hsum); 1333 1334 while (csum_data >> 16) 1335 csum_data = 1336 (csum_data >> 16) + (csum_data & 0xffff); 1337 } 1338#endif 1339 } 1340 out: 1341 m->m_pkthdr.csum_flags = csum_flags; 1342 m->m_pkthdr.csum_data = csum_data; 1343} 1344 1345/* 1346 * Handle receive interrupts. 1347 */ 1348int 1349fxp_rxintr(struct fxp_softc *sc) 1350{ 1351 struct ethercom *ec = &sc->sc_ethercom; 1352 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1353 struct mbuf *m, *m0; 1354 bus_dmamap_t rxmap; 1355 struct fxp_rfa *rfa; 1356 int rnr; 1357 u_int16_t len, rxstat; 1358 1359 rnr = 0; 1360 1361 for (;;) { 1362 m = sc->sc_rxq.ifq_head; 1363 rfa = FXP_MTORFA(m); 1364 rxmap = M_GETCTX(m, bus_dmamap_t); 1365 1366 FXP_RFASYNC(sc, m, 1367 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1368 1369 rxstat = le16toh(rfa->rfa_status); 1370 1371 if ((rxstat & FXP_RFA_STATUS_RNR) != 0) 1372 rnr = 1; 1373 1374 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1375 /* 1376 * We have processed all of the 1377 * receive buffers. 1378 */ 1379 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1380 return rnr; 1381 } 1382 1383 IF_DEQUEUE(&sc->sc_rxq, m); 1384 1385 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1386 1387 len = le16toh(rfa->actual_size) & 1388 (m->m_ext.ext_size - 1); 1389 if ((sc->sc_flags & FXPF_82559_RXCSUM) != 0) { 1390 /* Adjust for appended checksum bytes. */ 1391 len -= sizeof(uint16_t); 1392 } 1393 1394 if (len < sizeof(struct ether_header)) { 1395 /* 1396 * Runt packet; drop it now. 1397 */ 1398 FXP_INIT_RFABUF(sc, m); 1399 continue; 1400 } 1401 1402 /* 1403 * If support for 802.1Q VLAN sized frames is 1404 * enabled, we need to do some additional error 1405 * checking (as we are saving bad frames, in 1406 * order to receive the larger ones). 1407 */ 1408 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1409 (rxstat & (FXP_RFA_STATUS_OVERRUN| 1410 FXP_RFA_STATUS_RNR| 1411 FXP_RFA_STATUS_ALIGN| 1412 FXP_RFA_STATUS_CRC)) != 0) { 1413 FXP_INIT_RFABUF(sc, m); 1414 continue; 1415 } 1416 1417 /* 1418 * check VLAN tag stripping. 1419 */ 1420 if ((sc->sc_flags & FXPF_EXT_RFA) != 0 && 1421 (rfa->rfa_status & htole16(FXP_RFA_STATUS_VLAN)) != 0) { 1422 struct m_tag *vtag; 1423 1424 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), 1425 M_NOWAIT); 1426 if (vtag == NULL) 1427 goto dropit; 1428 *(u_int *)(vtag + 1) = be16toh(rfa->vlan_id); 1429 m_tag_prepend(m, vtag); 1430 } 1431 1432 /* Do checksum checking. */ 1433 if ((ifp->if_csum_flags_rx & (M_CSUM_TCPv4|M_CSUM_UDPv4)) != 0) 1434 fxp_rx_hwcksum(sc, m, rfa, len); 1435 1436 /* 1437 * If the packet is small enough to fit in a 1438 * single header mbuf, allocate one and copy 1439 * the data into it. This greatly reduces 1440 * memory consumption when we receive lots 1441 * of small packets. 1442 * 1443 * Otherwise, we add a new buffer to the receive 1444 * chain. If this fails, we drop the packet and 1445 * recycle the old buffer. 1446 */ 1447 if (fxp_copy_small != 0 && len <= MHLEN) { 1448 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1449 if (m0 == NULL) 1450 goto dropit; 1451 MCLAIM(m0, &sc->sc_ethercom.ec_rx_mowner); 1452 memcpy(mtod(m0, void *), 1453 mtod(m, void *), len); 1454 m0->m_pkthdr.csum_flags = m->m_pkthdr.csum_flags; 1455 m0->m_pkthdr.csum_data = m->m_pkthdr.csum_data; 1456 FXP_INIT_RFABUF(sc, m); 1457 m = m0; 1458 } else { 1459 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1460 dropit: 1461 ifp->if_ierrors++; 1462 FXP_INIT_RFABUF(sc, m); 1463 continue; 1464 } 1465 } 1466 1467 m->m_pkthdr.rcvif = ifp; 1468 m->m_pkthdr.len = m->m_len = len; 1469 1470#if NBPFILTER > 0 1471 /* 1472 * Pass this up to any BPF listeners, but only 1473 * pass it up the stack if it's for us. 1474 */ 1475 if (ifp->if_bpf) 1476 bpf_mtap(ifp->if_bpf, m); 1477#endif 1478 1479 /* Pass it on. */ 1480 (*ifp->if_input)(ifp, m); 1481 } 1482} 1483 1484/* 1485 * Update packet in/out/collision statistics. The i82557 doesn't 1486 * allow you to access these counters without doing a fairly 1487 * expensive DMA to get _all_ of the statistics it maintains, so 1488 * we do this operation here only once per second. The statistics 1489 * counters in the kernel are updated from the previous dump-stats 1490 * DMA and then a new dump-stats DMA is started. The on-chip 1491 * counters are zeroed when the DMA completes. If we can't start 1492 * the DMA immediately, we don't wait - we just prepare to read 1493 * them again next time. 1494 */ 1495void 1496fxp_tick(void *arg) 1497{ 1498 struct fxp_softc *sc = arg; 1499 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1500 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1501 int s; 1502 1503 if (!device_is_active(sc->sc_dev)) 1504 return; 1505 1506 s = splnet(); 1507 1508 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1509 1510 ifp->if_opackets += le32toh(sp->tx_good); 1511 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1512 if (sp->rx_good) { 1513 ifp->if_ipackets += le32toh(sp->rx_good); 1514 sc->sc_rxidle = 0; 1515 } else if (sc->sc_flags & FXPF_RECV_WORKAROUND) { 1516 sc->sc_rxidle++; 1517 } 1518 ifp->if_ierrors += 1519 le32toh(sp->rx_crc_errors) + 1520 le32toh(sp->rx_alignment_errors) + 1521 le32toh(sp->rx_rnr_errors) + 1522 le32toh(sp->rx_overrun_errors); 1523 /* 1524 * If any transmit underruns occurred, bump up the transmit 1525 * threshold by another 512 bytes (64 * 8). 1526 */ 1527 if (sp->tx_underruns) { 1528 ifp->if_oerrors += le32toh(sp->tx_underruns); 1529 if (tx_threshold < 192) 1530 tx_threshold += 64; 1531 } 1532#ifdef FXP_EVENT_COUNTERS 1533 if (sc->sc_flags & FXPF_FC) { 1534 sc->sc_ev_txpause.ev_count += sp->tx_pauseframes; 1535 sc->sc_ev_rxpause.ev_count += sp->rx_pauseframes; 1536 } 1537#endif 1538 1539 /* 1540 * If we haven't received any packets in FXP_MAX_RX_IDLE seconds, 1541 * then assume the receiver has locked up and attempt to clear 1542 * the condition by reprogramming the multicast filter (actually, 1543 * resetting the interface). This is a work-around for a bug in 1544 * the 82557 where the receiver locks up if it gets certain types 1545 * of garbage in the synchronization bits prior to the packet header. 1546 * This bug is supposed to only occur in 10Mbps mode, but has been 1547 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1548 * speed transition). 1549 */ 1550 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1551 (void) fxp_init(ifp); 1552 splx(s); 1553 return; 1554 } 1555 /* 1556 * If there is no pending command, start another stats 1557 * dump. Otherwise punt for now. 1558 */ 1559 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1560 /* 1561 * Start another stats dump. 1562 */ 1563 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1564 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1565 } else { 1566 /* 1567 * A previous command is still waiting to be accepted. 1568 * Just zero our copy of the stats and wait for the 1569 * next timer event to update them. 1570 */ 1571 /* BIG_ENDIAN: no swap required to store 0 */ 1572 sp->tx_good = 0; 1573 sp->tx_underruns = 0; 1574 sp->tx_total_collisions = 0; 1575 1576 sp->rx_good = 0; 1577 sp->rx_crc_errors = 0; 1578 sp->rx_alignment_errors = 0; 1579 sp->rx_rnr_errors = 0; 1580 sp->rx_overrun_errors = 0; 1581 if (sc->sc_flags & FXPF_FC) { 1582 sp->tx_pauseframes = 0; 1583 sp->rx_pauseframes = 0; 1584 } 1585 } 1586 1587 if (sc->sc_flags & FXPF_MII) { 1588 /* Tick the MII clock. */ 1589 mii_tick(&sc->sc_mii); 1590 } 1591 1592 splx(s); 1593 1594 /* 1595 * Schedule another timeout one second from now. 1596 */ 1597 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1598} 1599 1600/* 1601 * Drain the receive queue. 1602 */ 1603void 1604fxp_rxdrain(struct fxp_softc *sc) 1605{ 1606 bus_dmamap_t rxmap; 1607 struct mbuf *m; 1608 1609 for (;;) { 1610 IF_DEQUEUE(&sc->sc_rxq, m); 1611 if (m == NULL) 1612 break; 1613 rxmap = M_GETCTX(m, bus_dmamap_t); 1614 bus_dmamap_unload(sc->sc_dmat, rxmap); 1615 FXP_RXMAP_PUT(sc, rxmap); 1616 m_freem(m); 1617 } 1618} 1619 1620/* 1621 * Stop the interface. Cancels the statistics updater and resets 1622 * the interface. 1623 */ 1624void 1625fxp_stop(struct ifnet *ifp, int disable) 1626{ 1627 struct fxp_softc *sc = ifp->if_softc; 1628 struct fxp_txsoft *txs; 1629 int i; 1630 1631 /* 1632 * Turn down interface (done early to avoid bad interactions 1633 * between panics, shutdown hooks, and the watchdog timer) 1634 */ 1635 ifp->if_timer = 0; 1636 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1637 1638 /* 1639 * Cancel stats updater. 1640 */ 1641 callout_stop(&sc->sc_callout); 1642 if (sc->sc_flags & FXPF_MII) { 1643 /* Down the MII. */ 1644 mii_down(&sc->sc_mii); 1645 } 1646 1647 /* 1648 * Issue software reset. This unloads any microcode that 1649 * might already be loaded. 1650 */ 1651 sc->sc_flags &= ~FXPF_UCODE_LOADED; 1652 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1653 DELAY(50); 1654 1655 /* 1656 * Release any xmit buffers. 1657 */ 1658 for (i = 0; i < FXP_NTXCB; i++) { 1659 txs = FXP_DSTX(sc, i); 1660 if (txs->txs_mbuf != NULL) { 1661 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1662 m_freem(txs->txs_mbuf); 1663 txs->txs_mbuf = NULL; 1664 } 1665 } 1666 sc->sc_txpending = 0; 1667 1668 if (disable) { 1669 fxp_rxdrain(sc); 1670 fxp_disable(sc); 1671 } 1672 1673} 1674 1675/* 1676 * Watchdog/transmission transmit timeout handler. Called when a 1677 * transmission is started on the interface, but no interrupt is 1678 * received before the timeout. This usually indicates that the 1679 * card has wedged for some reason. 1680 */ 1681void 1682fxp_watchdog(struct ifnet *ifp) 1683{ 1684 struct fxp_softc *sc = ifp->if_softc; 1685 1686 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1687 ifp->if_oerrors++; 1688 1689 (void) fxp_init(ifp); 1690} 1691 1692/* 1693 * Initialize the interface. Must be called at splnet(). 1694 */ 1695int 1696fxp_init(struct ifnet *ifp) 1697{ 1698 struct fxp_softc *sc = ifp->if_softc; 1699 struct fxp_cb_config *cbp; 1700 struct fxp_cb_ias *cb_ias; 1701 struct fxp_txdesc *txd; 1702 bus_dmamap_t rxmap; 1703 int i, prm, save_bf, lrxen, vlan_drop, allm, error = 0; 1704 uint16_t status; 1705 1706 if ((error = fxp_enable(sc)) != 0) 1707 goto out; 1708 1709 /* 1710 * Cancel any pending I/O 1711 */ 1712 fxp_stop(ifp, 0); 1713 1714 /* 1715 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1716 * flag, and this prevents the MII from detaching resulting in 1717 * a panic. The flags field should perhaps be split in runtime 1718 * flags and more static information. For now, just clear the 1719 * only other flag set. 1720 */ 1721 1722 sc->sc_flags &= ~FXPF_WANTINIT; 1723 1724 /* 1725 * Initialize base of CBL and RFA memory. Loading with zero 1726 * sets it up for regular linear addressing. 1727 */ 1728 fxp_scb_wait(sc); 1729 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1730 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1731 1732 fxp_scb_wait(sc); 1733 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1734 1735 /* 1736 * Initialize the multicast filter. Do this now, since we might 1737 * have to setup the config block differently. 1738 */ 1739 fxp_mc_setup(sc); 1740 1741 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1742 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1743 1744 /* 1745 * In order to support receiving 802.1Q VLAN frames, we have to 1746 * enable "save bad frames", since they are 4 bytes larger than 1747 * the normal Ethernet maximum frame length. On i82558 and later, 1748 * we have a better mechanism for this. 1749 */ 1750 save_bf = 0; 1751 lrxen = 0; 1752 vlan_drop = 0; 1753 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1754 if (sc->sc_rev < FXP_REV_82558_A4) 1755 save_bf = 1; 1756 else 1757 lrxen = 1; 1758 if (sc->sc_rev >= FXP_REV_82550) 1759 vlan_drop = 1; 1760 } 1761 1762 /* 1763 * Initialize base of dump-stats buffer. 1764 */ 1765 fxp_scb_wait(sc); 1766 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1767 sc->sc_cddma + FXP_CDSTATSOFF); 1768 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1769 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1770 1771 cbp = &sc->sc_control_data->fcd_configcb; 1772 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1773 1774 /* 1775 * Load microcode for this controller. 1776 */ 1777 fxp_load_ucode(sc); 1778 1779 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK1)) 1780 sc->sc_flags |= FXPF_RECV_WORKAROUND; 1781 else 1782 sc->sc_flags &= ~FXPF_RECV_WORKAROUND; 1783 1784 /* 1785 * This copy is kind of disgusting, but there are a bunch of must be 1786 * zero and must be one bits in this structure and this is the easiest 1787 * way to initialize them all to proper values. 1788 */ 1789 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1790 1791 /* BIG_ENDIAN: no need to swap to store 0 */ 1792 cbp->cb_status = 0; 1793 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1794 FXP_CB_COMMAND_EL); 1795 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1796 cbp->link_addr = 0xffffffff; /* (no) next command */ 1797 /* bytes in config block */ 1798 cbp->byte_count = (sc->sc_flags & FXPF_EXT_RFA) ? 1799 FXP_EXT_CONFIG_LEN : FXP_CONFIG_LEN; 1800 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1801 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1802 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1803 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1804 cbp->type_enable = 0; /* actually reserved */ 1805 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1806 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1807 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1808 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1809 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1810 cbp->late_scb = 0; /* (don't) defer SCB update */ 1811 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1812 cbp->ci_int = 1; /* interrupt on CU idle */ 1813 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1814 cbp->ext_stats_dis = 1; /* disable extended counters */ 1815 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1816 cbp->save_bf = save_bf;/* save bad frames */ 1817 cbp->disc_short_rx = !prm; /* discard short packets */ 1818 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1819 cbp->ext_rfa = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1820 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1821 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1822 /* interface mode */ 1823 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1824 cbp->csma_dis = 0; /* (don't) disable link */ 1825 cbp->tcp_udp_cksum = (sc->sc_flags & FXPF_82559_RXCSUM) ? 1 : 0; 1826 /* (don't) enable RX checksum */ 1827 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1828 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1829 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1830 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1831 cbp->nsai = 1; /* (don't) disable source addr insert */ 1832 cbp->preamble_length = 2; /* (7 byte) preamble */ 1833 cbp->loopback = 0; /* (don't) loopback */ 1834 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1835 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1836 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1837 cbp->promiscuous = prm; /* promiscuous mode */ 1838 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1839 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1840 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1841 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1842 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1843 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1844 cbp->padding = 1; /* (do) pad short tx packets */ 1845 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1846 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1847 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1848 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1849 /* must set wake_en in PMCSR also */ 1850 cbp->force_fdx = 0; /* (don't) force full duplex */ 1851 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1852 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1853 cbp->mc_all = allm; /* accept all multicasts */ 1854 cbp->ext_rx_mode = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1855 cbp->vlan_drop_en = vlan_drop; 1856 1857 if (!(sc->sc_flags & FXPF_FC)) { 1858 /* 1859 * The i82557 has no hardware flow control, the values 1860 * here are the defaults for the chip. 1861 */ 1862 cbp->fc_delay_lsb = 0; 1863 cbp->fc_delay_msb = 0x40; 1864 cbp->pri_fc_thresh = 3; 1865 cbp->tx_fc_dis = 0; 1866 cbp->rx_fc_restop = 0; 1867 cbp->rx_fc_restart = 0; 1868 cbp->fc_filter = 0; 1869 cbp->pri_fc_loc = 1; 1870 } else { 1871 cbp->fc_delay_lsb = 0x1f; 1872 cbp->fc_delay_msb = 0x01; 1873 cbp->pri_fc_thresh = 3; 1874 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1875 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1876 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1877 cbp->fc_filter = !prm; /* drop FC frames to host */ 1878 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1879 cbp->ext_stats_dis = 0; /* enable extended stats */ 1880 } 1881 1882 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1883 1884 /* 1885 * Start the config command/DMA. 1886 */ 1887 fxp_scb_wait(sc); 1888 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1889 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1890 /* ...and wait for it to complete. */ 1891 for (i = 1000; i > 0; i--) { 1892 FXP_CDCONFIGSYNC(sc, 1893 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1894 status = le16toh(cbp->cb_status); 1895 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD); 1896 if ((status & FXP_CB_STATUS_C) != 0) 1897 break; 1898 DELAY(1); 1899 } 1900 if (i == 0) { 1901 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1902 device_xname(sc->sc_dev), __LINE__); 1903 return (ETIMEDOUT); 1904 } 1905 1906 /* 1907 * Initialize the station address. 1908 */ 1909 cb_ias = &sc->sc_control_data->fcd_iascb; 1910 /* BIG_ENDIAN: no need to swap to store 0 */ 1911 cb_ias->cb_status = 0; 1912 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1913 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1914 cb_ias->link_addr = 0xffffffff; 1915 memcpy(cb_ias->macaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1916 1917 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1918 1919 /* 1920 * Start the IAS (Individual Address Setup) command/DMA. 1921 */ 1922 fxp_scb_wait(sc); 1923 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1924 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1925 /* ...and wait for it to complete. */ 1926 for (i = 1000; i > 0; i++) { 1927 FXP_CDIASSYNC(sc, 1928 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1929 status = le16toh(cb_ias->cb_status); 1930 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD); 1931 if ((status & FXP_CB_STATUS_C) != 0) 1932 break; 1933 DELAY(1); 1934 } 1935 if (i == 0) { 1936 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1937 device_xname(sc->sc_dev), __LINE__); 1938 return (ETIMEDOUT); 1939 } 1940 1941 /* 1942 * Initialize the transmit descriptor ring. txlast is initialized 1943 * to the end of the list so that it will wrap around to the first 1944 * descriptor when the first packet is transmitted. 1945 */ 1946 for (i = 0; i < FXP_NTXCB; i++) { 1947 txd = FXP_CDTX(sc, i); 1948 memset(txd, 0, sizeof(*txd)); 1949 txd->txd_txcb.cb_command = 1950 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1951 txd->txd_txcb.link_addr = 1952 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1953 if (sc->sc_flags & FXPF_EXT_TXCB) 1954 txd->txd_txcb.tbd_array_addr = 1955 htole32(FXP_CDTBDADDR(sc, i) + 1956 (2 * sizeof(struct fxp_tbd))); 1957 else 1958 txd->txd_txcb.tbd_array_addr = 1959 htole32(FXP_CDTBDADDR(sc, i)); 1960 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1961 } 1962 sc->sc_txpending = 0; 1963 sc->sc_txdirty = 0; 1964 sc->sc_txlast = FXP_NTXCB - 1; 1965 1966 /* 1967 * Initialize the receive buffer list. 1968 */ 1969 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1970 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1971 rxmap = FXP_RXMAP_GET(sc); 1972 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1973 log(LOG_ERR, "%s: unable to allocate or map rx " 1974 "buffer %d, error = %d\n", 1975 device_xname(sc->sc_dev), 1976 sc->sc_rxq.ifq_len, error); 1977 /* 1978 * XXX Should attempt to run with fewer receive 1979 * XXX buffers instead of just failing. 1980 */ 1981 FXP_RXMAP_PUT(sc, rxmap); 1982 fxp_rxdrain(sc); 1983 goto out; 1984 } 1985 } 1986 sc->sc_rxidle = 0; 1987 1988 /* 1989 * Give the transmit ring to the chip. We do this by pointing 1990 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1991 * issuing a start command. It will execute the NOP and then 1992 * suspend, pointing at the first descriptor. 1993 */ 1994 fxp_scb_wait(sc); 1995 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1996 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1997 1998 /* 1999 * Initialize receiver buffer area - RFA. 2000 */ 2001#if 0 /* initialization will be done by FXP_SCB_INTRCNTL_REQUEST_SWI later */ 2002 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 2003 fxp_scb_wait(sc); 2004 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 2005 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 2006 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 2007#endif 2008 2009 if (sc->sc_flags & FXPF_MII) { 2010 /* 2011 * Set current media. 2012 */ 2013 if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0) 2014 goto out; 2015 } 2016 2017 /* 2018 * ...all done! 2019 */ 2020 ifp->if_flags |= IFF_RUNNING; 2021 ifp->if_flags &= ~IFF_OACTIVE; 2022 2023 /* 2024 * Request a software generated interrupt that will be used to 2025 * (re)start the RU processing. If we direct the chip to start 2026 * receiving from the start of queue now, instead of letting the 2027 * interrupt handler first process all received packets, we run 2028 * the risk of having it overwrite mbuf clusters while they are 2029 * being processed or after they have been returned to the pool. 2030 */ 2031 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTRCNTL_REQUEST_SWI); 2032 2033 /* 2034 * Start the one second timer. 2035 */ 2036 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 2037 2038 /* 2039 * Attempt to start output on the interface. 2040 */ 2041 fxp_start(ifp); 2042 2043 out: 2044 if (error) { 2045 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2046 ifp->if_timer = 0; 2047 log(LOG_ERR, "%s: interface not running\n", 2048 device_xname(sc->sc_dev)); 2049 } 2050 return (error); 2051} 2052 2053/* 2054 * Notify the world which media we're using. 2055 */ 2056void 2057fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2058{ 2059 struct fxp_softc *sc = ifp->if_softc; 2060 2061 if (sc->sc_enabled == 0) { 2062 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 2063 ifmr->ifm_status = 0; 2064 return; 2065 } 2066 2067 ether_mediastatus(ifp, ifmr); 2068} 2069 2070int 2071fxp_80c24_mediachange(struct ifnet *ifp) 2072{ 2073 2074 /* Nothing to do here. */ 2075 return (0); 2076} 2077 2078void 2079fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2080{ 2081 struct fxp_softc *sc = ifp->if_softc; 2082 2083 /* 2084 * Media is currently-selected media. We cannot determine 2085 * the link status. 2086 */ 2087 ifmr->ifm_status = 0; 2088 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 2089} 2090 2091/* 2092 * Add a buffer to the end of the RFA buffer list. 2093 * Return 0 if successful, error code on failure. 2094 * 2095 * The RFA struct is stuck at the beginning of mbuf cluster and the 2096 * data pointer is fixed up to point just past it. 2097 */ 2098int 2099fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 2100{ 2101 struct mbuf *m; 2102 int error; 2103 2104 MGETHDR(m, M_DONTWAIT, MT_DATA); 2105 if (m == NULL) 2106 return (ENOBUFS); 2107 2108 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2109 MCLGET(m, M_DONTWAIT); 2110 if ((m->m_flags & M_EXT) == 0) { 2111 m_freem(m); 2112 return (ENOBUFS); 2113 } 2114 2115 if (unload) 2116 bus_dmamap_unload(sc->sc_dmat, rxmap); 2117 2118 M_SETCTX(m, rxmap); 2119 2120 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2121 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, 2122 BUS_DMA_READ|BUS_DMA_NOWAIT); 2123 if (error) { 2124 /* XXX XXX XXX */ 2125 aprint_error_dev(sc->sc_dev, 2126 "can't load rx DMA map %d, error = %d\n", 2127 sc->sc_rxq.ifq_len, error); 2128 panic("fxp_add_rfabuf"); 2129 } 2130 2131 FXP_INIT_RFABUF(sc, m); 2132 2133 return (0); 2134} 2135 2136int 2137fxp_mdi_read(device_t self, int phy, int reg) 2138{ 2139 struct fxp_softc *sc = device_private(self); 2140 int count = 10000; 2141 int value; 2142 2143 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2144 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2145 2146 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 2147 0x10000000) == 0 && count--) 2148 DELAY(10); 2149 2150 if (count <= 0) 2151 log(LOG_WARNING, 2152 "%s: fxp_mdi_read: timed out\n", device_xname(self)); 2153 2154 return (value & 0xffff); 2155} 2156 2157void 2158fxp_statchg(device_t self) 2159{ 2160 2161 /* Nothing to do. */ 2162} 2163 2164void 2165fxp_mdi_write(device_t self, int phy, int reg, int value) 2166{ 2167 struct fxp_softc *sc = device_private(self); 2168 int count = 10000; 2169 2170 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2171 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2172 (value & 0xffff)); 2173 2174 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2175 count--) 2176 DELAY(10); 2177 2178 if (count <= 0) 2179 log(LOG_WARNING, 2180 "%s: fxp_mdi_write: timed out\n", device_xname(self)); 2181} 2182 2183int 2184fxp_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2185{ 2186 struct fxp_softc *sc = ifp->if_softc; 2187 struct ifreq *ifr = (struct ifreq *)data; 2188 int s, error; 2189 2190 s = splnet(); 2191 2192 switch (cmd) { 2193 case SIOCSIFMEDIA: 2194 case SIOCGIFMEDIA: 2195 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2196 break; 2197 2198 default: 2199 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 2200 break; 2201 2202 error = 0; 2203 2204 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2205 ; 2206 else if (ifp->if_flags & IFF_RUNNING) { 2207 /* 2208 * Multicast list has changed; set the 2209 * hardware filter accordingly. 2210 */ 2211 while (sc->sc_txpending) { 2212 sc->sc_flags |= FXPF_WANTINIT; 2213 tsleep(sc, PSOCK, "fxp_init", 0); 2214 } 2215 error = fxp_init(ifp); 2216 } 2217 break; 2218 } 2219 2220 /* Try to get more packets going. */ 2221 if (sc->sc_enabled) 2222 fxp_start(ifp); 2223 2224 splx(s); 2225 return (error); 2226} 2227 2228/* 2229 * Program the multicast filter. 2230 * 2231 * This function must be called at splnet(). 2232 */ 2233void 2234fxp_mc_setup(struct fxp_softc *sc) 2235{ 2236 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 2237 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2238 struct ethercom *ec = &sc->sc_ethercom; 2239 struct ether_multi *enm; 2240 struct ether_multistep step; 2241 int count, nmcasts; 2242 uint16_t status; 2243 2244#ifdef DIAGNOSTIC 2245 if (sc->sc_txpending) 2246 panic("fxp_mc_setup: pending transmissions"); 2247#endif 2248 2249 ifp->if_flags &= ~IFF_ALLMULTI; 2250 2251 /* 2252 * Initialize multicast setup descriptor. 2253 */ 2254 nmcasts = 0; 2255 ETHER_FIRST_MULTI(step, ec, enm); 2256 while (enm != NULL) { 2257 /* 2258 * Check for too many multicast addresses or if we're 2259 * listening to a range. Either way, we simply have 2260 * to accept all multicasts. 2261 */ 2262 if (nmcasts >= MAXMCADDR || 2263 memcmp(enm->enm_addrlo, enm->enm_addrhi, 2264 ETHER_ADDR_LEN) != 0) { 2265 /* 2266 * Callers of this function must do the 2267 * right thing with this. If we're called 2268 * from outside fxp_init(), the caller must 2269 * detect if the state if IFF_ALLMULTI changes. 2270 * If it does, the caller must then call 2271 * fxp_init(), since allmulti is handled by 2272 * the config block. 2273 */ 2274 ifp->if_flags |= IFF_ALLMULTI; 2275 return; 2276 } 2277 memcpy(&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 2278 ETHER_ADDR_LEN); 2279 nmcasts++; 2280 ETHER_NEXT_MULTI(step, enm); 2281 } 2282 2283 /* BIG_ENDIAN: no need to swap to store 0 */ 2284 mcsp->cb_status = 0; 2285 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2286 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 2287 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2288 2289 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2290 2291 /* 2292 * Wait until the command unit is not active. This should never 2293 * happen since nothing is queued, but make sure anyway. 2294 */ 2295 count = 100; 2296 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2297 FXP_SCB_CUS_ACTIVE && --count) 2298 DELAY(1); 2299 if (count == 0) { 2300 log(LOG_WARNING, "%s: line %d: command queue timeout\n", 2301 device_xname(sc->sc_dev), __LINE__); 2302 return; 2303 } 2304 2305 /* 2306 * Start the multicast setup command/DMA. 2307 */ 2308 fxp_scb_wait(sc); 2309 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2310 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2311 2312 /* ...and wait for it to complete. */ 2313 for (count = 1000; count > 0; count--) { 2314 FXP_CDMCSSYNC(sc, 2315 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2316 status = le16toh(mcsp->cb_status); 2317 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD); 2318 if ((status & FXP_CB_STATUS_C) != 0) 2319 break; 2320 DELAY(1); 2321 } 2322 if (count == 0) { 2323 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 2324 device_xname(sc->sc_dev), __LINE__); 2325 return; 2326 } 2327} 2328 2329static const uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2330static const uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2331static const uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2332static const uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2333static const uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2334static const uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2335 2336#define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2337 2338static const struct ucode { 2339 int32_t revision; 2340 const uint32_t *ucode; 2341 size_t length; 2342 uint16_t int_delay_offset; 2343 uint16_t bundle_max_offset; 2344} ucode_table[] = { 2345 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), 2346 D101_CPUSAVER_DWORD, 0 }, 2347 2348 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), 2349 D101_CPUSAVER_DWORD, 0 }, 2350 2351 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2352 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2353 2354 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2355 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2356 2357 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2358 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2359 2360 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2361 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2362 2363 { 0, NULL, 0, 0, 0 } 2364}; 2365 2366void 2367fxp_load_ucode(struct fxp_softc *sc) 2368{ 2369 const struct ucode *uc; 2370 struct fxp_cb_ucode *cbp = &sc->sc_control_data->fcd_ucode; 2371 int count, i; 2372 uint16_t status; 2373 2374 if (sc->sc_flags & FXPF_UCODE_LOADED) 2375 return; 2376 2377 /* 2378 * Only load the uCode if the user has requested that 2379 * we do so. 2380 */ 2381 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK0) == 0) { 2382 sc->sc_int_delay = 0; 2383 sc->sc_bundle_max = 0; 2384 return; 2385 } 2386 2387 for (uc = ucode_table; uc->ucode != NULL; uc++) { 2388 if (sc->sc_rev == uc->revision) 2389 break; 2390 } 2391 if (uc->ucode == NULL) 2392 return; 2393 2394 /* BIG ENDIAN: no need to swap to store 0 */ 2395 cbp->cb_status = 0; 2396 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2397 cbp->link_addr = 0xffffffff; /* (no) next command */ 2398 for (i = 0; i < uc->length; i++) 2399 cbp->ucode[i] = htole32(uc->ucode[i]); 2400 2401 if (uc->int_delay_offset) 2402 *(volatile uint16_t *) &cbp->ucode[uc->int_delay_offset] = 2403 htole16(fxp_int_delay + (fxp_int_delay / 2)); 2404 2405 if (uc->bundle_max_offset) 2406 *(volatile uint16_t *) &cbp->ucode[uc->bundle_max_offset] = 2407 htole16(fxp_bundle_max); 2408 2409 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2410 2411 /* 2412 * Download the uCode to the chip. 2413 */ 2414 fxp_scb_wait(sc); 2415 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDUCODEOFF); 2416 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2417 2418 /* ...and wait for it to complete. */ 2419 for (count = 10000; count > 0; count--) { 2420 FXP_CDUCODESYNC(sc, 2421 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2422 status = le16toh(cbp->cb_status); 2423 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD); 2424 if ((status & FXP_CB_STATUS_C) != 0) 2425 break; 2426 DELAY(2); 2427 } 2428 if (count == 0) { 2429 sc->sc_int_delay = 0; 2430 sc->sc_bundle_max = 0; 2431 log(LOG_WARNING, "%s: timeout loading microcode\n", 2432 device_xname(sc->sc_dev)); 2433 return; 2434 } 2435 2436 if (sc->sc_int_delay != fxp_int_delay || 2437 sc->sc_bundle_max != fxp_bundle_max) { 2438 sc->sc_int_delay = fxp_int_delay; 2439 sc->sc_bundle_max = fxp_bundle_max; 2440 log(LOG_INFO, "%s: Microcode loaded: int delay: %d usec, " 2441 "max bundle: %d\n", device_xname(sc->sc_dev), 2442 sc->sc_int_delay, 2443 uc->bundle_max_offset == 0 ? 0 : sc->sc_bundle_max); 2444 } 2445 2446 sc->sc_flags |= FXPF_UCODE_LOADED; 2447} 2448 2449int 2450fxp_enable(struct fxp_softc *sc) 2451{ 2452 2453 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2454 if ((*sc->sc_enable)(sc) != 0) { 2455 log(LOG_ERR, "%s: device enable failed\n", 2456 device_xname(sc->sc_dev)); 2457 return (EIO); 2458 } 2459 } 2460 2461 sc->sc_enabled = 1; 2462 return (0); 2463} 2464 2465void 2466fxp_disable(struct fxp_softc *sc) 2467{ 2468 2469 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2470 (*sc->sc_disable)(sc); 2471 sc->sc_enabled = 0; 2472 } 2473} 2474 2475/* 2476 * fxp_activate: 2477 * 2478 * Handle device activation/deactivation requests. 2479 */ 2480int 2481fxp_activate(device_t self, enum devact act) 2482{ 2483 struct fxp_softc *sc = device_private(self); 2484 int s, error = 0; 2485 2486 s = splnet(); 2487 switch (act) { 2488 case DVACT_ACTIVATE: 2489 error = EOPNOTSUPP; 2490 break; 2491 2492 case DVACT_DEACTIVATE: 2493 if (sc->sc_flags & FXPF_MII) 2494 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 2495 MII_OFFSET_ANY); 2496 if_deactivate(&sc->sc_ethercom.ec_if); 2497 break; 2498 } 2499 splx(s); 2500 2501 return (error); 2502} 2503 2504/* 2505 * fxp_detach: 2506 * 2507 * Detach an i82557 interface. 2508 */ 2509int 2510fxp_detach(struct fxp_softc *sc) 2511{ 2512 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2513 int i; 2514 2515 /* Succeed now if there's no work to do. */ 2516 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2517 return (0); 2518 2519 /* Unhook our tick handler. */ 2520 callout_stop(&sc->sc_callout); 2521 2522 if (sc->sc_flags & FXPF_MII) { 2523 /* Detach all PHYs */ 2524 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2525 } 2526 2527 /* Delete all remaining media. */ 2528 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2529 2530#if NRND > 0 2531 rnd_detach_source(&sc->rnd_source); 2532#endif 2533 ether_ifdetach(ifp); 2534 if_detach(ifp); 2535 2536 for (i = 0; i < FXP_NRFABUFS; i++) { 2537 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2538 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2539 } 2540 2541 for (i = 0; i < FXP_NTXCB; i++) { 2542 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2543 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2544 } 2545 2546 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2547 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2548 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 2549 sizeof(struct fxp_control_data)); 2550 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2551 2552 return (0); 2553} 2554