i82557.c revision 1.122
1/* $NetBSD: i82557.c,v 1.122 2009/01/18 10:37:04 mrg Exp $ */ 2 3/*- 4 * Copyright (c) 1997, 1998, 1999, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Copyright (c) 1995, David Greenman 35 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice unmodified, this list of conditions, and the following 43 * disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 61 */ 62 63/* 64 * Device driver for the Intel i82557 fast Ethernet controller, 65 * and its successors, the i82558 and i82559. 66 */ 67 68#include <sys/cdefs.h> 69__KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.122 2009/01/18 10:37:04 mrg Exp $"); 70 71#include "bpfilter.h" 72#include "rnd.h" 73 74#include <sys/param.h> 75#include <sys/systm.h> 76#include <sys/callout.h> 77#include <sys/mbuf.h> 78#include <sys/malloc.h> 79#include <sys/kernel.h> 80#include <sys/socket.h> 81#include <sys/ioctl.h> 82#include <sys/errno.h> 83#include <sys/device.h> 84#include <sys/syslog.h> 85 86#include <machine/endian.h> 87 88#include <uvm/uvm_extern.h> 89 90#if NRND > 0 91#include <sys/rnd.h> 92#endif 93 94#include <net/if.h> 95#include <net/if_dl.h> 96#include <net/if_media.h> 97#include <net/if_ether.h> 98 99#if NBPFILTER > 0 100#include <net/bpf.h> 101#endif 102 103#include <sys/bus.h> 104#include <sys/intr.h> 105 106#include <dev/mii/miivar.h> 107 108#include <dev/ic/i82557reg.h> 109#include <dev/ic/i82557var.h> 110 111#include <dev/microcode/i8255x/rcvbundl.h> 112 113/* 114 * NOTE! On the Alpha, we have an alignment constraint. The 115 * card DMAs the packet immediately following the RFA. However, 116 * the first thing in the packet is a 14-byte Ethernet header. 117 * This means that the packet is misaligned. To compensate, 118 * we actually offset the RFA 2 bytes into the cluster. This 119 * alignes the packet after the Ethernet header at a 32-bit 120 * boundary. HOWEVER! This means that the RFA is misaligned! 121 */ 122#define RFA_ALIGNMENT_FUDGE 2 123 124/* 125 * The configuration byte map has several undefined fields which 126 * must be one or must be zero. Set up a template for these bits 127 * only (assuming an i82557 chip), leaving the actual configuration 128 * for fxp_init(). 129 * 130 * See the definition of struct fxp_cb_config for the bit definitions. 131 */ 132const u_int8_t fxp_cb_config_template[] = { 133 0x0, 0x0, /* cb_status */ 134 0x0, 0x0, /* cb_command */ 135 0x0, 0x0, 0x0, 0x0, /* link_addr */ 136 0x0, /* 0 */ 137 0x0, /* 1 */ 138 0x0, /* 2 */ 139 0x0, /* 3 */ 140 0x0, /* 4 */ 141 0x0, /* 5 */ 142 0x32, /* 6 */ 143 0x0, /* 7 */ 144 0x0, /* 8 */ 145 0x0, /* 9 */ 146 0x6, /* 10 */ 147 0x0, /* 11 */ 148 0x0, /* 12 */ 149 0x0, /* 13 */ 150 0xf2, /* 14 */ 151 0x48, /* 15 */ 152 0x0, /* 16 */ 153 0x40, /* 17 */ 154 0xf0, /* 18 */ 155 0x0, /* 19 */ 156 0x3f, /* 20 */ 157 0x5, /* 21 */ 158 0x0, /* 22 */ 159 0x0, /* 23 */ 160 0x0, /* 24 */ 161 0x0, /* 25 */ 162 0x0, /* 26 */ 163 0x0, /* 27 */ 164 0x0, /* 28 */ 165 0x0, /* 29 */ 166 0x0, /* 30 */ 167 0x0, /* 31 */ 168}; 169 170void fxp_mii_initmedia(struct fxp_softc *); 171void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 172 173void fxp_80c24_initmedia(struct fxp_softc *); 174int fxp_80c24_mediachange(struct ifnet *); 175void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 176 177void fxp_start(struct ifnet *); 178int fxp_ioctl(struct ifnet *, u_long, void *); 179void fxp_watchdog(struct ifnet *); 180int fxp_init(struct ifnet *); 181void fxp_stop(struct ifnet *, int); 182 183void fxp_txintr(struct fxp_softc *); 184int fxp_rxintr(struct fxp_softc *); 185 186int fxp_rx_hwcksum(struct mbuf *, const struct fxp_rfa *); 187 188void fxp_rxdrain(struct fxp_softc *); 189int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 190int fxp_mdi_read(device_t, int, int); 191void fxp_statchg(device_t); 192void fxp_mdi_write(device_t, int, int, int); 193void fxp_autosize_eeprom(struct fxp_softc*); 194void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 195void fxp_write_eeprom(struct fxp_softc *, u_int16_t *, int, int); 196void fxp_eeprom_update_cksum(struct fxp_softc *); 197void fxp_get_info(struct fxp_softc *, u_int8_t *); 198void fxp_tick(void *); 199void fxp_mc_setup(struct fxp_softc *); 200void fxp_load_ucode(struct fxp_softc *); 201 202int fxp_copy_small = 0; 203 204/* 205 * Variables for interrupt mitigating microcode. 206 */ 207int fxp_int_delay = 1000; /* usec */ 208int fxp_bundle_max = 6; /* packets */ 209 210struct fxp_phytype { 211 int fp_phy; /* type of PHY, -1 for MII at the end. */ 212 void (*fp_init)(struct fxp_softc *); 213} fxp_phytype_table[] = { 214 { FXP_PHY_80C24, fxp_80c24_initmedia }, 215 { -1, fxp_mii_initmedia }, 216}; 217 218/* 219 * Set initial transmit threshold at 64 (512 bytes). This is 220 * increased by 64 (512 bytes) at a time, to maximum of 192 221 * (1536 bytes), if an underrun occurs. 222 */ 223static int tx_threshold = 64; 224 225/* 226 * Wait for the previous command to be accepted (but not necessarily 227 * completed). 228 */ 229static inline void 230fxp_scb_wait(struct fxp_softc *sc) 231{ 232 int i = 10000; 233 234 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 235 delay(2); 236 if (i == 0) 237 log(LOG_WARNING, 238 "%s: WARNING: SCB timed out!\n", device_xname(sc->sc_dev)); 239} 240 241/* 242 * Submit a command to the i82557. 243 */ 244static inline void 245fxp_scb_cmd(struct fxp_softc *sc, u_int8_t cmd) 246{ 247 248 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 249} 250 251/* 252 * Finish attaching an i82557 interface. Called by bus-specific front-end. 253 */ 254void 255fxp_attach(struct fxp_softc *sc) 256{ 257 u_int8_t enaddr[ETHER_ADDR_LEN]; 258 struct ifnet *ifp; 259 bus_dma_segment_t seg; 260 int rseg, i, error; 261 struct fxp_phytype *fp; 262 263 callout_init(&sc->sc_callout, 0); 264 265 /* 266 * Enable use of extended RFDs and TCBs for 82550 267 * and later chips. Note: we need extended TXCB support 268 * too, but that's already enabled by the code above. 269 * Be careful to do this only on the right devices. 270 */ 271 if (sc->sc_flags & FXPF_IPCB) 272 sc->sc_txcmd = htole16(FXP_CB_COMMAND_IPCBXMIT); 273 else 274 sc->sc_txcmd = htole16(FXP_CB_COMMAND_XMIT); 275 276 sc->sc_rfa_size = 277 (sc->sc_flags & FXPF_EXT_RFA) ? RFA_EXT_SIZE : RFA_SIZE; 278 279 /* 280 * Allocate the control data structures, and create and load the 281 * DMA map for it. 282 */ 283 if ((error = bus_dmamem_alloc(sc->sc_dmat, 284 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 285 0)) != 0) { 286 aprint_error_dev(sc->sc_dev, 287 "unable to allocate control data, error = %d\n", 288 error); 289 goto fail_0; 290 } 291 292 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 293 sizeof(struct fxp_control_data), (void **)&sc->sc_control_data, 294 BUS_DMA_COHERENT)) != 0) { 295 aprint_error_dev(sc->sc_dev, 296 "unable to map control data, error = %d\n", error); 297 goto fail_1; 298 } 299 sc->sc_cdseg = seg; 300 sc->sc_cdnseg = rseg; 301 302 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 303 304 if ((error = bus_dmamap_create(sc->sc_dmat, 305 sizeof(struct fxp_control_data), 1, 306 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 307 aprint_error_dev(sc->sc_dev, 308 "unable to create control data DMA map, error = %d\n", 309 error); 310 goto fail_2; 311 } 312 313 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 314 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 315 0)) != 0) { 316 aprint_error_dev(sc->sc_dev, 317 "can't load control data DMA map, error = %d\n", 318 error); 319 goto fail_3; 320 } 321 322 /* 323 * Create the transmit buffer DMA maps. 324 */ 325 for (i = 0; i < FXP_NTXCB; i++) { 326 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 327 (sc->sc_flags & FXPF_IPCB) ? FXP_IPCB_NTXSEG : FXP_NTXSEG, 328 MCLBYTES, 0, 0, &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 329 aprint_error_dev(sc->sc_dev, 330 "unable to create tx DMA map %d, error = %d\n", 331 i, error); 332 goto fail_4; 333 } 334 } 335 336 /* 337 * Create the receive buffer DMA maps. 338 */ 339 for (i = 0; i < FXP_NRFABUFS; i++) { 340 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 341 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 342 aprint_error_dev(sc->sc_dev, 343 "unable to create rx DMA map %d, error = %d\n", 344 i, error); 345 goto fail_5; 346 } 347 } 348 349 /* Initialize MAC address and media structures. */ 350 fxp_get_info(sc, enaddr); 351 352 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 353 ether_sprintf(enaddr)); 354 355 ifp = &sc->sc_ethercom.ec_if; 356 357 /* 358 * Get info about our media interface, and initialize it. Note 359 * the table terminates itself with a phy of -1, indicating 360 * that we're using MII. 361 */ 362 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 363 if (fp->fp_phy == sc->phy_primary_device) 364 break; 365 (*fp->fp_init)(sc); 366 367 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 368 ifp->if_softc = sc; 369 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 370 ifp->if_ioctl = fxp_ioctl; 371 ifp->if_start = fxp_start; 372 ifp->if_watchdog = fxp_watchdog; 373 ifp->if_init = fxp_init; 374 ifp->if_stop = fxp_stop; 375 IFQ_SET_READY(&ifp->if_snd); 376 377 if (sc->sc_flags & FXPF_IPCB) { 378 KASSERT(sc->sc_flags & FXPF_EXT_RFA); /* we have both or none */ 379 /* 380 * IFCAP_CSUM_IPv4_Tx seems to have a problem, 381 * at least, on i82550 rev.12. 382 * specifically, it doesn't set ipv4 checksum properly 383 * when sending UDP (and probably TCP) packets with 384 * 20 byte ipv4 header + 1 or 2 byte data, 385 * though ICMP packets seem working. 386 * FreeBSD driver has related comments. 387 * We've added a workaround to handle the bug by padding 388 * such packets manually. 389 */ 390 ifp->if_capabilities = 391 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 392 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 393 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 394 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 395 } 396 397 /* 398 * We can support 802.1Q VLAN-sized frames. 399 */ 400 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 401 402 /* 403 * Attach the interface. 404 */ 405 if_attach(ifp); 406 ether_ifattach(ifp, enaddr); 407#if NRND > 0 408 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 409 RND_TYPE_NET, 0); 410#endif 411 412#ifdef FXP_EVENT_COUNTERS 413 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 414 NULL, device_xname(sc->sc_dev), "txstall"); 415 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 416 NULL, device_xname(sc->sc_dev), "txintr"); 417 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 418 NULL, device_xname(sc->sc_dev), "rxintr"); 419 if (sc->sc_flags & FXPF_FC) { 420 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 421 NULL, device_xname(sc->sc_dev), "txpause"); 422 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 423 NULL, device_xname(sc->sc_dev), "rxpause"); 424 } 425#endif /* FXP_EVENT_COUNTERS */ 426 427 /* The attach is successful. */ 428 sc->sc_flags |= FXPF_ATTACHED; 429 430 return; 431 432 /* 433 * Free any resources we've allocated during the failed attach 434 * attempt. Do this in reverse order and fall though. 435 */ 436 fail_5: 437 for (i = 0; i < FXP_NRFABUFS; i++) { 438 if (sc->sc_rxmaps[i] != NULL) 439 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 440 } 441 fail_4: 442 for (i = 0; i < FXP_NTXCB; i++) { 443 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 444 bus_dmamap_destroy(sc->sc_dmat, 445 FXP_DSTX(sc, i)->txs_dmamap); 446 } 447 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 448 fail_3: 449 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 450 fail_2: 451 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 452 sizeof(struct fxp_control_data)); 453 fail_1: 454 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 455 fail_0: 456 return; 457} 458 459void 460fxp_mii_initmedia(struct fxp_softc *sc) 461{ 462 int flags; 463 464 sc->sc_flags |= FXPF_MII; 465 466 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 467 sc->sc_mii.mii_readreg = fxp_mdi_read; 468 sc->sc_mii.mii_writereg = fxp_mdi_write; 469 sc->sc_mii.mii_statchg = fxp_statchg; 470 471 sc->sc_ethercom.ec_mii = &sc->sc_mii; 472 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 473 fxp_mii_mediastatus); 474 475 flags = MIIF_NOISOLATE; 476 if (sc->sc_flags & FXPF_FC) 477 flags |= MIIF_FORCEANEG|MIIF_DOPAUSE; 478 /* 479 * The i82557 wedges if all of its PHYs are isolated! 480 */ 481 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 482 MII_OFFSET_ANY, flags); 483 if (LIST_EMPTY(&sc->sc_mii.mii_phys)) { 484 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 485 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 486 } else 487 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 488} 489 490void 491fxp_80c24_initmedia(struct fxp_softc *sc) 492{ 493 494 /* 495 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 496 * doesn't have a programming interface of any sort. The 497 * media is sensed automatically based on how the link partner 498 * is configured. This is, in essence, manual configuration. 499 */ 500 aprint_normal_dev(sc->sc_dev, 501 "Seeq 80c24 AutoDUPLEX media interface present\n"); 502 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 503 fxp_80c24_mediastatus); 504 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 505 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 506} 507 508/* 509 * Initialize the interface media. 510 */ 511void 512fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 513{ 514 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 515 516 /* 517 * Reset to a stable state. 518 */ 519 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 520 DELAY(100); 521 522 sc->sc_eeprom_size = 0; 523 fxp_autosize_eeprom(sc); 524 if (sc->sc_eeprom_size == 0) { 525 aprint_error_dev(sc->sc_dev, "failed to detect EEPROM size\n"); 526 sc->sc_eeprom_size = 6; /* XXX panic here? */ 527 } 528#ifdef DEBUG 529 aprint_debug_dev(sc->sc_dev, "detected %d word EEPROM\n", 530 1 << sc->sc_eeprom_size); 531#endif 532 533 /* 534 * Get info about the primary PHY 535 */ 536 fxp_read_eeprom(sc, &data, 6, 1); 537 sc->phy_primary_device = 538 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 539 540 /* 541 * Read MAC address. 542 */ 543 fxp_read_eeprom(sc, myea, 0, 3); 544 enaddr[0] = myea[0] & 0xff; 545 enaddr[1] = myea[0] >> 8; 546 enaddr[2] = myea[1] & 0xff; 547 enaddr[3] = myea[1] >> 8; 548 enaddr[4] = myea[2] & 0xff; 549 enaddr[5] = myea[2] >> 8; 550 551 /* 552 * Systems based on the ICH2/ICH2-M chip from Intel, as well 553 * as some i82559 designs, have a defect where the chip can 554 * cause a PCI protocol violation if it receives a CU_RESUME 555 * command when it is entering the IDLE state. 556 * 557 * The work-around is to disable Dynamic Standby Mode, so that 558 * the chip never deasserts #CLKRUN, and always remains in the 559 * active state. 560 * 561 * Unfortunately, the only way to disable Dynamic Standby is 562 * to frob an EEPROM setting and reboot (the EEPROM setting 563 * is only consulted when the PCI bus comes out of reset). 564 * 565 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 566 */ 567 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 568 fxp_read_eeprom(sc, &data, 10, 1); 569 if (data & 0x02) { /* STB enable */ 570 aprint_error_dev(sc->sc_dev, "WARNING: " 571 "Disabling dynamic standby mode in EEPROM " 572 "to work around a\n"); 573 aprint_normal_dev(sc->sc_dev, 574 "WARNING: hardware bug. You must reset " 575 "the system before using this\n"); 576 aprint_normal_dev(sc->sc_dev, "WARNING: interface.\n"); 577 data &= ~0x02; 578 fxp_write_eeprom(sc, &data, 10, 1); 579 aprint_normal_dev(sc->sc_dev, "new EEPROM ID: 0x%04x\n", 580 data); 581 fxp_eeprom_update_cksum(sc); 582 } 583 } 584 585 /* Receiver lock-up workaround detection. (FXPF_RECV_WORKAROUND) */ 586 /* Due to false positives we make it conditional on setting link1 */ 587 fxp_read_eeprom(sc, &data, 3, 1); 588 if ((data & 0x03) != 0x03) { 589 aprint_verbose_dev(sc->sc_dev, 590 "May need receiver lock-up workaround\n"); 591 } 592} 593 594static void 595fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 596{ 597 uint16_t reg; 598 int x; 599 600 for (x = 1 << (len - 1); x != 0; x >>= 1) { 601 DELAY(40); 602 if (data & x) 603 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 604 else 605 reg = FXP_EEPROM_EECS; 606 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 607 DELAY(40); 608 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 609 reg | FXP_EEPROM_EESK); 610 DELAY(40); 611 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 612 } 613 DELAY(40); 614} 615 616/* 617 * Figure out EEPROM size. 618 * 619 * 559's can have either 64-word or 256-word EEPROMs, the 558 620 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 621 * talks about the existence of 16 to 256 word EEPROMs. 622 * 623 * The only known sizes are 64 and 256, where the 256 version is used 624 * by CardBus cards to store CIS information. 625 * 626 * The address is shifted in msb-to-lsb, and after the last 627 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 628 * after which follows the actual data. We try to detect this zero, by 629 * probing the data-out bit in the EEPROM control register just after 630 * having shifted in a bit. If the bit is zero, we assume we've 631 * shifted enough address bits. The data-out should be tri-state, 632 * before this, which should translate to a logical one. 633 * 634 * Other ways to do this would be to try to read a register with known 635 * contents with a varying number of address bits, but no such 636 * register seem to be available. The high bits of register 10 are 01 637 * on the 558 and 559, but apparently not on the 557. 638 * 639 * The Linux driver computes a checksum on the EEPROM data, but the 640 * value of this checksum is not very well documented. 641 */ 642 643void 644fxp_autosize_eeprom(struct fxp_softc *sc) 645{ 646 int x; 647 648 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 649 DELAY(40); 650 651 /* Shift in read opcode. */ 652 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 653 654 /* 655 * Shift in address, wait for the dummy zero following a correct 656 * address shift. 657 */ 658 for (x = 1; x <= 8; x++) { 659 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 660 DELAY(40); 661 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 662 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 663 DELAY(40); 664 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 665 FXP_EEPROM_EEDO) == 0) 666 break; 667 DELAY(40); 668 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 669 DELAY(40); 670 } 671 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 672 DELAY(40); 673 if (x != 6 && x != 8) { 674#ifdef DEBUG 675 printf("%s: strange EEPROM size (%d)\n", 676 device_xname(sc->sc_dev), 1 << x); 677#endif 678 } else 679 sc->sc_eeprom_size = x; 680} 681 682/* 683 * Read from the serial EEPROM. Basically, you manually shift in 684 * the read opcode (one bit at a time) and then shift in the address, 685 * and then you shift out the data (all of this one bit at a time). 686 * The word size is 16 bits, so you have to provide the address for 687 * every 16 bits of data. 688 */ 689void 690fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 691{ 692 u_int16_t reg; 693 int i, x; 694 695 for (i = 0; i < words; i++) { 696 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 697 698 /* Shift in read opcode. */ 699 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 700 701 /* Shift in address. */ 702 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 703 704 reg = FXP_EEPROM_EECS; 705 data[i] = 0; 706 707 /* Shift out data. */ 708 for (x = 16; x > 0; x--) { 709 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 710 reg | FXP_EEPROM_EESK); 711 DELAY(40); 712 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 713 FXP_EEPROM_EEDO) 714 data[i] |= (1 << (x - 1)); 715 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 716 DELAY(40); 717 } 718 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 719 DELAY(40); 720 } 721} 722 723/* 724 * Write data to the serial EEPROM. 725 */ 726void 727fxp_write_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 728{ 729 int i, j; 730 731 for (i = 0; i < words; i++) { 732 /* Erase/write enable. */ 733 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 734 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 735 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 736 sc->sc_eeprom_size); 737 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 738 DELAY(4); 739 740 /* Shift in write opcode, address, data. */ 741 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 742 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 743 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 744 fxp_eeprom_shiftin(sc, data[i], 16); 745 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 746 DELAY(4); 747 748 /* Wait for the EEPROM to finish up. */ 749 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 750 DELAY(4); 751 for (j = 0; j < 1000; j++) { 752 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 753 FXP_EEPROM_EEDO) 754 break; 755 DELAY(50); 756 } 757 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 758 DELAY(4); 759 760 /* Erase/write disable. */ 761 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 762 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 763 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 764 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 765 DELAY(4); 766 } 767} 768 769/* 770 * Update the checksum of the EEPROM. 771 */ 772void 773fxp_eeprom_update_cksum(struct fxp_softc *sc) 774{ 775 int i; 776 uint16_t data, cksum; 777 778 cksum = 0; 779 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 780 fxp_read_eeprom(sc, &data, i, 1); 781 cksum += data; 782 } 783 i = (1 << sc->sc_eeprom_size) - 1; 784 cksum = 0xbaba - cksum; 785 fxp_read_eeprom(sc, &data, i, 1); 786 fxp_write_eeprom(sc, &cksum, i, 1); 787 log(LOG_INFO, "%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 788 device_xname(sc->sc_dev), i, data, cksum); 789} 790 791/* 792 * Start packet transmission on the interface. 793 */ 794void 795fxp_start(struct ifnet *ifp) 796{ 797 struct fxp_softc *sc = ifp->if_softc; 798 struct mbuf *m0, *m; 799 struct fxp_txdesc *txd; 800 struct fxp_txsoft *txs; 801 bus_dmamap_t dmamap; 802 int error, lasttx, nexttx, opending, seg, nsegs, len; 803 804 /* 805 * If we want a re-init, bail out now. 806 */ 807 if (sc->sc_flags & FXPF_WANTINIT) { 808 ifp->if_flags |= IFF_OACTIVE; 809 return; 810 } 811 812 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 813 return; 814 815 /* 816 * Remember the previous txpending and the current lasttx. 817 */ 818 opending = sc->sc_txpending; 819 lasttx = sc->sc_txlast; 820 821 /* 822 * Loop through the send queue, setting up transmit descriptors 823 * until we drain the queue, or use up all available transmit 824 * descriptors. 825 */ 826 for (;;) { 827 struct fxp_tbd *tbdp; 828 int csum_flags; 829 830 /* 831 * Grab a packet off the queue. 832 */ 833 IFQ_POLL(&ifp->if_snd, m0); 834 if (m0 == NULL) 835 break; 836 m = NULL; 837 838 if (sc->sc_txpending == FXP_NTXCB - 1) { 839 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 840 break; 841 } 842 843 /* 844 * Get the next available transmit descriptor. 845 */ 846 nexttx = FXP_NEXTTX(sc->sc_txlast); 847 txd = FXP_CDTX(sc, nexttx); 848 txs = FXP_DSTX(sc, nexttx); 849 dmamap = txs->txs_dmamap; 850 851 /* 852 * Load the DMA map. If this fails, the packet either 853 * didn't fit in the allotted number of frags, or we were 854 * short on resources. In this case, we'll copy and try 855 * again. 856 */ 857 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 858 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 859 MGETHDR(m, M_DONTWAIT, MT_DATA); 860 if (m == NULL) { 861 log(LOG_ERR, "%s: unable to allocate Tx mbuf\n", 862 device_xname(sc->sc_dev)); 863 break; 864 } 865 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 866 if (m0->m_pkthdr.len > MHLEN) { 867 MCLGET(m, M_DONTWAIT); 868 if ((m->m_flags & M_EXT) == 0) { 869 log(LOG_ERR, "%s: unable to allocate " 870 "Tx cluster\n", 871 device_xname(sc->sc_dev)); 872 m_freem(m); 873 break; 874 } 875 } 876 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 877 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 878 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 879 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 880 if (error) { 881 log(LOG_ERR, "%s: unable to load Tx buffer, " 882 "error = %d\n", 883 device_xname(sc->sc_dev), error); 884 break; 885 } 886 } 887 888 IFQ_DEQUEUE(&ifp->if_snd, m0); 889 csum_flags = m0->m_pkthdr.csum_flags; 890 if (m != NULL) { 891 m_freem(m0); 892 m0 = m; 893 } 894 895 /* Initialize the fraglist. */ 896 tbdp = txd->txd_tbd; 897 len = m0->m_pkthdr.len; 898 nsegs = dmamap->dm_nsegs; 899 if (sc->sc_flags & FXPF_IPCB) 900 tbdp++; 901 for (seg = 0; seg < nsegs; seg++) { 902 tbdp[seg].tb_addr = 903 htole32(dmamap->dm_segs[seg].ds_addr); 904 tbdp[seg].tb_size = 905 htole32(dmamap->dm_segs[seg].ds_len); 906 } 907 if (__predict_false(len <= FXP_IP4CSUMTX_PADLEN && 908 (csum_flags & M_CSUM_IPv4) != 0)) { 909 /* 910 * Pad short packets to avoid ip4csum-tx bug. 911 * 912 * XXX Should we still consider if such short 913 * (36 bytes or less) packets might already 914 * occupy FXP_IPCB_NTXSEG (15) fragments here? 915 */ 916 KASSERT(nsegs < FXP_IPCB_NTXSEG); 917 nsegs++; 918 tbdp[seg].tb_addr = htole32(FXP_CDTXPADADDR(sc)); 919 tbdp[seg].tb_size = 920 htole32(FXP_IP4CSUMTX_PADLEN + 1 - len); 921 } 922 923 /* Sync the DMA map. */ 924 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 925 BUS_DMASYNC_PREWRITE); 926 927 /* 928 * Store a pointer to the packet so we can free it later. 929 */ 930 txs->txs_mbuf = m0; 931 932 /* 933 * Initialize the transmit descriptor. 934 */ 935 /* BIG_ENDIAN: no need to swap to store 0 */ 936 txd->txd_txcb.cb_status = 0; 937 txd->txd_txcb.cb_command = 938 sc->sc_txcmd | htole16(FXP_CB_COMMAND_SF); 939 txd->txd_txcb.tx_threshold = tx_threshold; 940 txd->txd_txcb.tbd_number = nsegs; 941 942 KASSERT((csum_flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) == 0); 943 if (sc->sc_flags & FXPF_IPCB) { 944 struct m_tag *vtag; 945 struct fxp_ipcb *ipcb; 946 /* 947 * Deal with TCP/IP checksum offload. Note that 948 * in order for TCP checksum offload to work, 949 * the pseudo header checksum must have already 950 * been computed and stored in the checksum field 951 * in the TCP header. The stack should have 952 * already done this for us. 953 */ 954 ipcb = &txd->txd_u.txdu_ipcb; 955 memset(ipcb, 0, sizeof(*ipcb)); 956 /* 957 * always do hardware parsing. 958 */ 959 ipcb->ipcb_ip_activation_high = 960 FXP_IPCB_HARDWAREPARSING_ENABLE; 961 /* 962 * ip checksum offloading. 963 */ 964 if (csum_flags & M_CSUM_IPv4) { 965 ipcb->ipcb_ip_schedule |= 966 FXP_IPCB_IP_CHECKSUM_ENABLE; 967 } 968 /* 969 * TCP/UDP checksum offloading. 970 */ 971 if (csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 972 ipcb->ipcb_ip_schedule |= 973 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 974 } 975 976 /* 977 * request VLAN tag insertion if needed. 978 */ 979 vtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0); 980 if (vtag) { 981 ipcb->ipcb_vlan_id = 982 htobe16(*(u_int *)(vtag + 1)); 983 ipcb->ipcb_ip_activation_high |= 984 FXP_IPCB_INSERTVLAN_ENABLE; 985 } 986 } else { 987 KASSERT((csum_flags & 988 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) == 0); 989 } 990 991 FXP_CDTXSYNC(sc, nexttx, 992 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 993 994 /* Advance the tx pointer. */ 995 sc->sc_txpending++; 996 sc->sc_txlast = nexttx; 997 998#if NBPFILTER > 0 999 /* 1000 * Pass packet to bpf if there is a listener. 1001 */ 1002 if (ifp->if_bpf) 1003 bpf_mtap(ifp->if_bpf, m0); 1004#endif 1005 } 1006 1007 if (sc->sc_txpending == FXP_NTXCB - 1) { 1008 /* No more slots; notify upper layer. */ 1009 ifp->if_flags |= IFF_OACTIVE; 1010 } 1011 1012 if (sc->sc_txpending != opending) { 1013 /* 1014 * We enqueued packets. If the transmitter was idle, 1015 * reset the txdirty pointer. 1016 */ 1017 if (opending == 0) 1018 sc->sc_txdirty = FXP_NEXTTX(lasttx); 1019 1020 /* 1021 * Cause the chip to interrupt and suspend command 1022 * processing once the last packet we've enqueued 1023 * has been transmitted. 1024 * 1025 * To avoid a race between updating status bits 1026 * by the fxp chip and clearing command bits 1027 * by this function on machines which don't have 1028 * atomic methods to clear/set bits in memory 1029 * smaller than 32bits (both cb_status and cb_command 1030 * members are uint16_t and in the same 32bit word), 1031 * we have to prepare a dummy TX descriptor which has 1032 * NOP command and just causes a TX completion interrupt. 1033 */ 1034 sc->sc_txpending++; 1035 sc->sc_txlast = FXP_NEXTTX(sc->sc_txlast); 1036 txd = FXP_CDTX(sc, sc->sc_txlast); 1037 /* BIG_ENDIAN: no need to swap to store 0 */ 1038 txd->txd_txcb.cb_status = 0; 1039 txd->txd_txcb.cb_command = htole16(FXP_CB_COMMAND_NOP | 1040 FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 1041 FXP_CDTXSYNC(sc, sc->sc_txlast, 1042 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1043 1044 /* 1045 * The entire packet chain is set up. Clear the suspend bit 1046 * on the command prior to the first packet we set up. 1047 */ 1048 FXP_CDTXSYNC(sc, lasttx, 1049 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1050 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 1051 htole16(~FXP_CB_COMMAND_S); 1052 FXP_CDTXSYNC(sc, lasttx, 1053 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1054 1055 /* 1056 * Issue a Resume command in case the chip was suspended. 1057 */ 1058 fxp_scb_wait(sc); 1059 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1060 1061 /* Set a watchdog timer in case the chip flakes out. */ 1062 ifp->if_timer = 5; 1063 } 1064} 1065 1066/* 1067 * Process interface interrupts. 1068 */ 1069int 1070fxp_intr(void *arg) 1071{ 1072 struct fxp_softc *sc = arg; 1073 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1074 bus_dmamap_t rxmap; 1075 int claimed = 0, rnr; 1076 u_int8_t statack; 1077 1078 if (!device_is_active(sc->sc_dev) || sc->sc_enabled == 0) 1079 return (0); 1080 /* 1081 * If the interface isn't running, don't try to 1082 * service the interrupt.. just ack it and bail. 1083 */ 1084 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1085 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1086 if (statack) { 1087 claimed = 1; 1088 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1089 } 1090 return (claimed); 1091 } 1092 1093 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1094 claimed = 1; 1095 1096 /* 1097 * First ACK all the interrupts in this pass. 1098 */ 1099 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1100 1101 /* 1102 * Process receiver interrupts. If a no-resource (RNR) 1103 * condition exists, get whatever packets we can and 1104 * re-start the receiver. 1105 */ 1106 rnr = (statack & (FXP_SCB_STATACK_RNR | FXP_SCB_STATACK_SWI)) ? 1107 1 : 0; 1108 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR | 1109 FXP_SCB_STATACK_SWI)) { 1110 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1111 rnr |= fxp_rxintr(sc); 1112 } 1113 1114 /* 1115 * Free any finished transmit mbuf chains. 1116 */ 1117 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1118 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1119 fxp_txintr(sc); 1120 1121 /* 1122 * Try to get more packets going. 1123 */ 1124 fxp_start(ifp); 1125 1126 if (sc->sc_txpending == 0) { 1127 /* 1128 * Tell them that they can re-init now. 1129 */ 1130 if (sc->sc_flags & FXPF_WANTINIT) 1131 wakeup(sc); 1132 } 1133 } 1134 1135 if (rnr) { 1136 fxp_scb_wait(sc); 1137 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_ABORT); 1138 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1139 fxp_scb_wait(sc); 1140 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1141 rxmap->dm_segs[0].ds_addr + 1142 RFA_ALIGNMENT_FUDGE); 1143 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1144 } 1145 } 1146 1147#if NRND > 0 1148 if (claimed) 1149 rnd_add_uint32(&sc->rnd_source, statack); 1150#endif 1151 return (claimed); 1152} 1153 1154/* 1155 * Handle transmit completion interrupts. 1156 */ 1157void 1158fxp_txintr(struct fxp_softc *sc) 1159{ 1160 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1161 struct fxp_txdesc *txd; 1162 struct fxp_txsoft *txs; 1163 int i; 1164 u_int16_t txstat; 1165 1166 ifp->if_flags &= ~IFF_OACTIVE; 1167 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1168 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1169 txd = FXP_CDTX(sc, i); 1170 txs = FXP_DSTX(sc, i); 1171 1172 FXP_CDTXSYNC(sc, i, 1173 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1174 1175 /* skip dummy NOP TX descriptor */ 1176 if ((le16toh(txd->txd_txcb.cb_command) & FXP_CB_COMMAND_CMD) 1177 == FXP_CB_COMMAND_NOP) 1178 continue; 1179 1180 txstat = le16toh(txd->txd_txcb.cb_status); 1181 1182 if ((txstat & FXP_CB_STATUS_C) == 0) 1183 break; 1184 1185 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1186 0, txs->txs_dmamap->dm_mapsize, 1187 BUS_DMASYNC_POSTWRITE); 1188 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1189 m_freem(txs->txs_mbuf); 1190 txs->txs_mbuf = NULL; 1191 } 1192 1193 /* Update the dirty transmit buffer pointer. */ 1194 sc->sc_txdirty = i; 1195 1196 /* 1197 * Cancel the watchdog timer if there are no pending 1198 * transmissions. 1199 */ 1200 if (sc->sc_txpending == 0) 1201 ifp->if_timer = 0; 1202} 1203 1204/* 1205 * fxp_rx_hwcksum: check status of H/W offloading for received packets. 1206 */ 1207 1208int 1209fxp_rx_hwcksum(struct mbuf *m, const struct fxp_rfa *rfa) 1210{ 1211 u_int8_t rxparsestat; 1212 u_int8_t csum_stat; 1213 u_int32_t csum_data; 1214 int csum_flags; 1215 1216 /* 1217 * check VLAN tag stripping. 1218 */ 1219 1220 if (rfa->rfa_status & htole16(FXP_RFA_STATUS_VLAN)) { 1221 struct m_tag *vtag; 1222 1223 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), M_NOWAIT); 1224 if (vtag == NULL) 1225 return ENOMEM; 1226 *(u_int *)(vtag + 1) = be16toh(rfa->vlan_id); 1227 m_tag_prepend(m, vtag); 1228 } 1229 1230 /* 1231 * check H/W Checksumming. 1232 */ 1233 1234 csum_stat = rfa->cksum_stat; 1235 rxparsestat = rfa->rx_parse_stat; 1236 if (!(rfa->rfa_status & htole16(FXP_RFA_STATUS_PARSE))) 1237 return 0; 1238 1239 csum_flags = 0; 1240 csum_data = 0; 1241 1242 if (csum_stat & FXP_RFDX_CS_IP_CSUM_BIT_VALID) { 1243 csum_flags = M_CSUM_IPv4; 1244 if (!(csum_stat & FXP_RFDX_CS_IP_CSUM_VALID)) 1245 csum_flags |= M_CSUM_IPv4_BAD; 1246 } 1247 1248 if (csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) { 1249 csum_flags |= (M_CSUM_TCPv4|M_CSUM_UDPv4); /* XXX */ 1250 if (!(csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) 1251 csum_flags |= M_CSUM_TCP_UDP_BAD; 1252 } 1253 1254 m->m_pkthdr.csum_flags = csum_flags; 1255 m->m_pkthdr.csum_data = csum_data; 1256 1257 return 0; 1258} 1259 1260/* 1261 * Handle receive interrupts. 1262 */ 1263int 1264fxp_rxintr(struct fxp_softc *sc) 1265{ 1266 struct ethercom *ec = &sc->sc_ethercom; 1267 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1268 struct mbuf *m, *m0; 1269 bus_dmamap_t rxmap; 1270 struct fxp_rfa *rfa; 1271 int rnr; 1272 u_int16_t len, rxstat; 1273 1274 rnr = 0; 1275 1276 for (;;) { 1277 m = sc->sc_rxq.ifq_head; 1278 rfa = FXP_MTORFA(m); 1279 rxmap = M_GETCTX(m, bus_dmamap_t); 1280 1281 FXP_RFASYNC(sc, m, 1282 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1283 1284 rxstat = le16toh(rfa->rfa_status); 1285 1286 if ((rxstat & FXP_RFA_STATUS_RNR) != 0) 1287 rnr = 1; 1288 1289 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1290 /* 1291 * We have processed all of the 1292 * receive buffers. 1293 */ 1294 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1295 return rnr; 1296 } 1297 1298 IF_DEQUEUE(&sc->sc_rxq, m); 1299 1300 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1301 1302 len = le16toh(rfa->actual_size) & 1303 (m->m_ext.ext_size - 1); 1304 1305 if (len < sizeof(struct ether_header)) { 1306 /* 1307 * Runt packet; drop it now. 1308 */ 1309 FXP_INIT_RFABUF(sc, m); 1310 continue; 1311 } 1312 1313 /* 1314 * If support for 802.1Q VLAN sized frames is 1315 * enabled, we need to do some additional error 1316 * checking (as we are saving bad frames, in 1317 * order to receive the larger ones). 1318 */ 1319 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1320 (rxstat & (FXP_RFA_STATUS_OVERRUN| 1321 FXP_RFA_STATUS_RNR| 1322 FXP_RFA_STATUS_ALIGN| 1323 FXP_RFA_STATUS_CRC)) != 0) { 1324 FXP_INIT_RFABUF(sc, m); 1325 continue; 1326 } 1327 1328 /* Do checksum checking. */ 1329 m->m_pkthdr.csum_flags = 0; 1330 if (sc->sc_flags & FXPF_EXT_RFA) 1331 if (fxp_rx_hwcksum(m, rfa)) 1332 goto dropit; 1333 1334 /* 1335 * If the packet is small enough to fit in a 1336 * single header mbuf, allocate one and copy 1337 * the data into it. This greatly reduces 1338 * memory consumption when we receive lots 1339 * of small packets. 1340 * 1341 * Otherwise, we add a new buffer to the receive 1342 * chain. If this fails, we drop the packet and 1343 * recycle the old buffer. 1344 */ 1345 if (fxp_copy_small != 0 && len <= MHLEN) { 1346 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1347 if (m0 == NULL) 1348 goto dropit; 1349 MCLAIM(m0, &sc->sc_ethercom.ec_rx_mowner); 1350 memcpy(mtod(m0, void *), 1351 mtod(m, void *), len); 1352 m0->m_pkthdr.csum_flags = m->m_pkthdr.csum_flags; 1353 m0->m_pkthdr.csum_data = m->m_pkthdr.csum_data; 1354 FXP_INIT_RFABUF(sc, m); 1355 m = m0; 1356 } else { 1357 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1358 dropit: 1359 ifp->if_ierrors++; 1360 FXP_INIT_RFABUF(sc, m); 1361 continue; 1362 } 1363 } 1364 1365 m->m_pkthdr.rcvif = ifp; 1366 m->m_pkthdr.len = m->m_len = len; 1367 1368#if NBPFILTER > 0 1369 /* 1370 * Pass this up to any BPF listeners, but only 1371 * pass it up the stack if it's for us. 1372 */ 1373 if (ifp->if_bpf) 1374 bpf_mtap(ifp->if_bpf, m); 1375#endif 1376 1377 /* Pass it on. */ 1378 (*ifp->if_input)(ifp, m); 1379 } 1380} 1381 1382/* 1383 * Update packet in/out/collision statistics. The i82557 doesn't 1384 * allow you to access these counters without doing a fairly 1385 * expensive DMA to get _all_ of the statistics it maintains, so 1386 * we do this operation here only once per second. The statistics 1387 * counters in the kernel are updated from the previous dump-stats 1388 * DMA and then a new dump-stats DMA is started. The on-chip 1389 * counters are zeroed when the DMA completes. If we can't start 1390 * the DMA immediately, we don't wait - we just prepare to read 1391 * them again next time. 1392 */ 1393void 1394fxp_tick(void *arg) 1395{ 1396 struct fxp_softc *sc = arg; 1397 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1398 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1399 int s; 1400 1401 if (!device_is_active(sc->sc_dev)) 1402 return; 1403 1404 s = splnet(); 1405 1406 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1407 1408 ifp->if_opackets += le32toh(sp->tx_good); 1409 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1410 if (sp->rx_good) { 1411 ifp->if_ipackets += le32toh(sp->rx_good); 1412 sc->sc_rxidle = 0; 1413 } else if (sc->sc_flags & FXPF_RECV_WORKAROUND) { 1414 sc->sc_rxidle++; 1415 } 1416 ifp->if_ierrors += 1417 le32toh(sp->rx_crc_errors) + 1418 le32toh(sp->rx_alignment_errors) + 1419 le32toh(sp->rx_rnr_errors) + 1420 le32toh(sp->rx_overrun_errors); 1421 /* 1422 * If any transmit underruns occurred, bump up the transmit 1423 * threshold by another 512 bytes (64 * 8). 1424 */ 1425 if (sp->tx_underruns) { 1426 ifp->if_oerrors += le32toh(sp->tx_underruns); 1427 if (tx_threshold < 192) 1428 tx_threshold += 64; 1429 } 1430#ifdef FXP_EVENT_COUNTERS 1431 if (sc->sc_flags & FXPF_FC) { 1432 sc->sc_ev_txpause.ev_count += sp->tx_pauseframes; 1433 sc->sc_ev_rxpause.ev_count += sp->rx_pauseframes; 1434 } 1435#endif 1436 1437 /* 1438 * If we haven't received any packets in FXP_MAX_RX_IDLE seconds, 1439 * then assume the receiver has locked up and attempt to clear 1440 * the condition by reprogramming the multicast filter (actually, 1441 * resetting the interface). This is a work-around for a bug in 1442 * the 82557 where the receiver locks up if it gets certain types 1443 * of garbage in the synchronization bits prior to the packet header. 1444 * This bug is supposed to only occur in 10Mbps mode, but has been 1445 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1446 * speed transition). 1447 */ 1448 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1449 (void) fxp_init(ifp); 1450 splx(s); 1451 return; 1452 } 1453 /* 1454 * If there is no pending command, start another stats 1455 * dump. Otherwise punt for now. 1456 */ 1457 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1458 /* 1459 * Start another stats dump. 1460 */ 1461 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1462 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1463 } else { 1464 /* 1465 * A previous command is still waiting to be accepted. 1466 * Just zero our copy of the stats and wait for the 1467 * next timer event to update them. 1468 */ 1469 /* BIG_ENDIAN: no swap required to store 0 */ 1470 sp->tx_good = 0; 1471 sp->tx_underruns = 0; 1472 sp->tx_total_collisions = 0; 1473 1474 sp->rx_good = 0; 1475 sp->rx_crc_errors = 0; 1476 sp->rx_alignment_errors = 0; 1477 sp->rx_rnr_errors = 0; 1478 sp->rx_overrun_errors = 0; 1479 if (sc->sc_flags & FXPF_FC) { 1480 sp->tx_pauseframes = 0; 1481 sp->rx_pauseframes = 0; 1482 } 1483 } 1484 1485 if (sc->sc_flags & FXPF_MII) { 1486 /* Tick the MII clock. */ 1487 mii_tick(&sc->sc_mii); 1488 } 1489 1490 splx(s); 1491 1492 /* 1493 * Schedule another timeout one second from now. 1494 */ 1495 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1496} 1497 1498/* 1499 * Drain the receive queue. 1500 */ 1501void 1502fxp_rxdrain(struct fxp_softc *sc) 1503{ 1504 bus_dmamap_t rxmap; 1505 struct mbuf *m; 1506 1507 for (;;) { 1508 IF_DEQUEUE(&sc->sc_rxq, m); 1509 if (m == NULL) 1510 break; 1511 rxmap = M_GETCTX(m, bus_dmamap_t); 1512 bus_dmamap_unload(sc->sc_dmat, rxmap); 1513 FXP_RXMAP_PUT(sc, rxmap); 1514 m_freem(m); 1515 } 1516} 1517 1518/* 1519 * Stop the interface. Cancels the statistics updater and resets 1520 * the interface. 1521 */ 1522void 1523fxp_stop(struct ifnet *ifp, int disable) 1524{ 1525 struct fxp_softc *sc = ifp->if_softc; 1526 struct fxp_txsoft *txs; 1527 int i; 1528 1529 /* 1530 * Turn down interface (done early to avoid bad interactions 1531 * between panics, shutdown hooks, and the watchdog timer) 1532 */ 1533 ifp->if_timer = 0; 1534 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1535 1536 /* 1537 * Cancel stats updater. 1538 */ 1539 callout_stop(&sc->sc_callout); 1540 if (sc->sc_flags & FXPF_MII) { 1541 /* Down the MII. */ 1542 mii_down(&sc->sc_mii); 1543 } 1544 1545 /* 1546 * Issue software reset. This unloads any microcode that 1547 * might already be loaded. 1548 */ 1549 sc->sc_flags &= ~FXPF_UCODE_LOADED; 1550 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1551 DELAY(50); 1552 1553 /* 1554 * Release any xmit buffers. 1555 */ 1556 for (i = 0; i < FXP_NTXCB; i++) { 1557 txs = FXP_DSTX(sc, i); 1558 if (txs->txs_mbuf != NULL) { 1559 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1560 m_freem(txs->txs_mbuf); 1561 txs->txs_mbuf = NULL; 1562 } 1563 } 1564 sc->sc_txpending = 0; 1565 1566 if (disable) { 1567 fxp_rxdrain(sc); 1568 fxp_disable(sc); 1569 } 1570 1571} 1572 1573/* 1574 * Watchdog/transmission transmit timeout handler. Called when a 1575 * transmission is started on the interface, but no interrupt is 1576 * received before the timeout. This usually indicates that the 1577 * card has wedged for some reason. 1578 */ 1579void 1580fxp_watchdog(struct ifnet *ifp) 1581{ 1582 struct fxp_softc *sc = ifp->if_softc; 1583 1584 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1585 ifp->if_oerrors++; 1586 1587 (void) fxp_init(ifp); 1588} 1589 1590/* 1591 * Initialize the interface. Must be called at splnet(). 1592 */ 1593int 1594fxp_init(struct ifnet *ifp) 1595{ 1596 struct fxp_softc *sc = ifp->if_softc; 1597 struct fxp_cb_config *cbp; 1598 struct fxp_cb_ias *cb_ias; 1599 struct fxp_txdesc *txd; 1600 bus_dmamap_t rxmap; 1601 int i, prm, save_bf, lrxen, vlan_drop, allm, error = 0; 1602 uint16_t status; 1603 1604 if ((error = fxp_enable(sc)) != 0) 1605 goto out; 1606 1607 /* 1608 * Cancel any pending I/O 1609 */ 1610 fxp_stop(ifp, 0); 1611 1612 /* 1613 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1614 * flag, and this prevents the MII from detaching resulting in 1615 * a panic. The flags field should perhaps be split in runtime 1616 * flags and more static information. For now, just clear the 1617 * only other flag set. 1618 */ 1619 1620 sc->sc_flags &= ~FXPF_WANTINIT; 1621 1622 /* 1623 * Initialize base of CBL and RFA memory. Loading with zero 1624 * sets it up for regular linear addressing. 1625 */ 1626 fxp_scb_wait(sc); 1627 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1628 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1629 1630 fxp_scb_wait(sc); 1631 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1632 1633 /* 1634 * Initialize the multicast filter. Do this now, since we might 1635 * have to setup the config block differently. 1636 */ 1637 fxp_mc_setup(sc); 1638 1639 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1640 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1641 1642 /* 1643 * In order to support receiving 802.1Q VLAN frames, we have to 1644 * enable "save bad frames", since they are 4 bytes larger than 1645 * the normal Ethernet maximum frame length. On i82558 and later, 1646 * we have a better mechanism for this. 1647 */ 1648 save_bf = 0; 1649 lrxen = 0; 1650 vlan_drop = 0; 1651 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1652 if (sc->sc_rev < FXP_REV_82558_A4) 1653 save_bf = 1; 1654 else 1655 lrxen = 1; 1656 if (sc->sc_rev >= FXP_REV_82550) 1657 vlan_drop = 1; 1658 } 1659 1660 /* 1661 * Initialize base of dump-stats buffer. 1662 */ 1663 fxp_scb_wait(sc); 1664 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1665 sc->sc_cddma + FXP_CDSTATSOFF); 1666 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1667 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1668 1669 cbp = &sc->sc_control_data->fcd_configcb; 1670 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1671 1672 /* 1673 * Load microcode for this controller. 1674 */ 1675 fxp_load_ucode(sc); 1676 1677 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK1)) 1678 sc->sc_flags |= FXPF_RECV_WORKAROUND; 1679 else 1680 sc->sc_flags &= ~FXPF_RECV_WORKAROUND; 1681 1682 /* 1683 * This copy is kind of disgusting, but there are a bunch of must be 1684 * zero and must be one bits in this structure and this is the easiest 1685 * way to initialize them all to proper values. 1686 */ 1687 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1688 1689 /* BIG_ENDIAN: no need to swap to store 0 */ 1690 cbp->cb_status = 0; 1691 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1692 FXP_CB_COMMAND_EL); 1693 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1694 cbp->link_addr = 0xffffffff; /* (no) next command */ 1695 /* bytes in config block */ 1696 cbp->byte_count = (sc->sc_flags & FXPF_EXT_RFA) ? 1697 FXP_EXT_CONFIG_LEN : FXP_CONFIG_LEN; 1698 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1699 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1700 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1701 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1702 cbp->type_enable = 0; /* actually reserved */ 1703 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1704 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1705 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1706 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1707 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1708 cbp->late_scb = 0; /* (don't) defer SCB update */ 1709 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1710 cbp->ci_int = 1; /* interrupt on CU idle */ 1711 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1712 cbp->ext_stats_dis = 1; /* disable extended counters */ 1713 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1714 cbp->save_bf = save_bf;/* save bad frames */ 1715 cbp->disc_short_rx = !prm; /* discard short packets */ 1716 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1717 cbp->ext_rfa = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1718 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1719 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1720 /* interface mode */ 1721 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1722 cbp->csma_dis = 0; /* (don't) disable link */ 1723 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1724 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1725 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1726 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1727 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1728 cbp->nsai = 1; /* (don't) disable source addr insert */ 1729 cbp->preamble_length = 2; /* (7 byte) preamble */ 1730 cbp->loopback = 0; /* (don't) loopback */ 1731 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1732 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1733 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1734 cbp->promiscuous = prm; /* promiscuous mode */ 1735 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1736 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1737 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1738 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1739 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1740 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1741 cbp->padding = 1; /* (do) pad short tx packets */ 1742 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1743 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1744 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1745 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1746 /* must set wake_en in PMCSR also */ 1747 cbp->force_fdx = 0; /* (don't) force full duplex */ 1748 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1749 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1750 cbp->mc_all = allm; /* accept all multicasts */ 1751 cbp->ext_rx_mode = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1752 cbp->vlan_drop_en = vlan_drop; 1753 1754 if (!(sc->sc_flags & FXPF_FC)) { 1755 /* 1756 * The i82557 has no hardware flow control, the values 1757 * here are the defaults for the chip. 1758 */ 1759 cbp->fc_delay_lsb = 0; 1760 cbp->fc_delay_msb = 0x40; 1761 cbp->pri_fc_thresh = 3; 1762 cbp->tx_fc_dis = 0; 1763 cbp->rx_fc_restop = 0; 1764 cbp->rx_fc_restart = 0; 1765 cbp->fc_filter = 0; 1766 cbp->pri_fc_loc = 1; 1767 } else { 1768 cbp->fc_delay_lsb = 0x1f; 1769 cbp->fc_delay_msb = 0x01; 1770 cbp->pri_fc_thresh = 3; 1771 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1772 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1773 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1774 cbp->fc_filter = !prm; /* drop FC frames to host */ 1775 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1776 cbp->ext_stats_dis = 0; /* enable extended stats */ 1777 } 1778 1779 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1780 1781 /* 1782 * Start the config command/DMA. 1783 */ 1784 fxp_scb_wait(sc); 1785 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1786 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1787 /* ...and wait for it to complete. */ 1788 for (i = 1000; i > 0; i--) { 1789 FXP_CDCONFIGSYNC(sc, 1790 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1791 status = le16toh(cbp->cb_status); 1792 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD); 1793 if ((status & FXP_CB_STATUS_C) != 0) 1794 break; 1795 DELAY(1); 1796 } 1797 if (i == 0) { 1798 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1799 device_xname(sc->sc_dev), __LINE__); 1800 return (ETIMEDOUT); 1801 } 1802 1803 /* 1804 * Initialize the station address. 1805 */ 1806 cb_ias = &sc->sc_control_data->fcd_iascb; 1807 /* BIG_ENDIAN: no need to swap to store 0 */ 1808 cb_ias->cb_status = 0; 1809 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1810 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1811 cb_ias->link_addr = 0xffffffff; 1812 memcpy(cb_ias->macaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1813 1814 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1815 1816 /* 1817 * Start the IAS (Individual Address Setup) command/DMA. 1818 */ 1819 fxp_scb_wait(sc); 1820 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1821 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1822 /* ...and wait for it to complete. */ 1823 for (i = 1000; i > 0; i++) { 1824 FXP_CDIASSYNC(sc, 1825 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1826 status = le16toh(cb_ias->cb_status); 1827 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD); 1828 if ((status & FXP_CB_STATUS_C) != 0) 1829 break; 1830 DELAY(1); 1831 } 1832 if (i == 0) { 1833 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1834 device_xname(sc->sc_dev), __LINE__); 1835 return (ETIMEDOUT); 1836 } 1837 1838 /* 1839 * Initialize the transmit descriptor ring. txlast is initialized 1840 * to the end of the list so that it will wrap around to the first 1841 * descriptor when the first packet is transmitted. 1842 */ 1843 for (i = 0; i < FXP_NTXCB; i++) { 1844 txd = FXP_CDTX(sc, i); 1845 memset(txd, 0, sizeof(*txd)); 1846 txd->txd_txcb.cb_command = 1847 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1848 txd->txd_txcb.link_addr = 1849 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1850 if (sc->sc_flags & FXPF_EXT_TXCB) 1851 txd->txd_txcb.tbd_array_addr = 1852 htole32(FXP_CDTBDADDR(sc, i) + 1853 (2 * sizeof(struct fxp_tbd))); 1854 else 1855 txd->txd_txcb.tbd_array_addr = 1856 htole32(FXP_CDTBDADDR(sc, i)); 1857 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1858 } 1859 sc->sc_txpending = 0; 1860 sc->sc_txdirty = 0; 1861 sc->sc_txlast = FXP_NTXCB - 1; 1862 1863 /* 1864 * Initialize the receive buffer list. 1865 */ 1866 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1867 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1868 rxmap = FXP_RXMAP_GET(sc); 1869 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1870 log(LOG_ERR, "%s: unable to allocate or map rx " 1871 "buffer %d, error = %d\n", 1872 device_xname(sc->sc_dev), 1873 sc->sc_rxq.ifq_len, error); 1874 /* 1875 * XXX Should attempt to run with fewer receive 1876 * XXX buffers instead of just failing. 1877 */ 1878 FXP_RXMAP_PUT(sc, rxmap); 1879 fxp_rxdrain(sc); 1880 goto out; 1881 } 1882 } 1883 sc->sc_rxidle = 0; 1884 1885 /* 1886 * Give the transmit ring to the chip. We do this by pointing 1887 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1888 * issuing a start command. It will execute the NOP and then 1889 * suspend, pointing at the first descriptor. 1890 */ 1891 fxp_scb_wait(sc); 1892 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1893 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1894 1895 /* 1896 * Initialize receiver buffer area - RFA. 1897 */ 1898#if 0 /* initialization will be done by FXP_SCB_INTRCNTL_REQUEST_SWI later */ 1899 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1900 fxp_scb_wait(sc); 1901 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1902 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1903 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1904#endif 1905 1906 if (sc->sc_flags & FXPF_MII) { 1907 /* 1908 * Set current media. 1909 */ 1910 if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0) 1911 goto out; 1912 } 1913 1914 /* 1915 * ...all done! 1916 */ 1917 ifp->if_flags |= IFF_RUNNING; 1918 ifp->if_flags &= ~IFF_OACTIVE; 1919 1920 /* 1921 * Request a software generated interrupt that will be used to 1922 * (re)start the RU processing. If we direct the chip to start 1923 * receiving from the start of queue now, instead of letting the 1924 * interrupt handler first process all received packets, we run 1925 * the risk of having it overwrite mbuf clusters while they are 1926 * being processed or after they have been returned to the pool. 1927 */ 1928 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTRCNTL_REQUEST_SWI); 1929 1930 /* 1931 * Start the one second timer. 1932 */ 1933 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1934 1935 /* 1936 * Attempt to start output on the interface. 1937 */ 1938 fxp_start(ifp); 1939 1940 out: 1941 if (error) { 1942 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1943 ifp->if_timer = 0; 1944 log(LOG_ERR, "%s: interface not running\n", 1945 device_xname(sc->sc_dev)); 1946 } 1947 return (error); 1948} 1949 1950/* 1951 * Notify the world which media we're using. 1952 */ 1953void 1954fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1955{ 1956 struct fxp_softc *sc = ifp->if_softc; 1957 1958 if (sc->sc_enabled == 0) { 1959 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1960 ifmr->ifm_status = 0; 1961 return; 1962 } 1963 1964 ether_mediastatus(ifp, ifmr); 1965} 1966 1967int 1968fxp_80c24_mediachange(struct ifnet *ifp) 1969{ 1970 1971 /* Nothing to do here. */ 1972 return (0); 1973} 1974 1975void 1976fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1977{ 1978 struct fxp_softc *sc = ifp->if_softc; 1979 1980 /* 1981 * Media is currently-selected media. We cannot determine 1982 * the link status. 1983 */ 1984 ifmr->ifm_status = 0; 1985 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1986} 1987 1988/* 1989 * Add a buffer to the end of the RFA buffer list. 1990 * Return 0 if successful, error code on failure. 1991 * 1992 * The RFA struct is stuck at the beginning of mbuf cluster and the 1993 * data pointer is fixed up to point just past it. 1994 */ 1995int 1996fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 1997{ 1998 struct mbuf *m; 1999 int error; 2000 2001 MGETHDR(m, M_DONTWAIT, MT_DATA); 2002 if (m == NULL) 2003 return (ENOBUFS); 2004 2005 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2006 MCLGET(m, M_DONTWAIT); 2007 if ((m->m_flags & M_EXT) == 0) { 2008 m_freem(m); 2009 return (ENOBUFS); 2010 } 2011 2012 if (unload) 2013 bus_dmamap_unload(sc->sc_dmat, rxmap); 2014 2015 M_SETCTX(m, rxmap); 2016 2017 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2018 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, 2019 BUS_DMA_READ|BUS_DMA_NOWAIT); 2020 if (error) { 2021 /* XXX XXX XXX */ 2022 aprint_error_dev(sc->sc_dev, 2023 "can't load rx DMA map %d, error = %d\n", 2024 sc->sc_rxq.ifq_len, error); 2025 panic("fxp_add_rfabuf"); 2026 } 2027 2028 FXP_INIT_RFABUF(sc, m); 2029 2030 return (0); 2031} 2032 2033int 2034fxp_mdi_read(device_t self, int phy, int reg) 2035{ 2036 struct fxp_softc *sc = device_private(self); 2037 int count = 10000; 2038 int value; 2039 2040 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2041 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2042 2043 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 2044 0x10000000) == 0 && count--) 2045 DELAY(10); 2046 2047 if (count <= 0) 2048 log(LOG_WARNING, 2049 "%s: fxp_mdi_read: timed out\n", device_xname(self)); 2050 2051 return (value & 0xffff); 2052} 2053 2054void 2055fxp_statchg(device_t self) 2056{ 2057 2058 /* Nothing to do. */ 2059} 2060 2061void 2062fxp_mdi_write(device_t self, int phy, int reg, int value) 2063{ 2064 struct fxp_softc *sc = device_private(self); 2065 int count = 10000; 2066 2067 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2068 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2069 (value & 0xffff)); 2070 2071 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2072 count--) 2073 DELAY(10); 2074 2075 if (count <= 0) 2076 log(LOG_WARNING, 2077 "%s: fxp_mdi_write: timed out\n", device_xname(self)); 2078} 2079 2080int 2081fxp_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2082{ 2083 struct fxp_softc *sc = ifp->if_softc; 2084 struct ifreq *ifr = (struct ifreq *)data; 2085 int s, error; 2086 2087 s = splnet(); 2088 2089 switch (cmd) { 2090 case SIOCSIFMEDIA: 2091 case SIOCGIFMEDIA: 2092 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2093 break; 2094 2095 default: 2096 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 2097 break; 2098 2099 error = 0; 2100 2101 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2102 ; 2103 else if (ifp->if_flags & IFF_RUNNING) { 2104 /* 2105 * Multicast list has changed; set the 2106 * hardware filter accordingly. 2107 */ 2108 while (sc->sc_txpending) { 2109 sc->sc_flags |= FXPF_WANTINIT; 2110 tsleep(sc, PSOCK, "fxp_init", 0); 2111 } 2112 error = fxp_init(ifp); 2113 } 2114 break; 2115 } 2116 2117 /* Try to get more packets going. */ 2118 if (sc->sc_enabled) 2119 fxp_start(ifp); 2120 2121 splx(s); 2122 return (error); 2123} 2124 2125/* 2126 * Program the multicast filter. 2127 * 2128 * This function must be called at splnet(). 2129 */ 2130void 2131fxp_mc_setup(struct fxp_softc *sc) 2132{ 2133 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 2134 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2135 struct ethercom *ec = &sc->sc_ethercom; 2136 struct ether_multi *enm; 2137 struct ether_multistep step; 2138 int count, nmcasts; 2139 uint16_t status; 2140 2141#ifdef DIAGNOSTIC 2142 if (sc->sc_txpending) 2143 panic("fxp_mc_setup: pending transmissions"); 2144#endif 2145 2146 ifp->if_flags &= ~IFF_ALLMULTI; 2147 2148 /* 2149 * Initialize multicast setup descriptor. 2150 */ 2151 nmcasts = 0; 2152 ETHER_FIRST_MULTI(step, ec, enm); 2153 while (enm != NULL) { 2154 /* 2155 * Check for too many multicast addresses or if we're 2156 * listening to a range. Either way, we simply have 2157 * to accept all multicasts. 2158 */ 2159 if (nmcasts >= MAXMCADDR || 2160 memcmp(enm->enm_addrlo, enm->enm_addrhi, 2161 ETHER_ADDR_LEN) != 0) { 2162 /* 2163 * Callers of this function must do the 2164 * right thing with this. If we're called 2165 * from outside fxp_init(), the caller must 2166 * detect if the state if IFF_ALLMULTI changes. 2167 * If it does, the caller must then call 2168 * fxp_init(), since allmulti is handled by 2169 * the config block. 2170 */ 2171 ifp->if_flags |= IFF_ALLMULTI; 2172 return; 2173 } 2174 memcpy(&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 2175 ETHER_ADDR_LEN); 2176 nmcasts++; 2177 ETHER_NEXT_MULTI(step, enm); 2178 } 2179 2180 /* BIG_ENDIAN: no need to swap to store 0 */ 2181 mcsp->cb_status = 0; 2182 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2183 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 2184 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2185 2186 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2187 2188 /* 2189 * Wait until the command unit is not active. This should never 2190 * happen since nothing is queued, but make sure anyway. 2191 */ 2192 count = 100; 2193 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2194 FXP_SCB_CUS_ACTIVE && --count) 2195 DELAY(1); 2196 if (count == 0) { 2197 log(LOG_WARNING, "%s: line %d: command queue timeout\n", 2198 device_xname(sc->sc_dev), __LINE__); 2199 return; 2200 } 2201 2202 /* 2203 * Start the multicast setup command/DMA. 2204 */ 2205 fxp_scb_wait(sc); 2206 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2207 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2208 2209 /* ...and wait for it to complete. */ 2210 for (count = 1000; count > 0; count--) { 2211 FXP_CDMCSSYNC(sc, 2212 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2213 status = le16toh(mcsp->cb_status); 2214 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD); 2215 if ((status & FXP_CB_STATUS_C) != 0) 2216 break; 2217 DELAY(1); 2218 } 2219 if (count == 0) { 2220 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 2221 device_xname(sc->sc_dev), __LINE__); 2222 return; 2223 } 2224} 2225 2226static const uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2227static const uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2228static const uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2229static const uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2230static const uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2231static const uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2232 2233#define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2234 2235static const struct ucode { 2236 int32_t revision; 2237 const uint32_t *ucode; 2238 size_t length; 2239 uint16_t int_delay_offset; 2240 uint16_t bundle_max_offset; 2241} ucode_table[] = { 2242 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), 2243 D101_CPUSAVER_DWORD, 0 }, 2244 2245 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), 2246 D101_CPUSAVER_DWORD, 0 }, 2247 2248 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2249 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2250 2251 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2252 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2253 2254 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2255 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2256 2257 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2258 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2259 2260 { 0, NULL, 0, 0, 0 } 2261}; 2262 2263void 2264fxp_load_ucode(struct fxp_softc *sc) 2265{ 2266 const struct ucode *uc; 2267 struct fxp_cb_ucode *cbp = &sc->sc_control_data->fcd_ucode; 2268 int count, i; 2269 uint16_t status; 2270 2271 if (sc->sc_flags & FXPF_UCODE_LOADED) 2272 return; 2273 2274 /* 2275 * Only load the uCode if the user has requested that 2276 * we do so. 2277 */ 2278 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK0) == 0) { 2279 sc->sc_int_delay = 0; 2280 sc->sc_bundle_max = 0; 2281 return; 2282 } 2283 2284 for (uc = ucode_table; uc->ucode != NULL; uc++) { 2285 if (sc->sc_rev == uc->revision) 2286 break; 2287 } 2288 if (uc->ucode == NULL) 2289 return; 2290 2291 /* BIG ENDIAN: no need to swap to store 0 */ 2292 cbp->cb_status = 0; 2293 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2294 cbp->link_addr = 0xffffffff; /* (no) next command */ 2295 for (i = 0; i < uc->length; i++) 2296 cbp->ucode[i] = htole32(uc->ucode[i]); 2297 2298 if (uc->int_delay_offset) 2299 *(volatile uint16_t *) &cbp->ucode[uc->int_delay_offset] = 2300 htole16(fxp_int_delay + (fxp_int_delay / 2)); 2301 2302 if (uc->bundle_max_offset) 2303 *(volatile uint16_t *) &cbp->ucode[uc->bundle_max_offset] = 2304 htole16(fxp_bundle_max); 2305 2306 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2307 2308 /* 2309 * Download the uCode to the chip. 2310 */ 2311 fxp_scb_wait(sc); 2312 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDUCODEOFF); 2313 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2314 2315 /* ...and wait for it to complete. */ 2316 for (count = 10000; count > 0; count--) { 2317 FXP_CDUCODESYNC(sc, 2318 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2319 status = le16toh(cbp->cb_status); 2320 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD); 2321 if ((status & FXP_CB_STATUS_C) != 0) 2322 break; 2323 DELAY(2); 2324 } 2325 if (count == 0) { 2326 sc->sc_int_delay = 0; 2327 sc->sc_bundle_max = 0; 2328 log(LOG_WARNING, "%s: timeout loading microcode\n", 2329 device_xname(sc->sc_dev)); 2330 return; 2331 } 2332 2333 if (sc->sc_int_delay != fxp_int_delay || 2334 sc->sc_bundle_max != fxp_bundle_max) { 2335 sc->sc_int_delay = fxp_int_delay; 2336 sc->sc_bundle_max = fxp_bundle_max; 2337 log(LOG_INFO, "%s: Microcode loaded: int delay: %d usec, " 2338 "max bundle: %d\n", device_xname(sc->sc_dev), 2339 sc->sc_int_delay, 2340 uc->bundle_max_offset == 0 ? 0 : sc->sc_bundle_max); 2341 } 2342 2343 sc->sc_flags |= FXPF_UCODE_LOADED; 2344} 2345 2346int 2347fxp_enable(struct fxp_softc *sc) 2348{ 2349 2350 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2351 if ((*sc->sc_enable)(sc) != 0) { 2352 log(LOG_ERR, "%s: device enable failed\n", 2353 device_xname(sc->sc_dev)); 2354 return (EIO); 2355 } 2356 } 2357 2358 sc->sc_enabled = 1; 2359 return (0); 2360} 2361 2362void 2363fxp_disable(struct fxp_softc *sc) 2364{ 2365 2366 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2367 (*sc->sc_disable)(sc); 2368 sc->sc_enabled = 0; 2369 } 2370} 2371 2372/* 2373 * fxp_activate: 2374 * 2375 * Handle device activation/deactivation requests. 2376 */ 2377int 2378fxp_activate(device_t self, enum devact act) 2379{ 2380 struct fxp_softc *sc = device_private(self); 2381 int s, error = 0; 2382 2383 s = splnet(); 2384 switch (act) { 2385 case DVACT_ACTIVATE: 2386 error = EOPNOTSUPP; 2387 break; 2388 2389 case DVACT_DEACTIVATE: 2390 if (sc->sc_flags & FXPF_MII) 2391 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 2392 MII_OFFSET_ANY); 2393 if_deactivate(&sc->sc_ethercom.ec_if); 2394 break; 2395 } 2396 splx(s); 2397 2398 return (error); 2399} 2400 2401/* 2402 * fxp_detach: 2403 * 2404 * Detach an i82557 interface. 2405 */ 2406int 2407fxp_detach(struct fxp_softc *sc) 2408{ 2409 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2410 int i; 2411 2412 /* Succeed now if there's no work to do. */ 2413 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2414 return (0); 2415 2416 /* Unhook our tick handler. */ 2417 callout_stop(&sc->sc_callout); 2418 2419 if (sc->sc_flags & FXPF_MII) { 2420 /* Detach all PHYs */ 2421 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2422 } 2423 2424 /* Delete all remaining media. */ 2425 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2426 2427#if NRND > 0 2428 rnd_detach_source(&sc->rnd_source); 2429#endif 2430 ether_ifdetach(ifp); 2431 if_detach(ifp); 2432 2433 for (i = 0; i < FXP_NRFABUFS; i++) { 2434 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2435 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2436 } 2437 2438 for (i = 0; i < FXP_NTXCB; i++) { 2439 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2440 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2441 } 2442 2443 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2444 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2445 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 2446 sizeof(struct fxp_control_data)); 2447 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2448 2449 return (0); 2450} 2451