i82557.c revision 1.118
1/* $NetBSD: i82557.c,v 1.118 2008/12/04 15:22:01 tsutsui Exp $ */ 2 3/*- 4 * Copyright (c) 1997, 1998, 1999, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Copyright (c) 1995, David Greenman 35 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice unmodified, this list of conditions, and the following 43 * disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 61 */ 62 63/* 64 * Device driver for the Intel i82557 fast Ethernet controller, 65 * and its successors, the i82558 and i82559. 66 */ 67 68#include <sys/cdefs.h> 69__KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.118 2008/12/04 15:22:01 tsutsui Exp $"); 70 71#include "bpfilter.h" 72#include "rnd.h" 73 74#include <sys/param.h> 75#include <sys/systm.h> 76#include <sys/callout.h> 77#include <sys/mbuf.h> 78#include <sys/malloc.h> 79#include <sys/kernel.h> 80#include <sys/socket.h> 81#include <sys/ioctl.h> 82#include <sys/errno.h> 83#include <sys/device.h> 84#include <sys/syslog.h> 85 86#include <machine/endian.h> 87 88#include <uvm/uvm_extern.h> 89 90#if NRND > 0 91#include <sys/rnd.h> 92#endif 93 94#include <net/if.h> 95#include <net/if_dl.h> 96#include <net/if_media.h> 97#include <net/if_ether.h> 98 99#if NBPFILTER > 0 100#include <net/bpf.h> 101#endif 102 103#include <sys/bus.h> 104#include <sys/intr.h> 105 106#include <dev/mii/miivar.h> 107 108#include <dev/ic/i82557reg.h> 109#include <dev/ic/i82557var.h> 110 111#include <dev/microcode/i8255x/rcvbundl.h> 112 113/* 114 * NOTE! On the Alpha, we have an alignment constraint. The 115 * card DMAs the packet immediately following the RFA. However, 116 * the first thing in the packet is a 14-byte Ethernet header. 117 * This means that the packet is misaligned. To compensate, 118 * we actually offset the RFA 2 bytes into the cluster. This 119 * alignes the packet after the Ethernet header at a 32-bit 120 * boundary. HOWEVER! This means that the RFA is misaligned! 121 */ 122#define RFA_ALIGNMENT_FUDGE 2 123 124/* 125 * The configuration byte map has several undefined fields which 126 * must be one or must be zero. Set up a template for these bits 127 * only (assuming an i82557 chip), leaving the actual configuration 128 * for fxp_init(). 129 * 130 * See the definition of struct fxp_cb_config for the bit definitions. 131 */ 132const u_int8_t fxp_cb_config_template[] = { 133 0x0, 0x0, /* cb_status */ 134 0x0, 0x0, /* cb_command */ 135 0x0, 0x0, 0x0, 0x0, /* link_addr */ 136 0x0, /* 0 */ 137 0x0, /* 1 */ 138 0x0, /* 2 */ 139 0x0, /* 3 */ 140 0x0, /* 4 */ 141 0x0, /* 5 */ 142 0x32, /* 6 */ 143 0x0, /* 7 */ 144 0x0, /* 8 */ 145 0x0, /* 9 */ 146 0x6, /* 10 */ 147 0x0, /* 11 */ 148 0x0, /* 12 */ 149 0x0, /* 13 */ 150 0xf2, /* 14 */ 151 0x48, /* 15 */ 152 0x0, /* 16 */ 153 0x40, /* 17 */ 154 0xf0, /* 18 */ 155 0x0, /* 19 */ 156 0x3f, /* 20 */ 157 0x5, /* 21 */ 158 0x0, /* 22 */ 159 0x0, /* 23 */ 160 0x0, /* 24 */ 161 0x0, /* 25 */ 162 0x0, /* 26 */ 163 0x0, /* 27 */ 164 0x0, /* 28 */ 165 0x0, /* 29 */ 166 0x0, /* 30 */ 167 0x0, /* 31 */ 168}; 169 170void fxp_mii_initmedia(struct fxp_softc *); 171void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 172 173void fxp_80c24_initmedia(struct fxp_softc *); 174int fxp_80c24_mediachange(struct ifnet *); 175void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 176 177void fxp_start(struct ifnet *); 178int fxp_ioctl(struct ifnet *, u_long, void *); 179void fxp_watchdog(struct ifnet *); 180int fxp_init(struct ifnet *); 181void fxp_stop(struct ifnet *, int); 182 183void fxp_txintr(struct fxp_softc *); 184int fxp_rxintr(struct fxp_softc *); 185 186int fxp_rx_hwcksum(struct mbuf *, const struct fxp_rfa *); 187 188void fxp_rxdrain(struct fxp_softc *); 189int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 190int fxp_mdi_read(device_t, int, int); 191void fxp_statchg(device_t); 192void fxp_mdi_write(device_t, int, int, int); 193void fxp_autosize_eeprom(struct fxp_softc*); 194void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 195void fxp_write_eeprom(struct fxp_softc *, u_int16_t *, int, int); 196void fxp_eeprom_update_cksum(struct fxp_softc *); 197void fxp_get_info(struct fxp_softc *, u_int8_t *); 198void fxp_tick(void *); 199void fxp_mc_setup(struct fxp_softc *); 200void fxp_load_ucode(struct fxp_softc *); 201 202int fxp_copy_small = 0; 203 204/* 205 * Variables for interrupt mitigating microcode. 206 */ 207int fxp_int_delay = 1000; /* usec */ 208int fxp_bundle_max = 6; /* packets */ 209 210struct fxp_phytype { 211 int fp_phy; /* type of PHY, -1 for MII at the end. */ 212 void (*fp_init)(struct fxp_softc *); 213} fxp_phytype_table[] = { 214 { FXP_PHY_80C24, fxp_80c24_initmedia }, 215 { -1, fxp_mii_initmedia }, 216}; 217 218/* 219 * Set initial transmit threshold at 64 (512 bytes). This is 220 * increased by 64 (512 bytes) at a time, to maximum of 192 221 * (1536 bytes), if an underrun occurs. 222 */ 223static int tx_threshold = 64; 224 225/* 226 * Wait for the previous command to be accepted (but not necessarily 227 * completed). 228 */ 229static inline void 230fxp_scb_wait(struct fxp_softc *sc) 231{ 232 int i = 10000; 233 234 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 235 delay(2); 236 if (i == 0) 237 log(LOG_WARNING, 238 "%s: WARNING: SCB timed out!\n", device_xname(sc->sc_dev)); 239} 240 241/* 242 * Submit a command to the i82557. 243 */ 244static inline void 245fxp_scb_cmd(struct fxp_softc *sc, u_int8_t cmd) 246{ 247 248 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 249} 250 251/* 252 * Finish attaching an i82557 interface. Called by bus-specific front-end. 253 */ 254void 255fxp_attach(struct fxp_softc *sc) 256{ 257 u_int8_t enaddr[ETHER_ADDR_LEN]; 258 struct ifnet *ifp; 259 bus_dma_segment_t seg; 260 int rseg, i, error; 261 struct fxp_phytype *fp; 262 263 callout_init(&sc->sc_callout, 0); 264 265 /* 266 * Enable some good stuff on i82558 and later. 267 */ 268 if (sc->sc_rev >= FXP_REV_82558_A4) { 269 /* Enable the extended TxCB. */ 270 sc->sc_flags |= FXPF_EXT_TXCB; 271 } 272 273 /* 274 * Enable use of extended RFDs and TCBs for 82550 275 * and later chips. Note: we need extended TXCB support 276 * too, but that's already enabled by the code above. 277 * Be careful to do this only on the right devices. 278 */ 279 if (sc->sc_rev == FXP_REV_82550 || sc->sc_rev == FXP_REV_82550_C) { 280 sc->sc_flags |= FXPF_EXT_RFA | FXPF_IPCB; 281 sc->sc_txcmd = htole16(FXP_CB_COMMAND_IPCBXMIT); 282 } else { 283 sc->sc_txcmd = htole16(FXP_CB_COMMAND_XMIT); 284 } 285 286 sc->sc_rfa_size = 287 (sc->sc_flags & FXPF_EXT_RFA) ? RFA_EXT_SIZE : RFA_SIZE; 288 289 /* 290 * Allocate the control data structures, and create and load the 291 * DMA map for it. 292 */ 293 if ((error = bus_dmamem_alloc(sc->sc_dmat, 294 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 295 0)) != 0) { 296 aprint_error_dev(sc->sc_dev, 297 "unable to allocate control data, error = %d\n", 298 error); 299 goto fail_0; 300 } 301 302 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 303 sizeof(struct fxp_control_data), (void **)&sc->sc_control_data, 304 BUS_DMA_COHERENT)) != 0) { 305 aprint_error_dev(sc->sc_dev, "unable to map control data, error = %d\n", 306 error); 307 goto fail_1; 308 } 309 sc->sc_cdseg = seg; 310 sc->sc_cdnseg = rseg; 311 312 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 313 314 if ((error = bus_dmamap_create(sc->sc_dmat, 315 sizeof(struct fxp_control_data), 1, 316 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 317 aprint_error_dev(sc->sc_dev, "unable to create control data DMA map, " 318 "error = %d\n", error); 319 goto fail_2; 320 } 321 322 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 323 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 324 0)) != 0) { 325 aprint_error_dev(sc->sc_dev, 326 "can't load control data DMA map, error = %d\n", 327 error); 328 goto fail_3; 329 } 330 331 /* 332 * Create the transmit buffer DMA maps. 333 */ 334 for (i = 0; i < FXP_NTXCB; i++) { 335 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 336 (sc->sc_flags & FXPF_IPCB) ? FXP_IPCB_NTXSEG : FXP_NTXSEG, 337 MCLBYTES, 0, 0, &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 338 aprint_error_dev(sc->sc_dev, "unable to create tx DMA map %d, " 339 "error = %d\n", i, error); 340 goto fail_4; 341 } 342 } 343 344 /* 345 * Create the receive buffer DMA maps. 346 */ 347 for (i = 0; i < FXP_NRFABUFS; i++) { 348 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 349 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 350 aprint_error_dev(sc->sc_dev, "unable to create rx DMA map %d, " 351 "error = %d\n", i, error); 352 goto fail_5; 353 } 354 } 355 356 /* Initialize MAC address and media structures. */ 357 fxp_get_info(sc, enaddr); 358 359 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 360 ether_sprintf(enaddr)); 361 362 ifp = &sc->sc_ethercom.ec_if; 363 364 /* 365 * Get info about our media interface, and initialize it. Note 366 * the table terminates itself with a phy of -1, indicating 367 * that we're using MII. 368 */ 369 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 370 if (fp->fp_phy == sc->phy_primary_device) 371 break; 372 (*fp->fp_init)(sc); 373 374 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 375 ifp->if_softc = sc; 376 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 377 ifp->if_ioctl = fxp_ioctl; 378 ifp->if_start = fxp_start; 379 ifp->if_watchdog = fxp_watchdog; 380 ifp->if_init = fxp_init; 381 ifp->if_stop = fxp_stop; 382 IFQ_SET_READY(&ifp->if_snd); 383 384 if (sc->sc_flags & FXPF_IPCB) { 385 KASSERT(sc->sc_flags & FXPF_EXT_RFA); /* we have both or none */ 386 /* 387 * IFCAP_CSUM_IPv4_Tx seems to have a problem, 388 * at least, on i82550 rev.12. 389 * specifically, it doesn't set ipv4 checksum properly 390 * when sending UDP (and probably TCP) packets with 391 * 20 byte ipv4 header + 1 or 2 byte data, 392 * though ICMP packets seem working. 393 * FreeBSD driver has related comments. 394 * We've added a workaround to handle the bug by padding 395 * such packets manually. 396 */ 397 ifp->if_capabilities = 398 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 399 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 400 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 401 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 402 } 403 404 /* 405 * We can support 802.1Q VLAN-sized frames. 406 */ 407 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 408 409 /* 410 * Attach the interface. 411 */ 412 if_attach(ifp); 413 ether_ifattach(ifp, enaddr); 414#if NRND > 0 415 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 416 RND_TYPE_NET, 0); 417#endif 418 419#ifdef FXP_EVENT_COUNTERS 420 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 421 NULL, device_xname(sc->sc_dev), "txstall"); 422 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 423 NULL, device_xname(sc->sc_dev), "txintr"); 424 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 425 NULL, device_xname(sc->sc_dev), "rxintr"); 426 if (sc->sc_rev >= FXP_REV_82558_A4) { 427 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 428 NULL, device_xname(sc->sc_dev), "txpause"); 429 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 430 NULL, device_xname(sc->sc_dev), "rxpause"); 431 } 432#endif /* FXP_EVENT_COUNTERS */ 433 434 /* The attach is successful. */ 435 sc->sc_flags |= FXPF_ATTACHED; 436 437 return; 438 439 /* 440 * Free any resources we've allocated during the failed attach 441 * attempt. Do this in reverse order and fall though. 442 */ 443 fail_5: 444 for (i = 0; i < FXP_NRFABUFS; i++) { 445 if (sc->sc_rxmaps[i] != NULL) 446 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 447 } 448 fail_4: 449 for (i = 0; i < FXP_NTXCB; i++) { 450 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 451 bus_dmamap_destroy(sc->sc_dmat, 452 FXP_DSTX(sc, i)->txs_dmamap); 453 } 454 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 455 fail_3: 456 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 457 fail_2: 458 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 459 sizeof(struct fxp_control_data)); 460 fail_1: 461 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 462 fail_0: 463 return; 464} 465 466void 467fxp_mii_initmedia(struct fxp_softc *sc) 468{ 469 int flags; 470 471 sc->sc_flags |= FXPF_MII; 472 473 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 474 sc->sc_mii.mii_readreg = fxp_mdi_read; 475 sc->sc_mii.mii_writereg = fxp_mdi_write; 476 sc->sc_mii.mii_statchg = fxp_statchg; 477 478 sc->sc_ethercom.ec_mii = &sc->sc_mii; 479 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 480 fxp_mii_mediastatus); 481 482 flags = MIIF_NOISOLATE; 483 if (sc->sc_rev >= FXP_REV_82558_A4) 484 flags |= MIIF_DOPAUSE; 485 /* 486 * The i82557 wedges if all of its PHYs are isolated! 487 */ 488 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 489 MII_OFFSET_ANY, flags); 490 if (LIST_EMPTY(&sc->sc_mii.mii_phys)) { 491 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 492 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 493 } else 494 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 495} 496 497void 498fxp_80c24_initmedia(struct fxp_softc *sc) 499{ 500 501 /* 502 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 503 * doesn't have a programming interface of any sort. The 504 * media is sensed automatically based on how the link partner 505 * is configured. This is, in essence, manual configuration. 506 */ 507 aprint_normal_dev(sc->sc_dev, "Seeq 80c24 AutoDUPLEX media interface present\n"); 508 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 509 fxp_80c24_mediastatus); 510 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 511 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 512} 513 514/* 515 * Initialize the interface media. 516 */ 517void 518fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 519{ 520 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 521 522 /* 523 * Reset to a stable state. 524 */ 525 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 526 DELAY(100); 527 528 sc->sc_eeprom_size = 0; 529 fxp_autosize_eeprom(sc); 530 if (sc->sc_eeprom_size == 0) { 531 aprint_error_dev(sc->sc_dev, "failed to detect EEPROM size\n"); 532 sc->sc_eeprom_size = 6; /* XXX panic here? */ 533 } 534#ifdef DEBUG 535 aprint_debug_dev(sc->sc_dev, "detected %d word EEPROM\n", 536 1 << sc->sc_eeprom_size); 537#endif 538 539 /* 540 * Get info about the primary PHY 541 */ 542 fxp_read_eeprom(sc, &data, 6, 1); 543 sc->phy_primary_device = 544 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 545 546 /* 547 * Read MAC address. 548 */ 549 fxp_read_eeprom(sc, myea, 0, 3); 550 enaddr[0] = myea[0] & 0xff; 551 enaddr[1] = myea[0] >> 8; 552 enaddr[2] = myea[1] & 0xff; 553 enaddr[3] = myea[1] >> 8; 554 enaddr[4] = myea[2] & 0xff; 555 enaddr[5] = myea[2] >> 8; 556 557 /* 558 * Systems based on the ICH2/ICH2-M chip from Intel, as well 559 * as some i82559 designs, have a defect where the chip can 560 * cause a PCI protocol violation if it receives a CU_RESUME 561 * command when it is entering the IDLE state. 562 * 563 * The work-around is to disable Dynamic Standby Mode, so that 564 * the chip never deasserts #CLKRUN, and always remains in the 565 * active state. 566 * 567 * Unfortunately, the only way to disable Dynamic Standby is 568 * to frob an EEPROM setting and reboot (the EEPROM setting 569 * is only consulted when the PCI bus comes out of reset). 570 * 571 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 572 */ 573 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 574 fxp_read_eeprom(sc, &data, 10, 1); 575 if (data & 0x02) { /* STB enable */ 576 aprint_error_dev(sc->sc_dev, "WARNING: " 577 "Disabling dynamic standby mode in EEPROM " 578 "to work around a\n"); 579 aprint_normal_dev(sc->sc_dev, 580 "WARNING: hardware bug. You must reset " 581 "the system before using this\n"); 582 aprint_normal_dev(sc->sc_dev, "WARNING: interface.\n"); 583 data &= ~0x02; 584 fxp_write_eeprom(sc, &data, 10, 1); 585 aprint_normal_dev(sc->sc_dev, "new EEPROM ID: 0x%04x\n", 586 data); 587 fxp_eeprom_update_cksum(sc); 588 } 589 } 590 591 /* Receiver lock-up workaround detection. (FXPF_RECV_WORKAROUND) */ 592 /* Due to false positives we make it conditional on setting link1 */ 593 fxp_read_eeprom(sc, &data, 3, 1); 594 if ((data & 0x03) != 0x03) { 595 aprint_verbose_dev(sc->sc_dev, "May need receiver lock-up workaround\n"); 596 } 597} 598 599static void 600fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 601{ 602 uint16_t reg; 603 int x; 604 605 for (x = 1 << (len - 1); x != 0; x >>= 1) { 606 DELAY(40); 607 if (data & x) 608 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 609 else 610 reg = FXP_EEPROM_EECS; 611 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 612 DELAY(40); 613 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 614 reg | FXP_EEPROM_EESK); 615 DELAY(40); 616 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 617 } 618 DELAY(40); 619} 620 621/* 622 * Figure out EEPROM size. 623 * 624 * 559's can have either 64-word or 256-word EEPROMs, the 558 625 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 626 * talks about the existence of 16 to 256 word EEPROMs. 627 * 628 * The only known sizes are 64 and 256, where the 256 version is used 629 * by CardBus cards to store CIS information. 630 * 631 * The address is shifted in msb-to-lsb, and after the last 632 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 633 * after which follows the actual data. We try to detect this zero, by 634 * probing the data-out bit in the EEPROM control register just after 635 * having shifted in a bit. If the bit is zero, we assume we've 636 * shifted enough address bits. The data-out should be tri-state, 637 * before this, which should translate to a logical one. 638 * 639 * Other ways to do this would be to try to read a register with known 640 * contents with a varying number of address bits, but no such 641 * register seem to be available. The high bits of register 10 are 01 642 * on the 558 and 559, but apparently not on the 557. 643 * 644 * The Linux driver computes a checksum on the EEPROM data, but the 645 * value of this checksum is not very well documented. 646 */ 647 648void 649fxp_autosize_eeprom(struct fxp_softc *sc) 650{ 651 int x; 652 653 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 654 DELAY(40); 655 656 /* Shift in read opcode. */ 657 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 658 659 /* 660 * Shift in address, wait for the dummy zero following a correct 661 * address shift. 662 */ 663 for (x = 1; x <= 8; x++) { 664 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 665 DELAY(40); 666 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 667 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 668 DELAY(40); 669 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 670 FXP_EEPROM_EEDO) == 0) 671 break; 672 DELAY(40); 673 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 674 DELAY(40); 675 } 676 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 677 DELAY(40); 678 if (x != 6 && x != 8) { 679#ifdef DEBUG 680 printf("%s: strange EEPROM size (%d)\n", 681 device_xname(sc->sc_dev), 1 << x); 682#endif 683 } else 684 sc->sc_eeprom_size = x; 685} 686 687/* 688 * Read from the serial EEPROM. Basically, you manually shift in 689 * the read opcode (one bit at a time) and then shift in the address, 690 * and then you shift out the data (all of this one bit at a time). 691 * The word size is 16 bits, so you have to provide the address for 692 * every 16 bits of data. 693 */ 694void 695fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 696{ 697 u_int16_t reg; 698 int i, x; 699 700 for (i = 0; i < words; i++) { 701 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 702 703 /* Shift in read opcode. */ 704 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 705 706 /* Shift in address. */ 707 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 708 709 reg = FXP_EEPROM_EECS; 710 data[i] = 0; 711 712 /* Shift out data. */ 713 for (x = 16; x > 0; x--) { 714 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 715 reg | FXP_EEPROM_EESK); 716 DELAY(40); 717 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 718 FXP_EEPROM_EEDO) 719 data[i] |= (1 << (x - 1)); 720 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 721 DELAY(40); 722 } 723 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 724 DELAY(40); 725 } 726} 727 728/* 729 * Write data to the serial EEPROM. 730 */ 731void 732fxp_write_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 733{ 734 int i, j; 735 736 for (i = 0; i < words; i++) { 737 /* Erase/write enable. */ 738 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 739 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 740 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 741 sc->sc_eeprom_size); 742 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 743 DELAY(4); 744 745 /* Shift in write opcode, address, data. */ 746 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 747 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 748 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 749 fxp_eeprom_shiftin(sc, data[i], 16); 750 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 751 DELAY(4); 752 753 /* Wait for the EEPROM to finish up. */ 754 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 755 DELAY(4); 756 for (j = 0; j < 1000; j++) { 757 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 758 FXP_EEPROM_EEDO) 759 break; 760 DELAY(50); 761 } 762 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 763 DELAY(4); 764 765 /* Erase/write disable. */ 766 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 767 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 768 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 769 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 770 DELAY(4); 771 } 772} 773 774/* 775 * Update the checksum of the EEPROM. 776 */ 777void 778fxp_eeprom_update_cksum(struct fxp_softc *sc) 779{ 780 int i; 781 uint16_t data, cksum; 782 783 cksum = 0; 784 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 785 fxp_read_eeprom(sc, &data, i, 1); 786 cksum += data; 787 } 788 i = (1 << sc->sc_eeprom_size) - 1; 789 cksum = 0xbaba - cksum; 790 fxp_read_eeprom(sc, &data, i, 1); 791 fxp_write_eeprom(sc, &cksum, i, 1); 792 log(LOG_INFO, "%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 793 device_xname(sc->sc_dev), i, data, cksum); 794} 795 796/* 797 * Start packet transmission on the interface. 798 */ 799void 800fxp_start(struct ifnet *ifp) 801{ 802 struct fxp_softc *sc = ifp->if_softc; 803 struct mbuf *m0, *m; 804 struct fxp_txdesc *txd; 805 struct fxp_txsoft *txs; 806 bus_dmamap_t dmamap; 807 int error, lasttx, nexttx, opending, seg, nsegs, len; 808 809 /* 810 * If we want a re-init, bail out now. 811 */ 812 if (sc->sc_flags & FXPF_WANTINIT) { 813 ifp->if_flags |= IFF_OACTIVE; 814 return; 815 } 816 817 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 818 return; 819 820 /* 821 * Remember the previous txpending and the current lasttx. 822 */ 823 opending = sc->sc_txpending; 824 lasttx = sc->sc_txlast; 825 826 /* 827 * Loop through the send queue, setting up transmit descriptors 828 * until we drain the queue, or use up all available transmit 829 * descriptors. 830 */ 831 for (;;) { 832 struct fxp_tbd *tbdp; 833 int csum_flags; 834 835 /* 836 * Grab a packet off the queue. 837 */ 838 IFQ_POLL(&ifp->if_snd, m0); 839 if (m0 == NULL) 840 break; 841 m = NULL; 842 843 if (sc->sc_txpending == FXP_NTXCB - 1) { 844 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 845 break; 846 } 847 848 /* 849 * Get the next available transmit descriptor. 850 */ 851 nexttx = FXP_NEXTTX(sc->sc_txlast); 852 txd = FXP_CDTX(sc, nexttx); 853 txs = FXP_DSTX(sc, nexttx); 854 dmamap = txs->txs_dmamap; 855 856 /* 857 * Load the DMA map. If this fails, the packet either 858 * didn't fit in the allotted number of frags, or we were 859 * short on resources. In this case, we'll copy and try 860 * again. 861 */ 862 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 863 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 864 MGETHDR(m, M_DONTWAIT, MT_DATA); 865 if (m == NULL) { 866 log(LOG_ERR, "%s: unable to allocate Tx mbuf\n", 867 device_xname(sc->sc_dev)); 868 break; 869 } 870 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 871 if (m0->m_pkthdr.len > MHLEN) { 872 MCLGET(m, M_DONTWAIT); 873 if ((m->m_flags & M_EXT) == 0) { 874 log(LOG_ERR, 875 "%s: unable to allocate Tx " 876 "cluster\n", device_xname(sc->sc_dev)); 877 m_freem(m); 878 break; 879 } 880 } 881 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 882 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 883 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 884 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 885 if (error) { 886 log(LOG_ERR, "%s: unable to load Tx buffer, " 887 "error = %d\n", device_xname(sc->sc_dev), error); 888 break; 889 } 890 } 891 892 IFQ_DEQUEUE(&ifp->if_snd, m0); 893 csum_flags = m0->m_pkthdr.csum_flags; 894 if (m != NULL) { 895 m_freem(m0); 896 m0 = m; 897 } 898 899 /* Initialize the fraglist. */ 900 tbdp = txd->txd_tbd; 901 len = m0->m_pkthdr.len; 902 nsegs = dmamap->dm_nsegs; 903 if (sc->sc_flags & FXPF_IPCB) 904 tbdp++; 905 for (seg = 0; seg < nsegs; seg++) { 906 tbdp[seg].tb_addr = 907 htole32(dmamap->dm_segs[seg].ds_addr); 908 tbdp[seg].tb_size = 909 htole32(dmamap->dm_segs[seg].ds_len); 910 } 911 if (__predict_false(len <= FXP_IP4CSUMTX_PADLEN && 912 (csum_flags & M_CSUM_IPv4) != 0)) { 913 /* 914 * Pad short packets to avoid ip4csum-tx bug. 915 * 916 * XXX Should we still consider if such short 917 * (36 bytes or less) packets might already 918 * occupy FXP_IPCB_NTXSEG (15) fragments here? 919 */ 920 KASSERT(nsegs < FXP_IPCB_NTXSEG); 921 nsegs++; 922 tbdp[seg].tb_addr = htole32(FXP_CDTXPADADDR(sc)); 923 tbdp[seg].tb_size = FXP_IP4CSUMTX_PADLEN + 1 - len; 924 } 925 926 /* Sync the DMA map. */ 927 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 928 BUS_DMASYNC_PREWRITE); 929 930 /* 931 * Store a pointer to the packet so we can free it later. 932 */ 933 txs->txs_mbuf = m0; 934 935 /* 936 * Initialize the transmit descriptor. 937 */ 938 /* BIG_ENDIAN: no need to swap to store 0 */ 939 txd->txd_txcb.cb_status = 0; 940 txd->txd_txcb.cb_command = 941 sc->sc_txcmd | htole16(FXP_CB_COMMAND_SF); 942 txd->txd_txcb.tx_threshold = tx_threshold; 943 txd->txd_txcb.tbd_number = nsegs; 944 945 KASSERT((csum_flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) == 0); 946 if (sc->sc_flags & FXPF_IPCB) { 947 struct m_tag *vtag; 948 struct fxp_ipcb *ipcb; 949 /* 950 * Deal with TCP/IP checksum offload. Note that 951 * in order for TCP checksum offload to work, 952 * the pseudo header checksum must have already 953 * been computed and stored in the checksum field 954 * in the TCP header. The stack should have 955 * already done this for us. 956 */ 957 ipcb = &txd->txd_u.txdu_ipcb; 958 memset(ipcb, 0, sizeof(*ipcb)); 959 /* 960 * always do hardware parsing. 961 */ 962 ipcb->ipcb_ip_activation_high = 963 FXP_IPCB_HARDWAREPARSING_ENABLE; 964 /* 965 * ip checksum offloading. 966 */ 967 if (csum_flags & M_CSUM_IPv4) { 968 ipcb->ipcb_ip_schedule |= 969 FXP_IPCB_IP_CHECKSUM_ENABLE; 970 } 971 /* 972 * TCP/UDP checksum offloading. 973 */ 974 if (csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 975 ipcb->ipcb_ip_schedule |= 976 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 977 } 978 979 /* 980 * request VLAN tag insertion if needed. 981 */ 982 vtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0); 983 if (vtag) { 984 ipcb->ipcb_vlan_id = 985 htobe16(*(u_int *)(vtag + 1)); 986 ipcb->ipcb_ip_activation_high |= 987 FXP_IPCB_INSERTVLAN_ENABLE; 988 } 989 } else { 990 KASSERT((csum_flags & 991 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) == 0); 992 } 993 994 FXP_CDTXSYNC(sc, nexttx, 995 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 996 997 /* Advance the tx pointer. */ 998 sc->sc_txpending++; 999 sc->sc_txlast = nexttx; 1000 1001#if NBPFILTER > 0 1002 /* 1003 * Pass packet to bpf if there is a listener. 1004 */ 1005 if (ifp->if_bpf) 1006 bpf_mtap(ifp->if_bpf, m0); 1007#endif 1008 } 1009 1010 if (sc->sc_txpending == FXP_NTXCB - 1) { 1011 /* No more slots; notify upper layer. */ 1012 ifp->if_flags |= IFF_OACTIVE; 1013 } 1014 1015 if (sc->sc_txpending != opending) { 1016 /* 1017 * We enqueued packets. If the transmitter was idle, 1018 * reset the txdirty pointer. 1019 */ 1020 if (opending == 0) 1021 sc->sc_txdirty = FXP_NEXTTX(lasttx); 1022 1023 /* 1024 * Cause the chip to interrupt and suspend command 1025 * processing once the last packet we've enqueued 1026 * has been transmitted. 1027 * 1028 * To avoid a race between updating status bits 1029 * by the fxp chip and clearing command bits 1030 * by this function on machines which don't have 1031 * atomic methods to clear/set bits in memory 1032 * smaller than 32bits (both cb_status and cb_command 1033 * members are uint16_t and in the same 32bit word), 1034 * we have to prepare a dummy TX descriptor which has 1035 * NOP command and just causes a TX completion interrupt. 1036 */ 1037 sc->sc_txpending++; 1038 sc->sc_txlast = FXP_NEXTTX(sc->sc_txlast); 1039 txd = FXP_CDTX(sc, sc->sc_txlast); 1040 /* BIG_ENDIAN: no need to swap to store 0 */ 1041 txd->txd_txcb.cb_status = 0; 1042 txd->txd_txcb.cb_command = htole16(FXP_CB_COMMAND_NOP | 1043 FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 1044 FXP_CDTXSYNC(sc, sc->sc_txlast, 1045 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1046 1047 /* 1048 * The entire packet chain is set up. Clear the suspend bit 1049 * on the command prior to the first packet we set up. 1050 */ 1051 FXP_CDTXSYNC(sc, lasttx, 1052 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1053 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 1054 htole16(~FXP_CB_COMMAND_S); 1055 FXP_CDTXSYNC(sc, lasttx, 1056 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1057 1058 /* 1059 * Issue a Resume command in case the chip was suspended. 1060 */ 1061 fxp_scb_wait(sc); 1062 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1063 1064 /* Set a watchdog timer in case the chip flakes out. */ 1065 ifp->if_timer = 5; 1066 } 1067} 1068 1069/* 1070 * Process interface interrupts. 1071 */ 1072int 1073fxp_intr(void *arg) 1074{ 1075 struct fxp_softc *sc = arg; 1076 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1077 bus_dmamap_t rxmap; 1078 int claimed = 0, rnr; 1079 u_int8_t statack; 1080 1081 if (!device_is_active(sc->sc_dev) || sc->sc_enabled == 0) 1082 return (0); 1083 /* 1084 * If the interface isn't running, don't try to 1085 * service the interrupt.. just ack it and bail. 1086 */ 1087 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1088 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1089 if (statack) { 1090 claimed = 1; 1091 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1092 } 1093 return (claimed); 1094 } 1095 1096 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1097 claimed = 1; 1098 1099 /* 1100 * First ACK all the interrupts in this pass. 1101 */ 1102 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1103 1104 /* 1105 * Process receiver interrupts. If a no-resource (RNR) 1106 * condition exists, get whatever packets we can and 1107 * re-start the receiver. 1108 */ 1109 rnr = (statack & (FXP_SCB_STATACK_RNR | FXP_SCB_STATACK_SWI)) ? 1110 1 : 0; 1111 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR | 1112 FXP_SCB_STATACK_SWI)) { 1113 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1114 rnr |= fxp_rxintr(sc); 1115 } 1116 1117 /* 1118 * Free any finished transmit mbuf chains. 1119 */ 1120 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1121 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1122 fxp_txintr(sc); 1123 1124 /* 1125 * Try to get more packets going. 1126 */ 1127 fxp_start(ifp); 1128 1129 if (sc->sc_txpending == 0) { 1130 /* 1131 * Tell them that they can re-init now. 1132 */ 1133 if (sc->sc_flags & FXPF_WANTINIT) 1134 wakeup(sc); 1135 } 1136 } 1137 1138 if (rnr) { 1139 fxp_scb_wait(sc); 1140 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_ABORT); 1141 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1142 fxp_scb_wait(sc); 1143 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1144 rxmap->dm_segs[0].ds_addr + 1145 RFA_ALIGNMENT_FUDGE); 1146 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1147 } 1148 } 1149 1150#if NRND > 0 1151 if (claimed) 1152 rnd_add_uint32(&sc->rnd_source, statack); 1153#endif 1154 return (claimed); 1155} 1156 1157/* 1158 * Handle transmit completion interrupts. 1159 */ 1160void 1161fxp_txintr(struct fxp_softc *sc) 1162{ 1163 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1164 struct fxp_txdesc *txd; 1165 struct fxp_txsoft *txs; 1166 int i; 1167 u_int16_t txstat; 1168 1169 ifp->if_flags &= ~IFF_OACTIVE; 1170 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1171 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1172 txd = FXP_CDTX(sc, i); 1173 txs = FXP_DSTX(sc, i); 1174 1175 FXP_CDTXSYNC(sc, i, 1176 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1177 1178 /* skip dummy NOP TX descriptor */ 1179 if ((le16toh(txd->txd_txcb.cb_command) & FXP_CB_COMMAND_CMD) 1180 == FXP_CB_COMMAND_NOP) 1181 continue; 1182 1183 txstat = le16toh(txd->txd_txcb.cb_status); 1184 1185 if ((txstat & FXP_CB_STATUS_C) == 0) 1186 break; 1187 1188 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1189 0, txs->txs_dmamap->dm_mapsize, 1190 BUS_DMASYNC_POSTWRITE); 1191 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1192 m_freem(txs->txs_mbuf); 1193 txs->txs_mbuf = NULL; 1194 } 1195 1196 /* Update the dirty transmit buffer pointer. */ 1197 sc->sc_txdirty = i; 1198 1199 /* 1200 * Cancel the watchdog timer if there are no pending 1201 * transmissions. 1202 */ 1203 if (sc->sc_txpending == 0) 1204 ifp->if_timer = 0; 1205} 1206 1207/* 1208 * fxp_rx_hwcksum: check status of H/W offloading for received packets. 1209 */ 1210 1211int 1212fxp_rx_hwcksum(struct mbuf *m, const struct fxp_rfa *rfa) 1213{ 1214 u_int16_t rxparsestat; 1215 u_int16_t csum_stat; 1216 u_int32_t csum_data; 1217 int csum_flags; 1218 1219 /* 1220 * check VLAN tag stripping. 1221 */ 1222 1223 if (rfa->rfa_status & htole16(FXP_RFA_STATUS_VLAN)) { 1224 struct m_tag *vtag; 1225 1226 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), M_NOWAIT); 1227 if (vtag == NULL) 1228 return ENOMEM; 1229 *(u_int *)(vtag + 1) = be16toh(rfa->vlan_id); 1230 m_tag_prepend(m, vtag); 1231 } 1232 1233 /* 1234 * check H/W Checksumming. 1235 */ 1236 1237 csum_stat = le16toh(rfa->cksum_stat); 1238 rxparsestat = le16toh(rfa->rx_parse_stat); 1239 if (!(rfa->rfa_status & htole16(FXP_RFA_STATUS_PARSE))) 1240 return 0; 1241 1242 csum_flags = 0; 1243 csum_data = 0; 1244 1245 if (csum_stat & FXP_RFDX_CS_IP_CSUM_BIT_VALID) { 1246 csum_flags = M_CSUM_IPv4; 1247 if (!(csum_stat & FXP_RFDX_CS_IP_CSUM_VALID)) 1248 csum_flags |= M_CSUM_IPv4_BAD; 1249 } 1250 1251 if (csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) { 1252 csum_flags |= (M_CSUM_TCPv4|M_CSUM_UDPv4); /* XXX */ 1253 if (!(csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) 1254 csum_flags |= M_CSUM_TCP_UDP_BAD; 1255 } 1256 1257 m->m_pkthdr.csum_flags = csum_flags; 1258 m->m_pkthdr.csum_data = csum_data; 1259 1260 return 0; 1261} 1262 1263/* 1264 * Handle receive interrupts. 1265 */ 1266int 1267fxp_rxintr(struct fxp_softc *sc) 1268{ 1269 struct ethercom *ec = &sc->sc_ethercom; 1270 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1271 struct mbuf *m, *m0; 1272 bus_dmamap_t rxmap; 1273 struct fxp_rfa *rfa; 1274 int rnr; 1275 u_int16_t len, rxstat; 1276 1277 rnr = 0; 1278 1279 for (;;) { 1280 m = sc->sc_rxq.ifq_head; 1281 rfa = FXP_MTORFA(m); 1282 rxmap = M_GETCTX(m, bus_dmamap_t); 1283 1284 FXP_RFASYNC(sc, m, 1285 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1286 1287 rxstat = le16toh(rfa->rfa_status); 1288 1289 if ((rxstat & FXP_RFA_STATUS_RNR) != 0) 1290 rnr = 1; 1291 1292 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1293 /* 1294 * We have processed all of the 1295 * receive buffers. 1296 */ 1297 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1298 return rnr; 1299 } 1300 1301 IF_DEQUEUE(&sc->sc_rxq, m); 1302 1303 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1304 1305 len = le16toh(rfa->actual_size) & 1306 (m->m_ext.ext_size - 1); 1307 1308 if (len < sizeof(struct ether_header)) { 1309 /* 1310 * Runt packet; drop it now. 1311 */ 1312 FXP_INIT_RFABUF(sc, m); 1313 continue; 1314 } 1315 1316 /* 1317 * If support for 802.1Q VLAN sized frames is 1318 * enabled, we need to do some additional error 1319 * checking (as we are saving bad frames, in 1320 * order to receive the larger ones). 1321 */ 1322 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1323 (rxstat & (FXP_RFA_STATUS_OVERRUN| 1324 FXP_RFA_STATUS_RNR| 1325 FXP_RFA_STATUS_ALIGN| 1326 FXP_RFA_STATUS_CRC)) != 0) { 1327 FXP_INIT_RFABUF(sc, m); 1328 continue; 1329 } 1330 1331 /* Do checksum checking. */ 1332 m->m_pkthdr.csum_flags = 0; 1333 if (sc->sc_flags & FXPF_EXT_RFA) 1334 if (fxp_rx_hwcksum(m, rfa)) 1335 goto dropit; 1336 1337 /* 1338 * If the packet is small enough to fit in a 1339 * single header mbuf, allocate one and copy 1340 * the data into it. This greatly reduces 1341 * memory consumption when we receive lots 1342 * of small packets. 1343 * 1344 * Otherwise, we add a new buffer to the receive 1345 * chain. If this fails, we drop the packet and 1346 * recycle the old buffer. 1347 */ 1348 if (fxp_copy_small != 0 && len <= MHLEN) { 1349 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1350 if (m0 == NULL) 1351 goto dropit; 1352 MCLAIM(m0, &sc->sc_ethercom.ec_rx_mowner); 1353 memcpy(mtod(m0, void *), 1354 mtod(m, void *), len); 1355 m0->m_pkthdr.csum_flags = m->m_pkthdr.csum_flags; 1356 m0->m_pkthdr.csum_data = m->m_pkthdr.csum_data; 1357 FXP_INIT_RFABUF(sc, m); 1358 m = m0; 1359 } else { 1360 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1361 dropit: 1362 ifp->if_ierrors++; 1363 FXP_INIT_RFABUF(sc, m); 1364 continue; 1365 } 1366 } 1367 1368 m->m_pkthdr.rcvif = ifp; 1369 m->m_pkthdr.len = m->m_len = len; 1370 1371#if NBPFILTER > 0 1372 /* 1373 * Pass this up to any BPF listeners, but only 1374 * pass it up the stack if it's for us. 1375 */ 1376 if (ifp->if_bpf) 1377 bpf_mtap(ifp->if_bpf, m); 1378#endif 1379 1380 /* Pass it on. */ 1381 (*ifp->if_input)(ifp, m); 1382 } 1383} 1384 1385/* 1386 * Update packet in/out/collision statistics. The i82557 doesn't 1387 * allow you to access these counters without doing a fairly 1388 * expensive DMA to get _all_ of the statistics it maintains, so 1389 * we do this operation here only once per second. The statistics 1390 * counters in the kernel are updated from the previous dump-stats 1391 * DMA and then a new dump-stats DMA is started. The on-chip 1392 * counters are zeroed when the DMA completes. If we can't start 1393 * the DMA immediately, we don't wait - we just prepare to read 1394 * them again next time. 1395 */ 1396void 1397fxp_tick(void *arg) 1398{ 1399 struct fxp_softc *sc = arg; 1400 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1401 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1402 int s; 1403 1404 if (!device_is_active(sc->sc_dev)) 1405 return; 1406 1407 s = splnet(); 1408 1409 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1410 1411 ifp->if_opackets += le32toh(sp->tx_good); 1412 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1413 if (sp->rx_good) { 1414 ifp->if_ipackets += le32toh(sp->rx_good); 1415 sc->sc_rxidle = 0; 1416 } else if (sc->sc_flags & FXPF_RECV_WORKAROUND) { 1417 sc->sc_rxidle++; 1418 } 1419 ifp->if_ierrors += 1420 le32toh(sp->rx_crc_errors) + 1421 le32toh(sp->rx_alignment_errors) + 1422 le32toh(sp->rx_rnr_errors) + 1423 le32toh(sp->rx_overrun_errors); 1424 /* 1425 * If any transmit underruns occurred, bump up the transmit 1426 * threshold by another 512 bytes (64 * 8). 1427 */ 1428 if (sp->tx_underruns) { 1429 ifp->if_oerrors += le32toh(sp->tx_underruns); 1430 if (tx_threshold < 192) 1431 tx_threshold += 64; 1432 } 1433#ifdef FXP_EVENT_COUNTERS 1434 if (sc->sc_rev >= FXP_REV_82558_A4) { 1435 sc->sc_ev_txpause.ev_count += sp->tx_pauseframes; 1436 sc->sc_ev_rxpause.ev_count += sp->rx_pauseframes; 1437 } 1438#endif 1439 1440 /* 1441 * If we haven't received any packets in FXP_MAX_RX_IDLE seconds, 1442 * then assume the receiver has locked up and attempt to clear 1443 * the condition by reprogramming the multicast filter (actually, 1444 * resetting the interface). This is a work-around for a bug in 1445 * the 82557 where the receiver locks up if it gets certain types 1446 * of garbage in the synchronization bits prior to the packet header. 1447 * This bug is supposed to only occur in 10Mbps mode, but has been 1448 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1449 * speed transition). 1450 */ 1451 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1452 (void) fxp_init(ifp); 1453 splx(s); 1454 return; 1455 } 1456 /* 1457 * If there is no pending command, start another stats 1458 * dump. Otherwise punt for now. 1459 */ 1460 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1461 /* 1462 * Start another stats dump. 1463 */ 1464 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1465 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1466 } else { 1467 /* 1468 * A previous command is still waiting to be accepted. 1469 * Just zero our copy of the stats and wait for the 1470 * next timer event to update them. 1471 */ 1472 /* BIG_ENDIAN: no swap required to store 0 */ 1473 sp->tx_good = 0; 1474 sp->tx_underruns = 0; 1475 sp->tx_total_collisions = 0; 1476 1477 sp->rx_good = 0; 1478 sp->rx_crc_errors = 0; 1479 sp->rx_alignment_errors = 0; 1480 sp->rx_rnr_errors = 0; 1481 sp->rx_overrun_errors = 0; 1482 if (sc->sc_rev >= FXP_REV_82558_A4) { 1483 sp->tx_pauseframes = 0; 1484 sp->rx_pauseframes = 0; 1485 } 1486 } 1487 1488 if (sc->sc_flags & FXPF_MII) { 1489 /* Tick the MII clock. */ 1490 mii_tick(&sc->sc_mii); 1491 } 1492 1493 splx(s); 1494 1495 /* 1496 * Schedule another timeout one second from now. 1497 */ 1498 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1499} 1500 1501/* 1502 * Drain the receive queue. 1503 */ 1504void 1505fxp_rxdrain(struct fxp_softc *sc) 1506{ 1507 bus_dmamap_t rxmap; 1508 struct mbuf *m; 1509 1510 for (;;) { 1511 IF_DEQUEUE(&sc->sc_rxq, m); 1512 if (m == NULL) 1513 break; 1514 rxmap = M_GETCTX(m, bus_dmamap_t); 1515 bus_dmamap_unload(sc->sc_dmat, rxmap); 1516 FXP_RXMAP_PUT(sc, rxmap); 1517 m_freem(m); 1518 } 1519} 1520 1521/* 1522 * Stop the interface. Cancels the statistics updater and resets 1523 * the interface. 1524 */ 1525void 1526fxp_stop(struct ifnet *ifp, int disable) 1527{ 1528 struct fxp_softc *sc = ifp->if_softc; 1529 struct fxp_txsoft *txs; 1530 int i; 1531 1532 /* 1533 * Turn down interface (done early to avoid bad interactions 1534 * between panics, shutdown hooks, and the watchdog timer) 1535 */ 1536 ifp->if_timer = 0; 1537 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1538 1539 /* 1540 * Cancel stats updater. 1541 */ 1542 callout_stop(&sc->sc_callout); 1543 if (sc->sc_flags & FXPF_MII) { 1544 /* Down the MII. */ 1545 mii_down(&sc->sc_mii); 1546 } 1547 1548 /* 1549 * Issue software reset. This unloads any microcode that 1550 * might already be loaded. 1551 */ 1552 sc->sc_flags &= ~FXPF_UCODE_LOADED; 1553 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1554 DELAY(50); 1555 1556 /* 1557 * Release any xmit buffers. 1558 */ 1559 for (i = 0; i < FXP_NTXCB; i++) { 1560 txs = FXP_DSTX(sc, i); 1561 if (txs->txs_mbuf != NULL) { 1562 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1563 m_freem(txs->txs_mbuf); 1564 txs->txs_mbuf = NULL; 1565 } 1566 } 1567 sc->sc_txpending = 0; 1568 1569 if (disable) { 1570 fxp_rxdrain(sc); 1571 fxp_disable(sc); 1572 } 1573 1574} 1575 1576/* 1577 * Watchdog/transmission transmit timeout handler. Called when a 1578 * transmission is started on the interface, but no interrupt is 1579 * received before the timeout. This usually indicates that the 1580 * card has wedged for some reason. 1581 */ 1582void 1583fxp_watchdog(struct ifnet *ifp) 1584{ 1585 struct fxp_softc *sc = ifp->if_softc; 1586 1587 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1588 ifp->if_oerrors++; 1589 1590 (void) fxp_init(ifp); 1591} 1592 1593/* 1594 * Initialize the interface. Must be called at splnet(). 1595 */ 1596int 1597fxp_init(struct ifnet *ifp) 1598{ 1599 struct fxp_softc *sc = ifp->if_softc; 1600 struct fxp_cb_config *cbp; 1601 struct fxp_cb_ias *cb_ias; 1602 struct fxp_txdesc *txd; 1603 bus_dmamap_t rxmap; 1604 int i, prm, save_bf, lrxen, vlan_drop, allm, error = 0; 1605 uint16_t status; 1606 1607 if ((error = fxp_enable(sc)) != 0) 1608 goto out; 1609 1610 /* 1611 * Cancel any pending I/O 1612 */ 1613 fxp_stop(ifp, 0); 1614 1615 /* 1616 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1617 * flag, and this prevents the MII from detaching resulting in 1618 * a panic. The flags field should perhaps be split in runtime 1619 * flags and more static information. For now, just clear the 1620 * only other flag set. 1621 */ 1622 1623 sc->sc_flags &= ~FXPF_WANTINIT; 1624 1625 /* 1626 * Initialize base of CBL and RFA memory. Loading with zero 1627 * sets it up for regular linear addressing. 1628 */ 1629 fxp_scb_wait(sc); 1630 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1631 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1632 1633 fxp_scb_wait(sc); 1634 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1635 1636 /* 1637 * Initialize the multicast filter. Do this now, since we might 1638 * have to setup the config block differently. 1639 */ 1640 fxp_mc_setup(sc); 1641 1642 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1643 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1644 1645 /* 1646 * In order to support receiving 802.1Q VLAN frames, we have to 1647 * enable "save bad frames", since they are 4 bytes larger than 1648 * the normal Ethernet maximum frame length. On i82558 and later, 1649 * we have a better mechanism for this. 1650 */ 1651 save_bf = 0; 1652 lrxen = 0; 1653 vlan_drop = 0; 1654 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1655 if (sc->sc_rev < FXP_REV_82558_A4) 1656 save_bf = 1; 1657 else 1658 lrxen = 1; 1659 if (sc->sc_rev >= FXP_REV_82550) 1660 vlan_drop = 1; 1661 } 1662 1663 /* 1664 * Initialize base of dump-stats buffer. 1665 */ 1666 fxp_scb_wait(sc); 1667 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1668 sc->sc_cddma + FXP_CDSTATSOFF); 1669 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1670 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1671 1672 cbp = &sc->sc_control_data->fcd_configcb; 1673 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1674 1675 /* 1676 * Load microcode for this controller. 1677 */ 1678 fxp_load_ucode(sc); 1679 1680 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK1)) 1681 sc->sc_flags |= FXPF_RECV_WORKAROUND; 1682 else 1683 sc->sc_flags &= ~FXPF_RECV_WORKAROUND; 1684 1685 /* 1686 * This copy is kind of disgusting, but there are a bunch of must be 1687 * zero and must be one bits in this structure and this is the easiest 1688 * way to initialize them all to proper values. 1689 */ 1690 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1691 1692 /* BIG_ENDIAN: no need to swap to store 0 */ 1693 cbp->cb_status = 0; 1694 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1695 FXP_CB_COMMAND_EL); 1696 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1697 cbp->link_addr = 0xffffffff; /* (no) next command */ 1698 /* bytes in config block */ 1699 cbp->byte_count = (sc->sc_flags & FXPF_EXT_RFA) ? 1700 FXP_EXT_CONFIG_LEN : FXP_CONFIG_LEN; 1701 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1702 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1703 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1704 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1705 cbp->type_enable = 0; /* actually reserved */ 1706 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1707 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1708 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1709 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1710 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1711 cbp->late_scb = 0; /* (don't) defer SCB update */ 1712 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1713 cbp->ci_int = 1; /* interrupt on CU idle */ 1714 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1715 cbp->ext_stats_dis = 1; /* disable extended counters */ 1716 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1717 cbp->save_bf = save_bf;/* save bad frames */ 1718 cbp->disc_short_rx = !prm; /* discard short packets */ 1719 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1720 cbp->ext_rfa = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1721 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1722 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1723 /* interface mode */ 1724 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1725 cbp->csma_dis = 0; /* (don't) disable link */ 1726 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1727 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1728 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1729 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1730 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1731 cbp->nsai = 1; /* (don't) disable source addr insert */ 1732 cbp->preamble_length = 2; /* (7 byte) preamble */ 1733 cbp->loopback = 0; /* (don't) loopback */ 1734 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1735 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1736 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1737 cbp->promiscuous = prm; /* promiscuous mode */ 1738 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1739 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1740 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1741 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1742 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1743 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1744 cbp->padding = 1; /* (do) pad short tx packets */ 1745 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1746 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1747 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1748 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1749 /* must set wake_en in PMCSR also */ 1750 cbp->force_fdx = 0; /* (don't) force full duplex */ 1751 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1752 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1753 cbp->mc_all = allm; /* accept all multicasts */ 1754 cbp->ext_rx_mode = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1755 cbp->vlan_drop_en = vlan_drop; 1756 1757 if (sc->sc_rev < FXP_REV_82558_A4) { 1758 /* 1759 * The i82557 has no hardware flow control, the values 1760 * here are the defaults for the chip. 1761 */ 1762 cbp->fc_delay_lsb = 0; 1763 cbp->fc_delay_msb = 0x40; 1764 cbp->pri_fc_thresh = 3; 1765 cbp->tx_fc_dis = 0; 1766 cbp->rx_fc_restop = 0; 1767 cbp->rx_fc_restart = 0; 1768 cbp->fc_filter = 0; 1769 cbp->pri_fc_loc = 1; 1770 } else { 1771 cbp->fc_delay_lsb = 0x1f; 1772 cbp->fc_delay_msb = 0x01; 1773 cbp->pri_fc_thresh = 3; 1774 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1775 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1776 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1777 cbp->fc_filter = !prm; /* drop FC frames to host */ 1778 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1779 cbp->ext_stats_dis = 0; /* enable extended stats */ 1780 } 1781 1782 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1783 1784 /* 1785 * Start the config command/DMA. 1786 */ 1787 fxp_scb_wait(sc); 1788 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1789 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1790 /* ...and wait for it to complete. */ 1791 for (i = 1000; i > 0; i--) { 1792 FXP_CDCONFIGSYNC(sc, 1793 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1794 status = le16toh(cbp->cb_status); 1795 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD); 1796 if ((status & FXP_CB_STATUS_C) != 0) 1797 break; 1798 DELAY(1); 1799 } 1800 if (i == 0) { 1801 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1802 device_xname(sc->sc_dev), __LINE__); 1803 return (ETIMEDOUT); 1804 } 1805 1806 /* 1807 * Initialize the station address. 1808 */ 1809 cb_ias = &sc->sc_control_data->fcd_iascb; 1810 /* BIG_ENDIAN: no need to swap to store 0 */ 1811 cb_ias->cb_status = 0; 1812 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1813 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1814 cb_ias->link_addr = 0xffffffff; 1815 memcpy(cb_ias->macaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1816 1817 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1818 1819 /* 1820 * Start the IAS (Individual Address Setup) command/DMA. 1821 */ 1822 fxp_scb_wait(sc); 1823 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1824 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1825 /* ...and wait for it to complete. */ 1826 for (i = 1000; i > 0; i++) { 1827 FXP_CDIASSYNC(sc, 1828 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1829 status = le16toh(cb_ias->cb_status); 1830 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD); 1831 if ((status & FXP_CB_STATUS_C) != 0) 1832 break; 1833 DELAY(1); 1834 } 1835 if (i == 0) { 1836 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1837 device_xname(sc->sc_dev), __LINE__); 1838 return (ETIMEDOUT); 1839 } 1840 1841 /* 1842 * Initialize the transmit descriptor ring. txlast is initialized 1843 * to the end of the list so that it will wrap around to the first 1844 * descriptor when the first packet is transmitted. 1845 */ 1846 for (i = 0; i < FXP_NTXCB; i++) { 1847 txd = FXP_CDTX(sc, i); 1848 memset(txd, 0, sizeof(*txd)); 1849 txd->txd_txcb.cb_command = 1850 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1851 txd->txd_txcb.link_addr = 1852 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1853 if (sc->sc_flags & FXPF_EXT_TXCB) 1854 txd->txd_txcb.tbd_array_addr = 1855 htole32(FXP_CDTBDADDR(sc, i) + 1856 (2 * sizeof(struct fxp_tbd))); 1857 else 1858 txd->txd_txcb.tbd_array_addr = 1859 htole32(FXP_CDTBDADDR(sc, i)); 1860 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1861 } 1862 sc->sc_txpending = 0; 1863 sc->sc_txdirty = 0; 1864 sc->sc_txlast = FXP_NTXCB - 1; 1865 1866 /* 1867 * Initialize the receive buffer list. 1868 */ 1869 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1870 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1871 rxmap = FXP_RXMAP_GET(sc); 1872 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1873 log(LOG_ERR, "%s: unable to allocate or map rx " 1874 "buffer %d, error = %d\n", 1875 device_xname(sc->sc_dev), 1876 sc->sc_rxq.ifq_len, error); 1877 /* 1878 * XXX Should attempt to run with fewer receive 1879 * XXX buffers instead of just failing. 1880 */ 1881 FXP_RXMAP_PUT(sc, rxmap); 1882 fxp_rxdrain(sc); 1883 goto out; 1884 } 1885 } 1886 sc->sc_rxidle = 0; 1887 1888 /* 1889 * Give the transmit ring to the chip. We do this by pointing 1890 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1891 * issuing a start command. It will execute the NOP and then 1892 * suspend, pointing at the first descriptor. 1893 */ 1894 fxp_scb_wait(sc); 1895 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1896 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1897 1898 /* 1899 * Initialize receiver buffer area - RFA. 1900 */ 1901#if 0 /* initialization will be done by FXP_SCB_INTRCNTL_REQUEST_SWI later */ 1902 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1903 fxp_scb_wait(sc); 1904 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1905 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1906 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1907#endif 1908 1909 if (sc->sc_flags & FXPF_MII) { 1910 /* 1911 * Set current media. 1912 */ 1913 if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0) 1914 goto out; 1915 } 1916 1917 /* 1918 * ...all done! 1919 */ 1920 ifp->if_flags |= IFF_RUNNING; 1921 ifp->if_flags &= ~IFF_OACTIVE; 1922 1923 /* 1924 * Request a software generated interrupt that will be used to 1925 * (re)start the RU processing. If we direct the chip to start 1926 * receiving from the start of queue now, instead of letting the 1927 * interrupt handler first process all received packets, we run 1928 * the risk of having it overwrite mbuf clusters while they are 1929 * being processed or after they have been returned to the pool. 1930 */ 1931 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTRCNTL_REQUEST_SWI); 1932 1933 /* 1934 * Start the one second timer. 1935 */ 1936 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1937 1938 /* 1939 * Attempt to start output on the interface. 1940 */ 1941 fxp_start(ifp); 1942 1943 out: 1944 if (error) { 1945 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1946 ifp->if_timer = 0; 1947 log(LOG_ERR, "%s: interface not running\n", 1948 device_xname(sc->sc_dev)); 1949 } 1950 return (error); 1951} 1952 1953/* 1954 * Notify the world which media we're using. 1955 */ 1956void 1957fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1958{ 1959 struct fxp_softc *sc = ifp->if_softc; 1960 1961 if (sc->sc_enabled == 0) { 1962 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1963 ifmr->ifm_status = 0; 1964 return; 1965 } 1966 1967 ether_mediastatus(ifp, ifmr); 1968 1969 /* 1970 * XXX Flow control is always turned on if the chip supports 1971 * XXX it; we can't easily control it dynamically, since it 1972 * XXX requires sending a setup packet. 1973 */ 1974 if (sc->sc_rev >= FXP_REV_82558_A4) 1975 ifmr->ifm_active |= IFM_FLOW|IFM_ETH_TXPAUSE|IFM_ETH_RXPAUSE; 1976} 1977 1978int 1979fxp_80c24_mediachange(struct ifnet *ifp) 1980{ 1981 1982 /* Nothing to do here. */ 1983 return (0); 1984} 1985 1986void 1987fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1988{ 1989 struct fxp_softc *sc = ifp->if_softc; 1990 1991 /* 1992 * Media is currently-selected media. We cannot determine 1993 * the link status. 1994 */ 1995 ifmr->ifm_status = 0; 1996 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1997} 1998 1999/* 2000 * Add a buffer to the end of the RFA buffer list. 2001 * Return 0 if successful, error code on failure. 2002 * 2003 * The RFA struct is stuck at the beginning of mbuf cluster and the 2004 * data pointer is fixed up to point just past it. 2005 */ 2006int 2007fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 2008{ 2009 struct mbuf *m; 2010 int error; 2011 2012 MGETHDR(m, M_DONTWAIT, MT_DATA); 2013 if (m == NULL) 2014 return (ENOBUFS); 2015 2016 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2017 MCLGET(m, M_DONTWAIT); 2018 if ((m->m_flags & M_EXT) == 0) { 2019 m_freem(m); 2020 return (ENOBUFS); 2021 } 2022 2023 if (unload) 2024 bus_dmamap_unload(sc->sc_dmat, rxmap); 2025 2026 M_SETCTX(m, rxmap); 2027 2028 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2029 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, 2030 BUS_DMA_READ|BUS_DMA_NOWAIT); 2031 if (error) { 2032 /* XXX XXX XXX */ 2033 aprint_error_dev(sc->sc_dev, "can't load rx DMA map %d, error = %d\n", 2034 sc->sc_rxq.ifq_len, error); 2035 panic("fxp_add_rfabuf"); 2036 } 2037 2038 FXP_INIT_RFABUF(sc, m); 2039 2040 return (0); 2041} 2042 2043int 2044fxp_mdi_read(device_t self, int phy, int reg) 2045{ 2046 struct fxp_softc *sc = device_private(self); 2047 int count = 10000; 2048 int value; 2049 2050 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2051 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2052 2053 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 2054 0x10000000) == 0 && count--) 2055 DELAY(10); 2056 2057 if (count <= 0) 2058 log(LOG_WARNING, 2059 "%s: fxp_mdi_read: timed out\n", device_xname(self)); 2060 2061 return (value & 0xffff); 2062} 2063 2064void 2065fxp_statchg(device_t self) 2066{ 2067 2068 /* Nothing to do. */ 2069} 2070 2071void 2072fxp_mdi_write(device_t self, int phy, int reg, int value) 2073{ 2074 struct fxp_softc *sc = device_private(self); 2075 int count = 10000; 2076 2077 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2078 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2079 (value & 0xffff)); 2080 2081 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2082 count--) 2083 DELAY(10); 2084 2085 if (count <= 0) 2086 log(LOG_WARNING, 2087 "%s: fxp_mdi_write: timed out\n", device_xname(self)); 2088} 2089 2090int 2091fxp_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2092{ 2093 struct fxp_softc *sc = ifp->if_softc; 2094 struct ifreq *ifr = (struct ifreq *)data; 2095 int s, error; 2096 2097 s = splnet(); 2098 2099 switch (cmd) { 2100 case SIOCSIFMEDIA: 2101 case SIOCGIFMEDIA: 2102 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2103 break; 2104 2105 default: 2106 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 2107 break; 2108 2109 error = 0; 2110 2111 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2112 ; 2113 else if (ifp->if_flags & IFF_RUNNING) { 2114 /* 2115 * Multicast list has changed; set the 2116 * hardware filter accordingly. 2117 */ 2118 while (sc->sc_txpending) { 2119 sc->sc_flags |= FXPF_WANTINIT; 2120 tsleep(sc, PSOCK, "fxp_init", 0); 2121 } 2122 error = fxp_init(ifp); 2123 } 2124 break; 2125 } 2126 2127 /* Try to get more packets going. */ 2128 if (sc->sc_enabled) 2129 fxp_start(ifp); 2130 2131 splx(s); 2132 return (error); 2133} 2134 2135/* 2136 * Program the multicast filter. 2137 * 2138 * This function must be called at splnet(). 2139 */ 2140void 2141fxp_mc_setup(struct fxp_softc *sc) 2142{ 2143 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 2144 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2145 struct ethercom *ec = &sc->sc_ethercom; 2146 struct ether_multi *enm; 2147 struct ether_multistep step; 2148 int count, nmcasts; 2149 uint16_t status; 2150 2151#ifdef DIAGNOSTIC 2152 if (sc->sc_txpending) 2153 panic("fxp_mc_setup: pending transmissions"); 2154#endif 2155 2156 ifp->if_flags &= ~IFF_ALLMULTI; 2157 2158 /* 2159 * Initialize multicast setup descriptor. 2160 */ 2161 nmcasts = 0; 2162 ETHER_FIRST_MULTI(step, ec, enm); 2163 while (enm != NULL) { 2164 /* 2165 * Check for too many multicast addresses or if we're 2166 * listening to a range. Either way, we simply have 2167 * to accept all multicasts. 2168 */ 2169 if (nmcasts >= MAXMCADDR || 2170 memcmp(enm->enm_addrlo, enm->enm_addrhi, 2171 ETHER_ADDR_LEN) != 0) { 2172 /* 2173 * Callers of this function must do the 2174 * right thing with this. If we're called 2175 * from outside fxp_init(), the caller must 2176 * detect if the state if IFF_ALLMULTI changes. 2177 * If it does, the caller must then call 2178 * fxp_init(), since allmulti is handled by 2179 * the config block. 2180 */ 2181 ifp->if_flags |= IFF_ALLMULTI; 2182 return; 2183 } 2184 memcpy(&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 2185 ETHER_ADDR_LEN); 2186 nmcasts++; 2187 ETHER_NEXT_MULTI(step, enm); 2188 } 2189 2190 /* BIG_ENDIAN: no need to swap to store 0 */ 2191 mcsp->cb_status = 0; 2192 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2193 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 2194 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2195 2196 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2197 2198 /* 2199 * Wait until the command unit is not active. This should never 2200 * happen since nothing is queued, but make sure anyway. 2201 */ 2202 count = 100; 2203 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2204 FXP_SCB_CUS_ACTIVE && --count) 2205 DELAY(1); 2206 if (count == 0) { 2207 log(LOG_WARNING, "%s: line %d: command queue timeout\n", 2208 device_xname(sc->sc_dev), __LINE__); 2209 return; 2210 } 2211 2212 /* 2213 * Start the multicast setup command/DMA. 2214 */ 2215 fxp_scb_wait(sc); 2216 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2217 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2218 2219 /* ...and wait for it to complete. */ 2220 for (count = 1000; count > 0; count--) { 2221 FXP_CDMCSSYNC(sc, 2222 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2223 status = le16toh(mcsp->cb_status); 2224 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD); 2225 if ((status & FXP_CB_STATUS_C) != 0) 2226 break; 2227 DELAY(1); 2228 } 2229 if (count == 0) { 2230 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 2231 device_xname(sc->sc_dev), __LINE__); 2232 return; 2233 } 2234} 2235 2236static const uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2237static const uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2238static const uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2239static const uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2240static const uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2241static const uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2242 2243#define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2244 2245static const struct ucode { 2246 int32_t revision; 2247 const uint32_t *ucode; 2248 size_t length; 2249 uint16_t int_delay_offset; 2250 uint16_t bundle_max_offset; 2251} ucode_table[] = { 2252 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), 2253 D101_CPUSAVER_DWORD, 0 }, 2254 2255 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), 2256 D101_CPUSAVER_DWORD, 0 }, 2257 2258 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2259 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2260 2261 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2262 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2263 2264 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2265 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2266 2267 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2268 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2269 2270 { 0, NULL, 0, 0, 0 } 2271}; 2272 2273void 2274fxp_load_ucode(struct fxp_softc *sc) 2275{ 2276 const struct ucode *uc; 2277 struct fxp_cb_ucode *cbp = &sc->sc_control_data->fcd_ucode; 2278 int count, i; 2279 uint16_t status; 2280 2281 if (sc->sc_flags & FXPF_UCODE_LOADED) 2282 return; 2283 2284 /* 2285 * Only load the uCode if the user has requested that 2286 * we do so. 2287 */ 2288 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK0) == 0) { 2289 sc->sc_int_delay = 0; 2290 sc->sc_bundle_max = 0; 2291 return; 2292 } 2293 2294 for (uc = ucode_table; uc->ucode != NULL; uc++) { 2295 if (sc->sc_rev == uc->revision) 2296 break; 2297 } 2298 if (uc->ucode == NULL) 2299 return; 2300 2301 /* BIG ENDIAN: no need to swap to store 0 */ 2302 cbp->cb_status = 0; 2303 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2304 cbp->link_addr = 0xffffffff; /* (no) next command */ 2305 for (i = 0; i < uc->length; i++) 2306 cbp->ucode[i] = htole32(uc->ucode[i]); 2307 2308 if (uc->int_delay_offset) 2309 *(volatile uint16_t *) &cbp->ucode[uc->int_delay_offset] = 2310 htole16(fxp_int_delay + (fxp_int_delay / 2)); 2311 2312 if (uc->bundle_max_offset) 2313 *(volatile uint16_t *) &cbp->ucode[uc->bundle_max_offset] = 2314 htole16(fxp_bundle_max); 2315 2316 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2317 2318 /* 2319 * Download the uCode to the chip. 2320 */ 2321 fxp_scb_wait(sc); 2322 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDUCODEOFF); 2323 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2324 2325 /* ...and wait for it to complete. */ 2326 for (count = 10000; count > 0; count--) { 2327 FXP_CDUCODESYNC(sc, 2328 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2329 status = le16toh(cbp->cb_status); 2330 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD); 2331 if ((status & FXP_CB_STATUS_C) != 0) 2332 break; 2333 DELAY(2); 2334 } 2335 if (count == 0) { 2336 sc->sc_int_delay = 0; 2337 sc->sc_bundle_max = 0; 2338 log(LOG_WARNING, "%s: timeout loading microcode\n", 2339 device_xname(sc->sc_dev)); 2340 return; 2341 } 2342 2343 if (sc->sc_int_delay != fxp_int_delay || 2344 sc->sc_bundle_max != fxp_bundle_max) { 2345 sc->sc_int_delay = fxp_int_delay; 2346 sc->sc_bundle_max = fxp_bundle_max; 2347 log(LOG_INFO, "%s: Microcode loaded: int delay: %d usec, " 2348 "max bundle: %d\n", device_xname(sc->sc_dev), 2349 sc->sc_int_delay, 2350 uc->bundle_max_offset == 0 ? 0 : sc->sc_bundle_max); 2351 } 2352 2353 sc->sc_flags |= FXPF_UCODE_LOADED; 2354} 2355 2356int 2357fxp_enable(struct fxp_softc *sc) 2358{ 2359 2360 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2361 if ((*sc->sc_enable)(sc) != 0) { 2362 log(LOG_ERR, "%s: device enable failed\n", 2363 device_xname(sc->sc_dev)); 2364 return (EIO); 2365 } 2366 } 2367 2368 sc->sc_enabled = 1; 2369 return (0); 2370} 2371 2372void 2373fxp_disable(struct fxp_softc *sc) 2374{ 2375 2376 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2377 (*sc->sc_disable)(sc); 2378 sc->sc_enabled = 0; 2379 } 2380} 2381 2382/* 2383 * fxp_activate: 2384 * 2385 * Handle device activation/deactivation requests. 2386 */ 2387int 2388fxp_activate(device_t self, enum devact act) 2389{ 2390 struct fxp_softc *sc = device_private(self); 2391 int s, error = 0; 2392 2393 s = splnet(); 2394 switch (act) { 2395 case DVACT_ACTIVATE: 2396 error = EOPNOTSUPP; 2397 break; 2398 2399 case DVACT_DEACTIVATE: 2400 if (sc->sc_flags & FXPF_MII) 2401 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 2402 MII_OFFSET_ANY); 2403 if_deactivate(&sc->sc_ethercom.ec_if); 2404 break; 2405 } 2406 splx(s); 2407 2408 return (error); 2409} 2410 2411/* 2412 * fxp_detach: 2413 * 2414 * Detach an i82557 interface. 2415 */ 2416int 2417fxp_detach(struct fxp_softc *sc) 2418{ 2419 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2420 int i; 2421 2422 /* Succeed now if there's no work to do. */ 2423 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2424 return (0); 2425 2426 /* Unhook our tick handler. */ 2427 callout_stop(&sc->sc_callout); 2428 2429 if (sc->sc_flags & FXPF_MII) { 2430 /* Detach all PHYs */ 2431 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2432 } 2433 2434 /* Delete all remaining media. */ 2435 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2436 2437#if NRND > 0 2438 rnd_detach_source(&sc->rnd_source); 2439#endif 2440 ether_ifdetach(ifp); 2441 if_detach(ifp); 2442 2443 for (i = 0; i < FXP_NRFABUFS; i++) { 2444 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2445 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2446 } 2447 2448 for (i = 0; i < FXP_NTXCB; i++) { 2449 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2450 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2451 } 2452 2453 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2454 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2455 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 2456 sizeof(struct fxp_control_data)); 2457 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2458 2459 return (0); 2460} 2461