1/* $NetBSD: i82557.c,v 1.162 2024/06/29 12:11:11 riastradh Exp $ */ 2 3/*- 4 * Copyright (c) 1997, 1998, 1999, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Copyright (c) 1995, David Greenman 35 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice unmodified, this list of conditions, and the following 43 * disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 61 */ 62 63/* 64 * Device driver for the Intel i82557 fast Ethernet controller, 65 * and its successors, the i82558 and i82559. 66 */ 67 68#include <sys/cdefs.h> 69__KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.162 2024/06/29 12:11:11 riastradh Exp $"); 70 71#include <sys/param.h> 72#include <sys/systm.h> 73#include <sys/callout.h> 74#include <sys/mbuf.h> 75#include <sys/malloc.h> 76#include <sys/kernel.h> 77#include <sys/socket.h> 78#include <sys/ioctl.h> 79#include <sys/errno.h> 80#include <sys/device.h> 81#include <sys/syslog.h> 82#include <sys/proc.h> 83 84#include <machine/endian.h> 85 86#include <sys/rndsource.h> 87 88#include <net/if.h> 89#include <net/if_dl.h> 90#include <net/if_media.h> 91#include <net/if_ether.h> 92 93#include <netinet/in.h> 94#include <netinet/in_systm.h> 95#include <netinet/ip.h> 96#include <netinet/tcp.h> 97#include <netinet/udp.h> 98 99#include <net/bpf.h> 100 101#include <sys/bus.h> 102#include <sys/intr.h> 103 104#include <dev/mii/miivar.h> 105 106#include <dev/ic/i82557reg.h> 107#include <dev/ic/i82557var.h> 108 109#include <dev/microcode/i8255x/rcvbundl.h> 110 111/* 112 * NOTE! On the Alpha, we have an alignment constraint. The 113 * card DMAs the packet immediately following the RFA. However, 114 * the first thing in the packet is a 14-byte Ethernet header. 115 * This means that the packet is misaligned. To compensate, 116 * we actually offset the RFA 2 bytes into the cluster. This 117 * aligns the packet after the Ethernet header at a 32-bit 118 * boundary. HOWEVER! This means that the RFA is misaligned! 119 */ 120#define RFA_ALIGNMENT_FUDGE 2 121 122/* 123 * The configuration byte map has several undefined fields which 124 * must be one or must be zero. Set up a template for these bits 125 * only (assuming an i82557 chip), leaving the actual configuration 126 * for fxp_init(). 127 * 128 * See the definition of struct fxp_cb_config for the bit definitions. 129 */ 130const uint8_t fxp_cb_config_template[] = { 131 0x0, 0x0, /* cb_status */ 132 0x0, 0x0, /* cb_command */ 133 0x0, 0x0, 0x0, 0x0, /* link_addr */ 134 0x0, /* 0 */ 135 0x0, /* 1 */ 136 0x0, /* 2 */ 137 0x0, /* 3 */ 138 0x0, /* 4 */ 139 0x0, /* 5 */ 140 0x32, /* 6 */ 141 0x0, /* 7 */ 142 0x0, /* 8 */ 143 0x0, /* 9 */ 144 0x6, /* 10 */ 145 0x0, /* 11 */ 146 0x0, /* 12 */ 147 0x0, /* 13 */ 148 0xf2, /* 14 */ 149 0x48, /* 15 */ 150 0x0, /* 16 */ 151 0x40, /* 17 */ 152 0xf0, /* 18 */ 153 0x0, /* 19 */ 154 0x3f, /* 20 */ 155 0x5, /* 21 */ 156 0x0, /* 22 */ 157 0x0, /* 23 */ 158 0x0, /* 24 */ 159 0x0, /* 25 */ 160 0x0, /* 26 */ 161 0x0, /* 27 */ 162 0x0, /* 28 */ 163 0x0, /* 29 */ 164 0x0, /* 30 */ 165 0x0, /* 31 */ 166}; 167 168void fxp_mii_initmedia(struct fxp_softc *); 169void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 170 171void fxp_80c24_initmedia(struct fxp_softc *); 172int fxp_80c24_mediachange(struct ifnet *); 173void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 174 175void fxp_start(struct ifnet *); 176int fxp_ioctl(struct ifnet *, u_long, void *); 177void fxp_watchdog(struct ifnet *); 178int fxp_init(struct ifnet *); 179void fxp_stop(struct ifnet *, int); 180 181void fxp_txintr(struct fxp_softc *); 182int fxp_rxintr(struct fxp_softc *); 183 184void fxp_rx_hwcksum(struct fxp_softc *, struct mbuf *, 185 const struct fxp_rfa *, u_int); 186 187void fxp_rxdrain(struct fxp_softc *); 188int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 189int fxp_mdi_read(device_t, int, int, uint16_t *); 190void fxp_statchg(struct ifnet *); 191int fxp_mdi_write(device_t, int, int, uint16_t); 192void fxp_autosize_eeprom(struct fxp_softc*); 193void fxp_read_eeprom(struct fxp_softc *, uint16_t *, int, int); 194void fxp_write_eeprom(struct fxp_softc *, uint16_t *, int, int); 195void fxp_eeprom_update_cksum(struct fxp_softc *); 196void fxp_get_info(struct fxp_softc *, uint8_t *); 197void fxp_tick(void *); 198void fxp_mc_setup(struct fxp_softc *); 199void fxp_load_ucode(struct fxp_softc *); 200 201int fxp_copy_small = 0; 202 203/* 204 * Variables for interrupt mitigating microcode. 205 */ 206int fxp_int_delay = 1000; /* usec */ 207int fxp_bundle_max = 6; /* packets */ 208 209struct fxp_phytype { 210 int fp_phy; /* type of PHY, -1 for MII at the end. */ 211 void (*fp_init)(struct fxp_softc *); 212} fxp_phytype_table[] = { 213 { FXP_PHY_80C24, fxp_80c24_initmedia }, 214 { -1, fxp_mii_initmedia }, 215}; 216 217/* 218 * Set initial transmit threshold at 64 (512 bytes). This is 219 * increased by 64 (512 bytes) at a time, to maximum of 192 220 * (1536 bytes), if an underrun occurs. 221 */ 222static int tx_threshold = 64; 223 224/* 225 * Wait for the previous command to be accepted (but not necessarily 226 * completed). 227 */ 228static inline void 229fxp_scb_wait(struct fxp_softc *sc) 230{ 231 int i = 10000; 232 233 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 234 delay(2); 235 if (i == 0) 236 log(LOG_WARNING, 237 "%s: WARNING: SCB timed out!\n", device_xname(sc->sc_dev)); 238} 239 240/* 241 * Submit a command to the i82557. 242 */ 243static inline void 244fxp_scb_cmd(struct fxp_softc *sc, uint8_t cmd) 245{ 246 247 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 248} 249 250/* 251 * Finish attaching an i82557 interface. Called by bus-specific front-end. 252 */ 253void 254fxp_attach(struct fxp_softc *sc) 255{ 256 uint8_t enaddr[ETHER_ADDR_LEN]; 257 struct ifnet *ifp; 258 bus_dma_segment_t seg; 259 int rseg, i, error; 260 struct fxp_phytype *fp; 261 262 callout_init(&sc->sc_callout, 0); 263 callout_setfunc(&sc->sc_callout, fxp_tick, sc); 264 265 /* 266 * Enable use of extended RFDs and IPCBs for 82550 and later chips. 267 * Note: to use IPCB we need extended TXCB support too, and 268 * these feature flags should be set in each bus attachment. 269 */ 270 if (sc->sc_flags & FXPF_EXT_RFA) { 271 sc->sc_txcmd = htole16(FXP_CB_COMMAND_IPCBXMIT); 272 sc->sc_rfa_size = RFA_EXT_SIZE; 273 } else { 274 sc->sc_txcmd = htole16(FXP_CB_COMMAND_XMIT); 275 sc->sc_rfa_size = RFA_SIZE; 276 } 277 278 /* 279 * Allocate the control data structures, and create and load the 280 * DMA map for it. 281 */ 282 if ((error = bus_dmamem_alloc(sc->sc_dmat, 283 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 284 0)) != 0) { 285 aprint_error_dev(sc->sc_dev, 286 "unable to allocate control data, error = %d\n", 287 error); 288 goto fail_0; 289 } 290 291 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 292 sizeof(struct fxp_control_data), (void **)&sc->sc_control_data, 293 BUS_DMA_COHERENT)) != 0) { 294 aprint_error_dev(sc->sc_dev, 295 "unable to map control data, error = %d\n", error); 296 goto fail_1; 297 } 298 sc->sc_cdseg = seg; 299 sc->sc_cdnseg = rseg; 300 301 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 302 303 if ((error = bus_dmamap_create(sc->sc_dmat, 304 sizeof(struct fxp_control_data), 1, 305 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 306 aprint_error_dev(sc->sc_dev, 307 "unable to create control data DMA map, error = %d\n", 308 error); 309 goto fail_2; 310 } 311 312 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 313 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 314 0)) != 0) { 315 aprint_error_dev(sc->sc_dev, 316 "can't load control data DMA map, error = %d\n", 317 error); 318 goto fail_3; 319 } 320 321 /* 322 * Create the transmit buffer DMA maps. 323 */ 324 for (i = 0; i < FXP_NTXCB; i++) { 325 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 326 (sc->sc_flags & FXPF_EXT_RFA) ? 327 FXP_IPCB_NTXSEG : FXP_NTXSEG, 328 MCLBYTES, 0, 0, &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 329 aprint_error_dev(sc->sc_dev, 330 "unable to create tx DMA map %d, error = %d\n", 331 i, error); 332 goto fail_4; 333 } 334 } 335 336 /* 337 * Create the receive buffer DMA maps. 338 */ 339 for (i = 0; i < FXP_NRFABUFS; i++) { 340 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 341 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 342 aprint_error_dev(sc->sc_dev, 343 "unable to create rx DMA map %d, error = %d\n", 344 i, error); 345 goto fail_5; 346 } 347 } 348 349 /* Initialize MAC address and media structures. */ 350 fxp_get_info(sc, enaddr); 351 352 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 353 ether_sprintf(enaddr)); 354 355 ifp = &sc->sc_ethercom.ec_if; 356 357 /* 358 * Get info about our media interface, and initialize it. Note 359 * the table terminates itself with a phy of -1, indicating 360 * that we're using MII. 361 */ 362 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 363 if (fp->fp_phy == sc->phy_primary_device) 364 break; 365 (*fp->fp_init)(sc); 366 367 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 368 ifp->if_softc = sc; 369 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 370 ifp->if_ioctl = fxp_ioctl; 371 ifp->if_start = fxp_start; 372 ifp->if_watchdog = fxp_watchdog; 373 ifp->if_init = fxp_init; 374 ifp->if_stop = fxp_stop; 375 IFQ_SET_READY(&ifp->if_snd); 376 377 if (sc->sc_flags & FXPF_EXT_RFA) { 378 /* 379 * Enable hardware cksum support by EXT_RFA and IPCB. 380 * 381 * IFCAP_CSUM_IPv4_Tx seems to have a problem, 382 * at least, on i82550 rev.12. 383 * specifically, it doesn't set ipv4 checksum properly 384 * when sending UDP (and probably TCP) packets with 385 * 20 byte ipv4 header + 1 or 2 byte data, 386 * though ICMP packets seem working. 387 * FreeBSD driver has related comments. 388 * We've added a workaround to handle the bug by padding 389 * such packets manually. 390 */ 391 ifp->if_capabilities = 392 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 393 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 394 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 395 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 396 sc->sc_ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 397 } else if (sc->sc_flags & FXPF_82559_RXCSUM) { 398 ifp->if_capabilities = 399 IFCAP_CSUM_TCPv4_Rx | 400 IFCAP_CSUM_UDPv4_Rx; 401 } 402 403 /* 404 * We can support 802.1Q VLAN-sized frames. 405 */ 406 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 407 408 /* 409 * Attach the interface. 410 */ 411 if_attach(ifp); 412 if_deferred_start_init(ifp, NULL); 413 ether_ifattach(ifp, enaddr); 414 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 415 RND_TYPE_NET, RND_FLAG_DEFAULT); 416 417#ifdef FXP_EVENT_COUNTERS 418 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 419 NULL, device_xname(sc->sc_dev), "txstall"); 420 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 421 NULL, device_xname(sc->sc_dev), "txintr"); 422 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 423 NULL, device_xname(sc->sc_dev), "rxintr"); 424 if (sc->sc_flags & FXPF_FC) { 425 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 426 NULL, device_xname(sc->sc_dev), "txpause"); 427 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 428 NULL, device_xname(sc->sc_dev), "rxpause"); 429 } 430#endif /* FXP_EVENT_COUNTERS */ 431 432 /* The attach is successful. */ 433 sc->sc_flags |= FXPF_ATTACHED; 434 435 return; 436 437 /* 438 * Free any resources we've allocated during the failed attach 439 * attempt. Do this in reverse order and fall though. 440 */ 441 fail_5: 442 for (i = 0; i < FXP_NRFABUFS; i++) { 443 if (sc->sc_rxmaps[i] != NULL) 444 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 445 } 446 fail_4: 447 for (i = 0; i < FXP_NTXCB; i++) { 448 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 449 bus_dmamap_destroy(sc->sc_dmat, 450 FXP_DSTX(sc, i)->txs_dmamap); 451 } 452 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 453 fail_3: 454 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 455 fail_2: 456 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 457 sizeof(struct fxp_control_data)); 458 fail_1: 459 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 460 fail_0: 461 return; 462} 463 464void 465fxp_mii_initmedia(struct fxp_softc *sc) 466{ 467 struct mii_data * const mii = &sc->sc_mii; 468 int flags; 469 470 sc->sc_flags |= FXPF_MII; 471 472 mii->mii_ifp = &sc->sc_ethercom.ec_if; 473 mii->mii_readreg = fxp_mdi_read; 474 mii->mii_writereg = fxp_mdi_write; 475 mii->mii_statchg = fxp_statchg; 476 477 sc->sc_ethercom.ec_mii = mii; 478 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 479 fxp_mii_mediastatus); 480 481 flags = MIIF_NOISOLATE; 482 if (sc->sc_flags & FXPF_FC) 483 flags |= MIIF_FORCEANEG | MIIF_DOPAUSE; 484 /* 485 * The i82557 wedges if all of its PHYs are isolated! 486 */ 487 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 488 MII_OFFSET_ANY, flags); 489 if (LIST_EMPTY(&mii->mii_phys)) { 490 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 491 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 492 } else 493 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 494} 495 496void 497fxp_80c24_initmedia(struct fxp_softc *sc) 498{ 499 struct mii_data * const mii = &sc->sc_mii; 500 501 /* 502 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 503 * doesn't have a programming interface of any sort. The 504 * media is sensed automatically based on how the link partner 505 * is configured. This is, in essence, manual configuration. 506 */ 507 aprint_normal_dev(sc->sc_dev, 508 "Seeq 80c24 AutoDUPLEX media interface present\n"); 509 ifmedia_init(&mii->mii_media, 0, fxp_80c24_mediachange, 510 fxp_80c24_mediastatus); 511 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 512 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 513} 514 515/* 516 * Initialize the interface media. 517 */ 518void 519fxp_get_info(struct fxp_softc *sc, uint8_t *enaddr) 520{ 521 uint16_t data, myea[ETHER_ADDR_LEN / 2]; 522 523 /* 524 * Reset to a stable state. 525 */ 526 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 527 DELAY(100); 528 529 sc->sc_eeprom_size = 0; 530 fxp_autosize_eeprom(sc); 531 if (sc->sc_eeprom_size == 0) { 532 aprint_error_dev(sc->sc_dev, "failed to detect EEPROM size\n"); 533 sc->sc_eeprom_size = 6; /* XXX panic here? */ 534 } 535#ifdef DEBUG 536 aprint_debug_dev(sc->sc_dev, "detected %d word EEPROM\n", 537 1 << sc->sc_eeprom_size); 538#endif 539 540 /* 541 * Get info about the primary PHY 542 */ 543 fxp_read_eeprom(sc, &data, 6, 1); 544 sc->phy_primary_device = 545 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 546 547 /* 548 * Read MAC address. 549 */ 550 fxp_read_eeprom(sc, myea, 0, 3); 551 enaddr[0] = myea[0] & 0xff; 552 enaddr[1] = myea[0] >> 8; 553 enaddr[2] = myea[1] & 0xff; 554 enaddr[3] = myea[1] >> 8; 555 enaddr[4] = myea[2] & 0xff; 556 enaddr[5] = myea[2] >> 8; 557 558 /* 559 * Systems based on the ICH2/ICH2-M chip from Intel, as well 560 * as some i82559 designs, have a defect where the chip can 561 * cause a PCI protocol violation if it receives a CU_RESUME 562 * command when it is entering the IDLE state. 563 * 564 * The work-around is to disable Dynamic Standby Mode, so that 565 * the chip never deasserts #CLKRUN, and always remains in the 566 * active state. 567 * 568 * Unfortunately, the only way to disable Dynamic Standby is 569 * to frob an EEPROM setting and reboot (the EEPROM setting 570 * is only consulted when the PCI bus comes out of reset). 571 * 572 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 573 */ 574 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 575 fxp_read_eeprom(sc, &data, 10, 1); 576 if (data & 0x02) { /* STB enable */ 577 aprint_error_dev(sc->sc_dev, "WARNING: " 578 "Disabling dynamic standby mode in EEPROM " 579 "to work around a\n"); 580 aprint_normal_dev(sc->sc_dev, 581 "WARNING: hardware bug. You must reset " 582 "the system before using this\n"); 583 aprint_normal_dev(sc->sc_dev, "WARNING: interface.\n"); 584 data &= ~0x02; 585 fxp_write_eeprom(sc, &data, 10, 1); 586 aprint_normal_dev(sc->sc_dev, "new EEPROM ID: 0x%04x\n", 587 data); 588 fxp_eeprom_update_cksum(sc); 589 } 590 } 591 592 /* Receiver lock-up workaround detection. (FXPF_RECV_WORKAROUND) */ 593 /* Due to false positives we make it conditional on setting link1 */ 594 fxp_read_eeprom(sc, &data, 3, 1); 595 if ((data & 0x03) != 0x03) { 596 aprint_verbose_dev(sc->sc_dev, 597 "May need receiver lock-up workaround\n"); 598 } 599} 600 601static void 602fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 603{ 604 uint16_t reg; 605 int x; 606 607 for (x = 1 << (len - 1); x != 0; x >>= 1) { 608 DELAY(40); 609 if (data & x) 610 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 611 else 612 reg = FXP_EEPROM_EECS; 613 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 614 DELAY(40); 615 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 616 reg | FXP_EEPROM_EESK); 617 DELAY(40); 618 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 619 } 620 DELAY(40); 621} 622 623/* 624 * Figure out EEPROM size. 625 * 626 * 559's can have either 64-word or 256-word EEPROMs, the 558 627 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 628 * talks about the existence of 16 to 256 word EEPROMs. 629 * 630 * The only known sizes are 64 and 256, where the 256 version is used 631 * by CardBus cards to store CIS information. 632 * 633 * The address is shifted in msb-to-lsb, and after the last 634 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 635 * after which follows the actual data. We try to detect this zero, by 636 * probing the data-out bit in the EEPROM control register just after 637 * having shifted in a bit. If the bit is zero, we assume we've 638 * shifted enough address bits. The data-out should be tri-state, 639 * before this, which should translate to a logical one. 640 * 641 * Other ways to do this would be to try to read a register with known 642 * contents with a varying number of address bits, but no such 643 * register seem to be available. The high bits of register 10 are 01 644 * on the 558 and 559, but apparently not on the 557. 645 * 646 * The Linux driver computes a checksum on the EEPROM data, but the 647 * value of this checksum is not very well documented. 648 */ 649 650void 651fxp_autosize_eeprom(struct fxp_softc *sc) 652{ 653 int x; 654 655 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 656 DELAY(40); 657 658 /* Shift in read opcode. */ 659 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 660 661 /* 662 * Shift in address, wait for the dummy zero following a correct 663 * address shift. 664 */ 665 for (x = 1; x <= 8; x++) { 666 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 667 DELAY(40); 668 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 669 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 670 DELAY(40); 671 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 672 FXP_EEPROM_EEDO) == 0) 673 break; 674 DELAY(40); 675 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 676 DELAY(40); 677 } 678 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 679 DELAY(40); 680 if (x != 6 && x != 8) { 681#ifdef DEBUG 682 printf("%s: strange EEPROM size (%d)\n", 683 device_xname(sc->sc_dev), 1 << x); 684#endif 685 } else 686 sc->sc_eeprom_size = x; 687} 688 689/* 690 * Read from the serial EEPROM. Basically, you manually shift in 691 * the read opcode (one bit at a time) and then shift in the address, 692 * and then you shift out the data (all of this one bit at a time). 693 * The word size is 16 bits, so you have to provide the address for 694 * every 16 bits of data. 695 */ 696void 697fxp_read_eeprom(struct fxp_softc *sc, uint16_t *data, int offset, int words) 698{ 699 uint16_t reg; 700 int i, x; 701 702 for (i = 0; i < words; i++) { 703 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 704 705 /* Shift in read opcode. */ 706 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 707 708 /* Shift in address. */ 709 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 710 711 reg = FXP_EEPROM_EECS; 712 data[i] = 0; 713 714 /* Shift out data. */ 715 for (x = 16; x > 0; x--) { 716 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 717 reg | FXP_EEPROM_EESK); 718 DELAY(40); 719 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 720 FXP_EEPROM_EEDO) 721 data[i] |= (1 << (x - 1)); 722 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 723 DELAY(40); 724 } 725 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 726 DELAY(40); 727 } 728} 729 730/* 731 * Write data to the serial EEPROM. 732 */ 733void 734fxp_write_eeprom(struct fxp_softc *sc, uint16_t *data, int offset, int words) 735{ 736 int i, j; 737 738 for (i = 0; i < words; i++) { 739 /* Erase/write enable. */ 740 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 741 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 742 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 743 sc->sc_eeprom_size); 744 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 745 DELAY(4); 746 747 /* Shift in write opcode, address, data. */ 748 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 749 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 750 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 751 fxp_eeprom_shiftin(sc, data[i], 16); 752 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 753 DELAY(4); 754 755 /* Wait for the EEPROM to finish up. */ 756 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 757 DELAY(4); 758 for (j = 0; j < 1000; j++) { 759 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 760 FXP_EEPROM_EEDO) 761 break; 762 DELAY(50); 763 } 764 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 765 DELAY(4); 766 767 /* Erase/write disable. */ 768 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 769 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 770 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 771 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 772 DELAY(4); 773 } 774} 775 776/* 777 * Update the checksum of the EEPROM. 778 */ 779void 780fxp_eeprom_update_cksum(struct fxp_softc *sc) 781{ 782 int i; 783 uint16_t data, cksum; 784 785 cksum = 0; 786 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 787 fxp_read_eeprom(sc, &data, i, 1); 788 cksum += data; 789 } 790 i = (1 << sc->sc_eeprom_size) - 1; 791 cksum = 0xbaba - cksum; 792 fxp_read_eeprom(sc, &data, i, 1); 793 fxp_write_eeprom(sc, &cksum, i, 1); 794 log(LOG_INFO, "%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 795 device_xname(sc->sc_dev), i, data, cksum); 796} 797 798/* 799 * Start packet transmission on the interface. 800 */ 801void 802fxp_start(struct ifnet *ifp) 803{ 804 struct fxp_softc *sc = ifp->if_softc; 805 struct mbuf *m0, *m; 806 struct fxp_txdesc *txd; 807 struct fxp_txsoft *txs; 808 bus_dmamap_t dmamap; 809 int error, lasttx, nexttx, opending, seg, nsegs, len; 810 811 /* 812 * If we want a re-init, bail out now. 813 */ 814 if (sc->sc_flags & FXPF_WANTINIT) { 815 ifp->if_flags |= IFF_OACTIVE; 816 return; 817 } 818 819 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 820 return; 821 822 /* 823 * Remember the previous txpending and the current lasttx. 824 */ 825 opending = sc->sc_txpending; 826 lasttx = sc->sc_txlast; 827 828 /* 829 * Loop through the send queue, setting up transmit descriptors 830 * until we drain the queue, or use up all available transmit 831 * descriptors. 832 */ 833 for (;;) { 834 struct fxp_tbd *tbdp; 835 int csum_flags; 836 837 /* 838 * Grab a packet off the queue. 839 */ 840 IFQ_POLL(&ifp->if_snd, m0); 841 if (m0 == NULL) 842 break; 843 m = NULL; 844 845 if (sc->sc_txpending == FXP_NTXCB - 1) { 846 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 847 break; 848 } 849 850 /* 851 * Get the next available transmit descriptor. 852 */ 853 nexttx = FXP_NEXTTX(sc->sc_txlast); 854 txd = FXP_CDTX(sc, nexttx); 855 txs = FXP_DSTX(sc, nexttx); 856 dmamap = txs->txs_dmamap; 857 858 /* 859 * Load the DMA map. If this fails, the packet either 860 * didn't fit in the allotted number of frags, or we were 861 * short on resources. In this case, we'll copy and try 862 * again. 863 */ 864 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 865 BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0) { 866 MGETHDR(m, M_DONTWAIT, MT_DATA); 867 if (m == NULL) { 868 log(LOG_ERR, "%s: unable to allocate Tx mbuf\n", 869 device_xname(sc->sc_dev)); 870 break; 871 } 872 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 873 if (m0->m_pkthdr.len > MHLEN) { 874 MCLGET(m, M_DONTWAIT); 875 if ((m->m_flags & M_EXT) == 0) { 876 log(LOG_ERR, "%s: unable to allocate " 877 "Tx cluster\n", 878 device_xname(sc->sc_dev)); 879 m_freem(m); 880 break; 881 } 882 } 883 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 884 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 885 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 886 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 887 if (error) { 888 log(LOG_ERR, "%s: unable to load Tx buffer, " 889 "error = %d\n", 890 device_xname(sc->sc_dev), error); 891 break; 892 } 893 } 894 895 IFQ_DEQUEUE(&ifp->if_snd, m0); 896 csum_flags = m0->m_pkthdr.csum_flags; 897 if (m != NULL) { 898 m_freem(m0); 899 m0 = m; 900 } 901 902 /* Initialize the fraglist. */ 903 tbdp = txd->txd_tbd; 904 len = m0->m_pkthdr.len; 905 nsegs = dmamap->dm_nsegs; 906 if (sc->sc_flags & FXPF_EXT_RFA) 907 tbdp++; 908 for (seg = 0; seg < nsegs; seg++) { 909 tbdp[seg].tb_addr = 910 htole32(dmamap->dm_segs[seg].ds_addr); 911 tbdp[seg].tb_size = 912 htole32(dmamap->dm_segs[seg].ds_len); 913 } 914 if (__predict_false(len <= FXP_IP4CSUMTX_PADLEN && 915 (csum_flags & M_CSUM_IPv4) != 0)) { 916 /* 917 * Pad short packets to avoid ip4csum-tx bug. 918 * 919 * XXX Should we still consider if such short 920 * (36 bytes or less) packets might already 921 * occupy FXP_IPCB_NTXSEG (15) fragments here? 922 */ 923 KASSERT(nsegs < FXP_IPCB_NTXSEG); 924 nsegs++; 925 tbdp[seg].tb_addr = htole32(FXP_CDTXPADADDR(sc)); 926 tbdp[seg].tb_size = 927 htole32(FXP_IP4CSUMTX_PADLEN + 1 - len); 928 } 929 930 /* Sync the DMA map. */ 931 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 932 BUS_DMASYNC_PREWRITE); 933 934 /* 935 * Store a pointer to the packet so we can free it later. 936 */ 937 txs->txs_mbuf = m0; 938 939 /* 940 * Initialize the transmit descriptor. 941 */ 942 /* BIG_ENDIAN: no need to swap to store 0 */ 943 txd->txd_txcb.cb_status = 0; 944 txd->txd_txcb.cb_command = 945 sc->sc_txcmd | htole16(FXP_CB_COMMAND_SF); 946 txd->txd_txcb.tx_threshold = tx_threshold; 947 txd->txd_txcb.tbd_number = nsegs; 948 949 KASSERT((csum_flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) == 0); 950 if (sc->sc_flags & FXPF_EXT_RFA) { 951 struct fxp_ipcb *ipcb; 952 /* 953 * Deal with TCP/IP checksum offload. Note that 954 * in order for TCP checksum offload to work, 955 * the pseudo header checksum must have already 956 * been computed and stored in the checksum field 957 * in the TCP header. The stack should have 958 * already done this for us. 959 */ 960 ipcb = &txd->txd_u.txdu_ipcb; 961 memset(ipcb, 0, sizeof(*ipcb)); 962 /* 963 * always do hardware parsing. 964 */ 965 ipcb->ipcb_ip_activation_high = 966 FXP_IPCB_HARDWAREPARSING_ENABLE; 967 /* 968 * ip checksum offloading. 969 */ 970 if (csum_flags & M_CSUM_IPv4) { 971 ipcb->ipcb_ip_schedule |= 972 FXP_IPCB_IP_CHECKSUM_ENABLE; 973 } 974 /* 975 * TCP/UDP checksum offloading. 976 */ 977 if (csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 978 ipcb->ipcb_ip_schedule |= 979 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 980 } 981 982 /* 983 * request VLAN tag insertion if needed. 984 */ 985 if (vlan_has_tag(m0)) { 986 ipcb->ipcb_vlan_id = htobe16(vlan_get_tag(m0)); 987 ipcb->ipcb_ip_activation_high |= 988 FXP_IPCB_INSERTVLAN_ENABLE; 989 } 990 } else { 991 KASSERT((csum_flags & 992 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) == 0); 993 } 994 995 FXP_CDTXSYNC(sc, nexttx, 996 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 997 998 /* Advance the tx pointer. */ 999 sc->sc_txpending++; 1000 sc->sc_txlast = nexttx; 1001 1002 /* 1003 * Pass packet to bpf if there is a listener. 1004 */ 1005 bpf_mtap(ifp, m0, BPF_D_OUT); 1006 } 1007 1008 if (sc->sc_txpending == FXP_NTXCB - 1) { 1009 /* No more slots; notify upper layer. */ 1010 ifp->if_flags |= IFF_OACTIVE; 1011 } 1012 1013 if (sc->sc_txpending != opending) { 1014 /* 1015 * We enqueued packets. If the transmitter was idle, 1016 * reset the txdirty pointer. 1017 */ 1018 if (opending == 0) 1019 sc->sc_txdirty = FXP_NEXTTX(lasttx); 1020 1021 /* 1022 * Cause the chip to interrupt and suspend command 1023 * processing once the last packet we've enqueued 1024 * has been transmitted. 1025 * 1026 * To avoid a race between updating status bits 1027 * by the fxp chip and clearing command bits 1028 * by this function on machines which don't have 1029 * atomic methods to clear/set bits in memory 1030 * smaller than 32bits (both cb_status and cb_command 1031 * members are uint16_t and in the same 32bit word), 1032 * we have to prepare a dummy TX descriptor which has 1033 * NOP command and just causes a TX completion interrupt. 1034 */ 1035 sc->sc_txpending++; 1036 sc->sc_txlast = FXP_NEXTTX(sc->sc_txlast); 1037 txd = FXP_CDTX(sc, sc->sc_txlast); 1038 /* BIG_ENDIAN: no need to swap to store 0 */ 1039 txd->txd_txcb.cb_status = 0; 1040 txd->txd_txcb.cb_command = htole16(FXP_CB_COMMAND_NOP | 1041 FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 1042 FXP_CDTXSYNC(sc, sc->sc_txlast, 1043 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1044 1045 /* 1046 * The entire packet chain is set up. Clear the suspend bit 1047 * on the command prior to the first packet we set up. 1048 */ 1049 FXP_CDTXSYNC(sc, lasttx, 1050 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1051 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 1052 htole16(~FXP_CB_COMMAND_S); 1053 FXP_CDTXSYNC(sc, lasttx, 1054 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1055 1056 /* 1057 * Issue a Resume command in case the chip was suspended. 1058 */ 1059 fxp_scb_wait(sc); 1060 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1061 1062 /* Set a watchdog timer in case the chip flakes out. */ 1063 ifp->if_timer = 5; 1064 } 1065} 1066 1067/* 1068 * Process interface interrupts. 1069 */ 1070int 1071fxp_intr(void *arg) 1072{ 1073 struct fxp_softc *sc = arg; 1074 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1075 bus_dmamap_t rxmap; 1076 int claimed = 0, rnr; 1077 uint8_t statack, rndstat = 0; 1078 1079 if (!device_is_active(sc->sc_dev) || sc->sc_enabled == 0) 1080 return (0); 1081 /* 1082 * If the interface isn't running, don't try to 1083 * service the interrupt.. just ack it and bail. 1084 */ 1085 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1086 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1087 if (statack) { 1088 claimed = 1; 1089 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1090 } 1091 return (claimed); 1092 } 1093 1094 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1095 rndstat = statack; 1096 claimed = 1; 1097 1098 /* 1099 * First ACK all the interrupts in this pass. 1100 */ 1101 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1102 1103 /* 1104 * Process receiver interrupts. If a no-resource (RNR) 1105 * condition exists, get whatever packets we can and 1106 * re-start the receiver. 1107 */ 1108 rnr = (statack & (FXP_SCB_STATACK_RNR | FXP_SCB_STATACK_SWI)) ? 1109 1 : 0; 1110 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR | 1111 FXP_SCB_STATACK_SWI)) { 1112 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1113 rnr |= fxp_rxintr(sc); 1114 } 1115 1116 /* 1117 * Free any finished transmit mbuf chains. 1118 */ 1119 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1120 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1121 fxp_txintr(sc); 1122 1123 /* 1124 * Try to get more packets going. 1125 */ 1126 if_schedule_deferred_start(ifp); 1127 1128 if (sc->sc_txpending == 0) { 1129 /* 1130 * Tell them that they can re-init now. 1131 */ 1132 if (sc->sc_flags & FXPF_WANTINIT) 1133 wakeup(sc); 1134 } 1135 } 1136 1137 if (rnr) { 1138 fxp_scb_wait(sc); 1139 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_ABORT); 1140 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1141 fxp_scb_wait(sc); 1142 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1143 rxmap->dm_segs[0].ds_addr + 1144 RFA_ALIGNMENT_FUDGE); 1145 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1146 } 1147 } 1148 1149 if (claimed) 1150 rnd_add_uint32(&sc->rnd_source, rndstat); 1151 return (claimed); 1152} 1153 1154/* 1155 * Handle transmit completion interrupts. 1156 */ 1157void 1158fxp_txintr(struct fxp_softc *sc) 1159{ 1160 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1161 struct fxp_txdesc *txd; 1162 struct fxp_txsoft *txs; 1163 int i; 1164 uint16_t txstat; 1165 1166 ifp->if_flags &= ~IFF_OACTIVE; 1167 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1168 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1169 txd = FXP_CDTX(sc, i); 1170 txs = FXP_DSTX(sc, i); 1171 1172 FXP_CDTXSYNC(sc, i, 1173 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1174 1175 /* skip dummy NOP TX descriptor */ 1176 if ((le16toh(txd->txd_txcb.cb_command) & FXP_CB_COMMAND_CMD) 1177 == FXP_CB_COMMAND_NOP) 1178 continue; 1179 1180 txstat = le16toh(txd->txd_txcb.cb_status); 1181 1182 if ((txstat & FXP_CB_STATUS_C) == 0) 1183 break; 1184 1185 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1186 0, txs->txs_dmamap->dm_mapsize, 1187 BUS_DMASYNC_POSTWRITE); 1188 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1189 m_freem(txs->txs_mbuf); 1190 txs->txs_mbuf = NULL; 1191 } 1192 1193 /* Update the dirty transmit buffer pointer. */ 1194 sc->sc_txdirty = i; 1195 1196 /* 1197 * Cancel the watchdog timer if there are no pending 1198 * transmissions. 1199 */ 1200 if (sc->sc_txpending == 0) 1201 ifp->if_timer = 0; 1202} 1203 1204/* 1205 * fxp_rx_hwcksum: check status of H/W offloading for received packets. 1206 */ 1207 1208void 1209fxp_rx_hwcksum(struct fxp_softc *sc, struct mbuf *m, const struct fxp_rfa *rfa, 1210 u_int len) 1211{ 1212 uint32_t csum_data; 1213 int csum_flags; 1214 1215 /* 1216 * check H/W Checksumming. 1217 */ 1218 1219 csum_flags = 0; 1220 csum_data = 0; 1221 1222 if ((sc->sc_flags & FXPF_EXT_RFA) != 0) { 1223 uint8_t csum_stat; 1224 1225 csum_stat = rfa->cksum_stat; 1226 if ((rfa->rfa_status & htole16(FXP_RFA_STATUS_PARSE)) == 0) 1227 goto out; 1228 1229 if (csum_stat & FXP_RFDX_CS_IP_CSUM_BIT_VALID) { 1230 csum_flags = M_CSUM_IPv4; 1231 if ((csum_stat & FXP_RFDX_CS_IP_CSUM_VALID) == 0) 1232 csum_flags |= M_CSUM_IPv4_BAD; 1233 } 1234 1235 if (csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) { 1236 csum_flags |= (M_CSUM_TCPv4 | M_CSUM_UDPv4); /* XXX */ 1237 if ((csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_VALID) == 0) 1238 csum_flags |= M_CSUM_TCP_UDP_BAD; 1239 } 1240 1241 } else if ((sc->sc_flags & FXPF_82559_RXCSUM) != 0) { 1242 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1243 struct ether_header *eh; 1244 struct ip *ip; 1245 struct udphdr *uh; 1246 u_int hlen, pktlen; 1247 1248 if (len < ETHER_HDR_LEN + sizeof(struct ip)) 1249 goto out; 1250 pktlen = len - ETHER_HDR_LEN; 1251 eh = mtod(m, struct ether_header *); 1252 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1253 goto out; 1254 ip = (struct ip *)((uint8_t *)eh + ETHER_HDR_LEN); 1255 if (ip->ip_v != IPVERSION) 1256 goto out; 1257 1258 hlen = ip->ip_hl << 2; 1259 if (hlen < sizeof(struct ip)) 1260 goto out; 1261 1262 /* 1263 * Bail if too short, has random trailing garbage, truncated, 1264 * fragment, or has ethernet pad. 1265 */ 1266 if (ntohs(ip->ip_len) < hlen || 1267 ntohs(ip->ip_len) != pktlen || 1268 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK)) != 0) 1269 goto out; 1270 1271 switch (ip->ip_p) { 1272 case IPPROTO_TCP: 1273 if ((ifp->if_csum_flags_rx & M_CSUM_TCPv4) == 0 || 1274 pktlen < (hlen + sizeof(struct tcphdr))) 1275 goto out; 1276 csum_flags = 1277 M_CSUM_TCPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 1278 break; 1279 case IPPROTO_UDP: 1280 if ((ifp->if_csum_flags_rx & M_CSUM_UDPv4) == 0 || 1281 pktlen < (hlen + sizeof(struct udphdr))) 1282 goto out; 1283 uh = (struct udphdr *)((uint8_t *)ip + hlen); 1284 if (uh->uh_sum == 0) 1285 goto out; /* no checksum */ 1286 csum_flags = 1287 M_CSUM_UDPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 1288 break; 1289 default: 1290 goto out; 1291 } 1292 1293 /* Extract computed checksum. */ 1294 csum_data = be16dec(mtod(m, uint8_t *) + len); 1295 1296 /* 1297 * The computed checksum includes IP headers, 1298 * so we have to deduct them. 1299 */ 1300#if 0 1301 /* 1302 * But in TCP/UDP layer we can assume the IP header is valid, 1303 * i.e. a sum of the whole IP header should be 0xffff, 1304 * so we don't have to bother to deduct it. 1305 */ 1306 if (hlen > 0) { 1307 uint32_t hsum; 1308 const uint16_t *iphdr; 1309 hsum = 0; 1310 iphdr = (uint16_t *)ip; 1311 1312 while (hlen > 1) { 1313 hsum += ntohs(*iphdr++); 1314 hlen -= sizeof(uint16_t); 1315 } 1316 while (hsum >> 16) 1317 hsum = (hsum >> 16) + (hsum & 0xffff); 1318 1319 csum_data += (uint16_t)~hsum; 1320 1321 while (csum_data >> 16) 1322 csum_data = 1323 (csum_data >> 16) + (csum_data & 0xffff); 1324 } 1325#endif 1326 } 1327 out: 1328 m->m_pkthdr.csum_flags = csum_flags; 1329 m->m_pkthdr.csum_data = csum_data; 1330} 1331 1332/* 1333 * Handle receive interrupts. 1334 */ 1335int 1336fxp_rxintr(struct fxp_softc *sc) 1337{ 1338 struct ethercom *ec = &sc->sc_ethercom; 1339 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1340 struct mbuf *m, *m0; 1341 bus_dmamap_t rxmap; 1342 struct fxp_rfa *rfa; 1343 int rnr; 1344 uint16_t len, rxstat; 1345 1346 rnr = 0; 1347 1348 for (;;) { 1349 m = sc->sc_rxq.ifq_head; 1350 rfa = FXP_MTORFA(m); 1351 rxmap = M_GETCTX(m, bus_dmamap_t); 1352 1353 FXP_RFASYNC(sc, m, 1354 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1355 1356 rxstat = le16toh(rfa->rfa_status); 1357 1358 if ((rxstat & FXP_RFA_STATUS_RNR) != 0) 1359 rnr = 1; 1360 1361 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1362 /* 1363 * We have processed all of the 1364 * receive buffers. 1365 */ 1366 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1367 return rnr; 1368 } 1369 1370 IF_DEQUEUE(&sc->sc_rxq, m); 1371 1372 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1373 1374 len = le16toh(rfa->actual_size) & 1375 (m->m_ext.ext_size - 1); 1376 if ((sc->sc_flags & FXPF_82559_RXCSUM) != 0) { 1377 /* Adjust for appended checksum bytes. */ 1378 len -= sizeof(uint16_t); 1379 } 1380 1381 if (len < sizeof(struct ether_header)) { 1382 /* 1383 * Runt packet; drop it now. 1384 */ 1385 FXP_INIT_RFABUF(sc, m); 1386 continue; 1387 } 1388 1389 /* 1390 * If support for 802.1Q VLAN sized frames is 1391 * enabled, we need to do some additional error 1392 * checking (as we are saving bad frames, in 1393 * order to receive the larger ones). 1394 */ 1395 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1396 (rxstat & (FXP_RFA_STATUS_OVERRUN | 1397 FXP_RFA_STATUS_RNR | 1398 FXP_RFA_STATUS_ALIGN | 1399 FXP_RFA_STATUS_CRC)) != 0) { 1400 FXP_INIT_RFABUF(sc, m); 1401 continue; 1402 } 1403 1404 /* 1405 * check VLAN tag stripping. 1406 */ 1407 if ((sc->sc_flags & FXPF_EXT_RFA) != 0 && 1408 (rfa->rfa_status & htole16(FXP_RFA_STATUS_VLAN)) != 0) 1409 vlan_set_tag(m, be16toh(rfa->vlan_id)); 1410 1411 /* Do checksum checking. */ 1412 if ((ifp->if_csum_flags_rx & 1413 (M_CSUM_TCPv4 | M_CSUM_UDPv4)) != 0) 1414 fxp_rx_hwcksum(sc, m, rfa, len); 1415 1416 /* 1417 * If the packet is small enough to fit in a 1418 * single header mbuf, allocate one and copy 1419 * the data into it. This greatly reduces 1420 * memory consumption when we receive lots 1421 * of small packets. 1422 * 1423 * Otherwise, we add a new buffer to the receive 1424 * chain. If this fails, we drop the packet and 1425 * recycle the old buffer. 1426 */ 1427 if (fxp_copy_small != 0 && len <= MHLEN) { 1428 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1429 if (m0 == NULL) 1430 goto dropit; 1431 MCLAIM(m0, &sc->sc_ethercom.ec_rx_mowner); 1432 memcpy(mtod(m0, void *), 1433 mtod(m, void *), len); 1434 m0->m_pkthdr.csum_flags = m->m_pkthdr.csum_flags; 1435 m0->m_pkthdr.csum_data = m->m_pkthdr.csum_data; 1436 FXP_INIT_RFABUF(sc, m); 1437 m = m0; 1438 } else { 1439 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1440 dropit: 1441 if_statinc(ifp, if_ierrors); 1442 FXP_INIT_RFABUF(sc, m); 1443 continue; 1444 } 1445 } 1446 1447 m_set_rcvif(m, ifp); 1448 m->m_pkthdr.len = m->m_len = len; 1449 1450 /* Pass it on. */ 1451 if_percpuq_enqueue(ifp->if_percpuq, m); 1452 } 1453} 1454 1455/* 1456 * Update packet in/out/collision statistics. The i82557 doesn't 1457 * allow you to access these counters without doing a fairly 1458 * expensive DMA to get _all_ of the statistics it maintains, so 1459 * we do this operation here only once per second. The statistics 1460 * counters in the kernel are updated from the previous dump-stats 1461 * DMA and then a new dump-stats DMA is started. The on-chip 1462 * counters are zeroed when the DMA completes. If we can't start 1463 * the DMA immediately, we don't wait - we just prepare to read 1464 * them again next time. 1465 */ 1466void 1467fxp_tick(void *arg) 1468{ 1469 struct fxp_softc *sc = arg; 1470 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1471 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1472 int s; 1473 1474 if (!device_is_active(sc->sc_dev)) 1475 return; 1476 1477 s = splnet(); 1478 1479 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 1480 1481 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1482 1483 if_statadd_ref(ifp, nsr, if_opackets, le32toh(sp->tx_good)); 1484 if_statadd_ref(ifp, nsr, if_collisions, 1485 le32toh(sp->tx_total_collisions)); 1486 if (sp->rx_good) { 1487 sc->sc_rxidle = 0; 1488 } else if (sc->sc_flags & FXPF_RECV_WORKAROUND) { 1489 sc->sc_rxidle++; 1490 } 1491 if_statadd_ref(ifp, nsr, if_ierrors, 1492 le32toh(sp->rx_crc_errors) + 1493 le32toh(sp->rx_alignment_errors) + 1494 le32toh(sp->rx_rnr_errors) + 1495 le32toh(sp->rx_overrun_errors)); 1496 /* 1497 * If any transmit underruns occurred, bump up the transmit 1498 * threshold by another 512 bytes (64 * 8). 1499 */ 1500 if (sp->tx_underruns) { 1501 if_statadd_ref(ifp, nsr, if_oerrors, 1502 le32toh(sp->tx_underruns)); 1503 if (tx_threshold < 192) 1504 tx_threshold += 64; 1505 } 1506#ifdef FXP_EVENT_COUNTERS 1507 if (sc->sc_flags & FXPF_FC) { 1508 sc->sc_ev_txpause.ev_count += sp->tx_pauseframes; 1509 sc->sc_ev_rxpause.ev_count += sp->rx_pauseframes; 1510 } 1511#endif 1512 1513 IF_STAT_PUTREF(ifp); 1514 1515 /* 1516 * If we haven't received any packets in FXP_MAX_RX_IDLE seconds, 1517 * then assume the receiver has locked up and attempt to clear 1518 * the condition by reprogramming the multicast filter (actually, 1519 * resetting the interface). This is a work-around for a bug in 1520 * the 82557 where the receiver locks up if it gets certain types 1521 * of garbage in the synchronization bits prior to the packet header. 1522 * This bug is supposed to only occur in 10Mbps mode, but has been 1523 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1524 * speed transition). 1525 */ 1526 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1527 (void) fxp_init(ifp); 1528 splx(s); 1529 return; 1530 } 1531 /* 1532 * If there is no pending command, start another stats 1533 * dump. Otherwise punt for now. 1534 */ 1535 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1536 /* 1537 * Start another stats dump. 1538 */ 1539 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1540 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1541 } else { 1542 /* 1543 * A previous command is still waiting to be accepted. 1544 * Just zero our copy of the stats and wait for the 1545 * next timer event to update them. 1546 */ 1547 /* BIG_ENDIAN: no swap required to store 0 */ 1548 sp->tx_good = 0; 1549 sp->tx_underruns = 0; 1550 sp->tx_total_collisions = 0; 1551 1552 sp->rx_good = 0; 1553 sp->rx_crc_errors = 0; 1554 sp->rx_alignment_errors = 0; 1555 sp->rx_rnr_errors = 0; 1556 sp->rx_overrun_errors = 0; 1557 if (sc->sc_flags & FXPF_FC) { 1558 sp->tx_pauseframes = 0; 1559 sp->rx_pauseframes = 0; 1560 } 1561 } 1562 1563 if (sc->sc_flags & FXPF_MII) { 1564 /* Tick the MII clock. */ 1565 mii_tick(&sc->sc_mii); 1566 } 1567 1568 splx(s); 1569 1570 /* 1571 * Schedule another timeout one second from now. 1572 */ 1573 callout_schedule(&sc->sc_callout, hz); 1574} 1575 1576/* 1577 * Drain the receive queue. 1578 */ 1579void 1580fxp_rxdrain(struct fxp_softc *sc) 1581{ 1582 bus_dmamap_t rxmap; 1583 struct mbuf *m; 1584 1585 for (;;) { 1586 IF_DEQUEUE(&sc->sc_rxq, m); 1587 if (m == NULL) 1588 break; 1589 rxmap = M_GETCTX(m, bus_dmamap_t); 1590 bus_dmamap_unload(sc->sc_dmat, rxmap); 1591 FXP_RXMAP_PUT(sc, rxmap); 1592 m_freem(m); 1593 } 1594} 1595 1596/* 1597 * Stop the interface. Cancels the statistics updater and resets 1598 * the interface. 1599 */ 1600void 1601fxp_stop(struct ifnet *ifp, int disable) 1602{ 1603 struct fxp_softc *sc = ifp->if_softc; 1604 struct fxp_txsoft *txs; 1605 int i; 1606 1607 /* 1608 * Turn down interface (done early to avoid bad interactions 1609 * between panics, shutdown hooks, and the watchdog timer) 1610 */ 1611 ifp->if_timer = 0; 1612 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1613 1614 /* 1615 * Cancel stats updater. 1616 */ 1617 callout_stop(&sc->sc_callout); 1618 if (sc->sc_flags & FXPF_MII) { 1619 /* Down the MII. */ 1620 mii_down(&sc->sc_mii); 1621 } 1622 1623 /* 1624 * Issue software reset. This unloads any microcode that 1625 * might already be loaded. 1626 */ 1627 sc->sc_flags &= ~FXPF_UCODE_LOADED; 1628 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1629 DELAY(50); 1630 1631 /* 1632 * Release any xmit buffers. 1633 */ 1634 for (i = 0; i < FXP_NTXCB; i++) { 1635 txs = FXP_DSTX(sc, i); 1636 if (txs->txs_mbuf != NULL) { 1637 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1638 m_freem(txs->txs_mbuf); 1639 txs->txs_mbuf = NULL; 1640 } 1641 } 1642 sc->sc_txpending = 0; 1643 1644 if (disable) { 1645 fxp_rxdrain(sc); 1646 fxp_disable(sc); 1647 } 1648 1649} 1650 1651/* 1652 * Watchdog/transmission transmit timeout handler. Called when a 1653 * transmission is started on the interface, but no interrupt is 1654 * received before the timeout. This usually indicates that the 1655 * card has wedged for some reason. 1656 */ 1657void 1658fxp_watchdog(struct ifnet *ifp) 1659{ 1660 struct fxp_softc *sc = ifp->if_softc; 1661 1662 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1663 if_statinc(ifp, if_oerrors); 1664 1665 (void) fxp_init(ifp); 1666} 1667 1668/* 1669 * Initialize the interface. Must be called at splnet(). 1670 */ 1671int 1672fxp_init(struct ifnet *ifp) 1673{ 1674 struct fxp_softc *sc = ifp->if_softc; 1675 struct fxp_cb_config *cbp; 1676 struct fxp_cb_ias *cb_ias; 1677 struct fxp_txdesc *txd; 1678 bus_dmamap_t rxmap; 1679 int i, prm, save_bf, lrxen, vlan_drop, allm, error = 0; 1680 uint16_t status; 1681 1682 if ((error = fxp_enable(sc)) != 0) 1683 goto out; 1684 1685 /* 1686 * Cancel any pending I/O 1687 */ 1688 fxp_stop(ifp, 0); 1689 1690 /* 1691 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1692 * flag, and this prevents the MII from detaching resulting in 1693 * a panic. The flags field should perhaps be split in runtime 1694 * flags and more static information. For now, just clear the 1695 * only other flag set. 1696 */ 1697 1698 sc->sc_flags &= ~FXPF_WANTINIT; 1699 1700 /* 1701 * Initialize base of CBL and RFA memory. Loading with zero 1702 * sets it up for regular linear addressing. 1703 */ 1704 fxp_scb_wait(sc); 1705 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1706 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1707 1708 fxp_scb_wait(sc); 1709 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1710 1711 /* 1712 * Initialize the multicast filter. Do this now, since we might 1713 * have to setup the config block differently. 1714 */ 1715 fxp_mc_setup(sc); 1716 1717 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1718 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1719 1720 /* 1721 * In order to support receiving 802.1Q VLAN frames, we have to 1722 * enable "save bad frames", since they are 4 bytes larger than 1723 * the normal Ethernet maximum frame length. On i82558 and later, 1724 * we have a better mechanism for this. 1725 */ 1726 save_bf = 0; 1727 lrxen = 0; 1728 vlan_drop = 0; 1729 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1730 if (sc->sc_rev < FXP_REV_82558_A4) 1731 save_bf = 1; 1732 else 1733 lrxen = 1; 1734 if (sc->sc_rev >= FXP_REV_82550) 1735 vlan_drop = 1; 1736 } 1737 1738 /* 1739 * Initialize base of dump-stats buffer. 1740 */ 1741 fxp_scb_wait(sc); 1742 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1743 sc->sc_cddma + FXP_CDSTATSOFF); 1744 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1745 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1746 1747 cbp = &sc->sc_control_data->fcd_configcb; 1748 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1749 1750 /* 1751 * Load microcode for this controller. 1752 */ 1753 fxp_load_ucode(sc); 1754 1755 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK1)) 1756 sc->sc_flags |= FXPF_RECV_WORKAROUND; 1757 else 1758 sc->sc_flags &= ~FXPF_RECV_WORKAROUND; 1759 1760 /* 1761 * This copy is kind of disgusting, but there are a bunch of must be 1762 * zero and must be one bits in this structure and this is the easiest 1763 * way to initialize them all to proper values. 1764 */ 1765 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1766 1767 /* BIG_ENDIAN: no need to swap to store 0 */ 1768 cbp->cb_status = 0; 1769 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1770 FXP_CB_COMMAND_EL); 1771 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1772 cbp->link_addr = 0xffffffff; /* (no) next command */ 1773 /* bytes in config block */ 1774 cbp->byte_count = (sc->sc_flags & FXPF_EXT_RFA) ? 1775 FXP_EXT_CONFIG_LEN : FXP_CONFIG_LEN; 1776 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1777 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1778 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1779 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1780 cbp->type_enable = 0; /* actually reserved */ 1781 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1782 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1783 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1784 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1785 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1786 cbp->late_scb = 0; /* (don't) defer SCB update */ 1787 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1788 cbp->ci_int = 1; /* interrupt on CU idle */ 1789 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1790 cbp->ext_stats_dis = 1; /* disable extended counters */ 1791 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1792 cbp->save_bf = save_bf;/* save bad frames */ 1793 cbp->disc_short_rx = !prm; /* discard short packets */ 1794 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1795 cbp->ext_rfa = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1796 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1797 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1798 /* interface mode */ 1799 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1800 cbp->csma_dis = 0; /* (don't) disable link */ 1801 cbp->tcp_udp_cksum = (sc->sc_flags & FXPF_82559_RXCSUM) ? 1 : 0; 1802 /* (don't) enable RX checksum */ 1803 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1804 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1805 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1806 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1807 cbp->nsai = 1; /* (don't) disable source addr insert */ 1808 cbp->preamble_length = 2; /* (7 byte) preamble */ 1809 cbp->loopback = 0; /* (don't) loopback */ 1810 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1811 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1812 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1813 cbp->promiscuous = prm; /* promiscuous mode */ 1814 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1815 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1816 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1817 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1818 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1819 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1820 cbp->padding = 1; /* (do) pad short tx packets */ 1821 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1822 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1823 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1824 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1825 /* must set wake_en in PMCSR also */ 1826 cbp->force_fdx = 0; /* (don't) force full duplex */ 1827 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1828 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1829 cbp->mc_all = allm; /* accept all multicasts */ 1830 cbp->ext_rx_mode = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1831 cbp->vlan_drop_en = vlan_drop; 1832 1833 if (!(sc->sc_flags & FXPF_FC)) { 1834 /* 1835 * The i82557 has no hardware flow control, the values 1836 * here are the defaults for the chip. 1837 */ 1838 cbp->fc_delay_lsb = 0; 1839 cbp->fc_delay_msb = 0x40; 1840 cbp->pri_fc_thresh = 3; 1841 cbp->tx_fc_dis = 0; 1842 cbp->rx_fc_restop = 0; 1843 cbp->rx_fc_restart = 0; 1844 cbp->fc_filter = 0; 1845 cbp->pri_fc_loc = 1; 1846 } else { 1847 cbp->fc_delay_lsb = 0x1f; 1848 cbp->fc_delay_msb = 0x01; 1849 cbp->pri_fc_thresh = 3; 1850 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1851 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1852 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1853 cbp->fc_filter = !prm; /* drop FC frames to host */ 1854 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1855 cbp->ext_stats_dis = 0; /* enable extended stats */ 1856 } 1857 1858 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1859 1860 /* 1861 * Start the config command/DMA. 1862 */ 1863 fxp_scb_wait(sc); 1864 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1865 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1866 /* ...and wait for it to complete. */ 1867 for (i = 1000; i > 0; i--) { 1868 FXP_CDCONFIGSYNC(sc, 1869 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1870 status = le16toh(cbp->cb_status); 1871 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD); 1872 if ((status & FXP_CB_STATUS_C) != 0) 1873 break; 1874 DELAY(1); 1875 } 1876 if (i == 0) { 1877 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1878 device_xname(sc->sc_dev), __LINE__); 1879 return (ETIMEDOUT); 1880 } 1881 1882 /* 1883 * Initialize the station address. 1884 */ 1885 cb_ias = &sc->sc_control_data->fcd_iascb; 1886 /* BIG_ENDIAN: no need to swap to store 0 */ 1887 cb_ias->cb_status = 0; 1888 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1889 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1890 cb_ias->link_addr = 0xffffffff; 1891 memcpy(cb_ias->macaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1892 1893 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1894 1895 /* 1896 * Start the IAS (Individual Address Setup) command/DMA. 1897 */ 1898 fxp_scb_wait(sc); 1899 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1900 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1901 /* ...and wait for it to complete. */ 1902 for (i = 1000; i > 0; i--) { 1903 FXP_CDIASSYNC(sc, 1904 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1905 status = le16toh(cb_ias->cb_status); 1906 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD); 1907 if ((status & FXP_CB_STATUS_C) != 0) 1908 break; 1909 DELAY(1); 1910 } 1911 if (i == 0) { 1912 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1913 device_xname(sc->sc_dev), __LINE__); 1914 return (ETIMEDOUT); 1915 } 1916 1917 /* 1918 * Initialize the transmit descriptor ring. txlast is initialized 1919 * to the end of the list so that it will wrap around to the first 1920 * descriptor when the first packet is transmitted. 1921 */ 1922 for (i = 0; i < FXP_NTXCB; i++) { 1923 txd = FXP_CDTX(sc, i); 1924 memset(txd, 0, sizeof(*txd)); 1925 txd->txd_txcb.cb_command = 1926 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1927 txd->txd_txcb.link_addr = 1928 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1929 if (sc->sc_flags & FXPF_EXT_TXCB) 1930 txd->txd_txcb.tbd_array_addr = 1931 htole32(FXP_CDTBDADDR(sc, i) + 1932 (2 * sizeof(struct fxp_tbd))); 1933 else 1934 txd->txd_txcb.tbd_array_addr = 1935 htole32(FXP_CDTBDADDR(sc, i)); 1936 FXP_CDTXSYNC(sc, i, 1937 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1938 } 1939 sc->sc_txpending = 0; 1940 sc->sc_txdirty = 0; 1941 sc->sc_txlast = FXP_NTXCB - 1; 1942 1943 /* 1944 * Initialize the receive buffer list. 1945 */ 1946 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1947 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1948 rxmap = FXP_RXMAP_GET(sc); 1949 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1950 log(LOG_ERR, "%s: unable to allocate or map rx " 1951 "buffer %d, error = %d\n", 1952 device_xname(sc->sc_dev), 1953 sc->sc_rxq.ifq_len, error); 1954 /* 1955 * XXX Should attempt to run with fewer receive 1956 * XXX buffers instead of just failing. 1957 */ 1958 FXP_RXMAP_PUT(sc, rxmap); 1959 fxp_rxdrain(sc); 1960 goto out; 1961 } 1962 } 1963 sc->sc_rxidle = 0; 1964 1965 /* 1966 * Give the transmit ring to the chip. We do this by pointing 1967 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1968 * issuing a start command. It will execute the NOP and then 1969 * suspend, pointing at the first descriptor. 1970 */ 1971 fxp_scb_wait(sc); 1972 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1973 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1974 1975 /* 1976 * Initialize receiver buffer area - RFA. 1977 */ 1978#if 0 /* initialization will be done by FXP_SCB_INTRCNTL_REQUEST_SWI later */ 1979 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1980 fxp_scb_wait(sc); 1981 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1982 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1983 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1984#endif 1985 1986 if (sc->sc_flags & FXPF_MII) { 1987 /* 1988 * Set current media. 1989 */ 1990 if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0) 1991 goto out; 1992 } 1993 1994 /* 1995 * ...all done! 1996 */ 1997 ifp->if_flags |= IFF_RUNNING; 1998 ifp->if_flags &= ~IFF_OACTIVE; 1999 2000 /* 2001 * Request a software generated interrupt that will be used to 2002 * (re)start the RU processing. If we direct the chip to start 2003 * receiving from the start of queue now, instead of letting the 2004 * interrupt handler first process all received packets, we run 2005 * the risk of having it overwrite mbuf clusters while they are 2006 * being processed or after they have been returned to the pool. 2007 */ 2008 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTRCNTL_REQUEST_SWI); 2009 2010 /* 2011 * Start the one second timer. 2012 */ 2013 callout_schedule(&sc->sc_callout, hz); 2014 2015 /* 2016 * Attempt to start output on the interface. 2017 */ 2018 fxp_start(ifp); 2019 2020 out: 2021 if (error) { 2022 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2023 ifp->if_timer = 0; 2024 log(LOG_ERR, "%s: interface not running\n", 2025 device_xname(sc->sc_dev)); 2026 } 2027 return (error); 2028} 2029 2030/* 2031 * Notify the world which media we're using. 2032 */ 2033void 2034fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2035{ 2036 struct fxp_softc *sc = ifp->if_softc; 2037 2038 if (sc->sc_enabled == 0) { 2039 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 2040 ifmr->ifm_status = 0; 2041 return; 2042 } 2043 2044 ether_mediastatus(ifp, ifmr); 2045} 2046 2047int 2048fxp_80c24_mediachange(struct ifnet *ifp) 2049{ 2050 2051 /* Nothing to do here. */ 2052 return (0); 2053} 2054 2055void 2056fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2057{ 2058 struct fxp_softc *sc = ifp->if_softc; 2059 2060 /* 2061 * Media is currently-selected media. We cannot determine 2062 * the link status. 2063 */ 2064 ifmr->ifm_status = 0; 2065 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 2066} 2067 2068/* 2069 * Add a buffer to the end of the RFA buffer list. 2070 * Return 0 if successful, error code on failure. 2071 * 2072 * The RFA struct is stuck at the beginning of mbuf cluster and the 2073 * data pointer is fixed up to point just past it. 2074 */ 2075int 2076fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 2077{ 2078 struct mbuf *m; 2079 int error; 2080 2081 MGETHDR(m, M_DONTWAIT, MT_DATA); 2082 if (m == NULL) 2083 return (ENOBUFS); 2084 2085 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2086 MCLGET(m, M_DONTWAIT); 2087 if ((m->m_flags & M_EXT) == 0) { 2088 m_freem(m); 2089 return (ENOBUFS); 2090 } 2091 2092 if (unload) 2093 bus_dmamap_unload(sc->sc_dmat, rxmap); 2094 2095 M_SETCTX(m, rxmap); 2096 2097 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2098 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, 2099 BUS_DMA_READ | BUS_DMA_NOWAIT); 2100 if (error) { 2101 /* XXX XXX XXX */ 2102 aprint_error_dev(sc->sc_dev, 2103 "can't load rx DMA map %d, error = %d\n", 2104 sc->sc_rxq.ifq_len, error); 2105 panic("fxp_add_rfabuf"); 2106 } 2107 2108 FXP_INIT_RFABUF(sc, m); 2109 2110 return (0); 2111} 2112 2113int 2114fxp_mdi_read(device_t self, int phy, int reg, uint16_t *value) 2115{ 2116 struct fxp_softc *sc = device_private(self); 2117 int count = 10000; 2118 uint32_t data; 2119 2120 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2121 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2122 2123 while (((data = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 2124 0x10000000) == 0 && count--) 2125 DELAY(10); 2126 2127 if (count <= 0) { 2128 log(LOG_WARNING, 2129 "%s: fxp_mdi_read: timed out\n", device_xname(self)); 2130 return ETIMEDOUT; 2131 } 2132 2133 *value = data & 0xffff; 2134 return 0; 2135} 2136 2137void 2138fxp_statchg(struct ifnet *ifp) 2139{ 2140 2141 /* Nothing to do. */ 2142} 2143 2144int 2145fxp_mdi_write(device_t self, int phy, int reg, uint16_t value) 2146{ 2147 struct fxp_softc *sc = device_private(self); 2148 int count = 10000; 2149 2150 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2151 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | value); 2152 2153 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2154 count--) 2155 DELAY(10); 2156 2157 if (count <= 0) { 2158 log(LOG_WARNING, 2159 "%s: fxp_mdi_write: timed out\n", device_xname(self)); 2160 return ETIMEDOUT; 2161 } 2162 2163 return 0; 2164} 2165 2166int 2167fxp_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2168{ 2169 struct fxp_softc *sc = ifp->if_softc; 2170 int s, error; 2171 2172 s = splnet(); 2173 2174 switch (cmd) { 2175 default: 2176 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 2177 break; 2178 2179 error = 0; 2180 2181 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2182 ; 2183 else if (ifp->if_flags & IFF_RUNNING) { 2184 /* 2185 * Multicast list has changed; set the 2186 * hardware filter accordingly. 2187 */ 2188 while (sc->sc_txpending) { 2189 sc->sc_flags |= FXPF_WANTINIT; 2190 tsleep(sc, PSOCK, "fxp_init", 0); 2191 } 2192 error = fxp_init(ifp); 2193 } 2194 break; 2195 } 2196 2197 /* Try to get more packets going. */ 2198 if (sc->sc_enabled) 2199 fxp_start(ifp); 2200 2201 splx(s); 2202 return (error); 2203} 2204 2205/* 2206 * Program the multicast filter. 2207 * 2208 * This function must be called at splnet(). 2209 */ 2210void 2211fxp_mc_setup(struct fxp_softc *sc) 2212{ 2213 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 2214 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2215 struct ethercom *ec = &sc->sc_ethercom; 2216 struct ether_multi *enm; 2217 struct ether_multistep step; 2218 int count, nmcasts; 2219 uint16_t status; 2220 2221#ifdef DIAGNOSTIC 2222 if (sc->sc_txpending) 2223 panic("fxp_mc_setup: pending transmissions"); 2224#endif 2225 2226 2227 if (ifp->if_flags & IFF_PROMISC) { 2228 ifp->if_flags |= IFF_ALLMULTI; 2229 return; 2230 } else { 2231 ifp->if_flags &= ~IFF_ALLMULTI; 2232 } 2233 2234 /* 2235 * Initialize multicast setup descriptor. 2236 */ 2237 nmcasts = 0; 2238 ETHER_LOCK(ec); 2239 ETHER_FIRST_MULTI(step, ec, enm); 2240 while (enm != NULL) { 2241 /* 2242 * Check for too many multicast addresses or if we're 2243 * listening to a range. Either way, we simply have 2244 * to accept all multicasts. 2245 */ 2246 if (nmcasts >= MAXMCADDR || 2247 memcmp(enm->enm_addrlo, enm->enm_addrhi, 2248 ETHER_ADDR_LEN) != 0) { 2249 /* 2250 * Callers of this function must do the 2251 * right thing with this. If we're called 2252 * from outside fxp_init(), the caller must 2253 * detect if the state if IFF_ALLMULTI changes. 2254 * If it does, the caller must then call 2255 * fxp_init(), since allmulti is handled by 2256 * the config block. 2257 */ 2258 ifp->if_flags |= IFF_ALLMULTI; 2259 ETHER_UNLOCK(ec); 2260 return; 2261 } 2262 memcpy(&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 2263 ETHER_ADDR_LEN); 2264 nmcasts++; 2265 ETHER_NEXT_MULTI(step, enm); 2266 } 2267 ETHER_UNLOCK(ec); 2268 2269 /* BIG_ENDIAN: no need to swap to store 0 */ 2270 mcsp->cb_status = 0; 2271 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2272 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 2273 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2274 2275 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2276 2277 /* 2278 * Wait until the command unit is not active. This should never 2279 * happen since nothing is queued, but make sure anyway. 2280 */ 2281 count = 100; 2282 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2283 FXP_SCB_CUS_ACTIVE && --count) 2284 DELAY(1); 2285 if (count == 0) { 2286 log(LOG_WARNING, "%s: line %d: command queue timeout\n", 2287 device_xname(sc->sc_dev), __LINE__); 2288 return; 2289 } 2290 2291 /* 2292 * Start the multicast setup command/DMA. 2293 */ 2294 fxp_scb_wait(sc); 2295 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2296 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2297 2298 /* ...and wait for it to complete. */ 2299 for (count = 1000; count > 0; count--) { 2300 FXP_CDMCSSYNC(sc, 2301 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2302 status = le16toh(mcsp->cb_status); 2303 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD); 2304 if ((status & FXP_CB_STATUS_C) != 0) 2305 break; 2306 DELAY(1); 2307 } 2308 if (count == 0) { 2309 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 2310 device_xname(sc->sc_dev), __LINE__); 2311 return; 2312 } 2313} 2314 2315static const uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2316static const uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2317static const uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2318static const uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2319static const uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2320static const uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2321static const uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE; 2322 2323#define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2324 2325static const struct ucode { 2326 int32_t revision; 2327 const uint32_t *ucode; 2328 size_t length; 2329 uint16_t int_delay_offset; 2330 uint16_t bundle_max_offset; 2331} ucode_table[] = { 2332 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), 2333 D101_CPUSAVER_DWORD, 0 }, 2334 2335 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), 2336 D101_CPUSAVER_DWORD, 0 }, 2337 2338 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2339 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2340 2341 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2342 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2343 2344 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2345 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2346 2347 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2348 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2349 2350 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e), 2351 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 2352 2353 { FXP_REV_82551_10, UCODE(fxp_ucode_d102e), 2354 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 2355 2356 { 0, NULL, 0, 0, 0 } 2357}; 2358 2359void 2360fxp_load_ucode(struct fxp_softc *sc) 2361{ 2362 const struct ucode *uc; 2363 struct fxp_cb_ucode *cbp = &sc->sc_control_data->fcd_ucode; 2364 int count, i; 2365 uint16_t status; 2366 2367 if (sc->sc_flags & FXPF_UCODE_LOADED) 2368 return; 2369 2370 /* 2371 * Only load the uCode if the user has requested that 2372 * we do so. 2373 */ 2374 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK0) == 0) { 2375 sc->sc_int_delay = 0; 2376 sc->sc_bundle_max = 0; 2377 return; 2378 } 2379 2380 for (uc = ucode_table; uc->ucode != NULL; uc++) { 2381 if (sc->sc_rev == uc->revision) 2382 break; 2383 } 2384 if (uc->ucode == NULL) 2385 return; 2386 2387 /* BIG ENDIAN: no need to swap to store 0 */ 2388 cbp->cb_status = 0; 2389 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2390 cbp->link_addr = 0xffffffff; /* (no) next command */ 2391 for (i = 0; i < uc->length; i++) 2392 cbp->ucode[i] = htole32(uc->ucode[i]); 2393 2394 if (uc->int_delay_offset) 2395 *(volatile uint16_t *) &cbp->ucode[uc->int_delay_offset] = 2396 htole16(fxp_int_delay + (fxp_int_delay / 2)); 2397 2398 if (uc->bundle_max_offset) 2399 *(volatile uint16_t *) &cbp->ucode[uc->bundle_max_offset] = 2400 htole16(fxp_bundle_max); 2401 2402 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2403 2404 /* 2405 * Download the uCode to the chip. 2406 */ 2407 fxp_scb_wait(sc); 2408 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDUCODEOFF); 2409 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2410 2411 /* ...and wait for it to complete. */ 2412 for (count = 10000; count > 0; count--) { 2413 FXP_CDUCODESYNC(sc, 2414 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2415 status = le16toh(cbp->cb_status); 2416 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD); 2417 if ((status & FXP_CB_STATUS_C) != 0) 2418 break; 2419 DELAY(2); 2420 } 2421 if (count == 0) { 2422 sc->sc_int_delay = 0; 2423 sc->sc_bundle_max = 0; 2424 log(LOG_WARNING, "%s: timeout loading microcode\n", 2425 device_xname(sc->sc_dev)); 2426 return; 2427 } 2428 2429 if (sc->sc_int_delay != fxp_int_delay || 2430 sc->sc_bundle_max != fxp_bundle_max) { 2431 sc->sc_int_delay = fxp_int_delay; 2432 sc->sc_bundle_max = fxp_bundle_max; 2433 log(LOG_INFO, "%s: Microcode loaded: int delay: %d usec, " 2434 "max bundle: %d\n", device_xname(sc->sc_dev), 2435 sc->sc_int_delay, 2436 uc->bundle_max_offset == 0 ? 0 : sc->sc_bundle_max); 2437 } 2438 2439 sc->sc_flags |= FXPF_UCODE_LOADED; 2440} 2441 2442int 2443fxp_enable(struct fxp_softc *sc) 2444{ 2445 2446 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2447 if ((*sc->sc_enable)(sc) != 0) { 2448 log(LOG_ERR, "%s: device enable failed\n", 2449 device_xname(sc->sc_dev)); 2450 return (EIO); 2451 } 2452 } 2453 2454 sc->sc_enabled = 1; 2455 return (0); 2456} 2457 2458void 2459fxp_disable(struct fxp_softc *sc) 2460{ 2461 2462 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2463 (*sc->sc_disable)(sc); 2464 sc->sc_enabled = 0; 2465 } 2466} 2467 2468/* 2469 * fxp_activate: 2470 * 2471 * Handle device activation/deactivation requests. 2472 */ 2473int 2474fxp_activate(device_t self, enum devact act) 2475{ 2476 struct fxp_softc *sc = device_private(self); 2477 2478 switch (act) { 2479 case DVACT_DEACTIVATE: 2480 if_deactivate(&sc->sc_ethercom.ec_if); 2481 return 0; 2482 default: 2483 return EOPNOTSUPP; 2484 } 2485} 2486 2487/* 2488 * fxp_detach: 2489 * 2490 * Detach an i82557 interface. 2491 */ 2492int 2493fxp_detach(struct fxp_softc *sc, int flags) 2494{ 2495 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2496 int i, s; 2497 2498 /* Succeed now if there's no work to do. */ 2499 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2500 return (0); 2501 2502 s = splnet(); 2503 /* Stop the interface. Callouts are stopped in it. */ 2504 fxp_stop(ifp, 1); 2505 splx(s); 2506 2507 /* Destroy our callout. */ 2508 callout_destroy(&sc->sc_callout); 2509 2510 if (sc->sc_flags & FXPF_MII) { 2511 /* Detach all PHYs */ 2512 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2513 } 2514 2515 rnd_detach_source(&sc->rnd_source); 2516 ether_ifdetach(ifp); 2517 if_detach(ifp); 2518 2519 /* Delete all remaining media. */ 2520 ifmedia_fini(&sc->sc_mii.mii_media); 2521 2522 for (i = 0; i < FXP_NRFABUFS; i++) { 2523 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2524 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2525 } 2526 2527 for (i = 0; i < FXP_NTXCB; i++) { 2528 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2529 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2530 } 2531 2532 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2533 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2534 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 2535 sizeof(struct fxp_control_data)); 2536 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2537 2538 return (0); 2539} 2540