hmereg.h revision 1.14
1/* $NetBSD: hmereg.h,v 1.14 2003/05/14 19:46:59 petrov Exp $ */ 2 3/*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39/* 40 * HME Shared Ethernet Block register offsets 41 */ 42#define HME_SEBI_RESET (0*4) 43#define HME_SEBI_CFG (1*4) 44#define HME_SEBI_STAT (64*4) 45#define HME_SEBI_IMASK (65*4) 46 47/* HME SEB bits. */ 48#define HME_SEB_RESET_ETX 0x00000001 /* reset external transmitter */ 49#define HME_SEB_RESET_ERX 0x00000002 /* reset external receiver */ 50 51#define HME_SEB_CFG_BURSTMASK 0x00000003 /* covers all burst bits */ 52#define HME_SEB_CFG_BURST16 0x00000000 /* 16 byte bursts */ 53#define HME_SEB_CFG_BURST32 0x00000001 /* 32 byte bursts */ 54#define HME_SEB_CFG_BURST64 0x00000002 /* 64 byte bursts */ 55#define HME_SEB_CFG_64BIT 0x00000004 /* ? */ 56#define HME_SEB_CFG_PARITY 0x00000008 /* ? */ 57 58#define HME_SEB_STAT_GOTFRAME 0x00000001 /* frame received */ 59#define HME_SEB_STAT_RCNTEXP 0x00000002 /* rx frame count expired */ 60#define HME_SEB_STAT_ACNTEXP 0x00000004 /* align error count expired */ 61#define HME_SEB_STAT_CCNTEXP 0x00000008 /* crc error count expired */ 62#define HME_SEB_STAT_LCNTEXP 0x00000010 /* length error count expired */ 63#define HME_SEB_STAT_RFIFOVF 0x00000020 /* rx fifo overflow */ 64#define HME_SEB_STAT_CVCNTEXP 0x00000040 /* code violation counter exp */ 65#define HME_SEB_STAT_STSTERR 0x00000080 /* xif sqe test failed */ 66#define HME_SEB_STAT_SENTFRAME 0x00000100 /* frame sent */ 67#define HME_SEB_STAT_TFIFO_UND 0x00000200 /* tx fifo underrun */ 68#define HME_SEB_STAT_MAXPKTERR 0x00000400 /* max-packet size error */ 69#define HME_SEB_STAT_NCNTEXP 0x00000800 /* normal collision count exp */ 70#define HME_SEB_STAT_ECNTEXP 0x00001000 /* excess collision count exp */ 71#define HME_SEB_STAT_LCCNTEXP 0x00002000 /* late collision count exp */ 72#define HME_SEB_STAT_FCNTEXP 0x00004000 /* first collision count exp */ 73#define HME_SEB_STAT_DTIMEXP 0x00008000 /* defer timer expired */ 74#define HME_SEB_STAT_RXTOHOST 0x00010000 /* pkt moved from rx fifo->memory */ 75#define HME_SEB_STAT_NORXD 0x00020000 /* out of receive descriptors */ 76#define HME_SEB_STAT_RXERR 0x00040000 /* rx DMA error */ 77#define HME_SEB_STAT_RXLATERR 0x00080000 /* late error during rx DMA */ 78#define HME_SEB_STAT_RXPERR 0x00100000 /* parity error during rx DMA */ 79#define HME_SEB_STAT_RXTERR 0x00200000 /* tag error during rx DMA */ 80#define HME_SEB_STAT_EOPERR 0x00400000 /* tx descriptor did not set EOP */ 81#define HME_SEB_STAT_MIFIRQ 0x00800000 /* mif needs attention */ 82#define HME_SEB_STAT_HOSTTOTX 0x01000000 /* pkt moved from memory->tx fifo */ 83#define HME_SEB_STAT_TXALL 0x02000000 /* all pkts in fifo transmitted */ 84#define HME_SEB_STAT_TXEACK 0x04000000 /* error during tx DMA */ 85#define HME_SEB_STAT_TXLERR 0x08000000 /* late error during tx DMA */ 86#define HME_SEB_STAT_TXPERR 0x10000000 /* parity error during tx DMA */ 87#define HME_SEB_STAT_TXTERR 0x20000000 /* tag error durig tx DMA */ 88#define HME_SEB_STAT_SLVERR 0x40000000 /* pio access error */ 89#define HME_SEB_STAT_SLVPERR 0x80000000 /* pio access parity error */ 90#define HME_SEB_STAT_BITS "\177\020" \ 91 "b\0GOTFRAME\0b\1RCNTEXP\0b\2ACNTEXP\0" \ 92 "b\3CCNTEXP\0b\4LCNTEXP\0b\5RFIFOVF\0" \ 93 "b\6CVCNTEXP\0b\7STSTERR\0b\10SENTFRAME\0" \ 94 "b\11TFIFO_UND\0b\12MAXPKTERR\0b\13NCNTEXP\0" \ 95 "b\14ECNTEXP\0b\15LCCNTEXP\0b\16FCNTEXP\0" \ 96 "b\17DTIMEXP\0b\20RXTOHOST\0b\21NORXD\0" \ 97 "b\22RXERR\0b\23RXLATERR\0b\24RXPERR\0" \ 98 "b\25RXTERR\0b\26EOPERR\0b\27MIFIRQ\0" \ 99 "b\30HOSTTOTX\0b\31TXALL\0b\32XTEACK\0" \ 100 "b\33TXLERR\0b\34TXPERR\0b\35TXTERR\0" \ 101 "b\36SLVERR\0b\37SLVPERR\0\0" 102 103#ifdef HMEDEBUG 104#define HME_SEB_STAT_DEBUG_ERRORS (HME_SEB_STAT_DTIMEXP | HME_SEB_STAT_RFIFOVF) 105#endif 106 107#define HME_SEB_STAT_ALL_ERRORS \ 108 (HME_SEB_STAT_SLVPERR | HME_SEB_STAT_SLVERR | HME_SEB_STAT_TXTERR |\ 109 HME_SEB_STAT_TXPERR | HME_SEB_STAT_TXLERR | HME_SEB_STAT_TXEACK |\ 110 HME_SEB_STAT_EOPERR | HME_SEB_STAT_RXTERR | HME_SEB_STAT_RXPERR |\ 111 HME_SEB_STAT_RXLATERR | HME_SEB_STAT_RXERR | HME_SEB_STAT_NORXD |\ 112 HME_SEB_STAT_FCNTEXP | HME_SEB_STAT_LCCNTEXP |\ 113 HME_SEB_STAT_ECNTEXP | HME_SEB_STAT_NCNTEXP | HME_SEB_STAT_MAXPKTERR|\ 114 HME_SEB_STAT_TFIFO_UND| HME_SEB_STAT_STSTERR | HME_SEB_STAT_CVCNTEXP |\ 115 HME_SEB_STAT_LCNTEXP | HME_SEB_STAT_CCNTEXP |\ 116 HME_SEB_STAT_ACNTEXP | HME_SEB_STAT_DEBUG_ERRORS) 117 118#define HME_SEB_STAT_VLAN_ERRORS \ 119 (HME_SEB_STAT_SLVPERR | HME_SEB_STAT_SLVERR | HME_SEB_STAT_TXTERR |\ 120 HME_SEB_STAT_TXPERR | HME_SEB_STAT_TXLERR | HME_SEB_STAT_TXEACK |\ 121 HME_SEB_STAT_EOPERR | HME_SEB_STAT_RXTERR | HME_SEB_STAT_RXPERR |\ 122 HME_SEB_STAT_RXLATERR | HME_SEB_STAT_RXERR | HME_SEB_STAT_NORXD |\ 123 HME_SEB_STAT_DTIMEXP | HME_SEB_STAT_FCNTEXP | HME_SEB_STAT_LCCNTEXP |\ 124 HME_SEB_STAT_ECNTEXP | HME_SEB_STAT_NCNTEXP | \ 125 HME_SEB_STAT_TFIFO_UND| HME_SEB_STAT_STSTERR | HME_SEB_STAT_CVCNTEXP |\ 126 HME_SEB_STAT_RFIFOVF | HME_SEB_STAT_LCNTEXP | HME_SEB_STAT_CCNTEXP |\ 127 HME_SEB_STAT_ACNTEXP) 128 129/* 130 * HME Transmitter register offsets 131 */ 132#define HME_ETXI_PENDING (0*4) /* Pending/wakeup */ 133#define HME_ETXI_CFG (1*4) 134#define HME_ETXI_RING (2*4) /* Descriptor Ring pointer */ 135#define HME_ETXI_BBASE (3*4) /* Buffer base address (ro) */ 136#define HME_ETXI_BDISP (4*4) /* Buffer displacement (ro) */ 137#define HME_ETXI_FIFO_WPTR (5*4) /* FIFO write pointer */ 138#define HME_ETXI_FIFO_SWPTR (6*4) /* FIFO shadow write pointer */ 139#define HME_ETXI_FIFO_RPTR (7*4) /* FIFO read pointer */ 140#define HME_ETXI_FIFO_SRPTR (8*4) /* FIFO shadow read pointer */ 141#define HME_ETXI_FIFO_PKTCNT (9*4) /* FIFO packet counter */ 142#define HME_ETXI_STATEMACHINE (10*4) /* State machine */ 143#define HME_ETXI_RSIZE (11*4) /* Ring size */ 144#define HME_ETXI_BPTR (12*4) /* Buffer pointer */ 145 146 147/* TXI_PENDING bits */ 148#define HME_ETX_TP_DMAWAKEUP 0x00000001 /* Start tx (rw, auto-clear) */ 149 150/* TXI_CFG bits */ 151#define HME_ETX_CFG_DMAENABLE 0x00000001 /* Enable TX DMA */ 152#define HME_ETX_CFG_FIFOTHRESH 0x000003fe /* TX fifo threshold */ 153#define HME_ETX_CFG_IRQDAFTER 0x00000400 /* Intr after tx-fifo empty */ 154#define HME_ETX_CFG_IRQDBEFORE 0x00000000 /* Intr before tx-fifo empty */ 155 156 157/* 158 * HME Receiver register offsets 159 */ 160#define HME_ERXI_CFG (0*4) 161#define HME_ERXI_RING (1*4) /* Descriptor Ring pointer */ 162#define HME_ERXI_BPTR (2*4) /* Data Buffer pointer (ro) */ 163#define HME_ERXI_FIFO_WPTR (3*4) /* FIFO write pointer */ 164#define HME_ERXI_FIFO_SWPTR (4*4) /* FIFO shadow write pointer */ 165#define HME_ERXI_FIFO_RPTR (5*4) /* FIFO read pointer */ 166#define HME_ERXI_FIFO_SRPTR (6*4) /* FIFO shadow read pointer */ 167#define HME_ERXI_STATEMACHINE (7*4) /* State machine */ 168 169/* RXI_CFG bits */ 170#define HME_ERX_CFG_DMAENABLE 0x00000001 /* Enable RX DMA */ 171#define HME_ERX_CFG_BYTEOFFSET 0x00000038 /* RX first byte offset */ 172#define HME_ERX_CFG_RINGSIZE32 0x00000000 /* Descriptor ring size: 32 */ 173#define HME_ERX_CFG_RINGSIZE64 0x00000200 /* Descriptor ring size: 64 */ 174#define HME_ERX_CFG_RINGSIZE128 0x00000400 /* Descriptor ring size: 128 */ 175#define HME_ERX_CFG_RINGSIZE256 0x00000600 /* Descriptor ring size: 256 */ 176#define HME_ERX_CFG_CSUMSTART 0x007f0000 /* cksum offset */ 177 178/* 179 * HME MAC-core register offsets 180 */ 181#define HME_MACI_XIF (0*4) 182#define HME_MACI_TXSWRST (130*4) /* TX reset */ 183#define HME_MACI_TXCFG (131*4) /* TX config */ 184#define HME_MACI_JSIZE (139*4) /* TX jam size */ 185#define HME_MACI_TXSIZE (140*4) /* TX max size */ 186#define HME_MACI_NCCNT (144*4) /* TX normal collision cnt */ 187#define HME_MACI_FCCNT (145*4) /* TX first collision cnt */ 188#define HME_MACI_EXCNT (146*4) /* TX excess collision cnt */ 189#define HME_MACI_LTCNT (147*4) /* TX late collision cnt */ 190#define HME_MACI_RANDSEED (148*4) /* */ 191#define HME_MACI_RXSWRST (194*4) /* RX reset */ 192#define HME_MACI_RXCFG (195*4) /* RX config */ 193#define HME_MACI_RXSIZE (196*4) /* RX max size */ 194#define HME_MACI_MACADDR2 (198*4) /* MAC address */ 195#define HME_MACI_MACADDR1 (199*4) 196#define HME_MACI_MACADDR0 (200*4) 197#define HME_MACI_HASHTAB3 (208*4) /* Address hash table */ 198#define HME_MACI_HASHTAB2 (209*4) 199#define HME_MACI_HASHTAB1 (210*4) 200#define HME_MACI_HASHTAB0 (211*4) 201#define HME_MACI_AFILTER2 (212*4) /* Address filter */ 202#define HME_MACI_AFILTER1 (213*4) 203#define HME_MACI_AFILTER0 (214*4) 204#define HME_MACI_AFILTER_MASK (215*4) 205 206/* XIF config register. */ 207#define HME_MAC_XIF_OE 0x00000001 /* Output driver enable */ 208#define HME_MAC_XIF_XLBACK 0x00000002 /* Loopback-mode XIF enable */ 209#define HME_MAC_XIF_MLBACK 0x00000004 /* Loopback-mode MII enable */ 210#define HME_MAC_XIF_MIIENABLE 0x00000008 /* MII receive buffer enable */ 211#define HME_MAC_XIF_SQENABLE 0x00000010 /* SQE test enable */ 212#define HME_MAC_XIF_SQETWIN 0x000003e0 /* SQE time window */ 213#define HME_MAC_XIF_LANCE 0x00000010 /* Lance mode enable */ 214#define HME_MAC_XIF_LIPG0 0x000003e0 /* Lance mode IPG0 */ 215 216/* Transmit config register. */ 217#define HME_MAC_TXCFG_ENABLE 0x00000001 /* Enable the transmitter */ 218#define HME_MAC_TXCFG_SMODE 0x00000020 /* Enable slow transmit mode */ 219#define HME_MAC_TXCFG_CIGN 0x00000040 /* Ignore transmit collisions */ 220#define HME_MAC_TXCFG_FCSOFF 0x00000080 /* Do not emit FCS */ 221#define HME_MAC_TXCFG_DBACKOFF 0x00000100 /* Disable backoff */ 222#define HME_MAC_TXCFG_FULLDPLX 0x00000200 /* Enable full-duplex */ 223#define HME_MAC_TXCFG_DGIVEUP 0x00000400 /* Don't give up on transmits */ 224 225/* Receive config register. */ 226#define HME_MAC_RXCFG_ENABLE 0x00000001 /* Enable the receiver */ 227#define HME_MAC_RXCFG_PSTRIP 0x00000020 /* Pad byte strip enable */ 228#define HME_MAC_RXCFG_PMISC 0x00000040 /* Enable promiscous mode */ 229#define HME_MAC_RXCFG_DERR 0x00000080 /* Disable error checking */ 230#define HME_MAC_RXCFG_DCRCS 0x00000100 /* Disable CRC stripping */ 231#define HME_MAC_RXCFG_ME 0x00000200 /* Receive packets addressed to me */ 232#define HME_MAC_RXCFG_PGRP 0x00000400 /* Enable promisc group mode */ 233#define HME_MAC_RXCFG_HENABLE 0x00000800 /* Enable the hash filter */ 234#define HME_MAC_RXCFG_AENABLE 0x00001000 /* Enable the address filter */ 235 236/* 237 * HME MIF register offsets 238 */ 239#define HME_MIFI_BB_CLK (0*4) /* bit-bang clock */ 240#define HME_MIFI_BB_DATA (1*4) /* bit-bang data */ 241#define HME_MIFI_BB_OE (2*4) /* bit-bang output enable */ 242#define HME_MIFI_FO (3*4) /* frame output */ 243#define HME_MIFI_CFG (4*4) /* */ 244#define HME_MIFI_IMASK (5*4) /* Interrupt mask for status change */ 245#define HME_MIFI_STAT (6*4) /* Status (ro, auto-clear) */ 246#define HME_MIFI_SM (7*4) /* State machine (ro) */ 247 248/* MIF Configuration register */ 249#define HME_MIF_CFG_PHY 0x00000001 /* PHY select */ 250#define HME_MIF_CFG_PE 0x00000002 /* Poll enable */ 251#define HME_MIF_CFG_BBMODE 0x00000004 /* Bit-bang mode */ 252#define HME_MIF_CFG_PRADDR 0x000000f8 /* Poll register adddress */ 253#define HME_MIF_CFG_MDI0 0x00000100 /* MDI_0 (ro) */ 254#define HME_MIF_CFG_MDI1 0x00000200 /* MDI_1 (ro) */ 255#define HME_MIF_CFG_PPADDR 0x00007c00 /* Poll phy adddress */ 256 257/* MIF Frame/Output register */ 258#define HME_MIF_FO_ST 0xc0000000 /* Start of frame */ 259#define HME_MIF_FO_ST_SHIFT 30 /* */ 260#define HME_MIF_FO_OPC 0x30000000 /* Opcode */ 261#define HME_MIF_FO_OPC_SHIFT 28 /* */ 262#define HME_MIF_FO_PHYAD 0x0f800000 /* PHY Address */ 263#define HME_MIF_FO_PHYAD_SHIFT 23 /* */ 264#define HME_MIF_FO_REGAD 0x007c0000 /* Register Address */ 265#define HME_MIF_FO_REGAD_SHIFT 18 /* */ 266#define HME_MIF_FO_TAMSB 0x00020000 /* Turn-around MSB */ 267#define HME_MIF_FO_TALSB 0x00010000 /* Turn-around LSB */ 268#define HME_MIF_FO_DATA 0x0000ffff /* data to read or write */ 269 270/* Wired HME PHY addresses */ 271#define HME_PHYAD_INTERNAL 1 272#define HME_PHYAD_EXTERNAL 0 273 274/* 275 * Buffer Descriptors. 276 */ 277#ifdef notdef 278struct hme_xd { 279 volatile u_int32_t xd_flags; 280 volatile u_int32_t xd_addr; /* Buffer address (DMA) */ 281}; 282#endif 283#define HME_XD_SIZE 8 284#define HME_XD_FLAGS(base, index) ((base) + ((index) * HME_XD_SIZE) + 0) 285#define HME_XD_ADDR(base, index) ((base) + ((index) * HME_XD_SIZE) + 4) 286#define HME_XD_GETFLAGS(p, b, i) \ 287 (p) ? le32toh(*((u_int32_t *)HME_XD_FLAGS(b,i))) : \ 288 (*((u_int32_t *)HME_XD_FLAGS(b,i))) 289#define HME_XD_SETFLAGS(p, b, i, f) do { \ 290 *((u_int32_t *)HME_XD_FLAGS(b,i)) = ((p) ? htole32((f)) : (f)); \ 291} while(/* CONSTCOND */ 0) 292#define HME_XD_SETADDR(p, b, i, a) do { \ 293 *((u_int32_t *)HME_XD_ADDR(b,i)) = ((p) ? htole32((a)) : (a)); \ 294} while(/* CONSTCOND */ 0) 295 296/* Descriptor flag values */ 297#define HME_XD_OWN 0x80000000 /* ownership: 1=hw, 0=sw */ 298#define HME_XD_SOP 0x40000000 /* start of packet marker (tx) */ 299#define HME_XD_OFL 0x40000000 /* buffer overflow (rx) */ 300#define HME_XD_EOP 0x20000000 /* end of packet marker (tx) */ 301#define HME_XD_TXCKSUM 0x10000000 /* checksum enable (tx) */ 302#define HME_XD_RXLENMSK 0x3fff0000 /* packet length mask (rx) */ 303#define HME_XD_RXLENSHIFT 16 304#define HME_XD_TXLENMSK 0x00003fff /* packet length mask (tx) */ 305#define HME_XD_RXCKSUM 0x0000ffff /* packet checksum (rx) */ 306 307/* Macros to encode/decode the receive buffer size from the flags field */ 308#define HME_XD_ENCODE_RSIZE(sz) \ 309 (((sz) << HME_XD_RXLENSHIFT) & HME_XD_RXLENMSK) 310#define HME_XD_DECODE_RSIZE(flags) \ 311 (((flags) & HME_XD_RXLENMSK) >> HME_XD_RXLENSHIFT) 312 313/* Provide encode/decode macros for the transmit buffers for symmetry */ 314#define HME_XD_ENCODE_TSIZE(sz) \ 315 (((sz) << 0) & HME_XD_TXLENMSK) 316#define HME_XD_DECODE_TSIZE(flags) \ 317 (((flags) & HME_XD_TXLENMSK) >> 0) 318 319