1/* $NetBSD: elinkxlreg.h,v 1.14 2007/03/04 06:01:54 christos Exp $ */ 2 3/*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32/* 33 * This file defines the registers specific to the EtherLink XL family 34 * of NICs. 35 */ 36 37#define EEPROM_SOFTINFO3 0x15 /* Software info #3 */ 38#define EEPROM_SUBVENDOR_ELXL 0x17 /* Subsys vendor id */ 39#define EEPROM_SUBSYSID 0x18 /* Subsys id */ 40#define EEPROM_MEDIA 0x19 /* Media options (90xB) */ 41#define EEPROM_CHECKSUM_ELXL 0x20 /* EEPROM checksum */ 42 43#define READ_EEPROM8 0x0200 /* 8 bit EEPROM read command */ 44 45/* 46 * Flat address space registers (outside the windows) 47 */ 48 49#define ELINK_TXPKTID 0x18 /* 90xB only */ 50#define ELINK_TIMER 0x1a 51#define ELINK_TXSTATUS 0x1b 52#define ELINK_INTSTATUSAUTO 0x1e 53#define ELINK_DMACTRL 0x20 54# define ELINK_DMAC_DNCMPLREQ 0x00000002 55# define ELINK_DMAC_DNSTALLED 0x00000004 56# define ELINK_DMAC_UPCOMPLETE 0x00000008 57# define ELINK_DMAC_DNCOMPLETE 0x00000010 58# define ELINK_DMAC_UPRXEAREN 0x00000020 59# define ELINK_DMAC_ARNCNTDN 0x00000040 60# define ELINK_DMAC_DNINPROG 0x00000080 61# define ELINK_DMAC_CNTSPEED 0x00000100 62# define ELINK_DMAC_CNTDNMODE 0x00000200 63# define ELINK_DMAC_ALTSEQDIS 0x00010000 64# define ELINK_DMAC_DEFEATMWI 0x00100000 65# define ELINK_DMAC_DEFEATMRL 0x00200000 66# define ELINK_DMAC_UPOVERDIS 0x00400000 67# define ELINK_DMAC_TARGABORT 0x40000000 68# define ELINK_DMAC_MSTRABORT 0x80000000 69#define ELINK_DNLISTPTR 0x24 70#define ELINK_DNBURSTTHRESH 0x2a /* 90xB only */ 71#define ELINK_DNPRIOTHRESH 0x2c /* 90xB only */ 72#define ELINK_DNPOLL 0x2d /* 90xB only */ 73#define ELINK_TXFREETHRESH 0x2f /* 90x only */ 74#define ELINK_UPPKTSTATUS 0x30 75#define ELINK_FREETIMER 0x34 76#define ELINK_COUNTDOWN 0x36 77#define ELINK_UPLISTPTR 0x38 78#define ELINK_UPPRIOTHRESH 0x3c /* 90xB only */ 79#define ELINK_UPPOLL 0x3d /* 90xB only */ 80#define ELINK_UPBURSTTHRESH 0x3e /* 90xB only */ 81#define ELINK_REALTIMECNT 0x40 /* 90xB only */ 82#define ELINK_DNMAXBURST 0x78 /* 90xB only */ 83#define ELINK_UPMAXBURST 0x7a /* 90xB only */ 84 85/* 86 * This is reset options for the other cards, media options for 87 * the 90xB NICs. Reset options are in a separate register for 88 * the 90xB. 89 */ 90#define ELINK_W3_MEDIA_OPTIONS 0x08 91# define ELINK_MEDIACAP_100BASET4 0x0001 92# define ELINK_MEDIACAP_100BASETX 0x0002 93# define ELINK_MEDIACAP_100BASEFX 0x0004 94# define ELINK_MEDIACAP_10BASET 0x0008 95# define ELINK_MEDIACAP_10BASE2 0x0010 96# define ELINK_MEDIACAP_10BASE5 0x0020 97# define ELINK_MEDIACAP_MII 0x0040 98# define ELINK_MEDIACAP_10BASEFL 0x0080 99 100/* 101 * Reset options for the 90xB 102 */ 103#define ELINK_W2_RESET_OPTIONS 0x0c 104# define ELINK_RESET_OPT_LEDPOLAR 0x0010 105# define ELINK_RESET_OPT_PHYPOWER 0x4000 106 107/* 108 * Window 4, offset 8 is defined for MII/PHY access for EtherLink XL 109 * cards. 110 */ 111#define ELINK_W4_PHYSMGMT 0x08 112# define ELINK_PHY_CLK 0x0001 113# define ELINK_PHY_DATA 0x0002 114# define ELINK_PHY_DIR 0x0004 115 116/* 117 * Counter in window 4 for packets with a bad start-of-stream delimiter/ 118 */ 119#define ELINK_W4_BADSSD 0x0c 120#define ELINK_W4_UBYTESOK 0x0d 121 122/* 123 * Define for extra multicast hash filter bit implemented in the 90xB 124 */ 125#define FIL_MULTIHASH 0x10 126 127/* 128 * Defines for the interrupt status register, only for the 90x[B] 129 */ 130#define HOST_ERROR 0x0002 131#define LINK_EVENT 0x0100 132#define DN_COMPLETE 0x0200 133#define UP_COMPLETE 0x0400 134 135#define XL_WATCHED_INTERRUPTS \ 136 (HOST_ERROR | TX_COMPLETE | UPD_STATS | DN_COMPLETE | UP_COMPLETE) 137 138 139/* 140 * Window 7 registers. These are different for 90x and 90xB than 141 * for the EtherLink III / Fast EtherLink cards. 142 */ 143 144#define ELINK_W7_VLANMASK 0x00 /* 90xB only */ 145#define ELINK_W7_VLANTYPE 0x04 /* 90xB only */ 146#define ELINK_W7_TIMER 0x0a /* 90x only */ 147#define ELINK_W7_TX_STATUS 0x0b /* 90x only */ 148#define ELINK_W7_POWEREVENT 0x0c /* 90xB only */ 149#define ELINK_W7_INTSTATUS 0x0e 150 151/* 152 * Command definitions. 153 */ 154#define ELINK_UPSTALL 0x3000 155#define ELINK_UPUNSTALL 0x3001 156#define ELINK_DNSTALL 0x3002 157#define ELINK_DNUNSTALL 0x3003 158#define ELINK_TXRECLTHRESH 0xc000 159#define ELINK_TXSTARTTHRESH 0x9800 160#define ELINK_CLEARHASHFILBIT 0xc800 161#define ELINK_SETHASHFILBIT 0xcc00 162 163/* 164 * The Internal Config register is different on 90xB cards. The 165 * different masks / shifts are defined here. 166 */ 167 168/* 169 * Lower 16 bits. 170 */ 171#define CONFIG_TXLARGE (u_int16_t) 0x4000 172#define CONFIG_TXLARGE_SHIFT 14 173 174#define CONFIG_RXLARGE (u_int16_t) 0x8000 175#define CONFIG_RXLARGE_SHIFT 15 176 177/* 178 * Upper 16 bits. 179 */ 180#define CONFIG_XCVR_SEL (u_int16_t) 0x00f0 181#define CONFIG_XCVR_SEL_SHIFT 4 182 183#define ELINKMEDIA_AUTO 8 184 185#define CONFIG_AUTOSEL (u_int16_t) 0x0100 186#define CONFIG_AUTOSEL_SHIFT 8 187 188#define CONFIG_DISABLEROM (u_int16_t) 0x0200 189#define CONFIG_DISABLEROM_SHIFT 9 190 191/* 192 * ID of internal PHY. 193 */ 194 195#define ELINK_INTPHY_ID 24 196 197/* 198 * Fragment header as laid out in memory for DMA access. 199 */ 200 201struct ex_fraghdr { 202 volatile u_int32_t fr_addr; /* phys addr of frag */ 203 volatile u_int32_t fr_len; /* length of frag */ 204}; 205 206#define EX_FR_LENMASK 0x00001fff /* mask for length in fr_len field */ 207#define EX_FR_LAST 0x80000000 /* indicates last fragment */ 208 209#define EX_NDPD 256 210#define EX_NUPD 128 211 212/* 213 * Note: the number of receive fragments in an UPD is 1, since we're 214 * receiving into one contiguous mbuf. 215 */ 216#define EX_NRFRAGS 1 /* # fragments in rcv pkt (< 64) */ 217#define EX_NTFRAGS 32 /* # fragments in tx pkt (< 64) */ 218 219/* 220 * Type 0 Download Packet Descriptor (DPD). 221 */ 222struct ex_dpd { 223 volatile u_int32_t dpd_nextptr; /* prt to next fragheader */ 224 volatile u_int32_t dpd_fsh; /* frame start header */ 225 volatile struct ex_fraghdr dpd_frags[EX_NTFRAGS]; 226}; 227 228/* 229 * Type 1 DPD, supported by 90xB. 230 */ 231struct ex_dpd1 { 232 volatile u_int32_t dpd_nextptr; 233 volatile u_int32_t dpd_schedtime; /* time to download */ 234 volatile u_int32_t dpd_fsh; 235 volatile struct ex_fraghdr dpd_frags[EX_NTFRAGS]; 236}; 237 238struct ex_upd { 239 volatile u_int32_t upd_nextptr; 240 volatile u_int32_t upd_pktstatus; 241 volatile struct ex_fraghdr upd_frags[EX_NRFRAGS]; 242}; 243 244/* 245 * Higher level linked list of upload packet descriptors. 246 */ 247struct ex_rxdesc { 248 struct ex_rxdesc *rx_next; 249 struct mbuf *rx_mbhead; 250 bus_dmamap_t rx_dmamap; 251 struct ex_upd *rx_upd; 252}; 253 254/* 255 * .. and for download packet descriptors. 256 */ 257struct ex_txdesc { 258 struct ex_txdesc *tx_next; 259 struct mbuf *tx_mbhead; 260 bus_dmamap_t tx_dmamap; 261 struct ex_dpd *tx_dpd; 262}; 263 264/* 265 * hardware ip4csum-tx on ex(4) sometimes seems to set wrong IP checksums 266 * if the TX IP packet length is 21 or 22 bytes which requires autopadding. 267 * To avoid this bug, we have to pad such very short packets manually. 268 */ 269#define EX_IP4CSUMTX_MINLEN 22 270#define EX_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + EX_IP4CSUMTX_MINLEN) 271 272#define DPDMEM_SIZE (sizeof(struct ex_dpd) * EX_NDPD) 273#define DPDMEMPAD_OFF DPDMEM_SIZE 274#define DPDMEMPAD_DMADDR(sc) ((sc)->sc_dpddma + DPDMEMPAD_OFF) 275 276#define DPD_DMADDR(s,t) \ 277 ((s)->sc_dpddma + ((char *)((t)->tx_dpd) - (char *)((s)->sc_dpd))) 278 279/* 280 * Frame Start Header bitfields. 281 */ 282 283#define EX_DPD_DNIND 0x80000000 /* intr on download done */ 284#define EX_DPD_TXIND 0x00008000 /* intr on tx done */ 285#define EX_DPD_NOCRC 0x00002000 /* no CRC append */ 286 287/* 288 * Lower 12 bits are the tx length for the 90x family. The 90xB 289 * assumes that the tx length is the sum of all frame lengths, 290 * and uses the bits as below. It also defines some more bits in 291 * the upper part. 292 */ 293#define EX_DPD_EMPTY 0x20000000 /* no data in this DPD */ 294#define EX_DPD_UPDEFEAT 0x10000000 /* don't round tx lengths up */ 295#define EX_DPD_UDPCKSUM 0x08000000 /* do hardware UDP checksum */ 296#define EX_DPD_TCPCKSUM 0x04000000 /* do hardware TCP checksum */ 297#define EX_DPD_IPCKSUM 0x02000000 /* do hardware IP checksum */ 298#define EX_DPD_DNCMPLT 0x01000000 /* packet has been downloaded */ 299#define EX_DPD_IDMASK 0x000003fc /* mask for packet id */ 300# define EX_DPD_IDSHIFT 2 301#define EX_DPD_RNDMASK 0x00000003 /* mask for rounding */ 302 /* 0 -> dword, 2 -> word, 1,3 -> none */ 303 304/* 305 * Schedtime bitfields. 306 */ 307#define EX_SCHED_TIMEVALID 0x20000000 /* field contains value */ 308#define EX_SCHED_LDCOUNT 0x10000000 /* load schedtime onto NIC */ 309#define EX_SCHED_TIMEMASK 0x00ffffff 310 311/* 312 * upd_pktstatus bitfields. 313 * The *CKSUMERR fields are only valid if the matching *CHECKED field 314 * is set. 315 */ 316#define EX_UPD_PKTLENMASK 0x00001fff /* 12:0 -> packet length */ 317#define EX_UPD_ERROR 0x00004000 /* rcv error */ 318#define EX_UPD_COMPLETE 0x00008000 /* rcv complete */ 319#define EX_UPD_OVERRUN 0x00010000 /* rcv overrun */ 320#define EX_UPD_RUNT 0x00020000 /* pkt < 60 bytes */ 321#define EX_UPD_ALIGNERR 0x00040000 /* alignment error */ 322#define EX_UPD_CRCERR 0x00080000 /* CRC error */ 323#define EX_UPD_OVERSIZED 0x00100000 /* oversize frame */ 324#define EX_UPD_DRIBBLEBITS 0x00800000 /* pkt had dribble bits */ 325#define EX_UPD_OVERFLOW 0x01000000 /* insufficient space for pkt */ 326#define EX_UPD_IPCKSUMERR 0x02000000 /* IP cksum error (90xB) */ 327#define EX_UPD_TCPCKSUMERR 0x04000000 /* TCP cksum error (90xB) */ 328#define EX_UPD_UDPCKSUMERR 0x08000000 /* UDP cksum error (90xB) */ 329#define EX_UPD_IPCHECKED 0x20000000 /* IP cksum done */ 330#define EX_UPD_TCPCHECKED 0x40000000 /* TCP cksum done */ 331#define EX_UPD_UDPCHECKED 0x80000000 /* UDP cksum done */ 332 333#define EX_UPD_ERR 0x001f4000 /* Errors we check for */ 334#define EX_UPD_ERR_VLAN 0x000f0000 /* same for 802.1q */ 335