1/* $NetBSD: dwc_gmac_reg.h,v 1.22 2024/02/27 08:21:24 skrll Exp $ */ 2 3/*- 4 * Copyright (c) 2013, 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry and Martin Husemann. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32#define AWIN_GMAC_MAC_CONF 0x0000 33#define AWIN_GMAC_MAC_FFILT 0x0004 34#define AWIN_GMAC_MAC_HTHIGH 0x0008 35#define AWIN_GMAC_MAC_HTLOW 0x000c 36#define AWIN_GMAC_MAC_MIIADDR 0x0010 37#define AWIN_GMAC_MAC_MIIDATA 0x0014 38#define AWIN_GMAC_MAC_FLOWCTRL 0x0018 39#define AWIN_GMAC_MAC_VLANTAG 0x001c 40#define AWIN_GMAC_MAC_VERSION 0x0020 /* not always implemented? */ 41#define AWIN_GMAC_MAC_INTR 0x0038 42#define AWIN_GMAC_MAC_INTMASK 0x003c 43#define AWIN_GMAC_MAC_ADDR0HI 0x0040 44#define AWIN_GMAC_MAC_ADDR0LO 0x0044 45#define AWIN_GMAC_MII_STATUS 0x00D8 46 47#define AWIN_GMAC_MAC_CONF_DISABLEJABBER __BIT(22) /* jabber disable */ 48#define AWIN_GMAC_MAC_CONF_FRAMEBURST __BIT(21) /* allow TX frameburst when 49 in half duplex mode */ 50#define AWIN_GMAC_MAC_CONF_MIISEL __BIT(15) /* select MII phy */ 51#define AWIN_GMAC_MAC_CONF_FES100 __BIT(14) /* 100 mbit mode */ 52#define AWIN_GMAC_MAC_CONF_DISABLERXOWN __BIT(13) /* do not receive our own 53 TX frames in half duplex 54 mode */ 55#define AWIN_GMAC_MAC_CONF_FULLDPLX __BIT(11) /* select full duplex */ 56#define AWIN_GMAC_MAC_CONF_ACS __BIT(7) /* auto pad/CRC stripping */ 57#define AWIN_GMAC_MAC_CONF_TXENABLE __BIT(3) /* enable TX dma engine */ 58#define AWIN_GMAC_MAC_CONF_RXENABLE __BIT(2) /* enable RX dma engine */ 59 60#define AWIN_GMAC_MAC_FFILT_RA __BIT(31) /* receive all mode */ 61#define AWIN_GMAC_MAC_FFILT_HPF __BIT(10) /* hash or perfect filter */ 62#define AWIN_GMAC_MAC_FFILT_SAF __BIT(9) /* source address filter */ 63#define AWIN_GMAC_MAC_FFILT_SAIF __BIT(8) /* inverse filtering */ 64#define AWIN_GMAC_MAC_FFILT_DBF __BIT(5) /* disable broadcast frames */ 65#define AWIN_GMAC_MAC_FFILT_PM __BIT(4) /* promiscuous multicast */ 66#define AWIN_GMAC_MAC_FFILT_DAIF __BIT(3) /* DA inverse filtering */ 67#define AWIN_GMAC_MAC_FFILT_HMC __BIT(2) /* multicast hash compare */ 68#define AWIN_GMAC_MAC_FFILT_HUC __BIT(1) /* unicast hash compare */ 69#define AWIN_GMAC_MAC_FFILT_PR __BIT(0) /* promiscuous mode */ 70 71#define AWIN_GMAC_MAC_INT_LPI __BIT(10) 72#define AWIN_GMAC_MAC_INT_TSI __BIT(9) 73#define AWIN_GMAC_MAC_INT_ANEG __BIT(2) 74#define AWIN_GMAC_MAC_INT_LINKCHG __BIT(1) 75#define AWIN_GMAC_MAC_INT_RGSMII __BIT(0) 76 77#define AWIN_GMAC_MAC_FLOWCTRL_PAUSE __BITS(31,16) 78#define AWIN_GMAC_MAC_FLOWCTRL_RFE __BIT(2) 79#define AWIN_GMAC_MAC_FLOWCTRL_TFE __BIT(1) 80#define AWIN_GMAC_MAC_FLOWCTRL_BUSY __BIT(0) 81 82#define GMAC_MMC_CTRL 0x0100 /* MMC control */ 83#define GMAC_MMC_RX_INTR 0x0104 /* MMC RX interrupt */ 84#define GMAC_MMC_TX_INTR 0x0108 /* MMC TX interrupt */ 85#define GMAC_MMC_RX_INT_MSK 0x010c /* MMC RX interrupt mask */ 86#define GMAC_MMC_TX_INT_MSK 0x0110 /* MMC TX interrupt mask */ 87#define GMAC_MMC_TXOCTETCNT_GB 0x0114 /* TX octet good+bad */ 88#define GMAC_MMC_TXFRMCNT_GB 0x0118 /* TX frame good+bad */ 89#define GMAC_MMC_TXUNDFLWERR 0x0148 /* TX underflow */ 90#define GMAC_MMC_TXCARERR 0x0160 /* TX carrier error */ 91#define GMAC_MMC_TXOCTETCNT_G 0x0164 /* TX octet good */ 92#define GMAC_MMC_TXFRMCNT_G 0x0168 /* TX frame good */ 93#define GMAC_MMC_RXFRMCNT_GB 0x0180 /* RX frame good+bad */ 94#define GMAC_MMC_RXOCTETCNT_GB 0x0184 /* RX octet good+bad */ 95#define GMAC_MMC_RXOCTETCNT_G 0x0188 /* RX octet good */ 96#define GMAC_MMC_RXMCFRMCNT_G 0x0190 /* RX mcast frame good */ 97#define GMAC_MMC_RXCRCERR 0x0194 /* RX CRC error */ 98#define GMAC_MMC_RXLENERR 0x01c8 /* RX length error */ 99#define GMAC_MMC_RXFIFOOVRFLW 0x01d4 /* RX FIFO overflow */ 100#define GMAC_MMC_IPC_INT_MSK 0x0200 /* RX csum offload intr mask */ 101#define GMAC_MMC_IPC_INTR 0x0208 /* RX csum offload interrupt */ 102#define GMAC_MMC_RXIPV4GFRM 0x0210 /* RX IPv4 good frame */ 103#define GMAC_MMC_RXIPV4HDERRFRM 0x0214 /* RX IPv4 header error */ 104#define GMAC_MMC_RXIPV6GFRM 0x0224 /* RX IPv6 good frame */ 105#define GMAC_MMC_RXIPV6HDERRFRM 0x0228 /* RX IPv6 header error */ 106#define GMAC_MMC_RXUDPERRFRM 0x0234 /* RX UDP csum error frame */ 107#define GMAC_MMC_RXTCPERRFRM 0x023c /* RX TCP csum error frame */ 108#define GMAC_MMC_RXICMPERRFRM 0x0244 /* RX ICMP csum error frame */ 109#define GMAC_MMC_RXIPV4HDERROCT 0x0254 /* RX IPv4 header error octets */ 110#define GMAC_MMC_RXIPV6HDERROCT 0x0268 /* RX IPv6 header error octets */ 111#define GMAC_MMC_RXUDPERROCT 0x0274 /* RX UDP error octets */ 112#define GMAC_MMC_RXTCPERROCT 0x027c /* RX TCP error octets */ 113#define GMAC_MMC_RXICMPERROCT 0x0280 /* RX ICMP error octets */ 114 115#define GMAC_MMC_CTRL_FHP __BIT(5) /* Full-Half preset */ 116#define GMAC_MMC_CTRL_CP __BIT(4) /* Counters preset */ 117#define GMAC_MMC_CTRL_MCF __BIT(3) /* MMC counter freeze */ 118#define GMAC_MMC_CTRL_ROR __BIT(2) /* reset on read */ 119#define GMAC_MMC_CTRL_CSR __BIT(1) /* Counter stop rollover */ 120#define GMAC_MMC_CTRL_CR __BIT(0) /* Counters reset */ 121 122#define AWIN_GMAC_DMA_BUSMODE 0x1000 123#define AWIN_GMAC_DMA_TXPOLL 0x1004 124#define AWIN_GMAC_DMA_RXPOLL 0x1008 125#define AWIN_GMAC_DMA_RX_ADDR 0x100c 126#define AWIN_GMAC_DMA_TX_ADDR 0x1010 127#define AWIN_GMAC_DMA_STATUS 0x1014 128#define AWIN_GMAC_DMA_OPMODE 0x1018 129#define AWIN_GMAC_DMA_INTENABLE 0x101c 130#define AWIN_GMAC_DMA_CUR_TX_DESC 0x1048 131#define AWIN_GMAC_DMA_CUR_RX_DESC 0x104c 132#define AWIN_GMAC_DMA_CUR_TX_BUFADDR 0x1050 133#define AWIN_GMAC_DMA_CUR_RX_BUFADDR 0x1054 134#define AWIN_GMAC_DMA_HWFEATURES 0x1058 /* not always implemented? */ 135 136#define GMAC_MII_PHY_MASK __BITS(15,11) 137#define GMAC_MII_REG_MASK __BITS(10,6) 138 139#define GMAC_MII_BUSY __BIT(0) 140#define GMAC_MII_WRITE __BIT(1) 141#define GMAC_MII_CLK_60_100M_DIV42 0x0 142#define GMAC_MII_CLK_100_150M_DIV62 0x1 143#define GMAC_MII_CLK_25_35M_DIV16 0x2 144#define GMAC_MII_CLK_35_60M_DIV26 0x3 145#define GMAC_MII_CLK_150_250M_DIV102 0x4 146#define GMAC_MII_CLK_250_300M_DIV124 0x5 147#define GMAC_MII_CLK_DIV4 0x8 148#define GMAC_MII_CLK_DIV6 0x9 149#define GMAC_MII_CLK_DIV8 0xa 150#define GMAC_MII_CLK_DIV10 0xb 151#define GMAC_MII_CLK_DIV12 0xc 152#define GMAC_MII_CLK_DIV14 0xd 153#define GMAC_MII_CLK_DIV16 0xe 154#define GMAC_MII_CLK_DIV18 0xf 155#define GMAC_MII_CLKMASK __BITS(5,2) 156 157#define GMAC_BUSMODE_4PBL __BIT(24) 158#define GMAC_BUSMODE_RPBL __BITS(22,17) 159#define GMAC_BUSMODE_FIXEDBURST __BIT(16) 160#define GMAC_BUSMODE_PRIORXTX __BITS(15,14) 161#define GMAC_BUSMODE_PRIORXTX_41 3 162#define GMAC_BUSMODE_PRIORXTX_31 2 163#define GMAC_BUSMODE_PRIORXTX_21 1 164#define GMAC_BUSMODE_PRIORXTX_11 0 165#define GMAC_BUSMODE_PBL __BITS(13,8) /* possible DMA 166 burst len */ 167#define GMAC_BUSMODE_RESET __BIT(0) 168 169#define AWIN_GMAC_MRCOIS __BIT(7) /* MMC RX csum offload intr */ 170#define AWIN_GMAC_MTIS __BIT(6) /* MMC TX interrupt */ 171#define AWIN_GMAC_MRIS __BIT(3) /* MMC RX interrupt */ 172#define AWIN_GMAC_MIS __BIT(4) /* MMC interrupt */ 173#define AWIN_GMAC_PIS __BIT(3) /* PMT interrupt */ 174#define AWIN_GMAC_MII_IRQ __BIT(0) /* RGMII interrupt */ 175 176 177#define GMAC_DMA_OP_DISABLECSDROP __BIT(26) /* disable dropping of 178 frames with TCP/IP 179 checksum errors */ 180#define GMAC_DMA_OP_RXSTOREFORWARD __BIT(25) /* start RX when a 181 full frame is available */ 182#define GMAC_DMA_OP_DISABLERXFLUSH __BIT(24) /* Do not drop frames 183 when out of RX descr. */ 184#define GMAC_DMA_OP_TXSTOREFORWARD __BIT(21) /* start TX when a 185 full frame is available */ 186#define GMAC_DMA_OP_FLUSHTX __BIT(20) /* flush TX fifo */ 187#define GMAC_DMA_OP_TTC __BITS(16,14) /* TX thresh control */ 188#define GMAC_DMA_OP_TXSTART __BIT(13) /* start TX DMA engine */ 189#define GMAC_DMA_OP_RTC __BITS(4,3) /* RX thres control */ 190#define GMAC_DMA_OP_RXSTART __BIT(1) /* start RX DMA engine */ 191 192#define GMAC_DMA_INT_MMC __BIT(27) /* MMC interrupt */ 193#define GMAC_DMA_INT_NIE __BIT(16) /* Normal/Summary */ 194#define GMAC_DMA_INT_AIE __BIT(15) /* Abnormal/Summary */ 195#define GMAC_DMA_INT_ERE __BIT(14) /* Early receive */ 196#define GMAC_DMA_INT_FBE __BIT(13) /* Fatal bus error */ 197#define GMAC_DMA_INT_ETE __BIT(10) /* Early transmit */ 198#define GMAC_DMA_INT_RWE __BIT(9) /* Receive watchdog */ 199#define GMAC_DMA_INT_RSE __BIT(8) /* Receive stopped */ 200#define GMAC_DMA_INT_RUE __BIT(7) /* Receive buffer unavail. */ 201#define GMAC_DMA_INT_RIE __BIT(6) /* Receive interrupt */ 202#define GMAC_DMA_INT_UNE __BIT(5) /* Tx underflow */ 203#define GMAC_DMA_INT_OVE __BIT(4) /* Receive overflow */ 204#define GMAC_DMA_INT_TJE __BIT(3) /* Transmit jabber */ 205#define GMAC_DMA_INT_TUE __BIT(2) /* Transmit buffer unavail. */ 206#define GMAC_DMA_INT_TSE __BIT(1) /* Transmit stopped */ 207#define GMAC_DMA_INT_TIE __BIT(0) /* Transmit interrupt */ 208 209#define GMAC_DMA_INT_MASK __BITS(0,16) /* all possible intr bits */ 210 211#define GMAC_DMA_FEAT_ENHANCED_DESC __BIT(24) 212#define GMAC_DMA_FEAT_RMON __BIT(11) /* MMC */ 213 214struct dwc_gmac_dev_dmadesc { 215 uint32_t ddesc_status0; /* Status / TDES0 */ 216/* both: */ 217#define DDESC_STATUS_OWNEDBYDEV __BIT(31) 218 219/* for RX descriptors */ 220#define DDESC_STATUS_DAFILTERFAIL __BIT(30) 221#define DDESC_STATUS_FRMLENMSK __BITS(29,16) 222#define DDESC_STATUS_RXERROR __BIT(15) 223#define DDESC_STATUS_RXTRUNCATED __BIT(14) 224#define DDESC_STATUS_SAFILTERFAIL __BIT(13) 225#define DDESC_STATUS_RXIPC_GIANTFRAME __BIT(12) 226#define DDESC_STATUS_RXDAMAGED __BIT(11) 227#define DDESC_STATUS_RXVLANTAG __BIT(10) 228#define DDESC_STATUS_RXFIRST __BIT(9) 229#define DDESC_STATUS_RXLAST __BIT(8) 230#define DDESC_STATUS_RXIPC_GIANT __BIT(7) 231#define DDESC_STATUS_RXCOLLISION __BIT(6) 232#define DDESC_STATUS_RXFRAMEETHER __BIT(5) 233#define DDESC_STATUS_RXWATCHDOG __BIT(4) 234#define DDESC_STATUS_RXMIIERROR __BIT(3) 235#define DDESC_STATUS_RXDRIBBLING __BIT(2) 236#define DDESC_STATUS_RXCRC __BIT(1) 237 238 uint32_t ddesc_cntl1; /* Control / TDES1 */ 239 240/* for TX descriptors */ 241#define DDESC_CNTL_TXINT __BIT(31) 242#define DDESC_CNTL_TXLAST __BIT(30) 243#define DDESC_CNTL_TXFIRST __BIT(29) 244#define DDESC_CNTL_TXCHECKINSCTRL __BITS(27,28) 245 246#define DDESC_TXCHECK_DISABLED 0 247#define DDESC_TXCHECK_IP 1 248#define DDESC_TXCHECK_IP_NO_PSE 2 249#define DDESC_TXCHECK_FULL 3 250 251#define DDESC_CNTL_TXCRCDIS __BIT(26) 252#define DDESC_CNTL_TXRINGEND __BIT(25) 253#define DDESC_CNTL_TXCHAIN __BIT(24) 254#define DDESC_CNTL_TXDISPAD __BIT(23) 255 256/* for RX descriptors */ 257#define DDESC_CNTL_RXINTDIS __BIT(31) 258#define DDESC_CNTL_RXRINGEND __BIT(25) 259#define DDESC_CNTL_RXCHAIN __BIT(24) 260 261/* both */ 262#define DDESC_CNTL_SIZE1MASK __BITS(10,0) 263#define DDESC_CNTL_SIZE1SHIFT 0 264#define DDESC_CNTL_SIZE2MASK __BITS(21,11) 265#define DDESC_CNTL_SIZE2SHIFT 11 266 267 uint32_t ddesc_data; /* pointer to buffer data */ 268 uint32_t ddesc_next; /* link to next descriptor */ 269}; 270 271/* Common to enhanced descriptors */ 272 273#define DDESC_DES0_OWN __BIT(31) 274 275#define DDESC_DES1_SIZE2MASK __BITS(28,16) 276#define DDESC_DES1_SIZE1MASK __BITS(12,0) 277 278/* For enhanced TX descriptors */ 279 280#define DDESC_TDES0_IC __BIT(30) 281#define DDESC_TDES0_LS __BIT(29) 282#define DDESC_TDES0_FS __BIT(28) 283#define DDESC_TDES0_TCH __BIT(20) 284 285/* For enhanced RX descriptors */ 286 287#define DDESC_RDES0_FL __BITS(29,16) 288#define DDESC_RDES0_ES __BIT(15) 289#define DDESC_RDES0_LE __BIT(12) 290 291#define DDESC_RDES1_RCH __BIT(14) 292