1/* $NetBSD: dptreg.h,v 1.18 2007/03/04 06:01:54 christos Exp $ */ 2 3/* 4 * Copyright (c) 1999, 2000, 2001 Andrew Doran <ad@NetBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30#ifndef _IC_DPTREG_H_ 31#define _IC_DPTREG_H_ 1 32 33/* Hardware limits */ 34#define DPT_MAX_TARGETS 16 35#define DPT_MAX_LUNS 8 36#define DPT_MAX_CHANNELS 3 37 38/* 39 * HBA registers 40 */ 41#define HA_DATA 0 42#define HA_ERROR 1 43#define HA_DMA_BASE 2 44#define HA_ICMD_CODE2 4 45#define HA_ICMD_CODE1 5 46#define HA_ICMD 6 47 48/* EATA commands. There are many more that we don't define or use. */ 49#define HA_COMMAND 7 50#define CP_PIO_GETCFG 0xf0 /* Read configuration data, PIO */ 51#define CP_PIO_CMD 0xf2 /* Execute command, PIO */ 52#define CP_DMA_GETCFG 0xfd /* Read configuration data, DMA */ 53#define CP_DMA_CMD 0xff /* Execute command, DMA */ 54#define CP_PIO_TRUNCATE 0xf4 /* Truncate transfer command, PIO */ 55#define CP_RESET 0xf9 /* Reset controller and SCSI bus */ 56#define CP_REBOOT 0x06 /* Reboot controller (last resort) */ 57#define CP_IMMEDIATE 0xfa /* EATA immediate command */ 58#define CPI_GEN_ABORT 0x00 /* Generic abort */ 59#define CPI_SPEC_RESET 0x01 /* Specific reset */ 60#define CPI_BUS_RESET 0x02 /* Bus reset */ 61#define CPI_SPEC_ABORT 0x03 /* Specific abort */ 62#define CPI_QUIET_INTR 0x04 /* ?? */ 63#define CPI_ROM_DL_EN 0x05 /* ?? */ 64#define CPI_COLD_BOOT 0x06 /* Cold boot HBA */ 65#define CPI_FORCE_IO 0x07 /* ?? */ 66#define CPI_BUS_OFFLINE 0x08 /* Set SCSI bus offline */ 67#define CPI_RESET_MSKD_BUS 0x09 /* Reset masked bus */ 68#define CPI_POWEROFF_WARN 0x0a /* Power about to fail */ 69 70#define HA_STATUS 7 71#define HA_ST_ERROR 0x01 72#define HA_ST_MORE 0x02 73#define HA_ST_CORRECTD 0x04 74#define HA_ST_DRQ 0x08 75#define HA_ST_SEEK_COMPLETE 0x10 76#define HA_ST_WRT_FLT 0x20 77#define HA_ST_READY 0x40 78#define HA_ST_BUSY 0x80 79#define HA_ST_DATA_RDY (HA_ST_SEEK_COMPLETE|HA_ST_READY|HA_ST_DRQ) 80 81#define HA_AUX_STATUS 8 82#define HA_AUX_BUSY 0x01 83#define HA_AUX_INTR 0x02 84 85/* 86 * Structure of an EATA command packet. 87 */ 88struct eata_cp { 89 u_int8_t cp_ctl0; /* Control flags 0 */ 90 u_int8_t cp_senselen; /* Request sense length */ 91 u_int8_t cp_unused0[3]; /* Unused */ 92 u_int8_t cp_ctl1; /* Control flags 1 */ 93 u_int8_t cp_ctl2; /* Control flags 2 */ 94 u_int8_t cp_ctl3; /* Control flags 3 */ 95 u_int8_t cp_ctl4; /* Control flags 4 */ 96 u_int8_t cp_msg[3]; /* Message bytes 0-3 */ 97 u_int8_t cp_cdb_cmd; /* SCSI CDB */ 98 u_int8_t cp_cdb_more0[3]; /* SCSI CDB */ 99 u_int8_t cp_cdb_len; /* SCSI CDB */ 100 u_int8_t cp_cdb_more1[7]; /* SCSI CDB */ 101 102 u_int32_t cp_datalen; /* Bytes of data/SG list */ 103 u_int32_t cp_ccbid; /* ID of software CCB */ 104 u_int32_t cp_dataaddr; /* Addr of data/SG list */ 105 u_int32_t cp_stataddr; /* Addr of status packet */ 106 u_int32_t cp_senseaddr; /* Addr of req. sense */ 107} __packed; 108 109struct eata_ucp { 110 u_int8_t ucp_cp[sizeof(struct eata_cp) - 5*4]; /* XXX */ 111 u_long ucp_datalen; 112 u_long ucp_ccbid; 113 void * ucp_dataaddr; 114 void * ucp_stataddr; 115 void * ucp_senseaddr; 116 u_long ucp_timeout; 117 u_int8_t ucp_hstatus; 118 u_int8_t ucp_tstatus; 119 u_int8_t ucp_retries; 120 u_int8_t ucp_padding; 121} __packed; 122 123#define CP_C0_SCSI_RESET 0x01 /* Cause a bus reset */ 124#define CP_C0_HBA_INIT 0x02 /* Reinitialize HBA */ 125#define CP_C0_AUTO_SENSE 0x04 /* Auto request sense on error */ 126#define CP_C0_SCATTER 0x08 /* Do scatter/gather I/O */ 127#define CP_C0_QUICK 0x10 /* Return no status packet */ 128#define CP_C0_INTERPRET 0x20 /* HBA interprets SCSI CDB */ 129#define CP_C0_DATA_OUT 0x40 /* Data out phase */ 130#define CP_C0_DATA_IN 0x80 /* Data in phase */ 131 132#define CP_C1_TO_PHYS 0x01 /* Send to RAID component */ 133#define CP_C1_RESERVED 0xfe 134 135#define CP_C2_PHYS_UNIT 0x01 /* Physical unit on mirrored pair */ 136#define CP_C2_NO_AT 0x02 /* No address translation */ 137#define CP_C2_NO_CACHE 0x04 /* No HBA caching */ 138#define CP_C2_RESERVED 0xf8 139 140#define CP_C3_ID_MASK 0x1f /* Target ID */ 141#define CP_C3_ID_SHIFT 0 142#define CP_C3_CHANNEL_MASK 0xe0 /* Target channel */ 143#define CP_C3_CHANNEL_SHIFT 5 144 145#define CP_C4_LUN_MASK 0x07 /* Target LUN */ 146#define CP_C4_LUN_SHIFT 0 147#define CP_C4_RESERVED 0x18 148#define CP_C4_LUN_TAR 0x20 /* CP is for target ROUTINE */ 149#define CP_C4_DIS_PRI 0x40 /* Give disconnect privilege */ 150#define CP_C4_IDENTIFY 0x80 /* Always true */ 151 152/* 153 * EATA status packet as returned by controller upon command completion. It 154 * contains status, message info and a handle on the initiating CCB. 155 */ 156struct eata_sp { 157 u_int8_t sp_hba_status; /* Host adapter status */ 158 u_int8_t sp_scsi_status; /* SCSI bus status */ 159 u_int8_t sp_reserved[2]; /* Reserved */ 160 u_int32_t sp_inv_residue; /* Bytes not transferred */ 161 u_int32_t sp_ccbid; /* ID of software CCB */ 162 u_int8_t sp_id_message; 163 u_int8_t sp_que_message; 164 u_int8_t sp_tag_message; 165 u_int8_t sp_messages[9]; 166} __packed; 167 168/* 169 * HBA status as returned by status packet. Bit 7 signals end of command. 170 */ 171#define SP_HBA_NO_ERROR 0x00 /* No error on command */ 172#define SP_HBA_ERROR_SEL_TO 0x01 /* Device selection timeout */ 173#define SP_HBA_ERROR_CMD_TO 0x02 /* Device command timeout */ 174#define SP_HBA_ERROR_RESET 0x03 /* SCSI bus was reset */ 175#define SP_HBA_INIT_POWERUP 0x04 /* Initial controller power up */ 176#define SP_HBA_UNX_BUSPHASE 0x05 /* Unexpected bus phase */ 177#define SP_HBA_UNX_BUS_FREE 0x06 /* Unexpected bus free */ 178#define SP_HBA_BUS_PARITY 0x07 /* SCSI bus parity error */ 179#define SP_HBA_SCSI_HUNG 0x08 /* SCSI bus hung */ 180#define SP_HBA_UNX_MSGRJCT 0x09 /* Unexpected message reject */ 181#define SP_HBA_RESET_STUCK 0x0a /* SCSI bus reset stuck */ 182#define SP_HBA_RSENSE_FAIL 0x0b /* Auto-request sense failed */ 183#define SP_HBA_PARITY 0x0c /* HBA memory parity error */ 184#define SP_HBA_ABORT_NA 0x0d /* CP aborted - not on bus */ 185#define SP_HBA_ABORTED 0x0e /* CP aborted - was on bus */ 186#define SP_HBA_RESET_NA 0x0f /* CP reset - not on bus */ 187#define SP_HBA_RESET 0x10 /* CP reset - was on bus */ 188#define SP_HBA_ECC 0x11 /* HBA memory ECC error */ 189#define SP_HBA_PCI_PARITY 0x12 /* PCI parity error */ 190#define SP_HBA_PCI_MASTER 0x13 /* PCI master abort */ 191#define SP_HBA_PCI_TARGET 0x14 /* PCI target abort */ 192#define SP_HBA_PCI_SIG_TARGET 0x15 /* PCI signalled target abort */ 193#define SP_HBA_ABORT 0x20 /* Software abort (too many retries) */ 194 195/* 196 * Scatter-gather list element. 197 */ 198struct eata_sg { 199 u_int32_t sg_addr; 200 u_int32_t sg_len; 201} __packed; 202 203/* 204 * EATA configuration data as returned by HBA. XXX This is bogus - it 205 * doesn't sync up with the structure FreeBSD uses. [ad] 206 */ 207struct eata_cfg { 208 u_int8_t ec_devtype; 209 u_int8_t ec_pagecode; 210 u_int8_t ec_reserved0; 211 u_int8_t ec_cfglen; /* Length in bytes past here */ 212 u_int8_t ec_eatasig[4]; /* EATA signature */ 213 u_int8_t ec_eataversion; /* EATA version number */ 214 u_int8_t ec_feat0; /* First feature byte */ 215 u_int8_t ec_padlength[2]; /* Pad bytes for PIO cmds */ 216 u_int8_t ec_hba[4]; /* Host adapter SCSI IDs */ 217 u_int8_t ec_cplen[4]; /* Command packet length */ 218 u_int8_t ec_splen[4]; /* Status packet length */ 219 u_int8_t ec_queuedepth[2]; /* Controller queue depth */ 220 u_int8_t ec_reserved1[2]; 221 u_int8_t ec_sglen[2]; /* Maximum s/g list size */ 222 u_int8_t ec_feat1; /* 2nd feature byte */ 223 u_int8_t ec_irq; /* IRQ address */ 224 u_int8_t ec_feat2; /* 3rd feature byte */ 225 u_int8_t ec_feat3; /* 4th feature byte */ 226 u_int8_t ec_maxlun; /* Maximum LUN supported */ 227 u_int8_t ec_feat4; /* 5th feature byte */ 228 u_int8_t ec_raidnum; /* RAID host adapter humber */ 229} __packed; 230 231#define EC_F0_OVERLAP_CMDS 0x01 /* Overlapped cmds supported */ 232#define EC_F0_TARGET_MODE 0x02 /* Target mode supported */ 233#define EC_F0_TRUNC_NOT_REC 0x04 /* Truncate cmd not supported */ 234#define EC_F0_MORE_SUPPORTED 0x08 /* More cmd supported */ 235#define EC_F0_DMA_SUPPORTED 0x10 /* DMA mode supported */ 236#define EC_F0_DMA_NUM_VALID 0x20 /* DMA channel field is valid */ 237#define EC_F0_ATA_DEV 0x40 /* This is an ATA device */ 238#define EC_F0_HBA_VALID 0x80 /* HBA field is valid */ 239 240#define EC_F1_IRQ_NUM_MASK 0x0f /* IRQ number mask */ 241#define EC_F1_IRQ_NUM_SHIFT 0 242#define EC_F1_IRQ_TRIGGER 0x10 /* IRQ trigger: 0 = edge, 1 = level */ 243#define EC_F1_SECONDARY 0x20 /* Controller not at address 0x170 */ 244#define EC_F1_DMA_NUM_MASK 0xc0 /* DMA channel *index* for ISA */ 245#define EC_F1_DMA_NUM_SHIFT 6 246 247#define EC_F2_ISA_IO_DISABLE 0x01 /* ISA I/O address disabled */ 248#define EC_F2_FORCE_ADDR 0x02 /* HBA forced to EISA/ISA address */ 249#define EC_F2_SG_64K 0x04 /* 64kB of scatter/gather space */ 250#define EC_F2_SG_UNALIGNED 0x08 /* Can do unaligned scatter/gather */ 251#define EC_F2_RESERVED0 0x10 /* Reserved */ 252#define EC_F2_RESERVED1 0x20 /* Reserved */ 253#define EC_F2_RESERVED2 0x40 /* Reserved */ 254#define EC_F2_RESERVED3 0x40 /* Reserved */ 255 256#define EC_F3_MAX_TARGET_MASK 0x1f /* Maximum target ID supported */ 257#define EC_F3_MAX_TARGET_SHIFT 0 258#define EC_F3_MAX_CHANNEL_MASK 0xe0 /* Maximum channel ID supported */ 259#define EC_F3_MAX_CHANNEL_SHIFT 5 260 261#define EC_F4_RESERVED0 0x01 /* Reserved */ 262#define EC_F4_RESERVED1 0x02 /* Reserved */ 263#define EC_F4_RESERVED2 0x04 /* Reserved */ 264#define EC_F4_AUTO_TERM 0x08 /* Supports auto termination */ 265#define EC_F4_PCIM1 0x10 /* PCI M1 chipset */ 266#define EC_F4_BOGUS_RAID_ID 0x20 /* RAID ID may be questionable */ 267#define EC_F4_HBA_PCI 0x40 /* PCI adapter */ 268#define EC_F4_HBA_EISA 0x80 /* EISA adapter */ 269 270/* 271 * How SCSI inquiry data breaks down for EATA boards. 272 */ 273struct eata_inquiry_data { 274 u_int8_t ei_device; 275 u_int8_t ei_dev_qual2; 276 u_int8_t ei_version; 277 u_int8_t ei_response_format; 278 u_int8_t ei_additional_length; 279 u_int8_t ei_unused[2]; 280 u_int8_t ei_flags; 281 char ei_vendor[8]; /* Vendor, e.g: DPT, NEC */ 282 char ei_model[7]; /* Model number */ 283 char ei_suffix[9]; /* Model number suffix */ 284 char ei_fw[3]; /* Firmware */ 285 char ei_fwrev[1]; /* Firmware revision */ 286 u_int8_t ei_extra[8]; 287} __packed; 288 289#endif /* !defined _IC_DPTREG_H_ */ 290