dp83932.c revision 1.3
1/* $NetBSD: dp83932.c,v 1.3 2001/07/19 16:25:24 thorpej Exp $ */ 2 3/*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39/* 40 * Device driver for the National Semiconductor DP83932 41 * Systems-Oriented Network Interface Controller (SONIC). 42 */ 43 44#include "bpfilter.h" 45 46#include <sys/param.h> 47#include <sys/systm.h> 48#include <sys/mbuf.h> 49#include <sys/malloc.h> 50#include <sys/kernel.h> 51#include <sys/socket.h> 52#include <sys/ioctl.h> 53#include <sys/errno.h> 54#include <sys/device.h> 55 56#include <uvm/uvm_extern.h> 57 58#include <net/if.h> 59#include <net/if_dl.h> 60#include <net/if_ether.h> 61 62#if NBPFILTER > 0 63#include <net/bpf.h> 64#endif 65 66#include <machine/bus.h> 67#include <machine/intr.h> 68 69#include <dev/ic/dp83932reg.h> 70#include <dev/ic/dp83932var.h> 71 72void sonic_start(struct ifnet *); 73void sonic_watchdog(struct ifnet *); 74int sonic_ioctl(struct ifnet *, u_long, caddr_t); 75int sonic_init(struct ifnet *); 76void sonic_stop(struct ifnet *, int); 77 78void sonic_shutdown(void *); 79 80void sonic_reset(struct sonic_softc *); 81void sonic_rxdrain(struct sonic_softc *); 82int sonic_add_rxbuf(struct sonic_softc *, int); 83void sonic_set_filter(struct sonic_softc *); 84 85uint16_t sonic_txintr(struct sonic_softc *); 86void sonic_rxintr(struct sonic_softc *); 87 88int sonic_copy_small = 0; 89 90/* 91 * sonic_attach: 92 * 93 * Attach a SONIC interface to the system. 94 */ 95void 96sonic_attach(struct sonic_softc *sc, const uint8_t *enaddr) 97{ 98 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 99 int i, rseg, error; 100 bus_dma_segment_t seg; 101 size_t cdatasize; 102 103 /* 104 * Allocate the control data structures, and create and load the 105 * DMA map for it. 106 */ 107 if (sc->sc_32bit) 108 cdatasize = sizeof(struct sonic_control_data32); 109 else 110 cdatasize = sizeof(struct sonic_control_data16); 111 112 if ((error = bus_dmamem_alloc(sc->sc_dmat, cdatasize, 113 PAGE_SIZE, (64 * 1024), &seg, 1, &rseg, 114 BUS_DMA_NOWAIT)) != 0) { 115 printf("%s: unable to allocate control data, error = %d\n", 116 sc->sc_dev.dv_xname, error); 117 goto fail_0; 118 } 119 120 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 121 cdatasize, (caddr_t *) &sc->sc_cdata16, 122 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 123 printf("%s: unable to map control data, error = %d\n", 124 sc->sc_dev.dv_xname, error); 125 goto fail_1; 126 } 127 128 if ((error = bus_dmamap_create(sc->sc_dmat, 129 cdatasize, 1, cdatasize, 0, BUS_DMA_NOWAIT, 130 &sc->sc_cddmamap)) != 0) { 131 printf("%s: unable to create control data DMA map, " 132 "error = %d\n", sc->sc_dev.dv_xname, error); 133 goto fail_2; 134 } 135 136 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 137 sc->sc_cdata16, cdatasize, NULL, BUS_DMA_NOWAIT)) != 0) { 138 printf("%s: unable to load control data DMA map, error = %d\n", 139 sc->sc_dev.dv_xname, error); 140 goto fail_3; 141 } 142 143 /* 144 * Create the transmit buffer DMA maps. 145 */ 146 for (i = 0; i < SONIC_NTXDESC; i++) { 147 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 148 SONIC_NTXFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 149 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 150 printf("%s: unable to create tx DMA map %d, " 151 "error = %d\n", sc->sc_dev.dv_xname, i, error); 152 goto fail_4; 153 } 154 } 155 156 /* 157 * Create the receive buffer DMA maps. 158 */ 159 for (i = 0; i < SONIC_NRXDESC; i++) { 160 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 161 MCLBYTES, 0, BUS_DMA_NOWAIT, 162 &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 163 printf("%s: unable to create rx DMA map %d, " 164 "error = %d\n", sc->sc_dev.dv_xname, i, error); 165 goto fail_5; 166 } 167 sc->sc_rxsoft[i].ds_mbuf = NULL; 168 } 169 170 /* 171 * Reset the chip to a known state. 172 */ 173 sonic_reset(sc); 174 175 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 176 ether_sprintf(enaddr)); 177 178 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 179 ifp->if_softc = sc; 180 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 181 ifp->if_ioctl = sonic_ioctl; 182 ifp->if_start = sonic_start; 183 ifp->if_watchdog = sonic_watchdog; 184 ifp->if_init = sonic_init; 185 ifp->if_stop = sonic_stop; 186 IFQ_SET_READY(&ifp->if_snd); 187 188 /* 189 * Attach the interface. 190 */ 191 if_attach(ifp); 192 ether_ifattach(ifp, enaddr); 193 194 /* 195 * Make sure the interface is shutdown during reboot. 196 */ 197 sc->sc_sdhook = shutdownhook_establish(sonic_shutdown, sc); 198 if (sc->sc_sdhook == NULL) 199 printf("%s: WARNING: unable to establish shutdown hook\n", 200 sc->sc_dev.dv_xname); 201 return; 202 203 /* 204 * Free any resources we've allocated during the failed attach 205 * attempt. Do this in reverse order and fall through. 206 */ 207 fail_5: 208 for (i = 0; i < SONIC_NRXDESC; i++) { 209 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 210 bus_dmamap_destroy(sc->sc_dmat, 211 sc->sc_rxsoft[i].ds_dmamap); 212 } 213 fail_4: 214 for (i = 0; i < SONIC_NTXDESC; i++) { 215 if (sc->sc_txsoft[i].ds_dmamap != NULL) 216 bus_dmamap_destroy(sc->sc_dmat, 217 sc->sc_txsoft[i].ds_dmamap); 218 } 219 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 220 fail_3: 221 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 222 fail_2: 223 bus_dmamem_unmap(sc->sc_dmat, (caddr_t) sc->sc_cdata16, cdatasize); 224 fail_1: 225 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 226 fail_0: 227 return; 228} 229 230/* 231 * sonic_shutdown: 232 * 233 * Make sure the interface is stopped at reboot. 234 */ 235void 236sonic_shutdown(void *arg) 237{ 238 struct sonic_softc *sc = arg; 239 240 sonic_stop(&sc->sc_ethercom.ec_if, 1); 241} 242 243/* 244 * sonic_start: [ifnet interface function] 245 * 246 * Start packet transmission on the interface. 247 */ 248void 249sonic_start(struct ifnet *ifp) 250{ 251 struct sonic_softc *sc = ifp->if_softc; 252 struct mbuf *m0, *m; 253 struct sonic_tda16 *tda16; 254 struct sonic_tda32 *tda32; 255 struct sonic_descsoft *ds; 256 bus_dmamap_t dmamap; 257 int error, olasttx, nexttx, opending, seg, totlen, olseg; 258 259 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 260 return; 261 262 /* 263 * Remember the previous txpending and the current "last txdesc 264 * used" index. 265 */ 266 opending = sc->sc_txpending; 267 olasttx = sc->sc_txlast; 268 269 /* 270 * Loop through the send queue, setting up transmit descriptors 271 * until we drain the queue, or use up all available transmit 272 * descriptors. Leave one at the end for sanity's sake. 273 */ 274 while (sc->sc_txpending < (SONIC_NTXDESC - 1)) { 275 /* 276 * Grab a packet off the queue. 277 */ 278 IFQ_POLL(&ifp->if_snd, m0); 279 if (m0 == NULL) 280 break; 281 m = NULL; 282 283 /* 284 * Get the next available transmit descriptor. 285 */ 286 nexttx = SONIC_NEXTTX(sc->sc_txlast); 287 ds = &sc->sc_txsoft[nexttx]; 288 dmamap = ds->ds_dmamap; 289 290 /* 291 * Load the DMA map. If this fails, the packet either 292 * didn't fit in the allotted number of frags, or we were 293 * short on resources. In this case, we'll copy and try 294 * again. 295 */ 296 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 297 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 298 MGETHDR(m, M_DONTWAIT, MT_DATA); 299 if (m == NULL) { 300 printf("%s: unable to allocate Tx mbuf\n", 301 sc->sc_dev.dv_xname); 302 break; 303 } 304 if (m0->m_pkthdr.len > MHLEN) { 305 MCLGET(m, M_DONTWAIT); 306 if ((m->m_flags & M_EXT) == 0) { 307 printf("%s: unable to allocate Tx " 308 "cluster\n", sc->sc_dev.dv_xname); 309 m_freem(m); 310 break; 311 } 312 } 313 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 314 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 315 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 316 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 317 if (error) { 318 printf("%s: unable to load Tx buffer, " 319 "error = %d\n", sc->sc_dev.dv_xname, error); 320 m_freem(m); 321 break; 322 } 323 } 324 IFQ_DEQUEUE(&ifp->if_snd, m0); 325 if (m != NULL) { 326 m_freem(m0); 327 m0 = m; 328 } 329 330 /* 331 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 332 */ 333 334 /* Sync the DMA map. */ 335 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 336 BUS_DMASYNC_PREWRITE); 337 338 /* 339 * Store a pointer to the packet so we can free it later. 340 */ 341 ds->ds_mbuf = m0; 342 343 /* 344 * Initialize the transmit descriptor. 345 */ 346 totlen = 0; 347 if (sc->sc_32bit) { 348 tda32 = &sc->sc_tda32[nexttx]; 349 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 350 tda32->tda_frags[seg].frag_ptr1 = 351 htosonic32(sc, 352 (dmamap->dm_segs[seg].ds_addr >> 16) & 353 0xffff); 354 tda32->tda_frags[seg].frag_ptr0 = 355 htosonic32(sc, 356 dmamap->dm_segs[seg].ds_addr & 0xffff); 357 tda32->tda_frags[seg].frag_size = 358 htosonic32(sc, dmamap->dm_segs[seg].ds_len); 359 totlen += dmamap->dm_segs[seg].ds_len; 360 } 361 362 /* 363 * Pad the packet out if it's less than the 364 * minimum Ethernet frame size. 365 */ 366 if (totlen < (ETHER_MIN_LEN - ETHER_CRC_LEN)) { 367 tda32->tda_frags[seg - 1].frag_size = 368 htosonic32(sc, 369 dmamap->dm_segs[seg - 1].ds_len + 370 ((ETHER_MIN_LEN - ETHER_CRC_LEN) - totlen)); 371 totlen = ETHER_MIN_LEN - ETHER_CRC_LEN; 372 } 373 374 tda32->tda_status = 0; 375 tda32->tda_pktconfig = 0; 376 tda32->tda_pktsize = htosonic32(sc, totlen); 377 tda32->tda_fragcnt = htosonic32(sc, seg); 378 379 /* Link it up. */ 380 tda32->tda_frags[seg].frag_ptr0 = 381 htosonic32(sc, SONIC_CDTXADDR32(sc, 382 SONIC_NEXTTX(nexttx)) & 0xffff); 383 384 /* Sync the Tx descriptor. */ 385 SONIC_CDTXSYNC32(sc, nexttx, 386 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 387 } else { 388 tda16 = &sc->sc_tda16[nexttx]; 389 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 390 tda16->tda_frags[seg].frag_ptr1 = 391 htosonic16(sc, 392 (dmamap->dm_segs[seg].ds_addr >> 16) & 393 0xffff); 394 tda16->tda_frags[seg].frag_ptr0 = 395 htosonic16(sc, 396 dmamap->dm_segs[seg].ds_addr & 0xffff); 397 tda16->tda_frags[seg].frag_size = 398 htosonic16(sc, dmamap->dm_segs[seg].ds_len); 399 totlen += dmamap->dm_segs[seg].ds_len; 400 } 401 402 /* 403 * Pad the packet out if it's less than the 404 * minimum Ethernet frame size. 405 */ 406 if (totlen < (ETHER_MIN_LEN - ETHER_CRC_LEN)) { 407 tda16->tda_frags[seg - 1].frag_size = 408 htosonic16(sc, 409 dmamap->dm_segs[seg - 1].ds_len + 410 ((ETHER_MIN_LEN - ETHER_CRC_LEN) - totlen)); 411 totlen = ETHER_MIN_LEN - ETHER_CRC_LEN; 412 } 413 414 tda16->tda_status = 0; 415 tda16->tda_pktconfig = 0; 416 tda16->tda_pktsize = htosonic16(sc, totlen); 417 tda16->tda_fragcnt = htosonic16(sc, seg); 418 419 /* Link it up. */ 420 tda16->tda_frags[seg].frag_ptr0 = 421 htosonic16(sc, SONIC_CDTXADDR16(sc, 422 SONIC_NEXTTX(nexttx)) & 0xffff); 423 424 /* Sync the Tx descriptor. */ 425 SONIC_CDTXSYNC16(sc, nexttx, 426 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 427 } 428 429 /* Advance the Tx pointer. */ 430 sc->sc_txpending++; 431 sc->sc_txlast = nexttx; 432 433#if NBPFILTER > 0 434 /* 435 * Pass the packet to any BPF listeners. 436 */ 437 if (ifp->if_bpf) 438 bpf_mtap(ifp->if_bpf, m0); 439#endif 440 } 441 442 if (sc->sc_txpending == (SONIC_NTXDESC - 1)) { 443 /* No more slots left; notify upper layer. */ 444 ifp->if_flags |= IFF_OACTIVE; 445 } 446 447 if (sc->sc_txpending != opending) { 448 /* 449 * We enqueued packets. If the transmitter was idle, 450 * reset the txdirty pointer. 451 */ 452 if (opending == 0) 453 sc->sc_txdirty = SONIC_NEXTTX(olasttx); 454 455 /* 456 * Stop the SONIC on the last packet we've set up, 457 * and clear end-of-list on the descriptor previous 458 * to our new chain. 459 * 460 * NOTE: our `seg' variable should still be valid! 461 */ 462 if (sc->sc_32bit) { 463 olseg = 464 sonic32toh(sc, sc->sc_tda32[olasttx].tda_fragcnt); 465 sc->sc_tda32[sc->sc_txlast].tda_frags[seg].frag_ptr0 |= 466 htosonic32(sc, TDA_LINK_EOL); 467 SONIC_CDTXSYNC32(sc, sc->sc_txlast, 468 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 469 sc->sc_tda32[olasttx].tda_frags[olseg].frag_ptr0 &= 470 htosonic32(sc, ~TDA_LINK_EOL); 471 SONIC_CDTXSYNC32(sc, olasttx, 472 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 473 } else { 474 olseg = 475 sonic16toh(sc, sc->sc_tda16[olasttx].tda_fragcnt); 476 sc->sc_tda16[sc->sc_txlast].tda_frags[seg].frag_ptr0 |= 477 htosonic16(sc, TDA_LINK_EOL); 478 SONIC_CDTXSYNC16(sc, sc->sc_txlast, 479 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 480 sc->sc_tda16[olasttx].tda_frags[olseg].frag_ptr0 &= 481 htosonic16(sc, ~TDA_LINK_EOL); 482 SONIC_CDTXSYNC16(sc, olasttx, 483 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 484 } 485 486 /* Start the transmitter. */ 487 CSR_WRITE(sc, SONIC_CR, CR_TXP); 488 489 /* Set a watchdog timer in case the chip flakes out. */ 490 ifp->if_timer = 5; 491 } 492} 493 494/* 495 * sonic_watchdog: [ifnet interface function] 496 * 497 * Watchdog timer handler. 498 */ 499void 500sonic_watchdog(struct ifnet *ifp) 501{ 502 struct sonic_softc *sc = ifp->if_softc; 503 504 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 505 ifp->if_oerrors++; 506 507 (void) sonic_init(ifp); 508} 509 510/* 511 * sonic_ioctl: [ifnet interface function] 512 * 513 * Handle control requests from the operator. 514 */ 515int 516sonic_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 517{ 518 int s, error; 519 520 s = splnet(); 521 522 switch (cmd) { 523 default: 524 error = ether_ioctl(ifp, cmd, data); 525 if (error == ENETRESET) { 526 /* 527 * Multicast list has changed; set the hardware 528 * filter accordingly. 529 */ 530 (void) sonic_init(ifp); 531 error = 0; 532 } 533 break; 534 } 535 536 splx(s); 537 return (error); 538} 539 540/* 541 * sonic_intr: 542 * 543 * Interrupt service routine. 544 */ 545int 546sonic_intr(void *arg) 547{ 548 struct sonic_softc *sc = arg; 549 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 550 uint16_t isr; 551 int handled = 0, wantinit; 552 553 for (wantinit = 0; wantinit == 0;) { 554 isr = CSR_READ(sc, SONIC_ISR) & sc->sc_imr; 555 if (isr == 0) 556 break; 557 CSR_WRITE(sc, SONIC_ISR, isr); /* ACK */ 558 559 handled = 1; 560 561 if (isr & IMR_PRX) 562 sonic_rxintr(sc); 563 564 if (isr & (IMR_PTX|IMR_TXER)) { 565 if (sonic_txintr(sc) & TCR_FU) { 566 printf("%s: transmit FIFO underrun\n", 567 sc->sc_dev.dv_xname); 568 wantinit = 1; 569 } 570 } 571 572 if (isr & (IMR_RFO|IMR_RBA|IMR_RBE|IMR_RDE)) { 573#define PRINTERR(bit, str) \ 574 if (isr & (bit)) \ 575 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 576 PRINTERR(IMR_RFO, "receive FIFO overrun"); 577 PRINTERR(IMR_RBA, "receive buffer exceeded"); 578 PRINTERR(IMR_RBE, "receive buffers exhausted"); 579 PRINTERR(IMR_RDE, "receive descriptors exhausted"); 580 wantinit = 1; 581 } 582 } 583 584 if (handled) { 585 if (wantinit) 586 (void) sonic_init(ifp); 587 sonic_start(ifp); 588 } 589 590 return (handled); 591} 592 593/* 594 * sonic_txintr: 595 * 596 * Helper; handle transmit complete interrupts. 597 */ 598uint16_t 599sonic_txintr(struct sonic_softc *sc) 600{ 601 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 602 struct sonic_descsoft *ds; 603 struct sonic_tda32 *tda32; 604 struct sonic_tda16 *tda16; 605 uint16_t status, totstat = 0; 606 int i; 607 608 ifp->if_flags &= ~IFF_OACTIVE; 609 610 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 611 i = SONIC_NEXTTX(i), sc->sc_txpending--) { 612 ds = &sc->sc_txsoft[i]; 613 614 if (sc->sc_32bit) { 615 SONIC_CDTXSYNC32(sc, i, 616 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 617 tda32 = &sc->sc_tda32[i]; 618 status = sonic32toh(sc, tda32->tda_status); 619 } else { 620 SONIC_CDTXSYNC16(sc, i, 621 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 622 tda16 = &sc->sc_tda16[i]; 623 status = sonic16toh(sc, tda16->tda_status); 624 } 625 626 if ((status & ~(TCR_EXDIS|TCR_CRCI|TCR_POWC|TCR_PINT)) == 0) 627 break; 628 629 totstat |= status; 630 631 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 632 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 633 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 634 m_freem(ds->ds_mbuf); 635 ds->ds_mbuf = NULL; 636 637 /* 638 * Check for errors and collisions. 639 */ 640 if (status & TCR_PTX) 641 ifp->if_opackets++; 642 else 643 ifp->if_oerrors++; 644 ifp->if_collisions += TDA_STATUS_NCOL(status); 645 } 646 647 /* Update the dirty transmit buffer pointer. */ 648 sc->sc_txdirty = i; 649 650 /* 651 * Cancel the watchdog timer if there are no pending 652 * transmissions. 653 */ 654 if (sc->sc_txpending == 0) 655 ifp->if_timer = 0; 656 657 return (totstat); 658} 659 660/* 661 * sonic_rxintr: 662 * 663 * Helper; handle receive interrupts. 664 */ 665void 666sonic_rxintr(struct sonic_softc *sc) 667{ 668 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 669 struct sonic_descsoft *ds; 670 struct sonic_rda32 *rda32; 671 struct sonic_rda16 *rda16; 672 struct mbuf *m; 673 int i, len; 674 uint16_t status, bytecount, ptr0, ptr1, seqno; 675 676 for (i = sc->sc_rxptr;; i = SONIC_NEXTRX(i)) { 677 ds = &sc->sc_rxsoft[i]; 678 679 if (sc->sc_32bit) { 680 SONIC_CDRXSYNC32(sc, i, 681 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 682 rda32 = &sc->sc_rda32[i]; 683 if (rda32->rda_inuse != 0) 684 break; 685 status = sonic32toh(sc, rda32->rda_status); 686 bytecount = sonic32toh(sc, rda32->rda_bytecount); 687 ptr0 = sonic32toh(sc, rda32->rda_pkt_ptr0); 688 ptr1 = sonic32toh(sc, rda32->rda_pkt_ptr1); 689 seqno = sonic32toh(sc, rda32->rda_seqno); 690 } else { 691 SONIC_CDRXSYNC16(sc, i, 692 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 693 rda16 = &sc->sc_rda16[i]; 694 if (rda16->rda_inuse != 0) 695 break; 696 status = sonic16toh(sc, rda16->rda_status); 697 bytecount = sonic16toh(sc, rda16->rda_bytecount); 698 ptr0 = sonic16toh(sc, rda16->rda_pkt_ptr0); 699 ptr1 = sonic16toh(sc, rda16->rda_pkt_ptr1); 700 seqno = sonic16toh(sc, rda16->rda_seqno); 701 } 702 703 /* 704 * Make absolutely sure this is the only packet 705 * in this receive buffer. Our entire Rx buffer 706 * management scheme depends on this, and if the 707 * SONIC didn't follow our rule, it means we've 708 * misconfigured it. 709 */ 710 KASSERT(status & RCR_LPKT); 711 712 /* 713 * Make sure the packet arrived OK. If an error occurred, 714 * update stats and reset the descriptor. The buffer will 715 * be reused the next time the descriptor comes up in the 716 * ring. 717 */ 718 if ((status & RCR_PRX) == 0) { 719 if (status & RCR_FAER) 720 printf("%s: Rx frame alignment error\n", 721 sc->sc_dev.dv_xname); 722 else if (status & RCR_CRCR) 723 printf("%s: Rx CRC error\n", 724 sc->sc_dev.dv_xname); 725 ifp->if_ierrors++; 726 SONIC_INIT_RXDESC(sc, i); 727 continue; 728 } 729 730 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 731 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 732 733 /* 734 * The SONIC includes the CRC with every packet. 735 */ 736 len = bytecount; 737 738 /* 739 * Ok, if the chip is in 32-bit mode, then receive 740 * buffers must be aligned to 32-bit boundaries, 741 * which means the payload is misaligned. In this 742 * case, we must allocate a new mbuf, and copy the 743 * packet into it, scooted forward 2 bytes to ensure 744 * proper alignment. 745 * 746 * Note, in 16-bit mode, we can configure the SONIC 747 * to do what we want, and we have. 748 */ 749#ifndef __NO_STRICT_ALIGNMENT 750 if (sc->sc_32bit) { 751 MGETHDR(m, M_DONTWAIT, MT_DATA); 752 if (m == NULL) 753 goto dropit; 754 if (len > (MHLEN - 2)) { 755 MCLGET(m, M_DONTWAIT); 756 if ((m->m_flags & M_EXT) == 0) 757 goto dropit; 758 } 759 m->m_data += 2; 760 /* 761 * Note that we use a cluster for incoming frames, 762 * so the buffer is virtually contiguous. 763 */ 764 memcpy(mtod(m, caddr_t), mtod(ds->ds_mbuf, caddr_t), 765 len); 766 SONIC_INIT_RXDESC(sc, i); 767 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 768 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 769 } else 770#endif /* ! __NO_STRICT_ALIGNMENT */ 771 /* 772 * If the packet is small enough to fit in a single 773 * header mbuf, allocate one and copy the data into 774 * it. This greatly reduces memory consumption when 775 * we receive lots of small packets. 776 */ 777 if (sonic_copy_small != 0 && len <= (MHLEN - 2)) { 778 MGETHDR(m, M_DONTWAIT, MT_DATA); 779 if (m == NULL) 780 goto dropit; 781 m->m_data += 2; 782 /* 783 * Note that we use a cluster for incoming frames, 784 * so the buffer is virtually contiguous. 785 */ 786 memcpy(mtod(m, caddr_t), mtod(ds->ds_mbuf, caddr_t), 787 len); 788 SONIC_INIT_RXDESC(sc, i); 789 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 790 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 791 } else { 792 m = ds->ds_mbuf; 793 if (sonic_add_rxbuf(sc, i) != 0) { 794 dropit: 795 ifp->if_ierrors++; 796 SONIC_INIT_RXDESC(sc, i); 797 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 798 ds->ds_dmamap->dm_mapsize, 799 BUS_DMASYNC_PREREAD); 800 continue; 801 } 802 } 803 804 ifp->if_ipackets++; 805 m->m_flags |= M_HASFCS; 806 m->m_pkthdr.rcvif = ifp; 807 m->m_pkthdr.len = m->m_len = len; 808 809#if NBPFILTER > 0 810 /* 811 * Pass this up to any BPF listeners. 812 */ 813 if (ifp->if_bpf) 814 bpf_mtap(ifp->if_bpf, m); 815#endif /* NBPFILTER > 0 */ 816 817 /* Pass it on. */ 818 (*ifp->if_input)(ifp, m); 819 } 820 821 /* Update the receive pointer. */ 822 sc->sc_rxptr = i; 823 CSR_WRITE(sc, SONIC_RWR, SONIC_CDRRADDR(sc, SONIC_PREVRX(i))); 824} 825 826/* 827 * sonic_reset: 828 * 829 * Perform a soft reset on the SONIC. 830 */ 831void 832sonic_reset(struct sonic_softc *sc) 833{ 834 835 CSR_WRITE(sc, SONIC_CR, 0); /* ensure RST is clear */ 836 CSR_WRITE(sc, SONIC_CR, CR_RST); 837 delay(1000); 838 CSR_WRITE(sc, SONIC_CR, 0); 839 delay(1000); 840} 841 842/* 843 * sonic_init: [ifnet interface function] 844 * 845 * Initialize the interface. Must be called at splnet(). 846 */ 847int 848sonic_init(struct ifnet *ifp) 849{ 850 struct sonic_softc *sc = ifp->if_softc; 851 struct sonic_descsoft *ds; 852 int i, error = 0; 853 uint16_t reg; 854 855 /* 856 * Cancel any pending I/O. 857 */ 858 sonic_stop(ifp, 0); 859 860 /* 861 * Reset the SONIC to a known state. 862 */ 863 sonic_reset(sc); 864 865 /* 866 * Bring the SONIC into reset state, and program the DCR. 867 * 868 * Note: We don't bother optimizing the transmit and receive 869 * thresholds, here. We just use the most conservative values: 870 * 871 * - Rx: 4 bytes (RFT0,RFT0 == 0,0) 872 * - Tx: 28 bytes (TFT0,TFT1 == 1,1) 873 */ 874 reg = sc->sc_dcr | DCR_TFT0 | DCR_TFT1; 875 if (sc->sc_32bit) 876 reg |= DCR_DW; 877 CSR_WRITE(sc, SONIC_CR, CR_RST); 878 CSR_WRITE(sc, SONIC_DCR, reg); 879 CSR_WRITE(sc, SONIC_DCR2, sc->sc_dcr2); 880 CSR_WRITE(sc, SONIC_CR, 0); 881 882 /* 883 * Initialize the transmit descriptors. 884 */ 885 if (sc->sc_32bit) { 886 for (i = 0; i < SONIC_NTXDESC; i++) { 887 memset(&sc->sc_tda32[i], 0, sizeof(struct sonic_tda32)); 888 SONIC_CDTXSYNC32(sc, i, 889 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 890 } 891 } else { 892 for (i = 0; i < SONIC_NTXDESC; i++) { 893 memset(&sc->sc_tda16[i], 0, sizeof(struct sonic_tda16)); 894 SONIC_CDTXSYNC16(sc, i, 895 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 896 } 897 } 898 sc->sc_txpending = 0; 899 sc->sc_txdirty = 0; 900 sc->sc_txlast = SONIC_NTXDESC - 1; 901 902 /* 903 * Initialize the receive descriptor ring. 904 */ 905 for (i = 0; i < SONIC_NRXDESC; i++) { 906 ds = &sc->sc_rxsoft[i]; 907 if (ds->ds_mbuf == NULL) { 908 if ((error = sonic_add_rxbuf(sc, i)) != 0) { 909 printf("%s: unable to allocate or map Rx " 910 "buffer %d, error = %d\n", 911 sc->sc_dev.dv_xname, i, error); 912 /* 913 * XXX Should attempt to run with fewer receive 914 * XXX buffers instead of just failing. 915 */ 916 sonic_rxdrain(sc); 917 goto out; 918 } 919 } 920 } 921 sc->sc_rxptr = 0; 922 923 /* Give the transmit ring to the SONIC. */ 924 CSR_WRITE(sc, SONIC_UTDAR, (SONIC_CDTXADDR(sc, 0) >> 16) & 0xffff); 925 CSR_WRITE(sc, SONIC_CTDAR, SONIC_CDTXADDR(sc, 0) & 0xffff); 926 927 /* Give the receive descriptor ring to the SONIC. */ 928 CSR_WRITE(sc, SONIC_URDAR, (SONIC_CDRXADDR(sc, 0) >> 16) & 0xffff); 929 CSR_WRITE(sc, SONIC_CRDAR, SONIC_CDRXADDR(sc, 0) & 0xffff); 930 931 /* Give the receive buffer ring to the SONIC. */ 932 CSR_WRITE(sc, SONIC_URRAR, (SONIC_CDRRADDR(sc, 0) >> 16) & 0xffff); 933 CSR_WRITE(sc, SONIC_RSAR, SONIC_CDRRADDR(sc, 0) & 0xffff); 934 if (sc->sc_32bit) 935 CSR_WRITE(sc, SONIC_REAR, 936 (SONIC_CDRRADDR(sc, SONIC_NRXDESC - 1) + 937 sizeof(struct sonic_rra32)) & 0xffff); 938 else 939 CSR_WRITE(sc, SONIC_REAR, 940 (SONIC_CDRRADDR(sc, SONIC_NRXDESC - 1) + 941 sizeof(struct sonic_rra16)) & 0xffff); 942 CSR_WRITE(sc, SONIC_RRR, SONIC_CDRRADDR(sc, 0) & 0xffff); 943 CSR_WRITE(sc, SONIC_RWR, SONIC_CDRRADDR(sc, SONIC_NRXDESC - 1)); 944 945 /* 946 * Set the End-Of-Buffer counter such that only one packet 947 * will be placed into each buffer we provide. Note we are 948 * following the recommendation of section 3.4.4 of the manual 949 * here, and have "lengthened" the receive buffers accordingly. 950 */ 951 if (sc->sc_32bit) 952 CSR_WRITE(sc, SONIC_EOBC, (ETHER_MAX_LEN + 2) / 2); 953 else 954 CSR_WRITE(sc, SONIC_EOBC, (ETHER_MAX_LEN / 2)); 955 956 /* Reset the receive sequence counter. */ 957 CSR_WRITE(sc, SONIC_RSC, 0); 958 959 /* Clear the tally registers. */ 960 CSR_WRITE(sc, SONIC_CRCETC, 0xffff); 961 CSR_WRITE(sc, SONIC_FAET, 0xffff); 962 CSR_WRITE(sc, SONIC_MPT, 0xffff); 963 964 /* Set the receive filter. */ 965 sonic_set_filter(sc); 966 967 /* 968 * Set the interrupt mask register. 969 */ 970 sc->sc_imr = IMR_RFO | IMR_RBA | IMR_RBE | IMR_RDE | 971 IMR_TXER | IMR_PTX | IMR_PRX; 972 CSR_WRITE(sc, SONIC_IMR, sc->sc_imr); 973 974 /* 975 * Start the receive process in motion. Note, we don't 976 * start the transmit process until we actually try to 977 * transmit packets. 978 */ 979 CSR_WRITE(sc, SONIC_CR, CR_RXEN | CR_RRRA); 980 981 /* 982 * ...all done! 983 */ 984 ifp->if_flags |= IFF_RUNNING; 985 ifp->if_flags &= ~IFF_OACTIVE; 986 987 out: 988 if (error) 989 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 990 return (error); 991} 992 993/* 994 * sonic_rxdrain: 995 * 996 * Drain the receive queue. 997 */ 998void 999sonic_rxdrain(struct sonic_softc *sc) 1000{ 1001 struct sonic_descsoft *ds; 1002 int i; 1003 1004 for (i = 0; i < SONIC_NRXDESC; i++) { 1005 ds = &sc->sc_rxsoft[i]; 1006 if (ds->ds_mbuf != NULL) { 1007 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1008 m_freem(ds->ds_mbuf); 1009 ds->ds_mbuf = NULL; 1010 } 1011 } 1012} 1013 1014/* 1015 * sonic_stop: [ifnet interface function] 1016 * 1017 * Stop transmission on the interface. 1018 */ 1019void 1020sonic_stop(struct ifnet *ifp, int disable) 1021{ 1022 struct sonic_softc *sc = ifp->if_softc; 1023 struct sonic_descsoft *ds; 1024 int i; 1025 1026 /* 1027 * Disable interrupts. 1028 */ 1029 CSR_WRITE(sc, SONIC_IMR, 0); 1030 1031 /* 1032 * Stop the transmitter, receiver, and timer. 1033 */ 1034 CSR_WRITE(sc, SONIC_CR, CR_HTX|CR_RXDIS|CR_STP); 1035 for (i = 0; i < 1000; i++) { 1036 if ((CSR_READ(sc, SONIC_CR) & (CR_TXP|CR_RXEN|CR_ST)) == 0) 1037 break; 1038 delay(2); 1039 } 1040 if ((CSR_READ(sc, SONIC_CR) & (CR_TXP|CR_RXEN|CR_ST)) != 0) 1041 printf("%s: SONIC failed to stop\n", sc->sc_dev.dv_xname); 1042 1043 /* 1044 * Release any queued transmit buffers. 1045 */ 1046 for (i = 0; i < SONIC_NTXDESC; i++) { 1047 ds = &sc->sc_txsoft[i]; 1048 if (ds->ds_mbuf != NULL) { 1049 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1050 m_freem(ds->ds_mbuf); 1051 ds->ds_mbuf = NULL; 1052 } 1053 } 1054 1055 if (disable) 1056 sonic_rxdrain(sc); 1057 1058 /* 1059 * Mark the interface down and cancel the watchdog timer. 1060 */ 1061 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1062 ifp->if_timer = 0; 1063} 1064 1065/* 1066 * sonic_add_rxbuf: 1067 * 1068 * Add a receive buffer to the indicated descriptor. 1069 */ 1070int 1071sonic_add_rxbuf(struct sonic_softc *sc, int idx) 1072{ 1073 struct sonic_descsoft *ds = &sc->sc_rxsoft[idx]; 1074 struct mbuf *m; 1075 int error; 1076 1077 MGETHDR(m, M_DONTWAIT, MT_DATA); 1078 if (m == NULL) 1079 return (ENOBUFS); 1080 1081 MCLGET(m, M_DONTWAIT); 1082 if ((m->m_flags & M_EXT) == 0) { 1083 m_freem(m); 1084 return (ENOBUFS); 1085 } 1086 1087 if (ds->ds_mbuf != NULL) 1088 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1089 1090 ds->ds_mbuf = m; 1091 1092 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1093 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1094 BUS_DMA_READ|BUS_DMA_NOWAIT); 1095 if (error) { 1096 printf("%s: can't load rx DMA map %d, error = %d\n", 1097 sc->sc_dev.dv_xname, idx, error); 1098 panic("sonic_add_rxbuf"); /* XXX */ 1099 } 1100 1101 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1102 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1103 1104 SONIC_INIT_RXDESC(sc, idx); 1105 1106 return (0); 1107} 1108 1109static void 1110sonic_set_camentry(struct sonic_softc *sc, int entry, const uint8_t *enaddr) 1111{ 1112 1113 if (sc->sc_32bit) { 1114 struct sonic_cda32 *cda = &sc->sc_cda32[entry]; 1115 1116 cda->cda_entry = htosonic32(sc, entry); 1117 cda->cda_addr0 = htosonic32(sc, enaddr[0] | (enaddr[1] << 8)); 1118 cda->cda_addr1 = htosonic32(sc, enaddr[2] | (enaddr[3] << 8)); 1119 cda->cda_addr2 = htosonic32(sc, enaddr[4] | (enaddr[5] << 8)); 1120 } else { 1121 struct sonic_cda16 *cda = &sc->sc_cda16[entry]; 1122 1123 cda->cda_entry = htosonic16(sc, entry); 1124 cda->cda_addr0 = htosonic16(sc, enaddr[0] | (enaddr[1] << 8)); 1125 cda->cda_addr1 = htosonic16(sc, enaddr[2] | (enaddr[3] << 8)); 1126 cda->cda_addr2 = htosonic16(sc, enaddr[4] | (enaddr[5] << 8)); 1127 } 1128} 1129 1130/* 1131 * sonic_set_filter: 1132 * 1133 * Set the SONIC receive filter. 1134 */ 1135void 1136sonic_set_filter(struct sonic_softc *sc) 1137{ 1138 struct ethercom *ec = &sc->sc_ethercom; 1139 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1140 struct ether_multi *enm; 1141 struct ether_multistep step; 1142 int i, entry = 0; 1143 uint16_t camvalid = 0; 1144 uint16_t rcr = 0; 1145 1146 if (ifp->if_flags & IFF_BROADCAST) 1147 rcr |= RCR_BRD; 1148 1149 if (ifp->if_flags & IFF_PROMISC) { 1150 rcr |= RCR_PRO; 1151 goto allmulti; 1152 } 1153 1154 /* Put our station address in the first CAM slot. */ 1155 sonic_set_camentry(sc, entry, LLADDR(ifp->if_sadl)); 1156 camvalid |= (1U << entry); 1157 entry++; 1158 1159 /* Add the multicast addresses to the CAM. */ 1160 ETHER_FIRST_MULTI(step, ec, enm); 1161 while (enm != NULL) { 1162 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1163 /* 1164 * We must listen to a range of multicast addresses. 1165 * The only way to do this on the SONIC is to enable 1166 * reception of all multicast packets. 1167 */ 1168 goto allmulti; 1169 } 1170 1171 if (entry == 16) { 1172 /* 1173 * Out of CAM slots. Have to enable reception 1174 * of all multicast addresses. 1175 */ 1176 goto allmulti; 1177 } 1178 1179 sonic_set_camentry(sc, entry, enm->enm_addrlo); 1180 camvalid |= (1U << entry); 1181 entry++; 1182 1183 ETHER_NEXT_MULTI(step, enm); 1184 } 1185 1186 ifp->if_flags &= ~IFF_ALLMULTI; 1187 goto setit; 1188 1189 allmulti: 1190 /* Use only the first CAM slot (station address). */ 1191 camvalid = 0x0001; 1192 entry = 1; 1193 rcr |= RCR_AMC; 1194 1195 setit: 1196 /* Load the CAM. */ 1197 SONIC_CDCAMSYNC(sc, BUS_DMASYNC_PREWRITE); 1198 CSR_WRITE(sc, SONIC_CDP, SONIC_CDCAMADDR(sc) & 0xffff); 1199 CSR_WRITE(sc, SONIC_CDC, entry); 1200 CSR_WRITE(sc, SONIC_CR, CR_LCAM); 1201 for (i = 0; i < 10000; i++) { 1202 if ((CSR_READ(sc, SONIC_CR) & CR_LCAM) == 0) 1203 break; 1204 delay(2); 1205 } 1206 if (CSR_READ(sc, SONIC_CR) & CR_LCAM) 1207 printf("%s: CAM load failed\n", sc->sc_dev.dv_xname); 1208 SONIC_CDCAMSYNC(sc, BUS_DMASYNC_POSTWRITE); 1209 1210 /* Set the CAM enable resgiter. */ 1211 CSR_WRITE(sc, SONIC_CER, camvalid); 1212 1213 /* Set the receive control register. */ 1214 CSR_WRITE(sc, SONIC_RCR, rcr); 1215} 1216