atwvar.h revision 1.2
1/* $NetBSD: atwvar.h,v 1.2 2003/10/13 08:22:19 dyoung Exp $ */ 2 3/* 4 * Copyright (c) 2003, 2004 The NetBSD Foundation, Inc. All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by David Young. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. Neither the name of the author nor the names of any co-contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY David Young AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL David Young 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 35 * THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38#ifndef _DEV_IC_ATWVAR_H_ 39#define _DEV_IC_ATWVAR_H_ 40 41#include <sys/queue.h> 42#include <sys/callout.h> 43#include <sys/time.h> 44#if 0 45#endif 46 47/* 48 * Some misc. statics, useful for debugging. 49 */ 50struct atw_stats { 51 u_long ts_tx_tuf; /* transmit underflow errors */ 52 u_long ts_tx_tro; /* transmit jabber timeouts */ 53 u_long ts_tx_trt; /* retry count exceeded */ 54 u_long ts_tx_tlt; /* lifetime exceeded */ 55 u_long ts_tx_sofbr; /* packet size mismatch */ 56}; 57 58/* 59 * Transmit descriptor list size. This is arbitrary, but allocate 60 * enough descriptors for 64 pending transmissions and 16 segments 61 * per packet. Since a descriptor holds 2 buffer addresses, that's 62 * 8 descriptors per packet. This MUST work out to a power of 2. 63 */ 64#define ATW_NTXSEGS 16 65 66#define ATW_TXQUEUELEN 64 67#define ATW_NTXDESC (ATW_TXQUEUELEN * ATW_NTXSEGS) 68#define ATW_NTXDESC_MASK (ATW_NTXDESC - 1) 69#define ATW_NEXTTX(x) ((x + 1) & ATW_NTXDESC_MASK) 70 71/* 72 * Receive descriptor list size. We have one Rx buffer per incoming 73 * packet, so this logic is a little simpler. 74 */ 75#define ATW_NRXDESC 64 76#define ATW_NRXDESC_MASK (ATW_NRXDESC - 1) 77#define ATW_NEXTRX(x) ((x + 1) & ATW_NRXDESC_MASK) 78 79/* 80 * Control structures are DMA'd to the ADM8211 chip. We allocate them in 81 * a single clump that maps to a single DMA segment to make several things 82 * easier. 83 */ 84struct atw_control_data { 85 /* 86 * The transmit descriptors. 87 */ 88 struct atw_txdesc acd_txdescs[ATW_NTXDESC]; 89 90 /* 91 * The receive descriptors. 92 */ 93 struct atw_rxdesc acd_rxdescs[ATW_NRXDESC]; 94}; 95 96#define ATW_CDOFF(x) offsetof(struct atw_control_data, x) 97#define ATW_CDTXOFF(x) ATW_CDOFF(acd_txdescs[(x)]) 98#define ATW_CDRXOFF(x) ATW_CDOFF(acd_rxdescs[(x)]) 99/* 100 * Software state for transmit jobs. 101 */ 102struct atw_txsoft { 103 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 104 bus_dmamap_t txs_dmamap; /* our DMA map */ 105 int txs_firstdesc; /* first descriptor in packet */ 106 int txs_lastdesc; /* last descriptor in packet */ 107 int txs_ndescs; /* number of descriptors */ 108 SIMPLEQ_ENTRY(atw_txsoft) txs_q; 109}; 110 111SIMPLEQ_HEAD(atw_txsq, atw_txsoft); 112 113/* 114 * Software state for receive jobs. 115 */ 116struct atw_rxsoft { 117 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 118 bus_dmamap_t rxs_dmamap; /* our DMA map */ 119}; 120 121/* 122 * Table which describes the transmit threshold mode. We generally 123 * start at index 0. Whenever we get a transmit underrun, we increment 124 * our index, falling back if we encounter the NULL terminator. 125 */ 126struct atw_txthresh_tab { 127 u_int32_t txth_opmode; /* OPMODE bits */ 128 const char *txth_name; /* name of mode */ 129}; 130 131#define ATW_TXTHRESH_TAB_LO_RATE { \ 132 { ATW_NAR_TR_L64, "64 bytes" }, \ 133 { ATW_NAR_TR_L160, "160 bytes" }, \ 134 { ATW_NAR_TR_L192, "192 bytes" }, \ 135 { ATW_NAR_SF, "store and forward" }, \ 136 { 0, NULL }, \ 137} 138 139#define ATW_TXTHRESH_TAB_HI_RATE { \ 140 { ATW_NAR_TR_H96, "96 bytes" }, \ 141 { ATW_NAR_TR_H288, "288 bytes" }, \ 142 { ATW_NAR_TR_H544, "544 bytes" }, \ 143 { ATW_NAR_SF, "store and forward" }, \ 144 { 0, NULL }, \ 145} 146 147enum atw_rftype { ATW_RFTYPE_INTERSIL = 0, ATW_RFTYPE_RFMD = 1, 148 ATW_RFTYPE_MARVEL = 2 }; 149 150enum atw_bbptype { ATW_BBPTYPE_INTERSIL = 0, ATW_BBPTYPE_RFMD = 1, 151 ATW_BBPTYPE_MARVEL = 2 }; 152 153struct atw_softc { 154 struct device sc_dev; 155 struct ieee80211com sc_ic; 156 void *sc_ih; /* interrupt handler */ 157 int (*sc_enable)(struct atw_softc *); 158 void (*sc_disable)(struct atw_softc *); 159 void (*sc_power)(struct atw_softc *, int); 160 int (*sc_newstate)(struct ieee80211com *, 161 enum ieee80211_state, int); 162 void (*sc_recv_mgmt)(struct ieee80211com *, 163 struct mbuf *, struct ieee80211_node *, 164 int, int, u_int32_t); 165 struct ieee80211_node *(*sc_node_alloc)(struct ieee80211com *); 166 void (*sc_node_free)(struct ieee80211com *, 167 struct ieee80211_node *); 168 169 int sc_pci; /* attach to PCI-Bus */ 170 171 struct atw_stats sc_stats; /* debugging stats */ 172 173 int sc_tx_timer; 174 int sc_rescan_timer; 175 176 bus_space_tag_t sc_st; /* bus space tag */ 177 bus_space_handle_t sc_sh; /* bus space handle */ 178 bus_dma_tag_t sc_dmat; /* bus dma tag */ 179 void *sc_sdhook; /* shutdown hook */ 180 void *sc_powerhook; /* power management hook */ 181 u_int32_t sc_cacheline; /* cache line size */ 182 u_int32_t sc_maxburst; /* maximum burst length */ 183 184 const struct atw_txthresh_tab *sc_txth; 185 int sc_txthresh; /* current tx threshold */ 186 187 u_int sc_cur_chan; /* current channel */ 188 189 int sc_flags; 190 191 u_int16_t *sc_srom; 192 u_int16_t sc_sromsz; 193 194 caddr_t sc_radiobpf; 195 196 bus_dma_segment_t sc_cdseg; /* control data memory */ 197 int sc_cdnseg; /* number of segments */ 198 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 199#define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 200 201 /* 202 * Software state for transmit and receive descriptors. 203 */ 204 struct atw_txsoft sc_txsoft[ATW_TXQUEUELEN]; 205 struct atw_rxsoft sc_rxsoft[ATW_NRXDESC]; 206 207 /* 208 * Control data structures. 209 */ 210 struct atw_control_data *sc_control_data; 211#define sc_txdescs sc_control_data->acd_txdescs 212#define sc_rxdescs sc_control_data->acd_rxdescs 213#define sc_setup_desc sc_control_data->acd_setup_desc 214 215 int sc_txfree; /* number of free Tx descriptors */ 216 int sc_txnext; /* next ready Tx descriptor */ 217 int sc_ntxsegs; /* number of transmit segs per pkt */ 218 219 struct atw_txsq sc_txfreeq; /* free Tx descsofts */ 220 struct atw_txsq sc_txdirtyq; /* dirty Tx descsofts */ 221 222 int sc_rxptr; /* next ready RX descriptor/descsoft */ 223 224 u_int32_t sc_busmode; /* copy of ATW_PAR */ 225 u_int32_t sc_opmode; /* copy of ATW_NAR */ 226 u_int32_t sc_inten; /* copy of ATW_IER */ 227 u_int32_t sc_wepctl; /* copy of ATW_WEPCTL */ 228 229 u_int32_t sc_rxint_mask; /* mask of Rx interrupts we want */ 230 u_int32_t sc_txint_mask; /* mask of Tx interrupts we want */ 231 u_int32_t sc_linkint_mask;/* link-state interrupts mask */ 232 233 /* interrupt acknowledge hook */ 234 void (*sc_intr_ack) __P((struct atw_softc *)); 235 236 enum atw_rftype sc_rftype; 237 enum atw_bbptype sc_bbptype; 238 u_int32_t sc_synctl_rd; 239 u_int32_t sc_synctl_wr; 240 u_int32_t sc_bbpctl_rd; 241 u_int32_t sc_bbpctl_wr; 242 243 void (*sc_recv_beacon)(struct ieee80211com *, struct mbuf *, 244 int, u_int32_t); 245 void (*sc_recv_prresp)(struct ieee80211com *, struct mbuf *, 246 int, u_int32_t); 247 248 /* ADM8211 state variables. */ 249 u_int8_t sc_sram[ATW_SRAM_SIZE]; 250 u_int8_t sc_bssid[IEEE80211_ADDR_LEN]; 251 u_int8_t sc_lost_bcn_thresh; 252 253 struct timeval sc_last_beacon; 254 struct callout sc_scan_ch; 255}; 256 257#define sc_if sc_ic.ic_if 258 259/* XXX this is fragile. try not to introduce any u_int32_t's. */ 260struct atw_frame { 261/*00*/ u_int8_t atw_dst[IEEE80211_ADDR_LEN]; 262/*06*/ u_int8_t atw_rate; /* TX rate in 100Kbps */ 263/*07*/ u_int8_t atw_service; /* 0 */ 264/*08*/ u_int16_t atw_paylen; /* payload length */ 265/*0a*/ u_int8_t atw_fc[2]; /* 802.11 Frame 266 * Control 267 */ 268 /* 802.11 PLCP Length for first & last fragment */ 269/*0c*/ u_int16_t atw_tail_plcplen; 270/*0e*/ u_int16_t atw_head_plcplen; 271 /* 802.11 Duration for first & last fragment */ 272/*10*/ u_int16_t atw_tail_dur; 273/*12*/ u_int16_t atw_head_dur; 274/*14*/ u_int8_t atw_addr4[IEEE80211_ADDR_LEN]; 275 union { 276 struct { 277/*1a*/ u_int16_t hdrctl; /*transmission control*/ 278/*1c*/ u_int16_t fragthr;/* fragmentation threshold 279 * [0:11], zero [12:15]. 280 */ 281/*1e*/ u_int8_t fragnum;/* fragment number [4:7], 282 * zero [0:3]. 283 */ 284/*1f*/ u_int8_t rtylmt; /* retry limit */ 285/*20*/ u_int8_t wepkey0[4];/* ??? */ 286/*24*/ u_int8_t wepkey1[4];/* ??? */ 287/*28*/ u_int8_t wepkey2[4];/* ??? */ 288/*2c*/ u_int8_t wepkey3[4];/* ??? */ 289/*30*/ u_int8_t keyid; 290/*31*/ u_int8_t reserved0[7]; 291 } s1; 292 struct { 293 u_int8_t pad[6]; 294 struct ieee80211_frame ihdr; 295 } s2; 296 } u; 297} __attribute__((__packed__)); 298 299#define atw_hdrctl u.s1.hdrctl 300#define atw_fragthr u.s1.fragthr 301#define atw_fragnum u.s1.fragnum 302#define atw_rtylmt u.s1.rtylmt 303#define atw_keyid u.s1.keyid 304#define atw_ihdr u.s2.ihdr 305 306#define ATW_HDRCTL_SHORT_PREAMBLE BIT(0) /* use short preamble */ 307#define ATW_HDRCTL_RTSCTS BIT(4) /* send RTS */ 308#define ATW_HDRCTL_WEP BIT(5) 309#define ATW_HDRCTL_UNKNOWN1 BIT(15) /* MAC adds FCS? */ 310#define ATW_HDRCTL_UNKNOWN2 BIT(8) 311 312#define ATW_FRAGTHR_FRAGTHR_MASK BITS(0, 11) 313#define ATW_FRAGNUM_FRAGNUM_MASK BITS(4, 7) 314 315/* Values for sc_flags. */ 316#define ATWF_MRL 0x00000010 /* memory read line okay */ 317#define ATWF_MRM 0x00000020 /* memory read multi okay */ 318#define ATWF_MWI 0x00000040 /* memory write inval okay */ 319#define ATWF_SHORT_PREAMBLE 0x00000080 /* short preamble enabled */ 320#define ATWF_RTSCTS 0x00000100 /* RTS/CTS enabled */ 321#define ATWF_ATTACHED 0x00000800 /* attach has succeeded */ 322#define ATWF_ENABLED 0x00001000 /* chip is enabled */ 323 324#define ATW_IS_ENABLED(sc) ((sc)->sc_flags & ATWF_ENABLED) 325 326#define ATW_CDTXADDR(sc, x) ((sc)->sc_cddma + ATW_CDTXOFF((x))) 327#define ATW_CDRXADDR(sc, x) ((sc)->sc_cddma + ATW_CDRXOFF((x))) 328 329#define ATW_CDTXSYNC(sc, x, n, ops) \ 330do { \ 331 int __x, __n; \ 332 \ 333 __x = (x); \ 334 __n = (n); \ 335 \ 336 /* If it will wrap around, sync to the end of the ring. */ \ 337 if ((__x + __n) > ATW_NTXDESC) { \ 338 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 339 ATW_CDTXOFF(__x), sizeof(struct atw_txdesc) * \ 340 (ATW_NTXDESC - __x), (ops)); \ 341 __n -= (ATW_NTXDESC - __x); \ 342 __x = 0; \ 343 } \ 344 \ 345 /* Now sync whatever is left. */ \ 346 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 347 ATW_CDTXOFF(__x), sizeof(struct atw_txdesc) * __n, (ops)); \ 348} while (0) 349 350#define ATW_CDRXSYNC(sc, x, ops) \ 351 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 352 ATW_CDRXOFF((x)), sizeof(struct atw_rxdesc), (ops)) 353 354/* 355 * Note we rely on MCLBYTES being a power of two. Because the `length' 356 * field is only 11 bits, we must subtract 1 from the length to avoid 357 * having it truncated to 0! 358 * 359 * Apparently we have to set ATW_RXSTAT_SQL to make the ADM8211 tell 360 * us RSSI. 361 */ 362#define ATW_INIT_RXDESC(sc, x) \ 363do { \ 364 struct atw_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \ 365 struct atw_rxdesc *__rxd = &sc->sc_rxdescs[(x)]; \ 366 struct mbuf *__m = __rxs->rxs_mbuf; \ 367 \ 368 __m->m_data = __m->m_ext.ext_buf; \ 369 __rxd->ar_buf1 = \ 370 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 371 __rxd->ar_buf2 = /* for descriptor chaining */ \ 372 htole32(ATW_CDRXADDR((sc), ATW_NEXTRX((x)))); \ 373 __rxd->ar_ctl = \ 374 htole32(LSHIFT(((__m->m_ext.ext_size - 1) & ~0x3U), \ 375 ATW_RXCTL_RBS1_MASK) | \ 376 0 /* ATW_RXCTL_RCH */ | \ 377 ((x) == (ATW_NRXDESC - 1) ? ATW_RXCTL_RER : 0)); \ 378 __rxd->ar_stat = \ 379 htole32(ATW_RXSTAT_OWN|ATW_RXSTAT_SQL|ATW_RXSTAT_FS| \ 380 ATW_RXSTAT_LS); \ 381 ATW_CDRXSYNC((sc), (x), \ 382 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 383} while (0) 384 385/* country codes from ADM8211 SROM */ 386#define ATW_COUNTRY_FCC 0 /* USA 1-11 */ 387#define ATW_COUNTRY_IC 1 /* Canada 1-11 */ 388#define ATW_COUNTRY_ETSI 2 /* European Union (?) 1-13 */ 389#define ATW_COUNTRY_SPAIN 3 /* 10-11 */ 390#define ATW_COUNTRY_FRANCE 4 /* 10-13 */ 391#define ATW_COUNTRY_MKK 5 /* Japan: 14 */ 392#define ATW_COUNTRY_MKK2 6 /* Japan: 1-14 */ 393 394/* One Time Unit (TU) is 1Kus = 1024 microseconds. */ 395#define IEEE80211_DUR_TU 1024 396 397/* IEEE 802.11b durations for DSSS PHY in microseconds */ 398#define IEEE80211_DUR_DS_LONG_PREAMBLE 144 399#define IEEE80211_DUR_DS_SHORT_PREAMBLE 72 400#define IEEE80211_DUR_DS_FAST_PLCPHDR 24 401#define IEEE80211_DUR_DS_SLOW_PLCPHDR 48 402#define IEEE80211_DUR_DS_SLOW_ACK 112 403#define IEEE80211_DUR_DS_FAST_ACK 56 404#define IEEE80211_DUR_DS_SLOW_CTS 112 405#define IEEE80211_DUR_DS_FAST_CTS 56 406#define IEEE80211_DUR_DS_SLOT 20 407#define IEEE80211_DUR_DS_SIFS 10 408#define IEEE80211_DUR_DS_PIFS (IEEE80211_DUR_DS_SIFS + IEEE80211_DUR_DS_SLOT) 409#define IEEE80211_DUR_DS_DIFS (IEEE80211_DUR_DS_SIFS + \ 410 2 * IEEE80211_DUR_DS_SLOT) 411#define IEEE80211_DUR_DS_EIFS (IEEE80211_DUR_DS_SIFS + \ 412 IEEE80211_DUR_DS_SLOW_ACK + \ 413 IEEE80211_DUR_DS_LONG_PREAMBLE + \ 414 IEEE80211_DUR_DS_SLOW_PLCPHDR + \ 415 IEEE80211_DUR_DIFS) 416 417/* 418 * register space access macros 419 */ 420#define ATW_READ(sc, reg) \ 421 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 422 423#define ATW_WRITE(sc, reg, val) \ 424 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 425 426#define ATW_SET(sc, reg, mask) \ 427 ATW_WRITE((sc), (reg), ATW_READ((sc), (reg)) | (mask)) 428 429#define ATW_CLR(sc, reg, mask) \ 430 ATW_WRITE((sc), (reg), ATW_READ((sc), (reg)) & ~(mask)) 431 432#define ATW_ISSET(sc, reg, mask) \ 433 (ATW_READ((sc), (reg)) & (mask)) 434 435void atw_attach __P((struct atw_softc *)); 436int atw_detach __P((struct atw_softc *)); 437int atw_activate __P((struct device *, enum devact)); 438int atw_intr __P((void *arg)); 439void atw_power __P((int, void *)); 440void atw_shutdown __P((void *)); 441 442#endif /* _DEV_IC_ATWVAR_H_ */ 443