atw.c revision 1.56
1/* $NetBSD: atw.c,v 1.56 2004/07/15 07:10:25 dyoung Exp $ */ 2 3/*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39/* 40 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 41 */ 42 43#include <sys/cdefs.h> 44__KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.56 2004/07/15 07:10:25 dyoung Exp $"); 45 46#include "bpfilter.h" 47 48#include <sys/param.h> 49#include <sys/systm.h> 50#include <sys/callout.h> 51#include <sys/mbuf.h> 52#include <sys/malloc.h> 53#include <sys/kernel.h> 54#include <sys/socket.h> 55#include <sys/ioctl.h> 56#include <sys/errno.h> 57#include <sys/device.h> 58#include <sys/time.h> 59 60#include <machine/endian.h> 61 62#include <uvm/uvm_extern.h> 63 64#include <net/if.h> 65#include <net/if_dl.h> 66#include <net/if_media.h> 67#include <net/if_ether.h> 68 69#include <net80211/ieee80211_var.h> 70#include <net80211/ieee80211_compat.h> 71#include <net80211/ieee80211_radiotap.h> 72 73#if NBPFILTER > 0 74#include <net/bpf.h> 75#endif 76 77#include <machine/bus.h> 78#include <machine/intr.h> 79 80#include <dev/ic/atwreg.h> 81#include <dev/ic/rf3000reg.h> 82#include <dev/ic/si4136reg.h> 83#include <dev/ic/atwvar.h> 84#include <dev/ic/smc93cx6var.h> 85 86/* XXX TBD open questions 87 * 88 * 89 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 90 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 91 * handle this for me? 92 * 93 */ 94/* device attachment 95 * 96 * print TOFS[012] 97 * 98 * device initialization 99 * 100 * clear ATW_FRCTL_MAXPSP to disable max power saving 101 * set ATW_TXBR_ALCUPDATE to enable ALC 102 * set TOFS[012]? (hope not) 103 * disable rx/tx 104 * set ATW_PAR_SWR (software reset) 105 * wait for ATW_PAR_SWR clear 106 * disable interrupts 107 * ack status register 108 * enable interrupts 109 * 110 * rx/tx initialization 111 * 112 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 113 * allocate and init descriptor rings 114 * write ATW_PAR_DSL (descriptor skip length) 115 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 116 * write ATW_NAR_SQ for one/both transmit descriptor rings 117 * write ATW_NAR_SQ for one/both transmit descriptor rings 118 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 119 * 120 * rx/tx end 121 * 122 * stop DMA 123 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 124 * flush tx w/ ATW_NAR_HF 125 * 126 * scan 127 * 128 * initialize rx/tx 129 * 130 * BSS join: (re)association response 131 * 132 * set ATW_FRCTL_AID 133 * 134 * optimizations ??? 135 * 136 */ 137 138#define VOODOO_DUR_11_ROUNDING 0x01 /* necessary */ 139#define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */ 140int atw_voodoo = VOODOO_DUR_11_ROUNDING; 141 142int atw_rfio_enable_delay = 20 * 1000; 143int atw_rfio_disable_delay = 2 * 1000; 144int atw_writewep_delay = 5; 145int atw_beacon_len_adjust = 4; 146int atw_dwelltime = 200; 147 148#ifdef ATW_DEBUG 149int atw_debug = 0; 150 151#define ATW_DPRINTF(x) if (atw_debug > 0) printf x 152#define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 153#define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 154#define DPRINTF(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) printf x 155#define DPRINTF2(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 156#define DPRINTF3(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 157 158static void atw_print_regs(struct atw_softc *, const char *); 159static void atw_dump_pkt(struct ifnet *, struct mbuf *); 160 161/* Note well: I never got atw_rf3000_read or atw_si4126_read to work. */ 162# ifdef ATW_BBPDEBUG 163static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 164static void atw_rf3000_print(struct atw_softc *); 165# endif /* ATW_BBPDEBUG */ 166 167# ifdef ATW_SYNDEBUG 168static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 169static void atw_si4126_print(struct atw_softc *); 170# endif /* ATW_SYNDEBUG */ 171 172#else 173#define ATW_DPRINTF(x) 174#define ATW_DPRINTF2(x) 175#define ATW_DPRINTF3(x) 176#define DPRINTF(sc, x) /* nothing */ 177#define DPRINTF2(sc, x) /* nothing */ 178#define DPRINTF3(sc, x) /* nothing */ 179#endif 180 181#ifdef ATW_STATS 182void atw_print_stats(struct atw_softc *); 183#endif 184 185void atw_start(struct ifnet *); 186void atw_watchdog(struct ifnet *); 187int atw_ioctl(struct ifnet *, u_long, caddr_t); 188int atw_init(struct ifnet *); 189void atw_txdrain(struct atw_softc *); 190void atw_stop(struct ifnet *, int); 191 192void atw_reset(struct atw_softc *); 193int atw_read_srom(struct atw_softc *); 194 195void atw_shutdown(void *); 196 197void atw_rxdrain(struct atw_softc *); 198int atw_add_rxbuf(struct atw_softc *, int); 199void atw_idle(struct atw_softc *, u_int32_t); 200 201int atw_enable(struct atw_softc *); 202void atw_disable(struct atw_softc *); 203void atw_power(int, void *); 204 205void atw_rxintr(struct atw_softc *); 206void atw_txintr(struct atw_softc *); 207void atw_linkintr(struct atw_softc *, u_int32_t); 208 209static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 210static void atw_tsf(struct atw_softc *); 211static void atw_start_beacon(struct atw_softc *, int); 212static void atw_write_wep(struct atw_softc *); 213static void atw_write_bssid(struct atw_softc *); 214static void atw_write_ssid(struct atw_softc *); 215static void atw_write_sup_rates(struct atw_softc *); 216static void atw_clear_sram(struct atw_softc *); 217static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 218static int atw_media_change(struct ifnet *); 219static void atw_media_status(struct ifnet *, struct ifmediareq *); 220static void atw_filter_setup(struct atw_softc *); 221static void atw_frame_setdurs(struct atw_softc *, struct atw_frame *, int, int); 222static __inline u_int64_t atw_predict_beacon(u_int64_t, u_int32_t); 223static void atw_recv_beacon(struct ieee80211com *, struct mbuf *, 224 struct ieee80211_node *, int, int, u_int32_t); 225static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 226 struct ieee80211_node *, int, int, u_int32_t); 227static void atw_node_free(struct ieee80211com *, struct ieee80211_node *); 228static struct ieee80211_node *atw_node_alloc(struct ieee80211com *); 229 230static int atw_tune(struct atw_softc *); 231 232static void atw_rfio_enable(struct atw_softc *, int); 233 234/* RFMD RF3000 Baseband Processor */ 235static int atw_rf3000_init(struct atw_softc *); 236static int atw_rf3000_tune(struct atw_softc *, u_int8_t); 237static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 238#ifdef ATW_DEBUG 239static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 240#endif /* ATW_DEBUG */ 241 242/* Silicon Laboratories Si4126 RF/IF Synthesizer */ 243static int atw_si4126_tune(struct atw_softc *, u_int8_t); 244static int atw_si4126_write(struct atw_softc *, u_int, u_int); 245#ifdef ATW_DEBUG 246static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 247#endif /* ATW_DEBUG */ 248 249const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 250const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 251 252const char *atw_tx_state[] = { 253 "STOPPED", 254 "RUNNING - read descriptor", 255 "RUNNING - transmitting", 256 "RUNNING - filling fifo", /* XXX */ 257 "SUSPENDED", 258 "RUNNING -- write descriptor", 259 "RUNNING -- write last descriptor", 260 "RUNNING - fifo full" 261}; 262 263const char *atw_rx_state[] = { 264 "STOPPED", 265 "RUNNING - read descriptor", 266 "RUNNING - check this packet, pre-fetch next", 267 "RUNNING - wait for reception", 268 "SUSPENDED", 269 "RUNNING - write descriptor", 270 "RUNNING - flush fifo", 271 "RUNNING - fifo drain" 272}; 273 274int 275atw_activate(struct device *self, enum devact act) 276{ 277 struct atw_softc *sc = (struct atw_softc *)self; 278 int rv = 0, s; 279 280 s = splnet(); 281 switch (act) { 282 case DVACT_ACTIVATE: 283 rv = EOPNOTSUPP; 284 break; 285 286 case DVACT_DEACTIVATE: 287 if_deactivate(&sc->sc_ic.ic_if); 288 break; 289 } 290 splx(s); 291 return rv; 292} 293 294/* 295 * atw_enable: 296 * 297 * Enable the ADM8211 chip. 298 */ 299int 300atw_enable(struct atw_softc *sc) 301{ 302 303 if (ATW_IS_ENABLED(sc) == 0) { 304 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 305 printf("%s: device enable failed\n", 306 sc->sc_dev.dv_xname); 307 return (EIO); 308 } 309 sc->sc_flags |= ATWF_ENABLED; 310 } 311 return (0); 312} 313 314/* 315 * atw_disable: 316 * 317 * Disable the ADM8211 chip. 318 */ 319void 320atw_disable(struct atw_softc *sc) 321{ 322 if (!ATW_IS_ENABLED(sc)) 323 return; 324 if (sc->sc_disable != NULL) 325 (*sc->sc_disable)(sc); 326 sc->sc_flags &= ~ATWF_ENABLED; 327} 328 329/* Returns -1 on failure. */ 330int 331atw_read_srom(struct atw_softc *sc) 332{ 333 struct seeprom_descriptor sd; 334 u_int32_t reg; 335 336 (void)memset(&sd, 0, sizeof(sd)); 337 338 reg = ATW_READ(sc, ATW_TEST0); 339 340 if ((reg & (ATW_TEST0_EPNE|ATW_TEST0_EPSNM)) != 0) { 341 printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname); 342 return -1; 343 } 344 345 switch (reg & ATW_TEST0_EPTYP_MASK) { 346 case ATW_TEST0_EPTYP_93c66: 347 ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname)); 348 sc->sc_sromsz = 512; 349 sd.sd_chip = C56_66; 350 break; 351 case ATW_TEST0_EPTYP_93c46: 352 ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname)); 353 sc->sc_sromsz = 128; 354 sd.sd_chip = C46; 355 break; 356 default: 357 printf("%s: unknown SROM type %d\n", sc->sc_dev.dv_xname, 358 MASK_AND_RSHIFT(reg, ATW_TEST0_EPTYP_MASK)); 359 return -1; 360 } 361 362 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 363 364 if (sc->sc_srom == NULL) { 365 printf("%s: unable to allocate SROM buffer\n", 366 sc->sc_dev.dv_xname); 367 return -1; 368 } 369 370 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 371 372 /* ADM8211 has a single 32-bit register for controlling the 373 * 93cx6 SROM. Bit SRS enables the serial port. There is no 374 * "ready" bit. The ADM8211 input/output sense is the reverse 375 * of read_seeprom's. 376 */ 377 sd.sd_tag = sc->sc_st; 378 sd.sd_bsh = sc->sc_sh; 379 sd.sd_regsize = 4; 380 sd.sd_control_offset = ATW_SPR; 381 sd.sd_status_offset = ATW_SPR; 382 sd.sd_dataout_offset = ATW_SPR; 383 sd.sd_CK = ATW_SPR_SCLK; 384 sd.sd_CS = ATW_SPR_SCS; 385 sd.sd_DI = ATW_SPR_SDO; 386 sd.sd_DO = ATW_SPR_SDI; 387 sd.sd_MS = ATW_SPR_SRS; 388 sd.sd_RDY = 0; 389 390 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 391 printf("%s: could not read SROM\n", sc->sc_dev.dv_xname); 392 free(sc->sc_srom, M_DEVBUF); 393 return -1; 394 } 395#ifdef ATW_DEBUG 396 { 397 int i; 398 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 399 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 400 if (((i % 8) == 0) && (i != 0)) { 401 ATW_DPRINTF(("\n\t")); 402 } 403 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 404 } 405 ATW_DPRINTF(("\n")); 406 } 407#endif /* ATW_DEBUG */ 408 return 0; 409} 410 411#ifdef ATW_DEBUG 412static void 413atw_print_regs(struct atw_softc *sc, const char *where) 414{ 415#define PRINTREG(sc, reg) \ 416 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 417 sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg))) 418 419 ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where)); 420 421 PRINTREG(sc, ATW_PAR); 422 PRINTREG(sc, ATW_FRCTL); 423 PRINTREG(sc, ATW_TDR); 424 PRINTREG(sc, ATW_WTDP); 425 PRINTREG(sc, ATW_RDR); 426 PRINTREG(sc, ATW_WRDP); 427 PRINTREG(sc, ATW_RDB); 428 PRINTREG(sc, ATW_CSR3A); 429 PRINTREG(sc, ATW_TDBD); 430 PRINTREG(sc, ATW_TDBP); 431 PRINTREG(sc, ATW_STSR); 432 PRINTREG(sc, ATW_CSR5A); 433 PRINTREG(sc, ATW_NAR); 434 PRINTREG(sc, ATW_CSR6A); 435 PRINTREG(sc, ATW_IER); 436 PRINTREG(sc, ATW_CSR7A); 437 PRINTREG(sc, ATW_LPC); 438 PRINTREG(sc, ATW_TEST1); 439 PRINTREG(sc, ATW_SPR); 440 PRINTREG(sc, ATW_TEST0); 441 PRINTREG(sc, ATW_WCSR); 442 PRINTREG(sc, ATW_WPDR); 443 PRINTREG(sc, ATW_GPTMR); 444 PRINTREG(sc, ATW_GPIO); 445 PRINTREG(sc, ATW_BBPCTL); 446 PRINTREG(sc, ATW_SYNCTL); 447 PRINTREG(sc, ATW_PLCPHD); 448 PRINTREG(sc, ATW_MMIWADDR); 449 PRINTREG(sc, ATW_MMIRADDR1); 450 PRINTREG(sc, ATW_MMIRADDR2); 451 PRINTREG(sc, ATW_TXBR); 452 PRINTREG(sc, ATW_CSR15A); 453 PRINTREG(sc, ATW_ALCSTAT); 454 PRINTREG(sc, ATW_TOFS2); 455 PRINTREG(sc, ATW_CMDR); 456 PRINTREG(sc, ATW_PCIC); 457 PRINTREG(sc, ATW_PMCSR); 458 PRINTREG(sc, ATW_PAR0); 459 PRINTREG(sc, ATW_PAR1); 460 PRINTREG(sc, ATW_MAR0); 461 PRINTREG(sc, ATW_MAR1); 462 PRINTREG(sc, ATW_ATIMDA0); 463 PRINTREG(sc, ATW_ABDA1); 464 PRINTREG(sc, ATW_BSSID0); 465 PRINTREG(sc, ATW_TXLMT); 466 PRINTREG(sc, ATW_MIBCNT); 467 PRINTREG(sc, ATW_BCNT); 468 PRINTREG(sc, ATW_TSFTH); 469 PRINTREG(sc, ATW_TSC); 470 PRINTREG(sc, ATW_SYNRF); 471 PRINTREG(sc, ATW_BPLI); 472 PRINTREG(sc, ATW_CAP0); 473 PRINTREG(sc, ATW_CAP1); 474 PRINTREG(sc, ATW_RMD); 475 PRINTREG(sc, ATW_CFPP); 476 PRINTREG(sc, ATW_TOFS0); 477 PRINTREG(sc, ATW_TOFS1); 478 PRINTREG(sc, ATW_IFST); 479 PRINTREG(sc, ATW_RSPT); 480 PRINTREG(sc, ATW_TSFTL); 481 PRINTREG(sc, ATW_WEPCTL); 482 PRINTREG(sc, ATW_WESK); 483 PRINTREG(sc, ATW_WEPCNT); 484 PRINTREG(sc, ATW_MACTEST); 485 PRINTREG(sc, ATW_FER); 486 PRINTREG(sc, ATW_FEMR); 487 PRINTREG(sc, ATW_FPSR); 488 PRINTREG(sc, ATW_FFER); 489#undef PRINTREG 490} 491#endif /* ATW_DEBUG */ 492 493/* 494 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 495 */ 496void 497atw_attach(struct atw_softc *sc) 498{ 499 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 500 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 501 }; 502 struct ieee80211com *ic = &sc->sc_ic; 503 struct ifnet *ifp = &ic->ic_if; 504 int country_code, error, i, nrate; 505 u_int32_t reg; 506 static const char *type_strings[] = {"Intersil (not supported)", 507 "RFMD", "Marvel (not supported)"}; 508 509 sc->sc_txth = atw_txthresh_tab_lo; 510 511 SIMPLEQ_INIT(&sc->sc_txfreeq); 512 SIMPLEQ_INIT(&sc->sc_txdirtyq); 513 514#ifdef ATW_DEBUG 515 atw_print_regs(sc, "atw_attach"); 516#endif /* ATW_DEBUG */ 517 518 /* 519 * Allocate the control data structures, and create and load the 520 * DMA map for it. 521 */ 522 if ((error = bus_dmamem_alloc(sc->sc_dmat, 523 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 524 1, &sc->sc_cdnseg, 0)) != 0) { 525 printf("%s: unable to allocate control data, error = %d\n", 526 sc->sc_dev.dv_xname, error); 527 goto fail_0; 528 } 529 530 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 531 sizeof(struct atw_control_data), (caddr_t *)&sc->sc_control_data, 532 BUS_DMA_COHERENT)) != 0) { 533 printf("%s: unable to map control data, error = %d\n", 534 sc->sc_dev.dv_xname, error); 535 goto fail_1; 536 } 537 538 if ((error = bus_dmamap_create(sc->sc_dmat, 539 sizeof(struct atw_control_data), 1, 540 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 541 printf("%s: unable to create control data DMA map, " 542 "error = %d\n", sc->sc_dev.dv_xname, error); 543 goto fail_2; 544 } 545 546 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 547 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 548 0)) != 0) { 549 printf("%s: unable to load control data DMA map, error = %d\n", 550 sc->sc_dev.dv_xname, error); 551 goto fail_3; 552 } 553 554 /* 555 * Create the transmit buffer DMA maps. 556 */ 557 sc->sc_ntxsegs = ATW_NTXSEGS; 558 for (i = 0; i < ATW_TXQUEUELEN; i++) { 559 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 560 sc->sc_ntxsegs, MCLBYTES, 0, 0, 561 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 562 printf("%s: unable to create tx DMA map %d, " 563 "error = %d\n", sc->sc_dev.dv_xname, i, error); 564 goto fail_4; 565 } 566 } 567 568 /* 569 * Create the receive buffer DMA maps. 570 */ 571 for (i = 0; i < ATW_NRXDESC; i++) { 572 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 573 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 574 printf("%s: unable to create rx DMA map %d, " 575 "error = %d\n", sc->sc_dev.dv_xname, i, error); 576 goto fail_5; 577 } 578 } 579 for (i = 0; i < ATW_NRXDESC; i++) { 580 sc->sc_rxsoft[i].rxs_mbuf = NULL; 581 } 582 583 /* Reset the chip to a known state. */ 584 atw_reset(sc); 585 586 if (atw_read_srom(sc) == -1) 587 return; 588 589 sc->sc_rftype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 590 ATW_SR_RFTYPE_MASK); 591 592 sc->sc_bbptype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 593 ATW_SR_BBPTYPE_MASK); 594 595 if (sc->sc_rftype > sizeof(type_strings)/sizeof(type_strings[0])) { 596 printf("%s: unknown RF\n", sc->sc_dev.dv_xname); 597 return; 598 } 599 if (sc->sc_bbptype > sizeof(type_strings)/sizeof(type_strings[0])) { 600 printf("%s: unknown BBP\n", sc->sc_dev.dv_xname); 601 return; 602 } 603 604 printf("%s: %s RF, %s BBP", sc->sc_dev.dv_xname, 605 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 606 607 /* XXX There exists a Linux driver which seems to use RFType = 0 for 608 * MARVEL. My bug, or theirs? 609 */ 610 611 reg = LSHIFT(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 612 613 switch (sc->sc_rftype) { 614 case ATW_RFTYPE_INTERSIL: 615 reg |= ATW_SYNCTL_CS1; 616 break; 617 case ATW_RFTYPE_RFMD: 618 reg |= ATW_SYNCTL_CS0; 619 break; 620 case ATW_RFTYPE_MARVEL: 621 break; 622 } 623 624 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 625 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 626 627 reg = LSHIFT(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 628 629 switch (sc->sc_bbptype) { 630 case ATW_BBPTYPE_INTERSIL: 631 reg |= ATW_BBPCTL_TWI; 632 break; 633 case ATW_BBPTYPE_RFMD: 634 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 635 ATW_BBPCTL_CCA_ACTLO; 636 break; 637 case ATW_BBPTYPE_MARVEL: 638 break; 639 case ATW_C_BBPTYPE_RFMD: 640 printf("%s: ADM8211C MAC/RFMD BBP not supported yet.\n", 641 sc->sc_dev.dv_xname); 642 break; 643 } 644 645 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 646 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 647 648 /* 649 * From this point forward, the attachment cannot fail. A failure 650 * before this point releases all resources that may have been 651 * allocated. 652 */ 653 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 654 655 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 656 htole16(sc->sc_srom[ATW_SR_MAC00]), 657 htole16(sc->sc_srom[ATW_SR_MAC01]), 658 htole16(sc->sc_srom[ATW_SR_MAC10]))); 659 660 country_code = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 661 ATW_SR_CTRY_MASK); 662 663#define ADD_CHANNEL(_ic, _chan) do { \ 664 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 665 _ic->ic_channels[_chan].ic_freq = \ 666 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 667} while (0) 668 669 /* Find available channels */ 670 switch (country_code) { 671 case COUNTRY_MMK2: /* 1-14 */ 672 ADD_CHANNEL(ic, 14); 673 /*FALLTHROUGH*/ 674 case COUNTRY_ETSI: /* 1-13 */ 675 for (i = 1; i <= 13; i++) 676 ADD_CHANNEL(ic, i); 677 break; 678 case COUNTRY_FCC: /* 1-11 */ 679 case COUNTRY_IC: /* 1-11 */ 680 for (i = 1; i <= 11; i++) 681 ADD_CHANNEL(ic, i); 682 break; 683 case COUNTRY_MMK: /* 14 */ 684 ADD_CHANNEL(ic, 14); 685 break; 686 case COUNTRY_FRANCE: /* 10-13 */ 687 for (i = 10; i <= 13; i++) 688 ADD_CHANNEL(ic, i); 689 break; 690 default: /* assume channels 10-11 */ 691 case COUNTRY_SPAIN: /* 10-11 */ 692 for (i = 10; i <= 11; i++) 693 ADD_CHANNEL(ic, i); 694 break; 695 } 696 697 /* Read the MAC address. */ 698 reg = ATW_READ(sc, ATW_PAR0); 699 ic->ic_myaddr[0] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB0_MASK); 700 ic->ic_myaddr[1] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB1_MASK); 701 ic->ic_myaddr[2] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB2_MASK); 702 ic->ic_myaddr[3] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB3_MASK); 703 reg = ATW_READ(sc, ATW_PAR1); 704 ic->ic_myaddr[4] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB4_MASK); 705 ic->ic_myaddr[5] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB5_MASK); 706 707 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 708 printf(" could not get mac address, attach failed\n"); 709 return; 710 } 711 712 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 713 714 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 715 ifp->if_softc = sc; 716 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 717 IFF_NOTRAILERS; 718 ifp->if_ioctl = atw_ioctl; 719 ifp->if_start = atw_start; 720 ifp->if_watchdog = atw_watchdog; 721 ifp->if_init = atw_init; 722 ifp->if_stop = atw_stop; 723 IFQ_SET_READY(&ifp->if_snd); 724 725 ic->ic_phytype = IEEE80211_T_DS; 726 ic->ic_opmode = IEEE80211_M_STA; 727 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 728 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 729 730 nrate = 0; 731 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 732 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 733 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 734 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 735 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 736 737 /* 738 * Call MI attach routines. 739 */ 740 741 if_attach(ifp); 742 ieee80211_ifattach(ifp); 743 744 sc->sc_newstate = ic->ic_newstate; 745 ic->ic_newstate = atw_newstate; 746 747 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 748 ic->ic_recv_mgmt = atw_recv_mgmt; 749 750 sc->sc_node_free = ic->ic_node_free; 751 ic->ic_node_free = atw_node_free; 752 753 sc->sc_node_alloc = ic->ic_node_alloc; 754 ic->ic_node_alloc = atw_node_alloc; 755 756 /* possibly we should fill in our own sc_send_prresp, since 757 * the ADM8211 is probably sending probe responses in ad hoc 758 * mode. 759 */ 760 761 /* complete initialization */ 762 ieee80211_media_init(ifp, atw_media_change, atw_media_status); 763 callout_init(&sc->sc_scan_ch); 764 765#if NBPFILTER > 0 766 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 767 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 768#endif 769 770 /* 771 * Make sure the interface is shutdown during reboot. 772 */ 773 sc->sc_sdhook = shutdownhook_establish(atw_shutdown, sc); 774 if (sc->sc_sdhook == NULL) 775 printf("%s: WARNING: unable to establish shutdown hook\n", 776 sc->sc_dev.dv_xname); 777 778 /* 779 * Add a suspend hook to make sure we come back up after a 780 * resume. 781 */ 782 sc->sc_powerhook = powerhook_establish(atw_power, sc); 783 if (sc->sc_powerhook == NULL) 784 printf("%s: WARNING: unable to establish power hook\n", 785 sc->sc_dev.dv_xname); 786 787 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 788 sc->sc_rxtap.ar_ihdr.it_len = sizeof(sc->sc_rxtapu); 789 sc->sc_rxtap.ar_ihdr.it_present = ATW_RX_RADIOTAP_PRESENT; 790 791 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 792 sc->sc_txtap.at_ihdr.it_len = sizeof(sc->sc_txtapu); 793 sc->sc_txtap.at_ihdr.it_present = ATW_TX_RADIOTAP_PRESENT; 794 795 return; 796 797 /* 798 * Free any resources we've allocated during the failed attach 799 * attempt. Do this in reverse order and fall through. 800 */ 801 fail_5: 802 for (i = 0; i < ATW_NRXDESC; i++) { 803 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 804 continue; 805 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 806 } 807 fail_4: 808 for (i = 0; i < ATW_TXQUEUELEN; i++) { 809 if (sc->sc_txsoft[i].txs_dmamap == NULL) 810 continue; 811 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 812 } 813 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 814 fail_3: 815 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 816 fail_2: 817 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 818 sizeof(struct atw_control_data)); 819 fail_1: 820 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 821 fail_0: 822 return; 823} 824 825static struct ieee80211_node * 826atw_node_alloc(struct ieee80211com *ic) 827{ 828 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 829 struct ieee80211_node *ni = (*sc->sc_node_alloc)(ic); 830 831 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 832 return ni; 833} 834 835static void 836atw_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 837{ 838 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 839 840 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 841 ether_sprintf(ni->ni_bssid))); 842 (*sc->sc_node_free)(ic, ni); 843} 844 845/* 846 * atw_reset: 847 * 848 * Perform a soft reset on the ADM8211. 849 */ 850void 851atw_reset(struct atw_softc *sc) 852{ 853 int i; 854 855 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 856 857 for (i = 0; i < 10000; i++) { 858 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR) == 0) 859 break; 860 DELAY(1); 861 } 862 863 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i)); 864 865 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 866 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 867 868 /* Turn off maximum power saving. */ 869 ATW_CLR(sc, ATW_FRCTL, ATW_FRCTL_MAXPSP); 870 871 /* Recall EEPROM. */ 872 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 873 874 DELAY(10 * 1000); 875 876 /* A reset seems to affect the SRAM contents, so put them into 877 * a known state. 878 */ 879 atw_clear_sram(sc); 880 881 memset(sc->sc_bssid, 0, sizeof(sc->sc_bssid)); 882} 883 884static void 885atw_clear_sram(struct atw_softc *sc) 886{ 887 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 888 /* XXX not for revision 0x20. */ 889 atw_write_sram(sc, 0, sc->sc_sram, sizeof(sc->sc_sram)); 890} 891 892/* TBD atw_init 893 * 894 * set MAC based on ic->ic_bss->myaddr 895 * write WEP keys 896 * set TX rate 897 */ 898 899/* 900 * atw_init: [ ifnet interface function ] 901 * 902 * Initialize the interface. Must be called at splnet(). 903 */ 904int 905atw_init(struct ifnet *ifp) 906{ 907 struct atw_softc *sc = ifp->if_softc; 908 struct ieee80211com *ic = &sc->sc_ic; 909 struct atw_txsoft *txs; 910 struct atw_rxsoft *rxs; 911 u_int32_t reg; 912 int i, error = 0; 913 914 if ((error = atw_enable(sc)) != 0) 915 goto out; 916 917 /* 918 * Cancel any pending I/O. This also resets. 919 */ 920 atw_stop(ifp, 0); 921 922 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 923 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 924 __func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan), 925 ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags)); 926 927 /* Turn off APM??? (A binary-only driver does this.) 928 * 929 * Set Rx store-and-forward mode. 930 */ 931 reg = ATW_READ(sc, ATW_CMDR); 932 reg &= ~ATW_CMDR_APM; 933 reg &= ~ATW_CMDR_DRT_MASK; 934 reg |= ATW_CMDR_RTE | LSHIFT(0x2, ATW_CMDR_DRT_MASK); 935 936 ATW_WRITE(sc, ATW_CMDR, reg); 937 938 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 939 * 940 * XXX a binary-only driver sets a different service field than 941 * 0. why? 942 */ 943 reg = ATW_READ(sc, ATW_PLCPHD); 944 reg &= ~(ATW_PLCPHD_SERVICE_MASK|ATW_PLCPHD_SIGNAL_MASK); 945 reg |= LSHIFT(10, ATW_PLCPHD_SIGNAL_MASK) | 946 LSHIFT(0xb0, ATW_PLCPHD_SERVICE_MASK); 947 ATW_WRITE(sc, ATW_PLCPHD, reg); 948 949 /* XXX this magic can probably be figured out from the RFMD docs */ 950 reg = LSHIFT(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 951 LSHIFT(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 952 LSHIFT(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 953 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 954 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 955 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 956 LSHIFT(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 957 LSHIFT(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 958 ATW_WRITE(sc, ATW_TOFS2, reg); 959 960 ATW_WRITE(sc, ATW_TXLMT, LSHIFT(512, ATW_TXLMT_MTMLT_MASK) | 961 LSHIFT(224, ATW_TXLMT_SRTYLIM_MASK)); 962 963 /* XXX this resets an Intersil RF front-end? */ 964 /* TBD condition on Intersil RFType? */ 965 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 966 DELAY(10 * 1000); 967 ATW_WRITE(sc, ATW_SYNRF, 0); 968 DELAY(5 * 1000); 969 970 /* 16 TU max duration for contention-free period */ 971 reg = ATW_READ(sc, ATW_CFPP) & ~ATW_CFPP_CFPMD; 972 ATW_WRITE(sc, ATW_CFPP, reg | LSHIFT(16, ATW_CFPP_CFPMD)); 973 974 /* XXX I guess that the Cardbus clock is 22MHz? 975 * I am assuming that the role of ATW_TOFS0_USCNT is 976 * to divide the bus clock to get a 1MHz clock---the datasheet is not 977 * very clear on this point. It says in the datasheet that it is 978 * possible for the ADM8211 to accomodate bus speeds between 22MHz 979 * and 33MHz; maybe this is the way? I see a binary-only driver write 980 * these values. These values are also the power-on default. 981 */ 982 ATW_WRITE(sc, ATW_TOFS0, 983 LSHIFT(22, ATW_TOFS0_USCNT_MASK) | 984 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 985 986 /* Initialize interframe spacing. EIFS=0x64 is used by a binary-only 987 * driver. Go figure. 988 */ 989 reg = LSHIFT(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 990 LSHIFT(22 * IEEE80211_DUR_DS_SIFS /* # of 22MHz cycles */, 991 ATW_IFST_SIFS_MASK) | 992 LSHIFT(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 993 LSHIFT(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 994 995 ATW_WRITE(sc, ATW_IFST, reg); 996 997 /* XXX More magic. Might relate to ACK timing. */ 998 ATW_WRITE(sc, ATW_RSPT, LSHIFT(0xffff, ATW_RSPT_MART_MASK) | 999 LSHIFT(0xff, ATW_RSPT_MIRT_MASK)); 1000 1001 /* Set up the MMI read/write addresses for the BBP. 1002 * 1003 * TBD find out the Marvel settings. 1004 */ 1005 switch (sc->sc_bbptype) { 1006 case ATW_BBPTYPE_INTERSIL: 1007 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1008 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1009 ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_INTERSIL); 1010 break; 1011 case ATW_BBPTYPE_MARVEL: 1012 break; 1013 case ATW_BBPTYPE_RFMD: 1014 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1015 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1016 ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_RFMD); 1017 default: 1018 break; 1019 } 1020 1021 sc->sc_wepctl = 0; 1022 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1023 1024 if ((error = atw_rf3000_init(sc)) != 0) 1025 goto out; 1026 1027 /* 1028 * Initialize the PCI Access Register. 1029 */ 1030 sc->sc_busmode = ATW_PAR_BAR; /* XXX what is this? */ 1031 1032 /* 1033 * If we're allowed to do so, use Memory Read Line 1034 * and Memory Read Multiple. 1035 * 1036 * XXX Should we use Memory Write and Invalidate? 1037 */ 1038 if (sc->sc_flags & ATWF_MRL) 1039 sc->sc_busmode |= ATW_PAR_MRLE; 1040 if (sc->sc_flags & ATWF_MRM) 1041 sc->sc_busmode |= ATW_PAR_MRME; 1042 if (sc->sc_flags & ATWF_MWI) 1043 sc->sc_busmode |= ATW_PAR_MWIE; 1044 if (sc->sc_maxburst == 0) 1045 sc->sc_maxburst = 8; /* ADM8211 default */ 1046 1047 switch (sc->sc_cacheline) { 1048 default: 1049 /* Use burst length. */ 1050 break; 1051 case 8: 1052 sc->sc_busmode |= ATW_PAR_CAL_8DW; 1053 break; 1054 case 16: 1055 sc->sc_busmode |= ATW_PAR_CAL_16DW; 1056 break; 1057 case 32: 1058 sc->sc_busmode |= ATW_PAR_CAL_32DW; 1059 break; 1060 } 1061 switch (sc->sc_maxburst) { 1062 case 1: 1063 sc->sc_busmode |= ATW_PAR_PBL_1DW; 1064 break; 1065 case 2: 1066 sc->sc_busmode |= ATW_PAR_PBL_2DW; 1067 break; 1068 case 4: 1069 sc->sc_busmode |= ATW_PAR_PBL_4DW; 1070 break; 1071 case 8: 1072 sc->sc_busmode |= ATW_PAR_PBL_8DW; 1073 break; 1074 case 16: 1075 sc->sc_busmode |= ATW_PAR_PBL_16DW; 1076 break; 1077 case 32: 1078 sc->sc_busmode |= ATW_PAR_PBL_32DW; 1079 break; 1080 default: 1081 sc->sc_busmode |= ATW_PAR_PBL_8DW; 1082 break; 1083 } 1084 1085 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1086 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 1087 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1088 1089 /* 1090 * Initialize the OPMODE register. We don't write it until 1091 * we're ready to begin the transmit and receive processes. 1092 */ 1093 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1094 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1095 1096 /* 1097 * Initialize the transmit descriptor ring. 1098 */ 1099 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1100 for (i = 0; i < ATW_NTXDESC; i++) { 1101 sc->sc_txdescs[i].at_ctl = 0; 1102 /* no transmit chaining */ 1103 sc->sc_txdescs[i].at_flags = 0 /* ATW_TXFLAG_TCH */; 1104 sc->sc_txdescs[i].at_buf2 = 1105 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1106 } 1107 /* use ring mode */ 1108 sc->sc_txdescs[ATW_NTXDESC - 1].at_flags |= htole32(ATW_TXFLAG_TER); 1109 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1110 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1111 sc->sc_txfree = ATW_NTXDESC; 1112 sc->sc_txnext = 0; 1113 1114 /* 1115 * Initialize the transmit job descriptors. 1116 */ 1117 SIMPLEQ_INIT(&sc->sc_txfreeq); 1118 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1119 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1120 txs = &sc->sc_txsoft[i]; 1121 txs->txs_mbuf = NULL; 1122 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1123 } 1124 1125 /* 1126 * Initialize the receive descriptor and receive job 1127 * descriptor rings. 1128 */ 1129 for (i = 0; i < ATW_NRXDESC; i++) { 1130 rxs = &sc->sc_rxsoft[i]; 1131 if (rxs->rxs_mbuf == NULL) { 1132 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1133 printf("%s: unable to allocate or map rx " 1134 "buffer %d, error = %d\n", 1135 sc->sc_dev.dv_xname, i, error); 1136 /* 1137 * XXX Should attempt to run with fewer receive 1138 * XXX buffers instead of just failing. 1139 */ 1140 atw_rxdrain(sc); 1141 goto out; 1142 } 1143 } else 1144 ATW_INIT_RXDESC(sc, i); 1145 } 1146 sc->sc_rxptr = 0; 1147 1148 /* disable all wake-up events */ 1149 ATW_CLR(sc, ATW_WCSR, ATW_WCSR_WP1E|ATW_WCSR_WP2E|ATW_WCSR_WP3E| 1150 ATW_WCSR_WP4E|ATW_WCSR_WP5E|ATW_WCSR_TSFTWE| 1151 ATW_WCSR_TIMWE|ATW_WCSR_ATIMWE|ATW_WCSR_KEYWE| 1152 ATW_WCSR_WFRE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1153 1154 /* ack all wake-up events */ 1155 ATW_SET(sc, ATW_WCSR, 0); 1156 1157 /* 1158 * Initialize the interrupt mask and enable interrupts. 1159 */ 1160 /* normal interrupts */ 1161 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1162 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1163 1164 /* abnormal interrupts */ 1165 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1166 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1167 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1168 1169 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1170 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1171 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1172 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1173 ATW_INTR_TRT; 1174 1175 sc->sc_linkint_mask &= sc->sc_inten; 1176 sc->sc_rxint_mask &= sc->sc_inten; 1177 sc->sc_txint_mask &= sc->sc_inten; 1178 1179 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1180 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1181 if (sc->sc_intr_ack != NULL) 1182 (*sc->sc_intr_ack)(sc); 1183 1184 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1185 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten)); 1186 1187 /* 1188 * Give the transmit and receive rings to the ADM8211. 1189 */ 1190 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1191 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1192 1193 /* common 802.11 configuration */ 1194 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1195 switch (ic->ic_opmode) { 1196 case IEEE80211_M_STA: 1197 break; 1198 case IEEE80211_M_AHDEMO: /* XXX */ 1199 case IEEE80211_M_IBSS: 1200 ic->ic_flags |= IEEE80211_F_IBSSON; 1201 /*FALLTHROUGH*/ 1202 case IEEE80211_M_HOSTAP: /* XXX */ 1203 break; 1204 case IEEE80211_M_MONITOR: /* XXX */ 1205 break; 1206 } 1207 1208 atw_start_beacon(sc, 0); 1209 1210 switch (ic->ic_opmode) { 1211 case IEEE80211_M_AHDEMO: 1212 case IEEE80211_M_HOSTAP: 1213 ic->ic_bss->ni_intval = ic->ic_lintval; 1214 ic->ic_bss->ni_rssi = 0; 1215 ic->ic_bss->ni_rstamp = 0; 1216 break; 1217 default: /* XXX */ 1218 break; 1219 } 1220 1221 atw_write_ssid(sc); 1222 atw_write_sup_rates(sc); 1223 if (ic->ic_caps & IEEE80211_C_WEP) 1224 atw_write_wep(sc); 1225 1226 /* 1227 * Set the receive filter. This will start the transmit and 1228 * receive processes. 1229 */ 1230 atw_filter_setup(sc); 1231 1232 /* 1233 * Start the receive process. 1234 */ 1235 ATW_WRITE(sc, ATW_RDR, 0x1); 1236 1237 /* 1238 * Note that the interface is now running. 1239 */ 1240 ifp->if_flags |= IFF_RUNNING; 1241 ifp->if_flags &= ~IFF_OACTIVE; 1242 ic->ic_state = IEEE80211_S_INIT; 1243 1244 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1245 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1246 else 1247 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1248 out: 1249 if (error) { 1250 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1251 ifp->if_timer = 0; 1252 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1253 } 1254#ifdef ATW_DEBUG 1255 atw_print_regs(sc, "end of init"); 1256#endif /* ATW_DEBUG */ 1257 1258 return (error); 1259} 1260 1261/* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1262 * 0: MAC control of RF3000/Si4126. 1263 * 1264 * Applies power, or selects RF front-end? Sets reset condition. 1265 * 1266 * TBD support non-RFMD BBP, non-SiLabs synth. 1267 */ 1268static void 1269atw_rfio_enable(struct atw_softc *sc, int enable) 1270{ 1271 if (enable) { 1272 ATW_WRITE(sc, ATW_SYNRF, 1273 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1274 DELAY(atw_rfio_enable_delay); 1275 } else { 1276 ATW_WRITE(sc, ATW_SYNRF, 0); 1277 DELAY(atw_rfio_disable_delay); /* shorter for some reason */ 1278 } 1279} 1280 1281static int 1282atw_tune(struct atw_softc *sc) 1283{ 1284 int rc; 1285 u_int32_t reg; 1286 int chan; 1287 struct ieee80211com *ic = &sc->sc_ic; 1288 1289 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 1290 if (chan == IEEE80211_CHAN_ANY) 1291 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1292 1293 if (chan == sc->sc_cur_chan) 1294 return 0; 1295 1296 DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname, 1297 sc->sc_cur_chan, chan)); 1298 1299 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1300 1301 if ((rc = atw_si4126_tune(sc, chan)) != 0 || 1302 (rc = atw_rf3000_tune(sc, chan)) != 0) 1303 printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname, 1304 chan); 1305 1306 reg = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 1307 ATW_WRITE(sc, ATW_CAP0, 1308 reg | LSHIFT(chan, ATW_CAP0_CHN_MASK)); 1309 1310 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1311 1312 if (rc == 0) 1313 sc->sc_cur_chan = chan; 1314 1315 return rc; 1316} 1317 1318#ifdef ATW_DEBUG 1319static void 1320atw_si4126_print(struct atw_softc *sc) 1321{ 1322 struct ifnet *ifp = &sc->sc_ic.ic_if; 1323 u_int addr, val; 1324 1325 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1326 return; 1327 1328 for (addr = 0; addr <= 8; addr++) { 1329 printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr); 1330 if (atw_si4126_read(sc, addr, &val) == 0) { 1331 printf("<unknown> (quitting print-out)\n"); 1332 break; 1333 } 1334 printf("%05x\n", val); 1335 } 1336} 1337#endif /* ATW_DEBUG */ 1338 1339/* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1340 * 1341 * The RF/IF synthesizer produces two reference frequencies for 1342 * the RF2948B transceiver. The first frequency the RF2948B requires 1343 * is two times the so-called "intermediate frequency" (IF). Since 1344 * a SAW filter on the radio fixes the IF at 374MHz, I program the 1345 * Si4126 to generate IF LO = 374MHz x 2 = 748MHz. The second 1346 * frequency required by the transceiver is the radio frequency 1347 * (RF). This is a superheterodyne transceiver; for f(chan) the 1348 * center frequency of the channel we are tuning, RF = f(chan) - 1349 * IF. 1350 * 1351 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1352 * of XIN than the 2-25MHz mentioned by the datasheet, even *without* 1353 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1354 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1355 */ 1356static int 1357atw_si4126_tune(struct atw_softc *sc, u_int8_t chan) 1358{ 1359 int rc = 0; 1360 u_int mhz; 1361 u_int R; 1362 u_int32_t reg; 1363 u_int16_t gain; 1364 1365#ifdef ATW_DEBUG 1366 atw_si4126_print(sc); 1367#endif /* ATW_DEBUG */ 1368 1369 if (chan == 14) 1370 mhz = 2484; 1371 else 1372 mhz = 2412 + 5 * (chan - 1); 1373 1374 /* Tune IF to 748MHz to suit the IF LO input of the 1375 * RF2494B, which is 2 x IF. No need to set an IF divider 1376 * because an IF in 526MHz - 952MHz is allowed. 1377 * 1378 * XIN is 44.000MHz, so divide it by two to get allowable 1379 * range of 2-25MHz. SiLabs tells me that this is not 1380 * strictly necessary. 1381 */ 1382 1383 R = 44; 1384 1385 atw_rfio_enable(sc, 1); 1386 1387 /* Power-up RF, IF synthesizers. */ 1388 if ((rc = atw_si4126_write(sc, SI4126_POWER, 1389 SI4126_POWER_PDIB|SI4126_POWER_PDRB)) != 0) 1390 goto out; 1391 1392 /* If RF2 N > 2047, then set KP2 to 1. */ 1393 gain = LSHIFT(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1394 1395 if ((rc = atw_si4126_write(sc, SI4126_GAIN, gain)) != 0) 1396 goto out; 1397 1398 /* set LPWR, too? */ 1399 if ((rc = atw_si4126_write(sc, SI4126_MAIN, 1400 SI4126_MAIN_XINDIV2)) != 0) 1401 goto out; 1402 1403 /* We set XINDIV2 = 1, so IF = N/(2 * R) * XIN. XIN = 44MHz. 1404 * I choose N = 1496, R = 44 so that 1496/(2 * 44) * 44MHz = 748MHz. 1405 */ 1406 if ((rc = atw_si4126_write(sc, SI4126_IFN, 1496)) != 0) 1407 goto out; 1408 1409 if ((rc = atw_si4126_write(sc, SI4126_IFR, R)) != 0) 1410 goto out; 1411 1412 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1413 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1414 * which has no RF1! 1415 */ 1416 if ((rc = atw_si4126_write(sc, SI4126_RF1R, R)) != 0) 1417 goto out; 1418 1419 if ((rc = atw_si4126_write(sc, SI4126_RF1N, mhz - 374)) != 0) 1420 goto out; 1421 1422 /* N/R * XIN = RF. XIN = 44MHz. We desire RF = mhz - IF, 1423 * where IF = 374MHz. Let's divide XIN to 1MHz. So R = 44. 1424 * Now let's multiply it to mhz. So mhz - IF = N. 1425 */ 1426 if ((rc = atw_si4126_write(sc, SI4126_RF2R, R)) != 0) 1427 goto out; 1428 1429 if ((rc = atw_si4126_write(sc, SI4126_RF2N, mhz - 374)) != 0) 1430 goto out; 1431 1432 /* wait 100us from power-up for RF, IF to settle */ 1433 DELAY(100); 1434 1435 if ((sc->sc_if.if_flags & IFF_LINK1) == 0 || chan == 14) { 1436 /* XXX there is a binary driver which sends 1437 * ATW_GPIO_EN_MASK = 1, ATW_GPIO_O_MASK = 1. I had speculated 1438 * that this enables the Si4126 by raising its PWDN#, but I 1439 * think that it actually sets the Prism RF front-end 1440 * to a special mode for channel 14. 1441 */ 1442 reg = ATW_READ(sc, ATW_GPIO); 1443 reg &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1444 reg |= LSHIFT(1, ATW_GPIO_EN_MASK) | LSHIFT(1, ATW_GPIO_O_MASK); 1445 ATW_WRITE(sc, ATW_GPIO, reg); 1446 } 1447 1448#ifdef ATW_DEBUG 1449 atw_si4126_print(sc); 1450#endif /* ATW_DEBUG */ 1451 1452out: 1453 atw_rfio_enable(sc, 0); 1454 1455 return rc; 1456} 1457 1458/* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1459 * diversity. 1460 * 1461 * Call this w/ Tx/Rx suspended. 1462 */ 1463static int 1464atw_rf3000_init(struct atw_softc *sc) 1465{ 1466 int rc = 0; 1467 1468 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1469 1470 atw_rfio_enable(sc, 1); 1471 1472 /* enable diversity */ 1473 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1474 1475 if (rc != 0) 1476 goto out; 1477 1478 /* sensible setting from a binary-only driver */ 1479 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1480 LSHIFT(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1481 1482 if (rc != 0) 1483 goto out; 1484 1485 /* magic from a binary-only driver */ 1486 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1487 LSHIFT(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1488 1489 if (rc != 0) 1490 goto out; 1491 1492 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1493 1494 if (rc != 0) 1495 goto out; 1496 1497 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1498 1499 if (rc != 0) 1500 goto out; 1501 1502 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1503 1504 if (rc != 0) 1505 goto out; 1506 1507 /* CCA is acquisition sensitive */ 1508 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1509 LSHIFT(RF3000_CCACTL_MODE_ACQ, RF3000_CCACTL_MODE_MASK)); 1510 1511 if (rc != 0) 1512 goto out; 1513 1514out: 1515 atw_rfio_enable(sc, 0); 1516 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1517 return rc; 1518} 1519 1520#ifdef ATW_DEBUG 1521static void 1522atw_rf3000_print(struct atw_softc *sc) 1523{ 1524 struct ifnet *ifp = &sc->sc_ic.ic_if; 1525 u_int addr, val; 1526 1527 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1528 return; 1529 1530 for (addr = 0x01; addr <= 0x15; addr++) { 1531 printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr); 1532 if (atw_rf3000_read(sc, addr, &val) != 0) { 1533 printf("<unknown> (quitting print-out)\n"); 1534 break; 1535 } 1536 printf("%08x\n", val); 1537 } 1538} 1539#endif /* ATW_DEBUG */ 1540 1541/* Set the power settings on the BBP for channel `chan'. */ 1542static int 1543atw_rf3000_tune(struct atw_softc *sc, u_int8_t chan) 1544{ 1545 int rc = 0; 1546 u_int32_t reg; 1547 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1548 1549 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1550 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1551 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1552 1553 /* odd channels: LSB, even channels: MSB */ 1554 if (chan % 2 == 1) { 1555 txpower &= 0xFF; 1556 lpf_cutoff &= 0xFF; 1557 lna_gs_thresh &= 0xFF; 1558 } else { 1559 txpower >>= 8; 1560 lpf_cutoff >>= 8; 1561 lna_gs_thresh >>= 8; 1562 } 1563 1564#ifdef ATW_DEBUG 1565 atw_rf3000_print(sc); 1566#endif /* ATW_DEBUG */ 1567 1568 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1569 "lna_gs_thresh %02x\n", 1570 sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh)); 1571 1572 atw_rfio_enable(sc, 1); 1573 1574 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1575 LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1576 goto out; 1577 1578 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1579 goto out; 1580 1581 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1582 goto out; 1583 1584 /* from a binary-only driver. */ 1585 reg = ATW_READ(sc, ATW_PLCPHD); 1586 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1587 reg |= LSHIFT(LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK), 1588 ATW_PLCPHD_SERVICE_MASK); 1589 ATW_WRITE(sc, ATW_PLCPHD, reg); 1590 1591#ifdef ATW_DEBUG 1592 atw_rf3000_print(sc); 1593#endif /* ATW_DEBUG */ 1594 1595out: 1596 atw_rfio_enable(sc, 0); 1597 1598 return rc; 1599} 1600 1601/* Write a register on the RF3000 baseband processor using the 1602 * registers provided by the ADM8211 for this purpose. 1603 * 1604 * Return 0 on success. 1605 */ 1606static int 1607atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1608{ 1609 u_int32_t reg; 1610 int i; 1611 1612 for (i = 1000; --i >= 0; ) { 1613 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1614 break; 1615 DELAY(100); 1616 } 1617 1618 if (i < 0) { 1619 printf("%s: BBPCTL busy (pre-write)\n", sc->sc_dev.dv_xname); 1620 return ETIMEDOUT; 1621 } 1622 1623 reg = sc->sc_bbpctl_wr | 1624 LSHIFT(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1625 LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1626 1627 ATW_WRITE(sc, ATW_BBPCTL, reg); 1628 1629 for (i = 1000; --i >= 0; ) { 1630 DELAY(100); 1631 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1632 break; 1633 } 1634 1635 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_WR); 1636 1637 if (i < 0) { 1638 printf("%s: BBPCTL busy (post-write)\n", sc->sc_dev.dv_xname); 1639 return ETIMEDOUT; 1640 } 1641 return 0; 1642} 1643 1644/* Read a register on the RF3000 baseband processor using the registers 1645 * the ADM8211 provides for this purpose. 1646 * 1647 * The 7-bit register address is addr. Record the 8-bit data in the register 1648 * in *val. 1649 * 1650 * Return 0 on success. 1651 * 1652 * XXX This does not seem to work. The ADM8211 must require more or 1653 * different magic to read the chip than to write it. Possibly some 1654 * of the magic I have derived from a binary-only driver concerns 1655 * the "chip address" (see the RF3000 manual). 1656 */ 1657#ifdef ATW_DEBUG 1658static int 1659atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1660{ 1661 u_int32_t reg; 1662 int i; 1663 1664 for (i = 1000; --i >= 0; ) { 1665 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1666 break; 1667 DELAY(100); 1668 } 1669 1670 if (i < 0) { 1671 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1672 sc->sc_dev.dv_xname); 1673 return ETIMEDOUT; 1674 } 1675 1676 reg = sc->sc_bbpctl_rd | LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1677 1678 ATW_WRITE(sc, ATW_BBPCTL, reg); 1679 1680 for (i = 1000; --i >= 0; ) { 1681 DELAY(100); 1682 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1683 break; 1684 } 1685 1686 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1687 1688 if (i < 0) { 1689 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1690 sc->sc_dev.dv_xname, reg); 1691 return ETIMEDOUT; 1692 } 1693 if (val != NULL) 1694 *val = MASK_AND_RSHIFT(reg, ATW_BBPCTL_DATA_MASK); 1695 return 0; 1696} 1697#endif /* ATW_DEBUG */ 1698 1699/* Write a register on the Si4126 RF/IF synthesizer using the registers 1700 * provided by the ADM8211 for that purpose. 1701 * 1702 * val is 18 bits of data, and val is the 4-bit address of the register. 1703 * 1704 * Return 0 on success. 1705 */ 1706static int 1707atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1708{ 1709 u_int32_t bits, reg; 1710 int i; 1711 1712 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1713 KASSERT((val & ~PRESHIFT(SI4126_TWI_DATA_MASK)) == 0); 1714 1715 for (i = 1000; --i >= 0; ) { 1716 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1717 break; 1718 DELAY(100); 1719 } 1720 1721 if (i < 0) { 1722 printf("%s: start atw_si4126_write, SYNCTL busy\n", 1723 sc->sc_dev.dv_xname); 1724 return ETIMEDOUT; 1725 } 1726 1727 bits = LSHIFT(val, SI4126_TWI_DATA_MASK) | 1728 LSHIFT(addr, SI4126_TWI_ADDR_MASK); 1729 1730 reg = sc->sc_synctl_wr | LSHIFT(bits, ATW_SYNCTL_DATA_MASK); 1731 1732 ATW_WRITE(sc, ATW_SYNCTL, reg); 1733 1734 for (i = 1000; --i >= 0; ) { 1735 DELAY(100); 1736 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_WR) == 0) 1737 break; 1738 } 1739 1740 /* restore to acceptable starting condition */ 1741 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_WR); 1742 1743 if (i < 0) { 1744 printf("%s: atw_si4126_write wrote %08x, SYNCTL still busy\n", 1745 sc->sc_dev.dv_xname, reg); 1746 return ETIMEDOUT; 1747 } 1748 return 0; 1749} 1750 1751/* Read 18-bit data from the 4-bit address addr in Si4126 1752 * RF synthesizer and write the data to *val. Return 0 on success. 1753 * 1754 * XXX This does not seem to work. The ADM8211 must require more or 1755 * different magic to read the chip than to write it. 1756 */ 1757#ifdef ATW_DEBUG 1758static int 1759atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1760{ 1761 u_int32_t reg; 1762 int i; 1763 1764 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1765 1766 for (i = 1000; --i >= 0; ) { 1767 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1768 break; 1769 DELAY(100); 1770 } 1771 1772 if (i < 0) { 1773 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1774 sc->sc_dev.dv_xname); 1775 return ETIMEDOUT; 1776 } 1777 1778 reg = sc->sc_synctl_rd | LSHIFT(addr, ATW_SYNCTL_DATA_MASK); 1779 1780 ATW_WRITE(sc, ATW_SYNCTL, reg); 1781 1782 for (i = 1000; --i >= 0; ) { 1783 DELAY(100); 1784 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1785 break; 1786 } 1787 1788 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1789 1790 if (i < 0) { 1791 printf("%s: atw_si4126_read wrote %08x, SYNCTL still busy\n", 1792 sc->sc_dev.dv_xname, reg); 1793 return ETIMEDOUT; 1794 } 1795 if (val != NULL) 1796 *val = MASK_AND_RSHIFT(ATW_READ(sc, ATW_SYNCTL), 1797 ATW_SYNCTL_DATA_MASK); 1798 return 0; 1799} 1800#endif /* ATW_DEBUG */ 1801 1802/* XXX is the endianness correct? test. */ 1803#define atw_calchash(addr) \ 1804 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 1805 1806/* 1807 * atw_filter_setup: 1808 * 1809 * Set the ADM8211's receive filter. 1810 */ 1811static void 1812atw_filter_setup(struct atw_softc *sc) 1813{ 1814 struct ieee80211com *ic = &sc->sc_ic; 1815 struct ethercom *ec = &ic->ic_ec; 1816 struct ifnet *ifp = &sc->sc_ic.ic_if; 1817 int hash; 1818 u_int32_t hashes[2] = { 0, 0 }; 1819 struct ether_multi *enm; 1820 struct ether_multistep step; 1821 1822 DPRINTF(sc, ("%s: atw_filter_setup: sc_flags 0x%08x\n", 1823 sc->sc_dev.dv_xname, sc->sc_flags)); 1824 1825 /* 1826 * If we're running, idle the receive engine. If we're NOT running, 1827 * we're being called from atw_init(), and our writing ATW_NAR will 1828 * start the transmit and receive processes in motion. 1829 */ 1830 if (ifp->if_flags & IFF_RUNNING) 1831 atw_idle(sc, ATW_NAR_SR); 1832 1833 sc->sc_opmode &= ~(ATW_NAR_PR|ATW_NAR_MM); 1834 1835 ifp->if_flags &= ~IFF_ALLMULTI; 1836 1837 if (ifp->if_flags & IFF_PROMISC) { 1838 sc->sc_opmode |= ATW_NAR_PR; 1839allmulti: 1840 ifp->if_flags |= IFF_ALLMULTI; 1841 goto setit; 1842 } 1843 1844 /* 1845 * Program the 64-bit multicast hash filter. 1846 */ 1847 ETHER_FIRST_MULTI(step, ec, enm); 1848 while (enm != NULL) { 1849 /* XXX */ 1850 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1851 ETHER_ADDR_LEN) != 0) 1852 goto allmulti; 1853 1854 hash = atw_calchash(enm->enm_addrlo); 1855 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1856 ETHER_NEXT_MULTI(step, enm); 1857 } 1858 1859 if (ifp->if_flags & IFF_BROADCAST) { 1860 hash = atw_calchash(etherbroadcastaddr); 1861 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1862 } 1863 1864 /* all bits set => hash is useless */ 1865 if (~(hashes[0] & hashes[1]) == 0) 1866 goto allmulti; 1867 1868 setit: 1869 if (ifp->if_flags & IFF_ALLMULTI) 1870 sc->sc_opmode |= ATW_NAR_MM; 1871 1872 /* XXX in scan mode, do not filter packets. maybe this is 1873 * unnecessary. 1874 */ 1875 if (ic->ic_state == IEEE80211_S_SCAN) 1876 sc->sc_opmode |= ATW_NAR_PR; 1877 1878 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 1879 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 1880 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1881 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname, 1882 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 1883 1884 DPRINTF(sc, ("%s: atw_filter_setup: returning\n", sc->sc_dev.dv_xname)); 1885} 1886 1887/* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 1888 * a beacon's BSSID and SSID against the preferred BSSID and SSID 1889 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 1890 * no beacon with the preferred BSSID and SSID in the number of 1891 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 1892 */ 1893static void 1894atw_write_bssid(struct atw_softc *sc) 1895{ 1896 struct ieee80211com *ic = &sc->sc_ic; 1897 u_int8_t *bssid; 1898 1899 bssid = ic->ic_bss->ni_bssid; 1900 1901 ATW_WRITE(sc, ATW_BSSID0, 1902 LSHIFT(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 1903 LSHIFT(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 1904 LSHIFT(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 1905 LSHIFT(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 1906 1907 ATW_WRITE(sc, ATW_ABDA1, 1908 (ATW_READ(sc, ATW_ABDA1) & 1909 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 1910 LSHIFT(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 1911 LSHIFT(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 1912 1913 DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname, 1914 ether_sprintf(sc->sc_bssid))); 1915 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 1916 1917 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 1918} 1919 1920/* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 1921 * 16-bit word. 1922 */ 1923static void 1924atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) 1925{ 1926 u_int i; 1927 u_int8_t *ptr; 1928 1929 memcpy(&sc->sc_sram[ofs], buf, buflen); 1930 1931 if (ofs % 2 != 0) { 1932 ofs--; 1933 buflen++; 1934 } 1935 1936 if (buflen % 2 != 0) 1937 buflen++; 1938 1939 assert(buflen + ofs <= ATW_SRAM_SIZE); 1940 1941 ptr = &sc->sc_sram[ofs]; 1942 1943 for (i = 0; i < buflen; i += 2) { 1944 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 1945 LSHIFT((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 1946 DELAY(atw_writewep_delay); 1947 1948 ATW_WRITE(sc, ATW_WESK, 1949 LSHIFT((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 1950 DELAY(atw_writewep_delay); 1951 } 1952 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 1953 1954 if (sc->sc_if.if_flags & IFF_DEBUG) { 1955 int n_octets = 0; 1956 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 1957 sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl); 1958 for (i = 0; i < buflen; i++) { 1959 printf(" %02x", ptr[i]); 1960 if (++n_octets % 24 == 0) 1961 printf("\n"); 1962 } 1963 if (n_octets % 24 != 0) 1964 printf("\n"); 1965 } 1966} 1967 1968/* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 1969static void 1970atw_write_wep(struct atw_softc *sc) 1971{ 1972 struct ieee80211com *ic = &sc->sc_ic; 1973 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 1974 u_int8_t buf[IEEE80211_WEP_NKID] 1975 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 1976 u_int32_t reg; 1977 int i; 1978 1979 sc->sc_wepctl = 0; 1980 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 1981 1982 if ((ic->ic_flags & IEEE80211_F_WEPON) == 0) 1983 return; 1984 1985 memset(&buf[0][0], 0, sizeof(buf)); 1986 1987 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 1988 if (ic->ic_nw_keys[i].wk_len > 5) { 1989 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 1990 } else if (ic->ic_nw_keys[i].wk_len != 0) { 1991 buf[i][1] = ATW_WEP_ENABLED; 1992 } else { 1993 buf[i][1] = 0; 1994 continue; 1995 } 1996 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 1997 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 1998 ic->ic_nw_keys[i].wk_len - 1); 1999 } 2000 2001 reg = ATW_READ(sc, ATW_MACTEST); 2002 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2003 reg &= ~ATW_MACTEST_KEYID_MASK; 2004 reg |= LSHIFT(ic->ic_wep_txkey, ATW_MACTEST_KEYID_MASK); 2005 ATW_WRITE(sc, ATW_MACTEST, reg); 2006 2007 /* RX bypass WEP if revision != 0x20. (I assume revision != 0x20 2008 * throughout.) 2009 */ 2010 sc->sc_wepctl = ATW_WEPCTL_WEPENABLE | ATW_WEPCTL_WEPRXBYP; 2011 if (sc->sc_if.if_flags & IFF_LINK2) 2012 sc->sc_wepctl &= ~ATW_WEPCTL_WEPRXBYP; 2013 2014 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2015 sizeof(buf)); 2016} 2017 2018const struct timeval atw_beacon_mininterval = {1, 0}; /* 1s */ 2019 2020static void 2021atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2022 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2023{ 2024 struct atw_softc *sc = (struct atw_softc*)ic->ic_softc; 2025 2026 switch (subtype) { 2027 case IEEE80211_FC0_SUBTYPE_PROBE_REQ: 2028 /* do nothing: hardware answers probe request */ 2029 break; 2030 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2031 case IEEE80211_FC0_SUBTYPE_BEACON: 2032 atw_recv_beacon(ic, m, ni, subtype, rssi, rstamp); 2033 break; 2034 default: 2035 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2036 break; 2037 } 2038 return; 2039} 2040 2041/* In ad hoc mode, atw_recv_beacon is responsible for the coalescence 2042 * of IBSSs with like SSID/channel but different BSSID. It joins the 2043 * oldest IBSS (i.e., with greatest TSF time), since that is the WECA 2044 * convention. Possibly the ADMtek chip does this for us; I will have 2045 * to test to find out. 2046 * 2047 * XXX we should add the duration field of the received beacon to 2048 * the TSF time it contains before comparing it with the ADM8211's 2049 * TSF. 2050 */ 2051static void 2052atw_recv_beacon(struct ieee80211com *ic, struct mbuf *m0, 2053 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2054{ 2055 struct atw_softc *sc; 2056 struct ieee80211_frame *wh; 2057 uint32_t tsftl, tsfth; 2058 uint32_t bcn_tsftl, bcn_tsfth; 2059 int do_print = 0; 2060 union { 2061 uint32_t words[2]; 2062 uint8_t tstamp[8]; 2063 } u; 2064 2065 sc = (struct atw_softc*)ic->ic_if.if_softc; 2066 2067 if (ic->ic_if.if_flags & IFF_LINK0) { 2068 do_print = (ic->ic_if.if_flags & IFF_DEBUG) 2069 ? 1 : ratecheck(&sc->sc_last_beacon, 2070 &atw_beacon_mininterval); 2071 } 2072 2073 wh = mtod(m0, struct ieee80211_frame *); 2074 2075 (*sc->sc_recv_mgmt)(ic, m0, ni, subtype, rssi, rstamp); 2076 2077 if (ic->ic_state != IEEE80211_S_RUN) 2078 return; 2079 2080 if ((ni = ieee80211_lookup_node(ic, wh->i_addr2, 2081 ic->ic_bss->ni_chan)) == NULL) { 2082 if (do_print) 2083 printf("%s: atw_recv_beacon: no node %s\n", 2084 sc->sc_dev.dv_xname, ether_sprintf(wh->i_addr2)); 2085 return; 2086 } 2087 2088 if (ieee80211_match_bss(ic, ni) != 0) 2089 return; 2090 2091 if (memcmp(ni->ni_bssid, ic->ic_bss->ni_bssid, IEEE80211_ADDR_LEN) == 0) 2092 return; 2093 2094 if (do_print) 2095 printf("%s: atw_recv_beacon: bssid mismatch %s\n", 2096 sc->sc_dev.dv_xname, ether_sprintf(ni->ni_bssid)); 2097 2098 if (ic->ic_opmode != IEEE80211_M_IBSS) 2099 return; 2100 2101 atw_tsft(sc, &tsfth, &tsftl); 2102 2103 (void)memcpy(&u, &ic->ic_bss->ni_tstamp[0], sizeof(u)); 2104 bcn_tsftl = le32toh(u.words[0]); 2105 bcn_tsfth = le32toh(u.words[1]); 2106 2107 if (do_print) 2108 printf("%s: my tsft %" PRIu64 " beacon tsft %" PRIu64 "\n", 2109 sc->sc_dev.dv_xname, ((uint64_t)tsfth << 32) | tsftl, 2110 ((uint64_t)bcn_tsfth << 32) | bcn_tsftl); 2111 2112 /* we are faster, let the other guy catch up */ 2113 if (bcn_tsfth < tsfth) 2114 return; 2115 else if (bcn_tsfth == tsfth && bcn_tsftl < tsftl) 2116 return; 2117 2118 if (do_print) 2119 printf("%s: sync TSF with %s\n", sc->sc_dev.dv_xname, 2120 ether_sprintf(wh->i_addr2)); 2121 2122 ic->ic_flags &= ~IEEE80211_F_SIBSS; 2123 2124 atw_tsf(sc); 2125 2126 /* negotiate rates with new IBSS */ 2127 ieee80211_fix_rate(ic, ni, IEEE80211_F_DOFRATE | 2128 IEEE80211_F_DONEGO | IEEE80211_F_DODEL); 2129 if (ni->ni_rates.rs_nrates == 0) { 2130 printf("%s: rates mismatch, BSSID %s\n", sc->sc_dev.dv_xname, 2131 ether_sprintf(ni->ni_bssid)); 2132 return; 2133 } 2134 2135 if (do_print) { 2136 printf("%s: sync BSSID %s -> ", sc->sc_dev.dv_xname, 2137 ether_sprintf(ic->ic_bss->ni_bssid)); 2138 printf("%s ", ether_sprintf(ni->ni_bssid)); 2139 printf("(from %s)\n", ether_sprintf(wh->i_addr2)); 2140 } 2141 2142 (*ic->ic_node_copy)(ic, ic->ic_bss, ni); 2143 2144 atw_write_bssid(sc); 2145 atw_start_beacon(sc, 1); 2146} 2147 2148/* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2149 * In ad hoc mode, the SSID is written to the beacons sent by the 2150 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2151 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2152 * indications. 2153 */ 2154static void 2155atw_write_ssid(struct atw_softc *sc) 2156{ 2157 struct ieee80211com *ic = &sc->sc_ic; 2158 /* 34 bytes are reserved in ADM8211 SRAM for the SSID, but 2159 * it only expects the element length, not its ID. 2160 */ 2161 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2162 2163 memset(buf, 0, sizeof(buf)); 2164 buf[0] = ic->ic_bss->ni_esslen; 2165 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2166 2167 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, 2168 roundup(1 + ic->ic_bss->ni_esslen, 2)); 2169} 2170 2171/* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2172 * In ad hoc mode, the supported rates are written to beacons sent by the 2173 * ADM8211. 2174 */ 2175static void 2176atw_write_sup_rates(struct atw_softc *sc) 2177{ 2178 struct ieee80211com *ic = &sc->sc_ic; 2179 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2180 * supported rates 2181 */ 2182 u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; 2183 2184 memset(buf, 0, sizeof(buf)); 2185 2186 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2187 2188 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2189 ic->ic_bss->ni_rates.rs_nrates); 2190 2191 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2192} 2193 2194/* Start/stop sending beacons. */ 2195void 2196atw_start_beacon(struct atw_softc *sc, int start) 2197{ 2198 struct ieee80211com *ic = &sc->sc_ic; 2199 uint16_t chan; 2200 uint32_t bcnt, bpli, cap0, cap1, capinfo; 2201 size_t len; 2202 2203 if (ATW_IS_ENABLED(sc) == 0) 2204 return; 2205 2206 /* start beacons */ 2207 len = sizeof(struct ieee80211_frame) + 2208 8 /* timestamp */ + 2 /* beacon interval */ + 2209 2 /* capability info */ + 2210 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2211 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2212 3 /* DS parameters */ + 2213 IEEE80211_CRC_LEN; 2214 2215 bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2216 cap0 = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 2217 cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2218 2219 ATW_WRITE(sc, ATW_BCNT, bcnt); 2220 ATW_WRITE(sc, ATW_CAP1, cap1); 2221 2222 if (!start) 2223 return; 2224 2225 /* TBD use ni_capinfo */ 2226 2227 capinfo = 0; 2228 if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2229 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2230 if (ic->ic_flags & IEEE80211_F_WEPON) 2231 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2232 2233 switch (ic->ic_opmode) { 2234 case IEEE80211_M_IBSS: 2235 len += 4; /* IBSS parameters */ 2236 capinfo |= IEEE80211_CAPINFO_IBSS; 2237 break; 2238 case IEEE80211_M_HOSTAP: 2239 /* XXX 6-byte minimum TIM */ 2240 len += atw_beacon_len_adjust; 2241 capinfo |= IEEE80211_CAPINFO_ESS; 2242 break; 2243 default: 2244 return; 2245 } 2246 2247 /* set listen interval 2248 * XXX do software units agree w/ hardware? 2249 */ 2250 bpli = LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2251 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK); 2252 2253 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 2254 2255 bcnt |= LSHIFT(len, ATW_BCNT_BCNT_MASK); 2256 cap0 |= LSHIFT(chan, ATW_CAP0_CHN_MASK); 2257 cap1 |= LSHIFT(capinfo, ATW_CAP1_CAPI_MASK); 2258 2259 ATW_WRITE(sc, ATW_BCNT, bcnt); 2260 ATW_WRITE(sc, ATW_BPLI, bpli); 2261 ATW_WRITE(sc, ATW_CAP0, cap0); 2262 ATW_WRITE(sc, ATW_CAP1, cap1); 2263 2264 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2265 sc->sc_dev.dv_xname, bcnt)); 2266 2267 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2268 sc->sc_dev.dv_xname, cap1)); 2269} 2270 2271/* Return the 32 lsb of the last TSFT divisible by ival. */ 2272static __inline uint32_t 2273atw_last_even_tsft(uint32_t tsfth, uint32_t tsftl, uint32_t ival) 2274{ 2275 /* Following the reference driver's lead, I compute 2276 * 2277 * (uint32_t)((((uint64_t)tsfth << 32) | tsftl) % ival) 2278 * 2279 * without using 64-bit arithmetic, using the following 2280 * relationship: 2281 * 2282 * (0x100000000 * H + L) % m 2283 * = ((0x100000000 % m) * H + L) % m 2284 * = (((0xffffffff + 1) % m) * H + L) % m 2285 * = ((0xffffffff % m + 1 % m) * H + L) % m 2286 * = ((0xffffffff % m + 1) * H + L) % m 2287 */ 2288 return ((0xFFFFFFFF % ival + 1) * tsfth + tsftl) % ival; 2289} 2290 2291static __inline void 2292atw_tsft(struct atw_softc *sc, uint32_t *tsfth, uint32_t *tsftl) 2293{ 2294 int i; 2295 for (i = 0; i < 2; i++) { 2296 *tsfth = ATW_READ(sc, ATW_TSFTH); 2297 *tsftl = ATW_READ(sc, ATW_TSFTL); 2298 if (ATW_READ(sc, ATW_TSFTH) == *tsfth) 2299 break; 2300 } 2301} 2302 2303/* If we've created an IBSS, write the TSF time in the ADM8211 to 2304 * the ieee80211com. 2305 * 2306 * Predict the next target beacon transmission time (TBTT) and 2307 * write it to the ADM8211. 2308 */ 2309static void 2310atw_tsf(struct atw_softc *sc) 2311{ 2312#define TBTTOFS 20 /* TU */ 2313 2314 struct ieee80211com *ic = &sc->sc_ic; 2315 uint32_t ival, past_even, tbtt, tsfth, tsftl; 2316 union { 2317 uint32_t words[2]; 2318 uint8_t tstamp[8]; 2319 } u; 2320 2321 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2322 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2323 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2324 atw_tsft(sc, &tsfth, &tsftl); 2325 u.words[0] = htole32(tsftl); 2326 u.words[1] = htole32(tsfth); 2327 (void)memcpy(&ic->ic_bss->ni_tstamp[0], &u, 2328 sizeof(ic->ic_bss->ni_tstamp)); 2329 } else { 2330 (void)memcpy(&u, &ic->ic_bss->ni_tstamp[0], sizeof(u)); 2331 tsftl = le32toh(u.words[0]); 2332 tsfth = le32toh(u.words[1]); 2333 } 2334 2335 ival = ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2336 2337 /* We sent/received the last beacon `past' microseconds 2338 * after the interval divided the TSF timer. 2339 */ 2340 past_even = tsftl - atw_last_even_tsft(tsfth, tsftl, ival); 2341 2342 /* Skip ten beacons so that the TBTT cannot pass before 2343 * we've programmed it. Ten is an arbitrary number. 2344 */ 2345 tbtt = past_even + ival * 10; 2346 2347 ATW_WRITE(sc, ATW_TOFS1, 2348 LSHIFT(1, ATW_TOFS1_TSFTOFSR_MASK) | 2349 LSHIFT(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2350 LSHIFT(MASK_AND_RSHIFT(tbtt - TBTTOFS * IEEE80211_DUR_TU, 2351 ATW_TBTTPRE_MASK), ATW_TOFS1_TBTTPRE_MASK)); 2352#undef TBTTOFS 2353} 2354 2355static void 2356atw_next_scan(void *arg) 2357{ 2358 struct atw_softc *sc = arg; 2359 struct ieee80211com *ic = &sc->sc_ic; 2360 struct ifnet *ifp = &ic->ic_if; 2361 int s; 2362 2363 /* don't call atw_start w/o network interrupts blocked */ 2364 s = splnet(); 2365 if (ic->ic_state == IEEE80211_S_SCAN) 2366 ieee80211_next_scan(ifp); 2367 splx(s); 2368} 2369 2370/* Synchronize the hardware state with the software state. */ 2371static int 2372atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2373{ 2374 struct ifnet *ifp = &ic->ic_if; 2375 struct atw_softc *sc = ifp->if_softc; 2376 enum ieee80211_state ostate; 2377 int error; 2378 2379 ostate = ic->ic_state; 2380 2381 if (nstate == IEEE80211_S_INIT) { 2382 callout_stop(&sc->sc_scan_ch); 2383 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2384 atw_start_beacon(sc, 0); 2385 return (*sc->sc_newstate)(ic, nstate, arg); 2386 } 2387 2388 if ((error = atw_tune(sc)) != 0) 2389 return error; 2390 2391 switch (nstate) { 2392 case IEEE80211_S_ASSOC: 2393 break; 2394 case IEEE80211_S_INIT: 2395 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 2396 break; 2397 case IEEE80211_S_SCAN: 2398 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2399 atw_next_scan, sc); 2400 2401 break; 2402 case IEEE80211_S_RUN: 2403 if (ic->ic_opmode == IEEE80211_M_STA) 2404 break; 2405 /*FALLTHROUGH*/ 2406 case IEEE80211_S_AUTH: 2407 atw_write_bssid(sc); 2408 atw_write_ssid(sc); 2409 atw_write_sup_rates(sc); 2410 2411 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2412 ic->ic_opmode == IEEE80211_M_MONITOR) 2413 break; 2414 2415 /* set listen interval 2416 * XXX do software units agree w/ hardware? 2417 */ 2418 ATW_WRITE(sc, ATW_BPLI, 2419 LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2420 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, 2421 ATW_BPLI_LI_MASK)); 2422 2423 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", 2424 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_BPLI))); 2425 2426 atw_tsf(sc); 2427 break; 2428 } 2429 2430 if (nstate != IEEE80211_S_SCAN) 2431 callout_stop(&sc->sc_scan_ch); 2432 2433 if (nstate == IEEE80211_S_RUN && 2434 (ic->ic_opmode == IEEE80211_M_HOSTAP || 2435 ic->ic_opmode == IEEE80211_M_IBSS)) 2436 atw_start_beacon(sc, 1); 2437 else 2438 atw_start_beacon(sc, 0); 2439 2440 error = (*sc->sc_newstate)(ic, nstate, arg); 2441 2442 if (ostate == IEEE80211_S_INIT && nstate == IEEE80211_S_SCAN) 2443 atw_write_bssid(sc); 2444 2445 return error; 2446} 2447 2448/* 2449 * atw_add_rxbuf: 2450 * 2451 * Add a receive buffer to the indicated descriptor. 2452 */ 2453int 2454atw_add_rxbuf(struct atw_softc *sc, int idx) 2455{ 2456 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2457 struct mbuf *m; 2458 int error; 2459 2460 MGETHDR(m, M_DONTWAIT, MT_DATA); 2461 if (m == NULL) 2462 return (ENOBUFS); 2463 2464 MCLGET(m, M_DONTWAIT); 2465 if ((m->m_flags & M_EXT) == 0) { 2466 m_freem(m); 2467 return (ENOBUFS); 2468 } 2469 2470 if (rxs->rxs_mbuf != NULL) 2471 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2472 2473 rxs->rxs_mbuf = m; 2474 2475 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2476 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2477 BUS_DMA_READ|BUS_DMA_NOWAIT); 2478 if (error) { 2479 printf("%s: can't load rx DMA map %d, error = %d\n", 2480 sc->sc_dev.dv_xname, idx, error); 2481 panic("atw_add_rxbuf"); /* XXX */ 2482 } 2483 2484 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2485 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2486 2487 ATW_INIT_RXDESC(sc, idx); 2488 2489 return (0); 2490} 2491 2492/* 2493 * Release any queued transmit buffers. 2494 */ 2495void 2496atw_txdrain(struct atw_softc *sc) 2497{ 2498 struct atw_txsoft *txs; 2499 2500 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2501 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2502 if (txs->txs_mbuf != NULL) { 2503 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2504 m_freem(txs->txs_mbuf); 2505 txs->txs_mbuf = NULL; 2506 } 2507 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2508 } 2509 sc->sc_tx_timer = 0; 2510} 2511 2512/* 2513 * atw_stop: [ ifnet interface function ] 2514 * 2515 * Stop transmission on the interface. 2516 */ 2517void 2518atw_stop(struct ifnet *ifp, int disable) 2519{ 2520 struct atw_softc *sc = ifp->if_softc; 2521 struct ieee80211com *ic = &sc->sc_ic; 2522 2523 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2524 2525 /* Disable interrupts. */ 2526 ATW_WRITE(sc, ATW_IER, 0); 2527 2528 /* Stop the transmit and receive processes. */ 2529 sc->sc_opmode = 0; 2530 ATW_WRITE(sc, ATW_NAR, 0); 2531 DELAY(20 * 1000); 2532 ATW_WRITE(sc, ATW_TDBD, 0); 2533 ATW_WRITE(sc, ATW_TDBP, 0); 2534 ATW_WRITE(sc, ATW_RDB, 0); 2535 2536 atw_txdrain(sc); 2537 2538 if (disable) { 2539 atw_rxdrain(sc); 2540 atw_disable(sc); 2541 } 2542 2543 /* 2544 * Mark the interface down and cancel the watchdog timer. 2545 */ 2546 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2547 ifp->if_timer = 0; 2548 2549 if (!disable) 2550 atw_reset(sc); 2551} 2552 2553/* 2554 * atw_rxdrain: 2555 * 2556 * Drain the receive queue. 2557 */ 2558void 2559atw_rxdrain(struct atw_softc *sc) 2560{ 2561 struct atw_rxsoft *rxs; 2562 int i; 2563 2564 for (i = 0; i < ATW_NRXDESC; i++) { 2565 rxs = &sc->sc_rxsoft[i]; 2566 if (rxs->rxs_mbuf == NULL) 2567 continue; 2568 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2569 m_freem(rxs->rxs_mbuf); 2570 rxs->rxs_mbuf = NULL; 2571 } 2572} 2573 2574/* 2575 * atw_detach: 2576 * 2577 * Detach an ADM8211 interface. 2578 */ 2579int 2580atw_detach(struct atw_softc *sc) 2581{ 2582 struct ifnet *ifp = &sc->sc_ic.ic_if; 2583 struct atw_rxsoft *rxs; 2584 struct atw_txsoft *txs; 2585 int i; 2586 2587 /* 2588 * Succeed now if there isn't any work to do. 2589 */ 2590 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2591 return (0); 2592 2593 ieee80211_ifdetach(ifp); 2594 if_detach(ifp); 2595 2596 for (i = 0; i < ATW_NRXDESC; i++) { 2597 rxs = &sc->sc_rxsoft[i]; 2598 if (rxs->rxs_mbuf != NULL) { 2599 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2600 m_freem(rxs->rxs_mbuf); 2601 rxs->rxs_mbuf = NULL; 2602 } 2603 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2604 } 2605 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2606 txs = &sc->sc_txsoft[i]; 2607 if (txs->txs_mbuf != NULL) { 2608 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2609 m_freem(txs->txs_mbuf); 2610 txs->txs_mbuf = NULL; 2611 } 2612 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2613 } 2614 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2615 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2616 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2617 sizeof(struct atw_control_data)); 2618 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2619 2620 shutdownhook_disestablish(sc->sc_sdhook); 2621 powerhook_disestablish(sc->sc_powerhook); 2622 2623 if (sc->sc_srom) 2624 free(sc->sc_srom, M_DEVBUF); 2625 2626 return (0); 2627} 2628 2629/* atw_shutdown: make sure the interface is stopped at reboot time. */ 2630void 2631atw_shutdown(void *arg) 2632{ 2633 struct atw_softc *sc = arg; 2634 2635 atw_stop(&sc->sc_ic.ic_if, 1); 2636} 2637 2638int 2639atw_intr(void *arg) 2640{ 2641 struct atw_softc *sc = arg; 2642 struct ifnet *ifp = &sc->sc_ic.ic_if; 2643 u_int32_t status, rxstatus, txstatus, linkstatus; 2644 int handled = 0, txthresh; 2645 2646#ifdef DEBUG 2647 if (ATW_IS_ENABLED(sc) == 0) 2648 panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname); 2649#endif 2650 2651 /* 2652 * If the interface isn't running, the interrupt couldn't 2653 * possibly have come from us. 2654 */ 2655 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2656 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 2657 return (0); 2658 2659 for (;;) { 2660 status = ATW_READ(sc, ATW_STSR); 2661 2662 if (status) 2663 ATW_WRITE(sc, ATW_STSR, status); 2664 2665#ifdef ATW_DEBUG 2666#define PRINTINTR(flag) do { \ 2667 if ((status & flag) != 0) { \ 2668 printf("%s" #flag, delim); \ 2669 delim = ","; \ 2670 } \ 2671} while (0) 2672 2673 if (atw_debug > 1 && status) { 2674 const char *delim = "<"; 2675 2676 printf("%s: reg[STSR] = %x", 2677 sc->sc_dev.dv_xname, status); 2678 2679 PRINTINTR(ATW_INTR_FBE); 2680 PRINTINTR(ATW_INTR_LINKOFF); 2681 PRINTINTR(ATW_INTR_LINKON); 2682 PRINTINTR(ATW_INTR_RCI); 2683 PRINTINTR(ATW_INTR_RDU); 2684 PRINTINTR(ATW_INTR_REIS); 2685 PRINTINTR(ATW_INTR_RPS); 2686 PRINTINTR(ATW_INTR_TCI); 2687 PRINTINTR(ATW_INTR_TDU); 2688 PRINTINTR(ATW_INTR_TLT); 2689 PRINTINTR(ATW_INTR_TPS); 2690 PRINTINTR(ATW_INTR_TRT); 2691 PRINTINTR(ATW_INTR_TUF); 2692 PRINTINTR(ATW_INTR_BCNTC); 2693 PRINTINTR(ATW_INTR_ATIME); 2694 PRINTINTR(ATW_INTR_TBTT); 2695 PRINTINTR(ATW_INTR_TSCZ); 2696 PRINTINTR(ATW_INTR_TSFTF); 2697 printf(">\n"); 2698 } 2699#undef PRINTINTR 2700#endif /* ATW_DEBUG */ 2701 2702 if ((status & sc->sc_inten) == 0) 2703 break; 2704 2705 handled = 1; 2706 2707 rxstatus = status & sc->sc_rxint_mask; 2708 txstatus = status & sc->sc_txint_mask; 2709 linkstatus = status & sc->sc_linkint_mask; 2710 2711 if (linkstatus) { 2712 atw_linkintr(sc, linkstatus); 2713 } 2714 2715 if (rxstatus) { 2716 /* Grab any new packets. */ 2717 atw_rxintr(sc); 2718 2719 if (rxstatus & ATW_INTR_RDU) { 2720 printf("%s: receive ring overrun\n", 2721 sc->sc_dev.dv_xname); 2722 /* Get the receive process going again. */ 2723 ATW_WRITE(sc, ATW_RDR, 0x1); 2724 break; 2725 } 2726 } 2727 2728 if (txstatus) { 2729 /* Sweep up transmit descriptors. */ 2730 atw_txintr(sc); 2731 2732 if (txstatus & ATW_INTR_TLT) 2733 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2734 sc->sc_dev.dv_xname)); 2735 2736 if (txstatus & ATW_INTR_TRT) 2737 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2738 sc->sc_dev.dv_xname)); 2739 2740 /* If Tx under-run, increase our transmit threshold 2741 * if another is available. 2742 */ 2743 txthresh = sc->sc_txthresh + 1; 2744 if ((txstatus & ATW_INTR_TUF) && 2745 sc->sc_txth[txthresh].txth_name != NULL) { 2746 /* Idle the transmit process. */ 2747 atw_idle(sc, ATW_NAR_ST); 2748 2749 sc->sc_txthresh = txthresh; 2750 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2751 sc->sc_opmode |= 2752 sc->sc_txth[txthresh].txth_opmode; 2753 printf("%s: transmit underrun; new " 2754 "threshold: %s\n", sc->sc_dev.dv_xname, 2755 sc->sc_txth[txthresh].txth_name); 2756 2757 /* Set the new threshold and restart 2758 * the transmit process. 2759 */ 2760 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2761 DELAY(20 * 1000); 2762 ATW_WRITE(sc, ATW_RDR, 0x1); 2763 /* XXX Log every Nth underrun from 2764 * XXX now on? 2765 */ 2766 } 2767 } 2768 2769 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2770 if (status & ATW_INTR_TPS) 2771 printf("%s: transmit process stopped\n", 2772 sc->sc_dev.dv_xname); 2773 if (status & ATW_INTR_RPS) 2774 printf("%s: receive process stopped\n", 2775 sc->sc_dev.dv_xname); 2776 (void)atw_init(ifp); 2777 break; 2778 } 2779 2780 if (status & ATW_INTR_FBE) { 2781 printf("%s: fatal bus error\n", sc->sc_dev.dv_xname); 2782 (void)atw_init(ifp); 2783 break; 2784 } 2785 2786 /* 2787 * Not handled: 2788 * 2789 * Transmit buffer unavailable -- normal 2790 * condition, nothing to do, really. 2791 * 2792 * Early receive interrupt -- not available on 2793 * all chips, we just use RI. We also only 2794 * use single-segment receive DMA, so this 2795 * is mostly useless. 2796 * 2797 * TBD others 2798 */ 2799 } 2800 2801 /* Try to get more packets going. */ 2802 atw_start(ifp); 2803 2804 return (handled); 2805} 2806 2807/* 2808 * atw_idle: 2809 * 2810 * Cause the transmit and/or receive processes to go idle. 2811 * 2812 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2813 * process in STSR if I clear SR or ST after the process has already 2814 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2815 * do not seem to be too reliable. Perhaps I have the sense of the 2816 * Rx bits switched with the Tx bits? 2817 */ 2818void 2819atw_idle(struct atw_softc *sc, u_int32_t bits) 2820{ 2821 u_int32_t ackmask = 0, opmode, stsr, test0; 2822 int i, s; 2823 2824 s = splnet(); 2825 2826 opmode = sc->sc_opmode & ~bits; 2827 2828 if (bits & ATW_NAR_SR) 2829 ackmask |= ATW_INTR_RPS; 2830 2831 if (bits & ATW_NAR_ST) { 2832 ackmask |= ATW_INTR_TPS; 2833 /* set ATW_NAR_HF to flush TX FIFO. */ 2834 opmode |= ATW_NAR_HF; 2835 } 2836 2837 ATW_WRITE(sc, ATW_NAR, opmode); 2838 DELAY(20 * 1000); 2839 2840 for (i = 0; i < 10; i++) { 2841 stsr = ATW_READ(sc, ATW_STSR); 2842 if ((stsr & ackmask) == ackmask) 2843 break; 2844 DELAY(1000); 2845 } 2846 2847 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 2848 2849 if ((stsr & ackmask) == ackmask) 2850 goto out; 2851 2852 test0 = ATW_READ(sc, ATW_TEST0); 2853 2854 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 2855 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 2856 printf("%s: transmit process not idle [%s]\n", 2857 sc->sc_dev.dv_xname, 2858 atw_tx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_TS_MASK)]); 2859 printf("%s: bits %08x test0 %08x stsr %08x\n", 2860 sc->sc_dev.dv_xname, bits, test0, stsr); 2861 } 2862 2863 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 2864 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 2865 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 2866 sc->sc_dev.dv_xname, 2867 atw_rx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_RS_MASK)])); 2868 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 2869 sc->sc_dev.dv_xname, bits, test0, stsr)); 2870 } 2871out: 2872 if ((bits & ATW_NAR_ST) != 0) 2873 atw_txdrain(sc); 2874 splx(s); 2875 return; 2876} 2877 2878/* 2879 * atw_linkintr: 2880 * 2881 * Helper; handle link-status interrupts. 2882 */ 2883void 2884atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus) 2885{ 2886 struct ieee80211com *ic = &sc->sc_ic; 2887 2888 if (ic->ic_state != IEEE80211_S_RUN) 2889 return; 2890 2891 if (linkstatus & ATW_INTR_LINKON) { 2892 DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname)); 2893 sc->sc_rescan_timer = 0; 2894 } else if (linkstatus & ATW_INTR_LINKOFF) { 2895 DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname)); 2896 if (ic->ic_opmode != IEEE80211_M_STA) 2897 return; 2898 sc->sc_rescan_timer = 3; 2899 ic->ic_if.if_timer = 1; 2900 } 2901} 2902 2903/* 2904 * atw_rxintr: 2905 * 2906 * Helper; handle receive interrupts. 2907 */ 2908void 2909atw_rxintr(struct atw_softc *sc) 2910{ 2911 static int rate_tbl[] = {2, 4, 11, 22, 44}; 2912 struct ieee80211com *ic = &sc->sc_ic; 2913 struct ieee80211_node *ni; 2914 struct ieee80211_frame *wh; 2915 struct ifnet *ifp = &ic->ic_if; 2916 struct atw_rxsoft *rxs; 2917 struct mbuf *m; 2918 u_int32_t rxstat; 2919 int i, len, rate, rate0; 2920 u_int32_t rssi; 2921 2922 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 2923 rxs = &sc->sc_rxsoft[i]; 2924 2925 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2926 2927 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 2928 rssi = le32toh(sc->sc_rxdescs[i].ar_rssi); 2929 rate0 = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_RXDR_MASK); 2930 2931 if (rxstat & ATW_RXSTAT_OWN) 2932 break; /* We have processed all receive buffers. */ 2933 2934 DPRINTF3(sc, 2935 ("%s: rx stat %08x rssi %08x buf1 %08x buf2 %08x\n", 2936 sc->sc_dev.dv_xname, 2937 le32toh(sc->sc_rxdescs[i].ar_stat), 2938 le32toh(sc->sc_rxdescs[i].ar_rssi), 2939 le32toh(sc->sc_rxdescs[i].ar_buf1), 2940 le32toh(sc->sc_rxdescs[i].ar_buf2))); 2941 2942 /* 2943 * Make sure the packet fits in one buffer. This should 2944 * always be the case. 2945 */ 2946 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 2947 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 2948 printf("%s: incoming packet spilled, resetting\n", 2949 sc->sc_dev.dv_xname); 2950 (void)atw_init(ifp); 2951 return; 2952 } 2953 2954 /* 2955 * If an error occurred, update stats, clear the status 2956 * word, and leave the packet buffer in place. It will 2957 * simply be reused the next time the ring comes around. 2958 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 2959 * error. 2960 */ 2961 2962 if ((rxstat & ATW_RXSTAT_ES) != 0 && 2963 ((sc->sc_ic.ic_ec.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 2964 (rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_SFDE | 2965 ATW_RXSTAT_SIGE | ATW_RXSTAT_CRC16E | 2966 ATW_RXSTAT_RXTOE | ATW_RXSTAT_CRC32E | 2967 ATW_RXSTAT_ICVE)) != 0)) { 2968#define PRINTERR(bit, str) \ 2969 if (rxstat & (bit)) \ 2970 printf("%s: receive error: %s\n", \ 2971 sc->sc_dev.dv_xname, str) 2972 ifp->if_ierrors++; 2973 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 2974 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 2975 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 2976 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 2977 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 2978 PRINTERR(ATW_RXSTAT_CRC32E, "FCS error"); 2979 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 2980#undef PRINTERR 2981 ATW_INIT_RXDESC(sc, i); 2982 continue; 2983 } 2984 2985 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2986 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2987 2988 /* 2989 * No errors; receive the packet. Note the ADM8211 2990 * includes the CRC in promiscuous mode. 2991 */ 2992 len = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_FL_MASK); 2993 2994 /* 2995 * Allocate a new mbuf cluster. If that fails, we are 2996 * out of memory, and must drop the packet and recycle 2997 * the buffer that's already attached to this descriptor. 2998 */ 2999 m = rxs->rxs_mbuf; 3000 if (atw_add_rxbuf(sc, i) != 0) { 3001 ifp->if_ierrors++; 3002 ATW_INIT_RXDESC(sc, i); 3003 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3004 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3005 continue; 3006 } 3007 3008 ifp->if_ipackets++; 3009 if (sc->sc_opmode & ATW_NAR_PR) 3010 m->m_flags |= M_HASFCS; 3011 m->m_pkthdr.rcvif = ifp; 3012 m->m_pkthdr.len = m->m_len = MIN(m->m_ext.ext_size, len); 3013 3014 if (rate0 >= sizeof(rate_tbl) / sizeof(rate_tbl[0])) 3015 rate = 0; 3016 else 3017 rate = rate_tbl[rate0]; 3018 3019 #if NBPFILTER > 0 3020 /* Pass this up to any BPF listeners. */ 3021 if (sc->sc_radiobpf != NULL) { 3022 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3023 3024 tap->ar_rate = rate; 3025 tap->ar_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3026 tap->ar_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3027 3028 /* TBD verify units are dB */ 3029 tap->ar_antsignal = (int)rssi; 3030 /* TBD tap->ar_flags */ 3031 3032 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3033 tap->ar_ihdr.it_len, m); 3034 } 3035 #endif /* NPBFILTER > 0 */ 3036 3037 wh = mtod(m, struct ieee80211_frame *); 3038 ni = ieee80211_find_rxnode(ic, wh); 3039 ieee80211_input(ifp, m, ni, (int)rssi, 0); 3040 /* 3041 * The frame may have caused the node to be marked for 3042 * reclamation (e.g. in response to a DEAUTH message) 3043 * so use free_node here instead of unref_node. 3044 */ 3045 if (ni == ic->ic_bss) 3046 ieee80211_unref_node(&ni); 3047 else 3048 ieee80211_free_node(ic, ni); 3049 } 3050 3051 /* Update the receive pointer. */ 3052 sc->sc_rxptr = i; 3053} 3054 3055/* 3056 * atw_txintr: 3057 * 3058 * Helper; handle transmit interrupts. 3059 */ 3060void 3061atw_txintr(struct atw_softc *sc) 3062{ 3063#define TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | ATW_TXSTAT_TRT | \ 3064 ATW_TXSTAT_TRO | ATW_TXSTAT_SOFBR) 3065#define TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO\33ATW_TXSTAT_TUF" \ 3066 "\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT" 3067 3068 static char txstat_buf[sizeof("ffffffff<>" TXSTAT_FMT)]; 3069 struct ifnet *ifp = &sc->sc_ic.ic_if; 3070 struct atw_txsoft *txs; 3071 u_int32_t txstat; 3072 3073 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3074 sc->sc_dev.dv_xname, sc->sc_flags)); 3075 3076 ifp->if_flags &= ~IFF_OACTIVE; 3077 3078 /* 3079 * Go through our Tx list and free mbufs for those 3080 * frames that have been transmitted. 3081 */ 3082 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3083 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, 3084 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3085 3086#ifdef ATW_DEBUG 3087 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3088 int i; 3089 printf(" txsoft %p transmit chain:\n", txs); 3090 ATW_CDTXSYNC(sc, txs->txs_firstdesc, 3091 txs->txs_ndescs - 1, 3092 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3093 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3094 printf(" descriptor %d:\n", i); 3095 printf(" at_status: 0x%08x\n", 3096 le32toh(sc->sc_txdescs[i].at_stat)); 3097 printf(" at_flags: 0x%08x\n", 3098 le32toh(sc->sc_txdescs[i].at_flags)); 3099 printf(" at_buf1: 0x%08x\n", 3100 le32toh(sc->sc_txdescs[i].at_buf1)); 3101 printf(" at_buf2: 0x%08x\n", 3102 le32toh(sc->sc_txdescs[i].at_buf2)); 3103 if (i == txs->txs_lastdesc) 3104 break; 3105 } 3106 } 3107#endif 3108 3109 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3110 if (txstat & ATW_TXSTAT_OWN) 3111 break; 3112 3113 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3114 3115 sc->sc_txfree += txs->txs_ndescs; 3116 3117 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3118 0, txs->txs_dmamap->dm_mapsize, 3119 BUS_DMASYNC_POSTWRITE); 3120 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3121 m_freem(txs->txs_mbuf); 3122 txs->txs_mbuf = NULL; 3123 3124 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3125 3126 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3127 (txstat & TXSTAT_ERRMASK) != 0) { 3128 bitmask_snprintf(txstat & TXSTAT_ERRMASK, TXSTAT_FMT, 3129 txstat_buf, sizeof(txstat_buf)); 3130 printf("%s: txstat %s %d\n", sc->sc_dev.dv_xname, 3131 txstat_buf, 3132 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK)); 3133 } 3134 3135 /* 3136 * Check for errors and collisions. 3137 */ 3138 if (txstat & ATW_TXSTAT_TUF) 3139 sc->sc_stats.ts_tx_tuf++; 3140 if (txstat & ATW_TXSTAT_TLT) 3141 sc->sc_stats.ts_tx_tlt++; 3142 if (txstat & ATW_TXSTAT_TRT) 3143 sc->sc_stats.ts_tx_trt++; 3144 if (txstat & ATW_TXSTAT_TRO) 3145 sc->sc_stats.ts_tx_tro++; 3146 if (txstat & ATW_TXSTAT_SOFBR) { 3147 sc->sc_stats.ts_tx_sofbr++; 3148 } 3149 3150 if ((txstat & ATW_TXSTAT_ES) == 0) 3151 ifp->if_collisions += 3152 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK); 3153 else 3154 ifp->if_oerrors++; 3155 3156 ifp->if_opackets++; 3157 } 3158 3159 /* 3160 * If there are no more pending transmissions, cancel the watchdog 3161 * timer. 3162 */ 3163 if (txs == NULL) 3164 sc->sc_tx_timer = 0; 3165#undef TXSTAT_ERRMASK 3166#undef TXSTAT_FMT 3167} 3168 3169/* 3170 * atw_watchdog: [ifnet interface function] 3171 * 3172 * Watchdog timer handler. 3173 */ 3174void 3175atw_watchdog(struct ifnet *ifp) 3176{ 3177 struct atw_softc *sc = ifp->if_softc; 3178 struct ieee80211com *ic = &sc->sc_ic; 3179 3180 ifp->if_timer = 0; 3181 if (ATW_IS_ENABLED(sc) == 0) 3182 return; 3183 3184 if (sc->sc_rescan_timer) { 3185 if (--sc->sc_rescan_timer == 0) 3186 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3187 } 3188 if (sc->sc_tx_timer) { 3189 if (--sc->sc_tx_timer == 0 && 3190 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3191 printf("%s: transmit timeout\n", ifp->if_xname); 3192 ifp->if_oerrors++; 3193 (void)atw_init(ifp); 3194 atw_start(ifp); 3195 } 3196 } 3197 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3198 ifp->if_timer = 1; 3199 ieee80211_watchdog(ifp); 3200} 3201 3202/* Compute the 802.11 Duration field and the PLCP Length fields for 3203 * a len-byte frame (HEADER + PAYLOAD + FCS) sent at rate * 500Kbps. 3204 * Write the fields to the ADM8211 Tx header, frm. 3205 * 3206 * TBD use the fragmentation threshold to find the right duration for 3207 * the first & last fragments. 3208 * 3209 * TBD make certain of the duration fields applied by the ADM8211 to each 3210 * fragment. I think that the ADM8211 knows how to subtract the CTS 3211 * duration when ATW_HDRCTL_RTSCTS is clear; that is why I add it regardless. 3212 * I also think that the ADM8211 does *some* arithmetic for us, because 3213 * otherwise I think we would have to set a first duration for CTS/first 3214 * fragment, a second duration for fragments between the first and the 3215 * last, and a third duration for the last fragment. 3216 * 3217 * TBD make certain that duration fields reflect addition of FCS/WEP 3218 * and correct duration arithmetic as necessary. 3219 */ 3220static void 3221atw_frame_setdurs(struct atw_softc *sc, struct atw_frame *frm, int rate, 3222 int len) 3223{ 3224 int remainder; 3225 3226 /* deal also with encrypted fragments */ 3227 if (frm->atw_hdrctl & htole16(ATW_HDRCTL_WEP)) { 3228 DPRINTF2(sc, ("%s: atw_frame_setdurs len += 8\n", 3229 sc->sc_dev.dv_xname)); 3230 len += IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + 3231 IEEE80211_WEP_CRCLEN; 3232 } 3233 3234 /* 802.11 Duration Field for CTS/Data/ACK sequence minus FCS & WEP 3235 * duration (XXX added by MAC?). 3236 */ 3237 frm->atw_head_dur = (16 * (len - IEEE80211_CRC_LEN)) / rate; 3238 remainder = (16 * (len - IEEE80211_CRC_LEN)) % rate; 3239 3240 if (rate <= 4) 3241 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */ 3242 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3243 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3244 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3245 IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK; 3246 else 3247 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */ 3248 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3249 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3250 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3251 IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK; 3252 3253 /* lengthen duration if long preamble */ 3254 if ((sc->sc_flags & ATWF_SHORT_PREAMBLE) == 0) 3255 frm->atw_head_dur += 3256 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE - 3257 IEEE80211_DUR_DS_SHORT_PREAMBLE) + 3258 3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR - 3259 IEEE80211_DUR_DS_FAST_PLCPHDR); 3260 3261 if (remainder != 0) 3262 frm->atw_head_dur++; 3263 3264 if ((atw_voodoo & VOODOO_DUR_2_4_SPECIALCASE) && 3265 (rate == 2 || rate == 4)) { 3266 /* derived from Linux: how could this be right? */ 3267 frm->atw_head_plcplen = frm->atw_head_dur; 3268 } else { 3269 frm->atw_head_plcplen = (16 * len) / rate; 3270 remainder = (80 * len) % (rate * 5); 3271 3272 if (remainder != 0) { 3273 frm->atw_head_plcplen++; 3274 3275 /* XXX magic */ 3276 if ((atw_voodoo & VOODOO_DUR_11_ROUNDING) && 3277 rate == 22 && remainder <= 30) 3278 frm->atw_head_plcplen |= 0x8000; 3279 } 3280 } 3281 frm->atw_tail_plcplen = frm->atw_head_plcplen = 3282 htole16(frm->atw_head_plcplen); 3283 frm->atw_tail_dur = frm->atw_head_dur = htole16(frm->atw_head_dur); 3284} 3285 3286#ifdef ATW_DEBUG 3287static void 3288atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3289{ 3290 struct atw_softc *sc = ifp->if_softc; 3291 struct mbuf *m; 3292 int i, noctets = 0; 3293 3294 printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname, 3295 m0->m_pkthdr.len); 3296 3297 for (m = m0; m; m = m->m_next) { 3298 if (m->m_len == 0) 3299 continue; 3300 for (i = 0; i < m->m_len; i++) { 3301 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3302 if (++noctets % 24 == 0) 3303 printf("\n"); 3304 } 3305 } 3306 printf("%s%s: %d bytes emitted\n", 3307 (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets); 3308} 3309#endif /* ATW_DEBUG */ 3310 3311/* 3312 * atw_start: [ifnet interface function] 3313 * 3314 * Start packet transmission on the interface. 3315 */ 3316void 3317atw_start(struct ifnet *ifp) 3318{ 3319 struct atw_softc *sc = ifp->if_softc; 3320 struct ieee80211com *ic = &sc->sc_ic; 3321 struct ieee80211_node *ni; 3322 struct ieee80211_frame *wh; 3323 struct atw_frame *hh; 3324 struct mbuf *m0, *m; 3325 struct atw_txsoft *txs, *last_txs; 3326 struct atw_txdesc *txd; 3327 int do_encrypt, rate; 3328 bus_dmamap_t dmamap; 3329 int ctl, error, firsttx, nexttx, lasttx = -1, first, ofree, seg; 3330 3331 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3332 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 3333 3334 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3335 return; 3336 3337 /* 3338 * Remember the previous number of free descriptors and 3339 * the first descriptor we'll use. 3340 */ 3341 ofree = sc->sc_txfree; 3342 firsttx = sc->sc_txnext; 3343 3344 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3345 sc->sc_dev.dv_xname, ofree, firsttx)); 3346 3347 /* 3348 * Loop through the send queue, setting up transmit descriptors 3349 * until we drain the queue, or use up all available transmit 3350 * descriptors. 3351 */ 3352 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3353 sc->sc_txfree != 0) { 3354 3355 /* 3356 * Grab a packet off the management queue, if it 3357 * is not empty. Otherwise, from the data queue. 3358 */ 3359 IF_DEQUEUE(&ic->ic_mgtq, m0); 3360 if (m0 != NULL) { 3361 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 3362 m0->m_pkthdr.rcvif = NULL; 3363 } else { 3364 /* send no data packets until we are associated */ 3365 if (ic->ic_state != IEEE80211_S_RUN) 3366 break; 3367 IFQ_DEQUEUE(&ifp->if_snd, m0); 3368 if (m0 == NULL) 3369 break; 3370#if NBPFILTER > 0 3371 if (ifp->if_bpf != NULL) 3372 bpf_mtap(ifp->if_bpf, m0); 3373#endif /* NBPFILTER > 0 */ 3374 if ((m0 = ieee80211_encap(ifp, m0, &ni)) == NULL) { 3375 ifp->if_oerrors++; 3376 break; 3377 } 3378 } 3379 3380 rate = MAX(ieee80211_get_rate(ic), 2); 3381 3382#if NBPFILTER > 0 3383 /* 3384 * Pass the packet to any BPF listeners. 3385 */ 3386 if (ic->ic_rawbpf != NULL) 3387 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3388 3389 if (sc->sc_radiobpf != NULL) { 3390 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3391 3392 tap->at_rate = rate; 3393 tap->at_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3394 tap->at_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3395 3396 /* TBD tap->at_flags */ 3397 3398 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3399 tap->at_ihdr.it_len, m0); 3400 } 3401#endif /* NBPFILTER > 0 */ 3402 3403 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3404 3405 if (ni != NULL && ni != ic->ic_bss) 3406 ieee80211_free_node(ic, ni); 3407 3408 if (m0 == NULL) { 3409 ifp->if_oerrors++; 3410 break; 3411 } 3412 3413 /* just to make sure. */ 3414 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3415 3416 if (m0 == NULL) { 3417 ifp->if_oerrors++; 3418 break; 3419 } 3420 3421 hh = mtod(m0, struct atw_frame *); 3422 wh = &hh->atw_ihdr; 3423 3424 do_encrypt = ((wh->i_fc[1] & IEEE80211_FC1_WEP) != 0) ? 1 : 0; 3425 3426 /* Copy everything we need from the 802.11 header: 3427 * Frame Control; address 1, address 3, or addresses 3428 * 3 and 4. NIC fills in BSSID, SA. 3429 */ 3430 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3431 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3432 panic("%s: illegal WDS frame", 3433 sc->sc_dev.dv_xname); 3434 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3435 } else 3436 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3437 3438 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3439 3440 /* initialize remaining Tx parameters */ 3441 memset(&hh->u, 0, sizeof(hh->u)); 3442 3443 hh->atw_rate = rate * 5; 3444 /* XXX this could be incorrect if M_FCS. _encap should 3445 * probably strip FCS just in case it sticks around in 3446 * bridged packets. 3447 */ 3448 hh->atw_service = IEEE80211_PLCP_SERVICE; /* XXX guess */ 3449 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3450 sizeof(struct atw_frame)); 3451 3452 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3453 hh->atw_rtylmt = 3; 3454 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3455 if (do_encrypt) { 3456 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3457 hh->atw_keyid = ic->ic_wep_txkey; 3458 } 3459 3460 /* TBD 4-addr frames */ 3461 atw_frame_setdurs(sc, hh, rate, 3462 m0->m_pkthdr.len - sizeof(struct atw_frame) + 3463 sizeof(struct ieee80211_frame) + IEEE80211_CRC_LEN); 3464 3465 /* never fragment multicast frames */ 3466 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3467 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3468 } else if (sc->sc_flags & ATWF_RTSCTS) { 3469 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3470 } 3471 3472#ifdef ATW_DEBUG 3473 hh->atw_fragnum = 0; 3474 3475 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3476 printf("%s: dst = %s, rate = 0x%02x, " 3477 "service = 0x%02x, paylen = 0x%04x\n", 3478 sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst), 3479 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3480 3481 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3482 "dur1 = 0x%04x, dur2 = 0x%04x, " 3483 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3484 sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1], 3485 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3486 hh->atw_tail_dur, hh->atw_head_dur); 3487 3488 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3489 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3490 sc->sc_dev.dv_xname, hh->atw_hdrctl, 3491 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3492 3493 printf("%s: keyid = %d\n", 3494 sc->sc_dev.dv_xname, hh->atw_keyid); 3495 3496 atw_dump_pkt(ifp, m0); 3497 } 3498#endif /* ATW_DEBUG */ 3499 3500 dmamap = txs->txs_dmamap; 3501 3502 /* 3503 * Load the DMA map. Copy and try (once) again if the packet 3504 * didn't fit in the alloted number of segments. 3505 */ 3506 for (first = 1; 3507 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3508 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3509 first = 0) { 3510 MGETHDR(m, M_DONTWAIT, MT_DATA); 3511 if (m == NULL) { 3512 printf("%s: unable to allocate Tx mbuf\n", 3513 sc->sc_dev.dv_xname); 3514 break; 3515 } 3516 if (m0->m_pkthdr.len > MHLEN) { 3517 MCLGET(m, M_DONTWAIT); 3518 if ((m->m_flags & M_EXT) == 0) { 3519 printf("%s: unable to allocate Tx " 3520 "cluster\n", sc->sc_dev.dv_xname); 3521 m_freem(m); 3522 break; 3523 } 3524 } 3525 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3526 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3527 m_freem(m0); 3528 m0 = m; 3529 m = NULL; 3530 } 3531 if (error != 0) { 3532 printf("%s: unable to load Tx buffer, " 3533 "error = %d\n", sc->sc_dev.dv_xname, error); 3534 m_freem(m0); 3535 break; 3536 } 3537 3538 /* 3539 * Ensure we have enough descriptors free to describe 3540 * the packet. 3541 */ 3542 if (dmamap->dm_nsegs > sc->sc_txfree) { 3543 /* 3544 * Not enough free descriptors to transmit 3545 * this packet. Unload the DMA map and 3546 * drop the packet. Notify the upper layer 3547 * that there are no more slots left. 3548 * 3549 * XXX We could allocate an mbuf and copy, but 3550 * XXX it is worth it? 3551 */ 3552 ifp->if_flags |= IFF_OACTIVE; 3553 bus_dmamap_unload(sc->sc_dmat, dmamap); 3554 m_freem(m0); 3555 break; 3556 } 3557 3558 /* 3559 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3560 */ 3561 3562 /* Sync the DMA map. */ 3563 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3564 BUS_DMASYNC_PREWRITE); 3565 3566 /* XXX arbitrary retry limit; 8 because I have seen it in 3567 * use already and maybe 0 means "no tries" ! 3568 */ 3569 ctl = htole32(LSHIFT(8, ATW_TXCTL_TL_MASK)); 3570 3571 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3572 sc->sc_dev.dv_xname, rate * 5)); 3573 ctl |= htole32(LSHIFT(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3574 3575 /* 3576 * Initialize the transmit descriptors. 3577 */ 3578 for (nexttx = sc->sc_txnext, seg = 0; 3579 seg < dmamap->dm_nsegs; 3580 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3581 /* 3582 * If this is the first descriptor we're 3583 * enqueueing, don't set the OWN bit just 3584 * yet. That could cause a race condition. 3585 * We'll do it below. 3586 */ 3587 txd = &sc->sc_txdescs[nexttx]; 3588 txd->at_ctl = ctl | 3589 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3590 3591 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3592 txd->at_flags = 3593 htole32(LSHIFT(dmamap->dm_segs[seg].ds_len, 3594 ATW_TXFLAG_TBS1_MASK)) | 3595 ((nexttx == (ATW_NTXDESC - 1)) 3596 ? htole32(ATW_TXFLAG_TER) : 0); 3597 lasttx = nexttx; 3598 } 3599 3600 IASSERT(lasttx != -1, ("bad lastx")); 3601 /* Set `first segment' and `last segment' appropriately. */ 3602 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3603 htole32(ATW_TXFLAG_FS); 3604 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3605 3606#ifdef ATW_DEBUG 3607 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3608 printf(" txsoft %p transmit chain:\n", txs); 3609 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3610 printf(" descriptor %d:\n", seg); 3611 printf(" at_ctl: 0x%08x\n", 3612 le32toh(sc->sc_txdescs[seg].at_ctl)); 3613 printf(" at_flags: 0x%08x\n", 3614 le32toh(sc->sc_txdescs[seg].at_flags)); 3615 printf(" at_buf1: 0x%08x\n", 3616 le32toh(sc->sc_txdescs[seg].at_buf1)); 3617 printf(" at_buf2: 0x%08x\n", 3618 le32toh(sc->sc_txdescs[seg].at_buf2)); 3619 if (seg == lasttx) 3620 break; 3621 } 3622 } 3623#endif 3624 3625 /* Sync the descriptors we're using. */ 3626 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3627 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3628 3629 /* 3630 * Store a pointer to the packet so we can free it later, 3631 * and remember what txdirty will be once the packet is 3632 * done. 3633 */ 3634 txs->txs_mbuf = m0; 3635 txs->txs_firstdesc = sc->sc_txnext; 3636 txs->txs_lastdesc = lasttx; 3637 txs->txs_ndescs = dmamap->dm_nsegs; 3638 3639 /* Advance the tx pointer. */ 3640 sc->sc_txfree -= dmamap->dm_nsegs; 3641 sc->sc_txnext = nexttx; 3642 3643 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3644 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3645 3646 last_txs = txs; 3647 } 3648 3649 if (txs == NULL || sc->sc_txfree == 0) { 3650 /* No more slots left; notify upper layer. */ 3651 ifp->if_flags |= IFF_OACTIVE; 3652 } 3653 3654 if (sc->sc_txfree != ofree) { 3655 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3656 sc->sc_dev.dv_xname, lasttx, firsttx)); 3657 /* 3658 * Cause a transmit interrupt to happen on the 3659 * last packet we enqueued. 3660 */ 3661 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3662 ATW_CDTXSYNC(sc, lasttx, 1, 3663 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3664 3665 /* 3666 * The entire packet chain is set up. Give the 3667 * first descriptor to the chip now. 3668 */ 3669 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3670 ATW_CDTXSYNC(sc, firsttx, 1, 3671 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3672 3673 /* Wake up the transmitter. */ 3674 ATW_WRITE(sc, ATW_TDR, 0x1); 3675 3676 /* Set a watchdog timer in case the chip flakes out. */ 3677 sc->sc_tx_timer = 5; 3678 ifp->if_timer = 1; 3679 } 3680} 3681 3682/* 3683 * atw_power: 3684 * 3685 * Power management (suspend/resume) hook. 3686 */ 3687void 3688atw_power(int why, void *arg) 3689{ 3690 struct atw_softc *sc = arg; 3691 struct ifnet *ifp = &sc->sc_ic.ic_if; 3692 int s; 3693 3694 DPRINTF(sc, ("%s: atw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3695 3696 s = splnet(); 3697 switch (why) { 3698 case PWR_STANDBY: 3699 /* XXX do nothing. */ 3700 break; 3701 case PWR_SUSPEND: 3702 atw_stop(ifp, 0); 3703 if (sc->sc_power != NULL) 3704 (*sc->sc_power)(sc, why); 3705 break; 3706 case PWR_RESUME: 3707 if (ifp->if_flags & IFF_UP) { 3708 if (sc->sc_power != NULL) 3709 (*sc->sc_power)(sc, why); 3710 atw_init(ifp); 3711 } 3712 break; 3713 case PWR_SOFTSUSPEND: 3714 case PWR_SOFTSTANDBY: 3715 case PWR_SOFTRESUME: 3716 break; 3717 } 3718 splx(s); 3719} 3720 3721/* 3722 * atw_ioctl: [ifnet interface function] 3723 * 3724 * Handle control requests from the operator. 3725 */ 3726int 3727atw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3728{ 3729 struct atw_softc *sc = ifp->if_softc; 3730 struct ifreq *ifr = (struct ifreq *)data; 3731 int s, error = 0; 3732 3733 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 3734 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 3735 return ENXIO; 3736 3737 s = splnet(); 3738 3739 switch (cmd) { 3740 case SIOCSIFFLAGS: 3741 if (ifp->if_flags & IFF_UP) { 3742 if (ATW_IS_ENABLED(sc)) { 3743 /* 3744 * To avoid rescanning another access point, 3745 * do not call atw_init() here. Instead, 3746 * only reflect media settings. 3747 */ 3748 atw_filter_setup(sc); 3749 } else 3750 error = atw_init(ifp); 3751 } else if (ATW_IS_ENABLED(sc)) 3752 atw_stop(ifp, 1); 3753 break; 3754 case SIOCADDMULTI: 3755 case SIOCDELMULTI: 3756 error = (cmd == SIOCADDMULTI) ? 3757 ether_addmulti(ifr, &sc->sc_ic.ic_ec) : 3758 ether_delmulti(ifr, &sc->sc_ic.ic_ec); 3759 if (error == ENETRESET) { 3760 if (ATW_IS_ENABLED(sc)) 3761 atw_filter_setup(sc); /* do not rescan */ 3762 error = 0; 3763 } 3764 break; 3765 default: 3766 error = ieee80211_ioctl(ifp, cmd, data); 3767 if (error == ENETRESET) { 3768 if (ATW_IS_ENABLED(sc)) 3769 error = atw_init(ifp); 3770 else 3771 error = 0; 3772 } 3773 break; 3774 } 3775 3776 /* Try to get more packets going. */ 3777 if (ATW_IS_ENABLED(sc)) 3778 atw_start(ifp); 3779 3780 splx(s); 3781 return (error); 3782} 3783 3784static int 3785atw_media_change(struct ifnet *ifp) 3786{ 3787 int error; 3788 3789 error = ieee80211_media_change(ifp); 3790 if (error == ENETRESET) { 3791 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3792 (IFF_RUNNING|IFF_UP)) 3793 atw_init(ifp); /* XXX lose error */ 3794 error = 0; 3795 } 3796 return error; 3797} 3798 3799static void 3800atw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3801{ 3802 struct atw_softc *sc = ifp->if_softc; 3803 3804 if (ATW_IS_ENABLED(sc) == 0) { 3805 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3806 imr->ifm_status = 0; 3807 return; 3808 } 3809 ieee80211_media_status(ifp, imr); 3810} 3811