atw.c revision 1.19
1/* $NetBSD: atw.c,v 1.19 2004/01/13 23:37:29 dyoung Exp $ */ 2 3/*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39/* 40 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 41 */ 42 43#include <sys/cdefs.h> 44__KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.19 2004/01/13 23:37:29 dyoung Exp $"); 45 46#include "bpfilter.h" 47 48#include <sys/param.h> 49#include <sys/systm.h> 50#include <sys/callout.h> 51#include <sys/mbuf.h> 52#include <sys/malloc.h> 53#include <sys/kernel.h> 54#include <sys/socket.h> 55#include <sys/ioctl.h> 56#include <sys/errno.h> 57#include <sys/device.h> 58#include <sys/time.h> 59 60#include <machine/endian.h> 61 62#include <uvm/uvm_extern.h> 63 64#include <net/if.h> 65#include <net/if_dl.h> 66#include <net/if_media.h> 67#include <net/if_ether.h> 68 69#include <net80211/ieee80211_var.h> 70#include <net80211/ieee80211_compat.h> 71#include <net80211/ieee80211_radiotap.h> 72 73#if NBPFILTER > 0 74#include <net/bpf.h> 75#endif 76 77#include <machine/bus.h> 78#include <machine/intr.h> 79 80#include <dev/ic/atwreg.h> 81#include <dev/ic/atwvar.h> 82#include <dev/ic/smc93cx6var.h> 83 84/* XXX TBD open questions 85 * 86 * 87 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 88 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 89 * handle this for me? 90 * 91 */ 92/* device attachment 93 * 94 * print TOFS[012] 95 * 96 * device initialization 97 * 98 * clear ATW_FRCTL_MAXPSP to disable max power saving 99 * set ATW_TXBR_ALCUPDATE to enable ALC 100 * set TOFS[012]? (hope not) 101 * disable rx/tx 102 * set ATW_PAR_SWR (software reset) 103 * wait for ATW_PAR_SWR clear 104 * disable interrupts 105 * ack status register 106 * enable interrupts 107 * 108 * rx/tx initialization 109 * 110 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 111 * allocate and init descriptor rings 112 * write ATW_PAR_DSL (descriptor skip length) 113 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 114 * write ATW_NAR_SQ for one/both transmit descriptor rings 115 * write ATW_NAR_SQ for one/both transmit descriptor rings 116 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 117 * 118 * rx/tx end 119 * 120 * stop DMA 121 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 122 * flush tx w/ ATW_NAR_HF 123 * 124 * scan 125 * 126 * initialize rx/tx 127 * 128 * IBSS join/create 129 * 130 * set ATW_NAR_EA (is set by ASIC?) 131 * 132 * BSS join: (re)association response 133 * 134 * set ATW_FRCTL_AID 135 * 136 * optimizations ??? 137 * 138 */ 139 140#define VOODOO_DUR_11_ROUNDING 0x01 /* necessary */ 141#define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */ 142int atw_voodoo = VOODOO_DUR_11_ROUNDING; 143 144int atw_rfio_enable_delay = 20 * 1000; 145int atw_rfio_disable_delay = 2 * 1000; 146int atw_writewep_delay = 5; 147int atw_beacon_len_adjust = 4; 148int atw_dwelltime = 200; 149 150#ifdef ATW_DEBUG 151int atw_xhdrctl = 0; 152int atw_xrtylmt = ~0; 153int atw_xservice = IEEE80211_PLCP_SERVICE; 154int atw_xpaylen = 0; 155 156int atw_debug = 0; 157 158#define ATW_DPRINTF(x) if (atw_debug > 0) printf x 159#define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 160#define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 161#define DPRINTF(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) printf x 162#define DPRINTF2(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 163#define DPRINTF3(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 164static void atw_print_regs(struct atw_softc *, const char *); 165static void atw_rf3000_print(struct atw_softc *); 166static void atw_si4126_print(struct atw_softc *); 167static void atw_dump_pkt(struct ifnet *, struct mbuf *); 168#else 169#define ATW_DPRINTF(x) 170#define ATW_DPRINTF2(x) 171#define ATW_DPRINTF3(x) 172#define DPRINTF(sc, x) /* nothing */ 173#define DPRINTF2(sc, x) /* nothing */ 174#define DPRINTF3(sc, x) /* nothing */ 175#endif 176 177#ifdef ATW_STATS 178void atw_print_stats __P((struct atw_softc *)); 179#endif 180 181void atw_start __P((struct ifnet *)); 182void atw_watchdog __P((struct ifnet *)); 183int atw_ioctl __P((struct ifnet *, u_long, caddr_t)); 184int atw_init __P((struct ifnet *)); 185void atw_stop __P((struct ifnet *, int)); 186 187void atw_reset __P((struct atw_softc *)); 188int atw_read_srom __P((struct atw_softc *)); 189 190void atw_shutdown __P((void *)); 191 192void atw_rxdrain __P((struct atw_softc *)); 193int atw_add_rxbuf __P((struct atw_softc *, int)); 194void atw_idle __P((struct atw_softc *, u_int32_t)); 195 196int atw_enable __P((struct atw_softc *)); 197void atw_disable __P((struct atw_softc *)); 198void atw_power __P((int, void *)); 199 200void atw_rxintr __P((struct atw_softc *)); 201void atw_txintr __P((struct atw_softc *)); 202void atw_linkintr __P((struct atw_softc *, u_int32_t)); 203 204static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 205static void atw_tsf(struct atw_softc *); 206static void atw_start_beacon(struct atw_softc *, int); 207static void atw_write_wep(struct atw_softc *); 208static void atw_write_bssid(struct atw_softc *); 209static void atw_write_bcn_thresh(struct atw_softc *); 210static void atw_write_ssid(struct atw_softc *); 211static void atw_write_sup_rates(struct atw_softc *); 212static void atw_clear_sram(struct atw_softc *); 213static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 214static int atw_media_change(struct ifnet *); 215static void atw_media_status(struct ifnet *, struct ifmediareq *); 216static void atw_filter_setup(struct atw_softc *); 217static void atw_frame_setdurs(struct atw_softc *, struct atw_frame *, int, int); 218static __inline u_int64_t atw_predict_beacon(u_int64_t, u_int32_t); 219static void atw_recv_beacon(struct ieee80211com *, struct mbuf *, 220 struct ieee80211_node *, int, int, u_int32_t); 221static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 222 struct ieee80211_node *, int, int, u_int32_t); 223static void atw_node_free(struct ieee80211com *, struct ieee80211_node *); 224static struct ieee80211_node *atw_node_alloc(struct ieee80211com *); 225 226static int atw_tune(struct atw_softc *); 227 228static void atw_rfio_enable(struct atw_softc *, int); 229 230/* RFMD RF3000 Baseband Processor */ 231static int atw_rf3000_init(struct atw_softc *); 232static int atw_rf3000_tune(struct atw_softc *, u_int8_t); 233static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 234#ifdef ATW_DEBUG 235static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 236#endif /* ATW_DEBUG */ 237 238/* Silicon Laboratories Si4126 RF/IF Synthesizer */ 239static int atw_si4126_tune(struct atw_softc *, u_int8_t); 240static int atw_si4126_write(struct atw_softc *, u_int, u_int); 241#ifdef ATW_DEBUG 242static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 243#endif /* ATW_DEBUG */ 244 245const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 246const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 247 248const char *atw_tx_state[] = { 249 "STOPPED", 250 "RUNNING - FETCH", 251 "RUNNING - WAIT", 252 "RUNNING - READING", 253 "-- RESERVED1 --", 254 "-- RESERVED2 --", 255 "SUSPENDED", 256 "RUNNING - CLOSE" 257}; 258 259const char *atw_rx_state[] = { 260 "STOPPED", 261 "RUNNING - FETCH", 262 "RUNNING - CHECK", 263 "RUNNING - WAIT", 264 "SUSPENDED", 265 "RUNNING - CLOSE", 266 "RUNNING - FLUSH", 267 "RUNNING - QUEUE" 268}; 269 270int 271atw_activate(struct device *self, enum devact act) 272{ 273 struct atw_softc *sc = (struct atw_softc *)self; 274 int rv = 0, s; 275 276 s = splnet(); 277 switch (act) { 278 case DVACT_ACTIVATE: 279 rv = EOPNOTSUPP; 280 break; 281 282 case DVACT_DEACTIVATE: 283 if_deactivate(&sc->sc_ic.ic_if); 284 break; 285 } 286 splx(s); 287 return rv; 288} 289 290/* 291 * atw_enable: 292 * 293 * Enable the ADM8211 chip. 294 */ 295int 296atw_enable(sc) 297 struct atw_softc *sc; 298{ 299 300 if (ATW_IS_ENABLED(sc) == 0) { 301 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 302 printf("%s: device enable failed\n", 303 sc->sc_dev.dv_xname); 304 return (EIO); 305 } 306 sc->sc_flags |= ATWF_ENABLED; 307 } 308 return (0); 309} 310 311/* 312 * atw_disable: 313 * 314 * Disable the ADM8211 chip. 315 */ 316void 317atw_disable(sc) 318 struct atw_softc *sc; 319{ 320 if (!ATW_IS_ENABLED(sc)) 321 return; 322 if (sc->sc_disable != NULL) 323 (*sc->sc_disable)(sc); 324 sc->sc_flags &= ~ATWF_ENABLED; 325} 326 327/* Returns -1 on failure. */ 328int 329atw_read_srom(struct atw_softc *sc) 330{ 331 struct seeprom_descriptor sd; 332 u_int32_t reg; 333 334 (void)memset(&sd, 0, sizeof(sd)); 335 336 reg = ATW_READ(sc, ATW_TEST0); 337 338 if ((reg & (ATW_TEST0_EPNE|ATW_TEST0_EPSNM)) != 0) { 339 printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname); 340 return -1; 341 } 342 343 switch (reg & ATW_TEST0_EPTYP_MASK) { 344 case ATW_TEST0_EPTYP_93c66: 345 ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname)); 346 sc->sc_sromsz = 512; 347 sd.sd_chip = C56_66; 348 break; 349 case ATW_TEST0_EPTYP_93c46: 350 ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname)); 351 sc->sc_sromsz = 128; 352 sd.sd_chip = C46; 353 break; 354 default: 355 printf("%s: unknown SROM type %d\n", sc->sc_dev.dv_xname, 356 MASK_AND_RSHIFT(reg, ATW_TEST0_EPTYP_MASK)); 357 return -1; 358 } 359 360 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 361 362 if (sc->sc_srom == NULL) { 363 printf("%s: unable to allocate SROM buffer\n", 364 sc->sc_dev.dv_xname); 365 return -1; 366 } 367 368 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 369 370 /* ADM8211 has a single 32-bit register for controlling the 371 * 93cx6 SROM. Bit SRS enables the serial port. There is no 372 * "ready" bit. The ADM8211 input/output sense is the reverse 373 * of read_seeprom's. 374 */ 375 sd.sd_tag = sc->sc_st; 376 sd.sd_bsh = sc->sc_sh; 377 sd.sd_regsize = 4; 378 sd.sd_control_offset = ATW_SPR; 379 sd.sd_status_offset = ATW_SPR; 380 sd.sd_dataout_offset = ATW_SPR; 381 sd.sd_CK = ATW_SPR_SCLK; 382 sd.sd_CS = ATW_SPR_SCS; 383 sd.sd_DI = ATW_SPR_SDO; 384 sd.sd_DO = ATW_SPR_SDI; 385 sd.sd_MS = ATW_SPR_SRS; 386 sd.sd_RDY = 0; 387 388 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 389 printf("%s: could not read SROM\n", sc->sc_dev.dv_xname); 390 free(sc->sc_srom, M_DEVBUF); 391 return -1; 392 } 393#ifdef ATW_DEBUG 394 { 395 int i; 396 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 397 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 398 if (((i % 8) == 0) && (i != 0)) { 399 ATW_DPRINTF(("\n\t")); 400 } 401 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 402 } 403 ATW_DPRINTF(("\n")); 404 } 405#endif /* ATW_DEBUG */ 406 return 0; 407} 408 409#ifdef ATW_DEBUG 410static void 411atw_print_regs(struct atw_softc *sc, const char *where) 412{ 413#define PRINTREG(sc, reg) \ 414 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 415 sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg))) 416 417 ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where)); 418 419 PRINTREG(sc, ATW_PAR); 420 PRINTREG(sc, ATW_FRCTL); 421 PRINTREG(sc, ATW_TDR); 422 PRINTREG(sc, ATW_WTDP); 423 PRINTREG(sc, ATW_RDR); 424 PRINTREG(sc, ATW_WRDP); 425 PRINTREG(sc, ATW_RDB); 426 PRINTREG(sc, ATW_CSR3A); 427 PRINTREG(sc, ATW_TDBD); 428 PRINTREG(sc, ATW_TDBP); 429 PRINTREG(sc, ATW_STSR); 430 PRINTREG(sc, ATW_CSR5A); 431 PRINTREG(sc, ATW_NAR); 432 PRINTREG(sc, ATW_CSR6A); 433 PRINTREG(sc, ATW_IER); 434 PRINTREG(sc, ATW_CSR7A); 435 PRINTREG(sc, ATW_LPC); 436 PRINTREG(sc, ATW_TEST1); 437 PRINTREG(sc, ATW_SPR); 438 PRINTREG(sc, ATW_TEST0); 439 PRINTREG(sc, ATW_WCSR); 440 PRINTREG(sc, ATW_WPDR); 441 PRINTREG(sc, ATW_GPTMR); 442 PRINTREG(sc, ATW_GPIO); 443 PRINTREG(sc, ATW_BBPCTL); 444 PRINTREG(sc, ATW_SYNCTL); 445 PRINTREG(sc, ATW_PLCPHD); 446 PRINTREG(sc, ATW_MMIWADDR); 447 PRINTREG(sc, ATW_MMIRADDR1); 448 PRINTREG(sc, ATW_MMIRADDR2); 449 PRINTREG(sc, ATW_TXBR); 450 PRINTREG(sc, ATW_CSR15A); 451 PRINTREG(sc, ATW_ALCSTAT); 452 PRINTREG(sc, ATW_TOFS2); 453 PRINTREG(sc, ATW_CMDR); 454 PRINTREG(sc, ATW_PCIC); 455 PRINTREG(sc, ATW_PMCSR); 456 PRINTREG(sc, ATW_PAR0); 457 PRINTREG(sc, ATW_PAR1); 458 PRINTREG(sc, ATW_MAR0); 459 PRINTREG(sc, ATW_MAR1); 460 PRINTREG(sc, ATW_ATIMDA0); 461 PRINTREG(sc, ATW_ABDA1); 462 PRINTREG(sc, ATW_BSSID0); 463 PRINTREG(sc, ATW_TXLMT); 464 PRINTREG(sc, ATW_MIBCNT); 465 PRINTREG(sc, ATW_BCNT); 466 PRINTREG(sc, ATW_TSFTH); 467 PRINTREG(sc, ATW_TSC); 468 PRINTREG(sc, ATW_SYNRF); 469 PRINTREG(sc, ATW_BPLI); 470 PRINTREG(sc, ATW_CAP0); 471 PRINTREG(sc, ATW_CAP1); 472 PRINTREG(sc, ATW_RMD); 473 PRINTREG(sc, ATW_CFPP); 474 PRINTREG(sc, ATW_TOFS0); 475 PRINTREG(sc, ATW_TOFS1); 476 PRINTREG(sc, ATW_IFST); 477 PRINTREG(sc, ATW_RSPT); 478 PRINTREG(sc, ATW_TSFTL); 479 PRINTREG(sc, ATW_WEPCTL); 480 PRINTREG(sc, ATW_WESK); 481 PRINTREG(sc, ATW_WEPCNT); 482 PRINTREG(sc, ATW_MACTEST); 483 PRINTREG(sc, ATW_FER); 484 PRINTREG(sc, ATW_FEMR); 485 PRINTREG(sc, ATW_FPSR); 486 PRINTREG(sc, ATW_FFER); 487#undef PRINTREG 488} 489#endif /* ATW_DEBUG */ 490 491/* 492 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 493 */ 494void 495atw_attach(struct atw_softc *sc) 496{ 497 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 498 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 499 }; 500 struct ieee80211com *ic = &sc->sc_ic; 501 struct ifnet *ifp = &ic->ic_if; 502 int country_code, error, i, nrate; 503 u_int32_t reg; 504 static const char *type_strings[] = {"Intersil (not supported)", 505 "RFMD", "Marvel (not supported)"}; 506 507 sc->sc_txth = atw_txthresh_tab_lo; 508 509 SIMPLEQ_INIT(&sc->sc_txfreeq); 510 SIMPLEQ_INIT(&sc->sc_txdirtyq); 511 512#ifdef ATW_DEBUG 513 atw_print_regs(sc, "atw_attach"); 514#endif /* ATW_DEBUG */ 515 516 /* 517 * Allocate the control data structures, and create and load the 518 * DMA map for it. 519 */ 520 if ((error = bus_dmamem_alloc(sc->sc_dmat, 521 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 522 1, &sc->sc_cdnseg, 0)) != 0) { 523 printf("%s: unable to allocate control data, error = %d\n", 524 sc->sc_dev.dv_xname, error); 525 goto fail_0; 526 } 527 528 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 529 sizeof(struct atw_control_data), (caddr_t *)&sc->sc_control_data, 530 BUS_DMA_COHERENT)) != 0) { 531 printf("%s: unable to map control data, error = %d\n", 532 sc->sc_dev.dv_xname, error); 533 goto fail_1; 534 } 535 536 if ((error = bus_dmamap_create(sc->sc_dmat, 537 sizeof(struct atw_control_data), 1, 538 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 539 printf("%s: unable to create control data DMA map, " 540 "error = %d\n", sc->sc_dev.dv_xname, error); 541 goto fail_2; 542 } 543 544 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 545 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 546 0)) != 0) { 547 printf("%s: unable to load control data DMA map, error = %d\n", 548 sc->sc_dev.dv_xname, error); 549 goto fail_3; 550 } 551 552 /* 553 * Create the transmit buffer DMA maps. 554 */ 555 sc->sc_ntxsegs = ATW_NTXSEGS; 556 for (i = 0; i < ATW_TXQUEUELEN; i++) { 557 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 558 sc->sc_ntxsegs, MCLBYTES, 0, 0, 559 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 560 printf("%s: unable to create tx DMA map %d, " 561 "error = %d\n", sc->sc_dev.dv_xname, i, error); 562 goto fail_4; 563 } 564 } 565 566 /* 567 * Create the receive buffer DMA maps. 568 */ 569 for (i = 0; i < ATW_NRXDESC; i++) { 570 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 571 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 572 printf("%s: unable to create rx DMA map %d, " 573 "error = %d\n", sc->sc_dev.dv_xname, i, error); 574 goto fail_5; 575 } 576 } 577 for (i = 0; i < ATW_NRXDESC; i++) { 578 sc->sc_rxsoft[i].rxs_mbuf = NULL; 579 } 580 581 /* Reset the chip to a known state. */ 582 atw_reset(sc); 583 584 if (atw_read_srom(sc) == -1) 585 return; 586 587 sc->sc_rftype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 588 ATW_SR_RFTYPE_MASK); 589 590 sc->sc_bbptype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 591 ATW_SR_BBPTYPE_MASK); 592 593 if (sc->sc_rftype > sizeof(type_strings)/sizeof(type_strings[0])) { 594 printf("%s: unknown RF\n", sc->sc_dev.dv_xname); 595 return; 596 } 597 if (sc->sc_bbptype > sizeof(type_strings)/sizeof(type_strings[0])) { 598 printf("%s: unknown BBP\n", sc->sc_dev.dv_xname); 599 return; 600 } 601 602 printf("%s: %s RF, %s BBP", sc->sc_dev.dv_xname, 603 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 604 605 /* XXX There exists a Linux driver which seems to use RFType = 0 for 606 * MARVEL. My bug, or theirs? 607 */ 608 609 reg = LSHIFT(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 610 611 switch (sc->sc_rftype) { 612 case ATW_RFTYPE_INTERSIL: 613 reg |= ATW_SYNCTL_CS1; 614 break; 615 case ATW_RFTYPE_RFMD: 616 reg |= ATW_SYNCTL_CS0; 617 break; 618 case ATW_RFTYPE_MARVEL: 619 break; 620 } 621 622 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 623 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 624 625 reg = LSHIFT(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 626 627 switch (sc->sc_bbptype) { 628 case ATW_RFTYPE_INTERSIL: 629 reg |= ATW_BBPCTL_TWI; 630 break; 631 case ATW_RFTYPE_RFMD: 632 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 633 ATW_BBPCTL_CCA_ACTLO; 634 break; 635 case ATW_RFTYPE_MARVEL: 636 break; 637 } 638 639 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 640 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 641 642 /* 643 * From this point forward, the attachment cannot fail. A failure 644 * before this point releases all resources that may have been 645 * allocated. 646 */ 647 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 648 649 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 650 htole16(sc->sc_srom[ATW_SR_MAC00]), 651 htole16(sc->sc_srom[ATW_SR_MAC01]), 652 htole16(sc->sc_srom[ATW_SR_MAC10]))); 653 654 country_code = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 655 ATW_SR_CTRY_MASK); 656 657#define ADD_CHANNEL(_ic, _chan) do { \ 658 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 659 _ic->ic_channels[_chan].ic_freq = \ 660 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 661} while (0) 662 663 /* Find available channels */ 664 switch (country_code) { 665 case COUNTRY_MMK2: /* 1-14 */ 666 ADD_CHANNEL(ic, 14); 667 /*FALLTHROUGH*/ 668 case COUNTRY_ETSI: /* 1-13 */ 669 for (i = 1; i <= 13; i++) 670 ADD_CHANNEL(ic, i); 671 break; 672 case COUNTRY_FCC: /* 1-11 */ 673 case COUNTRY_IC: /* 1-11 */ 674 for (i = 1; i <= 11; i++) 675 ADD_CHANNEL(ic, i); 676 break; 677 case COUNTRY_MMK: /* 14 */ 678 ADD_CHANNEL(ic, 14); 679 break; 680 case COUNTRY_FRANCE: /* 10-13 */ 681 for (i = 10; i <= 13; i++) 682 ADD_CHANNEL(ic, i); 683 break; 684 default: /* assume channels 10-11 */ 685 case COUNTRY_SPAIN: /* 10-11 */ 686 for (i = 10; i <= 11; i++) 687 ADD_CHANNEL(ic, i); 688 break; 689 } 690 691 /* Read the MAC address. */ 692 reg = ATW_READ(sc, ATW_PAR0); 693 ic->ic_myaddr[0] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB0_MASK); 694 ic->ic_myaddr[1] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB1_MASK); 695 ic->ic_myaddr[2] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB2_MASK); 696 ic->ic_myaddr[3] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB3_MASK); 697 reg = ATW_READ(sc, ATW_PAR1); 698 ic->ic_myaddr[4] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB4_MASK); 699 ic->ic_myaddr[5] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB5_MASK); 700 701 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 702 printf(" could not get mac address, attach failed\n"); 703 return; 704 } 705 706 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 707 708 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 709 ifp->if_softc = sc; 710 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 711 IFF_NOTRAILERS; 712 ifp->if_ioctl = atw_ioctl; 713 ifp->if_start = atw_start; 714 ifp->if_watchdog = atw_watchdog; 715 ifp->if_init = atw_init; 716 ifp->if_stop = atw_stop; 717 IFQ_SET_READY(&ifp->if_snd); 718 719 ic->ic_phytype = IEEE80211_T_DS; 720 ic->ic_opmode = IEEE80211_M_STA; 721 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 722 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 723 724 nrate = 0; 725 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 726 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 727 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 728 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 729 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 730 731 /* 732 * Call MI attach routines. 733 */ 734 735 if_attach(ifp); 736 ieee80211_ifattach(ifp); 737 738 sc->sc_newstate = ic->ic_newstate; 739 ic->ic_newstate = atw_newstate; 740 741 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 742 ic->ic_recv_mgmt = atw_recv_mgmt; 743 744 sc->sc_node_free = ic->ic_node_free; 745 ic->ic_node_free = atw_node_free; 746 747 sc->sc_node_alloc = ic->ic_node_alloc; 748 ic->ic_node_alloc = atw_node_alloc; 749 750 /* possibly we should fill in our own sc_send_prresp, since 751 * the ADM8211 is probably sending probe responses in ad hoc 752 * mode. 753 */ 754 755 /* complete initialization */ 756 ieee80211_media_init(ifp, atw_media_change, atw_media_status); 757 callout_init(&sc->sc_scan_ch); 758 759#if NBPFILTER > 0 760 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 761 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 762#endif 763 764 /* 765 * Make sure the interface is shutdown during reboot. 766 */ 767 sc->sc_sdhook = shutdownhook_establish(atw_shutdown, sc); 768 if (sc->sc_sdhook == NULL) 769 printf("%s: WARNING: unable to establish shutdown hook\n", 770 sc->sc_dev.dv_xname); 771 772 /* 773 * Add a suspend hook to make sure we come back up after a 774 * resume. 775 */ 776 sc->sc_powerhook = powerhook_establish(atw_power, sc); 777 if (sc->sc_powerhook == NULL) 778 printf("%s: WARNING: unable to establish power hook\n", 779 sc->sc_dev.dv_xname); 780 781 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 782 sc->sc_rxtap.ar_ihdr.it_len = sizeof(sc->sc_rxtapu); 783 sc->sc_rxtap.ar_ihdr.it_present = ATW_RX_RADIOTAP_PRESENT; 784 785 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 786 sc->sc_txtap.at_ihdr.it_len = sizeof(sc->sc_txtapu); 787 sc->sc_txtap.at_ihdr.it_present = ATW_TX_RADIOTAP_PRESENT; 788 789 return; 790 791 /* 792 * Free any resources we've allocated during the failed attach 793 * attempt. Do this in reverse order and fall through. 794 */ 795 fail_5: 796 for (i = 0; i < ATW_NRXDESC; i++) { 797 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 798 continue; 799 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 800 } 801 fail_4: 802 for (i = 0; i < ATW_TXQUEUELEN; i++) { 803 if (sc->sc_txsoft[i].txs_dmamap == NULL) 804 continue; 805 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 806 } 807 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 808 fail_3: 809 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 810 fail_2: 811 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 812 sizeof(struct atw_control_data)); 813 fail_1: 814 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 815 fail_0: 816 return; 817} 818 819static struct ieee80211_node * 820atw_node_alloc(struct ieee80211com *ic) 821{ 822 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 823 struct ieee80211_node *ni = (*sc->sc_node_alloc)(ic); 824 825 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 826 return ni; 827} 828 829static void 830atw_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 831{ 832 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 833 834 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 835 ether_sprintf(ni->ni_bssid))); 836 (*sc->sc_node_free)(ic, ni); 837} 838 839/* 840 * atw_reset: 841 * 842 * Perform a soft reset on the ADM8211. 843 */ 844void 845atw_reset(sc) 846 struct atw_softc *sc; 847{ 848 int i; 849 850 if (ATW_IS_ENABLED(sc) == 0) 851 return; 852 853 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 854 855 for (i = 0; i < 10000; i++) { 856 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR) == 0) 857 break; 858 DELAY(1); 859 } 860 861 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i)); 862 863 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 864 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 865 866 /* Turn off maximum power saving. */ 867 ATW_CLR(sc, ATW_FRCTL, ATW_FRCTL_MAXPSP); 868 869 /* Recall EEPROM. */ 870 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 871 872 DELAY(10 * 1000); 873 874 /* A reset seems to affect the SRAM contents, so put them into 875 * a known state. 876 */ 877 atw_clear_sram(sc); 878 879 memset(sc->sc_bssid, 0, sizeof(sc->sc_bssid)); 880 881 sc->sc_lost_bcn_thresh = 0; 882} 883 884static void 885atw_clear_sram(sc) 886 struct atw_softc *sc; 887{ 888#if 0 889 for (addr = 0; addr < 448; addr++) { 890 ATW_WRITE(sc, ATW_WEPCTL, 891 ATW_WEPCTL_WR | ATW_WEPCTL_UNKNOWN0 | addr); 892 DELAY(1000); 893 ATW_WRITE(sc, ATW_WESK, 0); 894 DELAY(1000); /* paranoia */ 895 } 896 return; 897#endif 898 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 899 /* XXX not for revision 0x20. */ 900 atw_write_sram(sc, 0, sc->sc_sram, sizeof(sc->sc_sram)); 901} 902 903/* TBD atw_init 904 * 905 * set MAC based on ic->ic_bss->myaddr 906 * write WEP keys 907 * set TX rate 908 */ 909 910/* 911 * atw_init: [ ifnet interface function ] 912 * 913 * Initialize the interface. Must be called at splnet(). 914 */ 915int 916atw_init(ifp) 917 struct ifnet *ifp; 918{ 919 struct atw_softc *sc = ifp->if_softc; 920 struct ieee80211com *ic = &sc->sc_ic; 921 struct atw_txsoft *txs; 922 struct atw_rxsoft *rxs; 923 u_int32_t reg; 924 int i, error = 0; 925 926 if ((error = atw_enable(sc)) != 0) 927 goto out; 928 929 /* 930 * Cancel any pending I/O. This also resets. 931 */ 932 atw_stop(ifp, 0); 933 934 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 935 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 936 __func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan), 937 ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags)); 938 939 /* Turn off APM??? (A binary-only driver does this.) 940 * 941 * Set Rx store-and-forward mode. 942 */ 943 reg = ATW_READ(sc, ATW_CMDR); 944 reg &= ~ATW_CMDR_APM; 945 reg &= ~ATW_CMDR_DRT_MASK; 946 reg |= ATW_CMDR_RTE | LSHIFT(0x2, ATW_CMDR_DRT_MASK); 947 948 ATW_WRITE(sc, ATW_CMDR, reg); 949 950 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 951 * 952 * XXX a binary-only driver sets a different service field than 953 * 0. why? 954 */ 955 reg = ATW_READ(sc, ATW_PLCPHD); 956 reg &= ~(ATW_PLCPHD_SERVICE_MASK|ATW_PLCPHD_SIGNAL_MASK); 957 reg |= LSHIFT(10, ATW_PLCPHD_SIGNAL_MASK) | 958 LSHIFT(0xb0, ATW_PLCPHD_SERVICE_MASK); 959 ATW_WRITE(sc, ATW_PLCPHD, reg); 960 961 /* XXX this magic can probably be figured out from the RFMD docs */ 962 reg = LSHIFT(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 963 LSHIFT(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 964 LSHIFT(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 965 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 966 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 967 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 968 LSHIFT(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 969 LSHIFT(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 970 ATW_WRITE(sc, ATW_TOFS2, reg); 971 972 ATW_WRITE(sc, ATW_TXLMT, LSHIFT(512, ATW_TXLMT_MTMLT_MASK) | 973 LSHIFT(224, ATW_TXLMT_SRTYLIM_MASK)); 974 975 /* XXX this resets an Intersil RF front-end? */ 976 /* TBD condition on Intersil RFType? */ 977 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 978 DELAY(10 * 1000); 979 ATW_WRITE(sc, ATW_SYNRF, 0); 980 DELAY(5 * 1000); 981 982 /* 16 TU max duration for contention-free period */ 983 reg = ATW_READ(sc, ATW_CFPP) & ~ATW_CFPP_CFPMD; 984 ATW_WRITE(sc, ATW_CFPP, reg | LSHIFT(16, ATW_CFPP_CFPMD)); 985 986 /* XXX I guess that the Cardbus clock is 22MHz? 987 * I am assuming that the role of ATW_TOFS0_USCNT is 988 * to divide the bus clock to get a 1MHz clock---the datasheet is not 989 * very clear on this point. It says in the datasheet that it is 990 * possible for the ADM8211 to accomodate bus speeds between 22MHz 991 * and 33MHz; maybe this is the way? I see a binary-only driver write 992 * these values. These values are also the power-on default. 993 */ 994 ATW_WRITE(sc, ATW_TOFS0, 995 LSHIFT(22, ATW_TOFS0_USCNT_MASK) | 996 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 997 998 /* Initialize interframe spacing. EIFS=0x64 is used by a binary-only 999 * driver. Go figure. 1000 */ 1001 reg = LSHIFT(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 1002 LSHIFT(22 * IEEE80211_DUR_DS_SIFS /* # of 22MHz cycles */, 1003 ATW_IFST_SIFS_MASK) | 1004 LSHIFT(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1005 LSHIFT(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 1006 1007 ATW_WRITE(sc, ATW_IFST, reg); 1008 1009 /* XXX More magic. Might relate to ACK timing. */ 1010 ATW_WRITE(sc, ATW_RSPT, LSHIFT(0xffff, ATW_RSPT_MART_MASK) | 1011 LSHIFT(0xff, ATW_RSPT_MIRT_MASK)); 1012 1013 /* Set up the MMI read/write addresses for the BBP. 1014 * 1015 * TBD find out the Marvel settings. 1016 */ 1017 switch (sc->sc_bbptype) { 1018 case ATW_BBPTYPE_INTERSIL: 1019 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1020 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1021 ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_INTERSIL); 1022 break; 1023 case ATW_BBPTYPE_MARVEL: 1024 break; 1025 case ATW_BBPTYPE_RFMD: 1026 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1027 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1028 ATW_WRITE(sc, ATW_MMIRADDR2, ATW_MMIRADDR2_RFMD); 1029 default: 1030 break; 1031 } 1032 1033 sc->sc_wepctl = 0; 1034 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1035 1036 if ((error = atw_rf3000_init(sc)) != 0) 1037 goto out; 1038 1039 /* 1040 * Initialize the PCI Access Register. 1041 */ 1042 sc->sc_busmode = ATW_PAR_BAR; /* XXX what is this? */ 1043 1044 /* 1045 * If we're allowed to do so, use Memory Read Line 1046 * and Memory Read Multiple. 1047 * 1048 * XXX Should we use Memory Write and Invalidate? 1049 */ 1050 if (sc->sc_flags & ATWF_MRL) 1051 sc->sc_busmode |= ATW_PAR_MRLE; 1052 if (sc->sc_flags & ATWF_MRM) 1053 sc->sc_busmode |= ATW_PAR_MRME; 1054 if (sc->sc_flags & ATWF_MWI) 1055 sc->sc_busmode |= ATW_PAR_MWIE; 1056 if (sc->sc_maxburst == 0) 1057 sc->sc_maxburst = 8; /* ADM8211 default */ 1058 1059 switch (sc->sc_cacheline) { 1060 default: 1061 /* Use burst length. */ 1062 break; 1063 case 8: 1064 sc->sc_busmode |= ATW_PAR_CAL_8DW; 1065 break; 1066 case 16: 1067 sc->sc_busmode |= ATW_PAR_CAL_16DW; 1068 break; 1069 case 32: 1070 sc->sc_busmode |= ATW_PAR_CAL_32DW; 1071 break; 1072 } 1073 switch (sc->sc_maxburst) { 1074 case 1: 1075 sc->sc_busmode |= ATW_PAR_PBL_1DW; 1076 break; 1077 case 2: 1078 sc->sc_busmode |= ATW_PAR_PBL_2DW; 1079 break; 1080 case 4: 1081 sc->sc_busmode |= ATW_PAR_PBL_4DW; 1082 break; 1083 case 8: 1084 sc->sc_busmode |= ATW_PAR_PBL_8DW; 1085 break; 1086 case 16: 1087 sc->sc_busmode |= ATW_PAR_PBL_16DW; 1088 break; 1089 case 32: 1090 sc->sc_busmode |= ATW_PAR_PBL_32DW; 1091 break; 1092 default: 1093 sc->sc_busmode |= ATW_PAR_PBL_8DW; 1094 break; 1095 } 1096 1097 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1098 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 1099 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1100 1101 /* 1102 * Initialize the OPMODE register. We don't write it until 1103 * we're ready to begin the transmit and receive processes. 1104 */ 1105 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1106 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1107 1108 /* 1109 * Initialize the transmit descriptor ring. 1110 */ 1111 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1112 for (i = 0; i < ATW_NTXDESC; i++) { 1113 /* no transmit chaining */ 1114 sc->sc_txdescs[i].at_ctl = 0 /* ATW_TXFLAG_TCH */; 1115 sc->sc_txdescs[i].at_buf2 = 1116 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1117 } 1118 /* use ring mode */ 1119 sc->sc_txdescs[ATW_NTXDESC - 1].at_ctl |= ATW_TXFLAG_TER; 1120 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1121 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1122 sc->sc_txfree = ATW_NTXDESC; 1123 sc->sc_txnext = 0; 1124 1125 /* 1126 * Initialize the transmit job descriptors. 1127 */ 1128 SIMPLEQ_INIT(&sc->sc_txfreeq); 1129 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1130 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1131 txs = &sc->sc_txsoft[i]; 1132 txs->txs_mbuf = NULL; 1133 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1134 } 1135 1136 /* 1137 * Initialize the receive descriptor and receive job 1138 * descriptor rings. 1139 */ 1140 for (i = 0; i < ATW_NRXDESC; i++) { 1141 rxs = &sc->sc_rxsoft[i]; 1142 if (rxs->rxs_mbuf == NULL) { 1143 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1144 printf("%s: unable to allocate or map rx " 1145 "buffer %d, error = %d\n", 1146 sc->sc_dev.dv_xname, i, error); 1147 /* 1148 * XXX Should attempt to run with fewer receive 1149 * XXX buffers instead of just failing. 1150 */ 1151 atw_rxdrain(sc); 1152 goto out; 1153 } 1154 } else 1155 ATW_INIT_RXDESC(sc, i); 1156 } 1157 sc->sc_rxptr = 0; 1158 1159 /* disable all wake-up events */ 1160 ATW_CLR(sc, ATW_WCSR, ATW_WCSR_WP1E|ATW_WCSR_WP2E|ATW_WCSR_WP3E| 1161 ATW_WCSR_WP4E|ATW_WCSR_WP5E|ATW_WCSR_TSFTWE| 1162 ATW_WCSR_TIMWE|ATW_WCSR_ATIMWE|ATW_WCSR_KEYWE| 1163 ATW_WCSR_WFRE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1164 1165 /* ack all wake-up events */ 1166 ATW_SET(sc, ATW_WCSR, 0); 1167 1168 /* 1169 * Initialize the interrupt mask and enable interrupts. 1170 */ 1171 /* normal interrupts */ 1172 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1173 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1174 1175 /* abnormal interrupts */ 1176 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1177 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1178 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1179 1180 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1181 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1182 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1183 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1184 ATW_INTR_TRT; 1185 1186 sc->sc_linkint_mask &= sc->sc_inten; 1187 sc->sc_rxint_mask &= sc->sc_inten; 1188 sc->sc_txint_mask &= sc->sc_inten; 1189 1190 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1191 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1192 if (sc->sc_intr_ack != NULL) 1193 (*sc->sc_intr_ack)(sc); 1194 1195 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1196 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten)); 1197 1198 /* 1199 * Give the transmit and receive rings to the ADM8211. 1200 */ 1201 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1202 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1203 1204 /* common 802.11 configuration */ 1205 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1206 switch (ic->ic_opmode) { 1207 case IEEE80211_M_STA: 1208 sc->sc_opmode &= ~ATW_NAR_EA; 1209 break; 1210 case IEEE80211_M_AHDEMO: /* XXX */ 1211 case IEEE80211_M_IBSS: 1212 ic->ic_flags |= IEEE80211_F_IBSSON; 1213 /*FALLTHROUGH*/ 1214 case IEEE80211_M_HOSTAP: /* XXX */ 1215 /* EA bit seems important for ad hoc reception. */ 1216 sc->sc_opmode |= ATW_NAR_EA; 1217 break; 1218 case IEEE80211_M_MONITOR: /* XXX */ 1219 break; 1220 } 1221 1222 atw_start_beacon(sc, 0); 1223 1224 switch (ic->ic_opmode) { 1225 case IEEE80211_M_AHDEMO: 1226 case IEEE80211_M_HOSTAP: 1227 ic->ic_bss->ni_intval = ic->ic_lintval; 1228 ic->ic_bss->ni_rssi = 0; 1229 ic->ic_bss->ni_rstamp = 0; 1230 break; 1231 default: /* XXX */ 1232 break; 1233 } 1234 1235 atw_write_ssid(sc); 1236 atw_write_sup_rates(sc); 1237 if (ic->ic_caps & IEEE80211_C_WEP) 1238 atw_write_wep(sc); 1239 1240 /* 1241 * Set the receive filter. This will start the transmit and 1242 * receive processes. 1243 */ 1244 atw_filter_setup(sc); 1245 1246 /* 1247 * Start the receive process. 1248 */ 1249 ATW_WRITE(sc, ATW_RDR, 0x1); 1250 1251 /* 1252 * Note that the interface is now running. 1253 */ 1254 ifp->if_flags |= IFF_RUNNING; 1255 ifp->if_flags &= ~IFF_OACTIVE; 1256 ic->ic_state = IEEE80211_S_INIT; 1257 1258 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1259 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1260 else 1261 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1262 out: 1263 if (error) { 1264 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1265 ifp->if_timer = 0; 1266 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1267 } 1268#ifdef ATW_DEBUG 1269 atw_print_regs(sc, "end of init"); 1270#endif /* ATW_DEBUG */ 1271 1272 return (error); 1273} 1274 1275/* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1276 * 0: MAC control of RF3000/Si4126. 1277 * 1278 * Applies power, or selects RF front-end? Sets reset condition. 1279 * 1280 * TBD support non-RFMD BBP, non-SiLabs synth. 1281 */ 1282static void 1283atw_rfio_enable(struct atw_softc *sc, int enable) 1284{ 1285 if (enable) { 1286 ATW_WRITE(sc, ATW_SYNRF, 1287 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1288 DELAY(atw_rfio_enable_delay); 1289 } else { 1290 ATW_WRITE(sc, ATW_SYNRF, 0); 1291 DELAY(atw_rfio_disable_delay); /* shorter for some reason */ 1292 } 1293} 1294 1295static int 1296atw_tune(sc) 1297 struct atw_softc *sc; 1298{ 1299 int rc; 1300 u_int32_t reg; 1301 int chan; 1302 struct ieee80211com *ic = &sc->sc_ic; 1303 1304 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 1305 if (chan == IEEE80211_CHAN_ANY) 1306 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1307 1308 if (chan == sc->sc_cur_chan) 1309 return 0; 1310 1311 DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname, 1312 sc->sc_cur_chan, chan)); 1313 1314 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1315 1316 if ((rc = atw_si4126_tune(sc, chan)) != 0 || 1317 (rc = atw_rf3000_tune(sc, chan)) != 0) 1318 printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname, 1319 chan); 1320 1321 reg = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 1322 ATW_WRITE(sc, ATW_CAP0, 1323 reg | LSHIFT(chan, ATW_CAP0_CHN_MASK)); 1324 1325 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1326 1327 if (rc == 0) 1328 sc->sc_cur_chan = chan; 1329 1330 return rc; 1331} 1332 1333#ifdef ATW_DEBUG 1334static void 1335atw_si4126_print(sc) 1336 struct atw_softc *sc; 1337{ 1338 struct ifnet *ifp = &sc->sc_ic.ic_if; 1339 u_int addr, val; 1340 1341 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1342 return; 1343 1344 for (addr = 0; addr <= 8; addr++) { 1345 printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr); 1346 if (atw_si4126_read(sc, addr, &val) == 0) { 1347 printf("<unknown> (quitting print-out)\n"); 1348 break; 1349 } 1350 printf("%05x\n", val); 1351 } 1352} 1353#endif /* ATW_DEBUG */ 1354 1355/* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1356 * 1357 * The RF/IF synthesizer produces two reference frequencies for 1358 * the RF2948B transceiver. The first frequency the RF2948B requires 1359 * is two times the so-called "intermediate frequency" (IF). Since 1360 * a SAW filter on the radio fixes the IF at 374MHz, I program the 1361 * Si4126 to generate IF LO = 374MHz x 2 = 748MHz. The second 1362 * frequency required by the transceiver is the radio frequency 1363 * (RF). This is a superheterodyne transceiver; for f(chan) the 1364 * center frequency of the channel we are tuning, RF = f(chan) - 1365 * IF. 1366 * 1367 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1368 * of XIN than the 2-25MHz mentioned by the datasheet, even *without* 1369 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1370 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1371 */ 1372static int 1373atw_si4126_tune(sc, chan) 1374 struct atw_softc *sc; 1375 u_int8_t chan; 1376{ 1377 int rc = 0; 1378 u_int mhz; 1379 u_int R; 1380 u_int32_t reg; 1381 u_int16_t gain; 1382 1383#ifdef ATW_DEBUG 1384 atw_si4126_print(sc); 1385#endif /* ATW_DEBUG */ 1386 1387 if (chan == 14) 1388 mhz = 2484; 1389 else 1390 mhz = 2412 + 5 * (chan - 1); 1391 1392 /* Tune IF to 748MHz to suit the IF LO input of the 1393 * RF2494B, which is 2 x IF. No need to set an IF divider 1394 * because an IF in 526MHz - 952MHz is allowed. 1395 * 1396 * XIN is 44.000MHz, so divide it by two to get allowable 1397 * range of 2-25MHz. SiLabs tells me that this is not 1398 * strictly necessary. 1399 */ 1400 1401 R = 44; 1402 1403 atw_rfio_enable(sc, 1); 1404 1405 /* Power-up RF, IF synthesizers. */ 1406 if ((rc = atw_si4126_write(sc, SI4126_POWER, 1407 SI4126_POWER_PDIB|SI4126_POWER_PDRB)) != 0) 1408 goto out; 1409 1410 /* If RF2 N > 2047, then set KP2 to 1. */ 1411 gain = LSHIFT(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1412 1413 if ((rc = atw_si4126_write(sc, SI4126_GAIN, gain)) != 0) 1414 goto out; 1415 1416 /* set LPWR, too? */ 1417 if ((rc = atw_si4126_write(sc, SI4126_MAIN, 1418 SI4126_MAIN_XINDIV2)) != 0) 1419 goto out; 1420 1421 /* We set XINDIV2 = 1, so IF = N/(2 * R) * XIN. XIN = 44MHz. 1422 * I choose N = 1496, R = 44 so that 1496/(2 * 44) * 44MHz = 748MHz. 1423 */ 1424 if ((rc = atw_si4126_write(sc, SI4126_IFN, 1496)) != 0) 1425 goto out; 1426 1427 if ((rc = atw_si4126_write(sc, SI4126_IFR, R)) != 0) 1428 goto out; 1429 1430 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1431 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1432 * which has no RF1! 1433 */ 1434 if ((rc = atw_si4126_write(sc, SI4126_RF1R, R)) != 0) 1435 goto out; 1436 1437 if ((rc = atw_si4126_write(sc, SI4126_RF1N, mhz - 374)) != 0) 1438 goto out; 1439 1440 /* N/R * XIN = RF. XIN = 44MHz. We desire RF = mhz - IF, 1441 * where IF = 374MHz. Let's divide XIN to 1MHz. So R = 44. 1442 * Now let's multiply it to mhz. So mhz - IF = N. 1443 */ 1444 if ((rc = atw_si4126_write(sc, SI4126_RF2R, R)) != 0) 1445 goto out; 1446 1447 if ((rc = atw_si4126_write(sc, SI4126_RF2N, mhz - 374)) != 0) 1448 goto out; 1449 1450 /* wait 100us from power-up for RF, IF to settle */ 1451 DELAY(100); 1452 1453 if ((sc->sc_if.if_flags & IFF_LINK1) == 0 || chan == 14) { 1454 /* XXX there is a binary driver which sends 1455 * ATW_GPIO_EN_MASK = 1, ATW_GPIO_O_MASK = 1. I had speculated 1456 * that this enables the Si4126 by raising its PWDN#, but I 1457 * think that it actually sets the Prism RF front-end 1458 * to a special mode for channel 14. 1459 */ 1460 reg = ATW_READ(sc, ATW_GPIO); 1461 reg &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1462 reg |= LSHIFT(1, ATW_GPIO_EN_MASK) | LSHIFT(1, ATW_GPIO_O_MASK); 1463 ATW_WRITE(sc, ATW_GPIO, reg); 1464 } 1465 1466#ifdef ATW_DEBUG 1467 atw_si4126_print(sc); 1468#endif /* ATW_DEBUG */ 1469 1470out: 1471 atw_rfio_enable(sc, 0); 1472 1473 return rc; 1474} 1475 1476/* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1477 * diversity. 1478 * 1479 * Call this w/ Tx/Rx suspended. 1480 */ 1481static int 1482atw_rf3000_init(sc) 1483 struct atw_softc *sc; 1484{ 1485 int rc = 0; 1486 1487 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1488 1489 atw_rfio_enable(sc, 1); 1490 1491 /* enable diversity */ 1492 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1493 1494 if (rc != 0) 1495 goto out; 1496 1497 /* sensible setting from a binary-only driver */ 1498 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1499 LSHIFT(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1500 1501 if (rc != 0) 1502 goto out; 1503 1504 /* magic from a binary-only driver */ 1505 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1506 LSHIFT(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1507 1508 if (rc != 0) 1509 goto out; 1510 1511 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1512 1513 if (rc != 0) 1514 goto out; 1515 1516 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1517 1518 if (rc != 0) 1519 goto out; 1520 1521 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1522 1523 if (rc != 0) 1524 goto out; 1525 1526 /* CCA is acquisition sensitive */ 1527 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1528 LSHIFT(RF3000_CCACTL_MODE_ACQ, RF3000_CCACTL_MODE_MASK)); 1529 1530 if (rc != 0) 1531 goto out; 1532 1533out: 1534 atw_rfio_enable(sc, 0); 1535 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1536 return rc; 1537} 1538 1539#ifdef ATW_DEBUG 1540static void 1541atw_rf3000_print(sc) 1542 struct atw_softc *sc; 1543{ 1544 struct ifnet *ifp = &sc->sc_ic.ic_if; 1545 u_int addr, val; 1546 1547 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1548 return; 1549 1550 for (addr = 0x01; addr <= 0x15; addr++) { 1551 printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr); 1552 if (atw_rf3000_read(sc, addr, &val) != 0) { 1553 printf("<unknown> (quitting print-out)\n"); 1554 break; 1555 } 1556 printf("%08x\n", val); 1557 } 1558} 1559#endif /* ATW_DEBUG */ 1560 1561/* Set the power settings on the BBP for channel `chan'. */ 1562static int 1563atw_rf3000_tune(sc, chan) 1564 struct atw_softc *sc; 1565 u_int8_t chan; 1566{ 1567 int rc = 0; 1568 u_int32_t reg; 1569 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1570 1571 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1572 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1573 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1574 1575 /* odd channels: LSB, even channels: MSB */ 1576 if (chan % 2 == 1) { 1577 txpower &= 0xFF; 1578 lpf_cutoff &= 0xFF; 1579 lna_gs_thresh &= 0xFF; 1580 } else { 1581 txpower >>= 8; 1582 lpf_cutoff >>= 8; 1583 lna_gs_thresh >>= 8; 1584 } 1585 1586#ifdef ATW_DEBUG 1587 atw_rf3000_print(sc); 1588#endif /* ATW_DEBUG */ 1589 1590 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1591 "lna_gs_thresh %02x\n", 1592 sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh)); 1593 1594 atw_rfio_enable(sc, 1); 1595 1596 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1597 LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1598 goto out; 1599 1600 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1601 goto out; 1602 1603 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1604 goto out; 1605 1606 /* from a binary-only driver. */ 1607 reg = ATW_READ(sc, ATW_PLCPHD); 1608 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1609 reg |= LSHIFT(txpower << 2, ATW_PLCPHD_SERVICE_MASK); 1610 ATW_WRITE(sc, ATW_PLCPHD, reg); 1611 1612#ifdef ATW_DEBUG 1613 atw_rf3000_print(sc); 1614#endif /* ATW_DEBUG */ 1615 1616out: 1617 atw_rfio_enable(sc, 0); 1618 1619 return rc; 1620} 1621 1622/* Write a register on the RF3000 baseband processor using the 1623 * registers provided by the ADM8211 for this purpose. 1624 * 1625 * Return 0 on success. 1626 */ 1627static int 1628atw_rf3000_write(sc, addr, val) 1629 struct atw_softc *sc; 1630 u_int addr, val; 1631{ 1632 u_int32_t reg; 1633 int i; 1634 1635 for (i = 1000; --i >= 0; ) { 1636 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1637 break; 1638 DELAY(100); 1639 } 1640 1641 if (i < 0) { 1642 printf("%s: BBPCTL busy (pre-write)\n", sc->sc_dev.dv_xname); 1643 return ETIMEDOUT; 1644 } 1645 1646 reg = sc->sc_bbpctl_wr | 1647 LSHIFT(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1648 LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1649 1650 ATW_WRITE(sc, ATW_BBPCTL, reg); 1651 1652 for (i = 1000; --i >= 0; ) { 1653 DELAY(100); 1654 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1655 break; 1656 } 1657 1658 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_WR); 1659 1660 if (i < 0) { 1661 printf("%s: BBPCTL busy (post-write)\n", sc->sc_dev.dv_xname); 1662 return ETIMEDOUT; 1663 } 1664 return 0; 1665} 1666 1667/* Read a register on the RF3000 baseband processor using the registers 1668 * the ADM8211 provides for this purpose. 1669 * 1670 * The 7-bit register address is addr. Record the 8-bit data in the register 1671 * in *val. 1672 * 1673 * Return 0 on success. 1674 * 1675 * XXX This does not seem to work. The ADM8211 must require more or 1676 * different magic to read the chip than to write it. Possibly some 1677 * of the magic I have derived from a binary-only driver concerns 1678 * the "chip address" (see the RF3000 manual). 1679 */ 1680#ifdef ATW_DEBUG 1681static int 1682atw_rf3000_read(sc, addr, val) 1683 struct atw_softc *sc; 1684 u_int addr, *val; 1685{ 1686 u_int32_t reg; 1687 int i; 1688 1689 for (i = 1000; --i >= 0; ) { 1690 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1691 break; 1692 DELAY(100); 1693 } 1694 1695 if (i < 0) { 1696 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1697 sc->sc_dev.dv_xname); 1698 return ETIMEDOUT; 1699 } 1700 1701 reg = sc->sc_bbpctl_rd | LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1702 1703 ATW_WRITE(sc, ATW_BBPCTL, reg); 1704 1705 for (i = 1000; --i >= 0; ) { 1706 DELAY(100); 1707 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1708 break; 1709 } 1710 1711 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1712 1713 if (i < 0) { 1714 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1715 sc->sc_dev.dv_xname, reg); 1716 return ETIMEDOUT; 1717 } 1718 if (val != NULL) 1719 *val = MASK_AND_RSHIFT(reg, ATW_BBPCTL_DATA_MASK); 1720 return 0; 1721} 1722#endif /* ATW_DEBUG */ 1723 1724/* Write a register on the Si4126 RF/IF synthesizer using the registers 1725 * provided by the ADM8211 for that purpose. 1726 * 1727 * val is 18 bits of data, and val is the 4-bit address of the register. 1728 * 1729 * Return 0 on success. 1730 */ 1731static int 1732atw_si4126_write(sc, addr, val) 1733 struct atw_softc *sc; 1734 u_int addr, val; 1735{ 1736 u_int32_t reg; 1737 int i; 1738 1739 for (i = 1000; --i >= 0; ) { 1740 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1741 break; 1742 DELAY(100); 1743 } 1744 1745 if (i < 0) { 1746 printf("%s: start atw_si4126_write, SYNCTL busy\n", 1747 sc->sc_dev.dv_xname); 1748 return ETIMEDOUT; 1749 } 1750 1751 reg = sc->sc_synctl_wr | 1752 LSHIFT(((val & 0x3ffff) << 4) | (addr & 0xf), ATW_SYNCTL_DATA_MASK); 1753 1754 ATW_WRITE(sc, ATW_SYNCTL, reg); 1755 1756 for (i = 1000; --i >= 0; ) { 1757 DELAY(100); 1758 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_WR) == 0) 1759 break; 1760 } 1761 1762 /* restore to acceptable starting condition */ 1763 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_WR); 1764 1765 if (i < 0) { 1766 printf("%s: atw_si4126_write wrote %08x, SYNCTL still busy\n", 1767 sc->sc_dev.dv_xname, reg); 1768 return ETIMEDOUT; 1769 } 1770 return 0; 1771} 1772 1773/* Read 18-bit data from the 4-bit address addr in Si4126 1774 * RF synthesizer and write the data to *val. Return 0 on success. 1775 * 1776 * XXX This does not seem to work. The ADM8211 must require more or 1777 * different magic to read the chip than to write it. 1778 */ 1779#ifdef ATW_DEBUG 1780static int 1781atw_si4126_read(sc, addr, val) 1782 struct atw_softc *sc; 1783 u_int addr; 1784 u_int *val; 1785{ 1786 u_int32_t reg; 1787 int i; 1788 1789 for (i = 1000; --i >= 0; ) { 1790 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1791 break; 1792 DELAY(100); 1793 } 1794 1795 if (i < 0) { 1796 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1797 sc->sc_dev.dv_xname); 1798 return ETIMEDOUT; 1799 } 1800 1801 reg = sc->sc_synctl_rd | LSHIFT(addr & 0xf, ATW_SYNCTL_DATA_MASK); 1802 1803 ATW_WRITE(sc, ATW_SYNCTL, reg); 1804 1805 for (i = 1000; --i >= 0; ) { 1806 DELAY(100); 1807 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1808 break; 1809 } 1810 1811 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1812 1813 if (i < 0) { 1814 printf("%s: atw_si4126_read wrote %08x, SYNCTL still busy\n", 1815 sc->sc_dev.dv_xname, reg); 1816 return ETIMEDOUT; 1817 } 1818 if (val != NULL) 1819 *val = MASK_AND_RSHIFT(ATW_READ(sc, ATW_SYNCTL), 1820 ATW_SYNCTL_DATA_MASK); 1821 return 0; 1822} 1823#endif /* ATW_DEBUG */ 1824 1825/* XXX is the endianness correct? test. */ 1826#define atw_calchash(addr) \ 1827 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0)) 1828 1829/* 1830 * atw_filter_setup: 1831 * 1832 * Set the ADM8211's receive filter. 1833 */ 1834static void 1835atw_filter_setup(sc) 1836 struct atw_softc *sc; 1837{ 1838 struct ieee80211com *ic = &sc->sc_ic; 1839 struct ethercom *ec = &ic->ic_ec; 1840 struct ifnet *ifp = &sc->sc_ic.ic_if; 1841 int hash; 1842 u_int32_t hashes[2] = { 0, 0 }; 1843 struct ether_multi *enm; 1844 struct ether_multistep step; 1845 1846 DPRINTF(sc, ("%s: atw_filter_setup: sc_flags 0x%08x\n", 1847 sc->sc_dev.dv_xname, sc->sc_flags)); 1848 1849 /* 1850 * If we're running, idle the receive engine. If we're NOT running, 1851 * we're being called from atw_init(), and our writing ATW_NAR will 1852 * start the transmit and receive processes in motion. 1853 */ 1854 if (ifp->if_flags & IFF_RUNNING) 1855 atw_idle(sc, ATW_NAR_SR); 1856 1857 sc->sc_opmode &= ~(ATW_NAR_PR|ATW_NAR_MM); 1858 1859 ifp->if_flags &= ~IFF_ALLMULTI; 1860 1861 if (ifp->if_flags & IFF_PROMISC) { 1862 sc->sc_opmode |= ATW_NAR_PR; 1863allmulti: 1864 ifp->if_flags |= IFF_ALLMULTI; 1865 goto setit; 1866 } 1867 1868 /* 1869 * Program the 64-bit multicast hash filter. 1870 */ 1871 ETHER_FIRST_MULTI(step, ec, enm); 1872 while (enm != NULL) { 1873 /* XXX */ 1874 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1875 ETHER_ADDR_LEN) != 0) 1876 goto allmulti; 1877 1878 hash = atw_calchash(enm->enm_addrlo); 1879 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1880 ETHER_NEXT_MULTI(step, enm); 1881 } 1882 1883 if (ifp->if_flags & IFF_BROADCAST) { 1884 hash = atw_calchash(etherbroadcastaddr); 1885 hashes[hash >> 5] |= 1 << (hash & 0x1f); 1886 } 1887 1888 /* all bits set => hash is useless */ 1889 if (~(hashes[0] & hashes[1]) == 0) 1890 goto allmulti; 1891 1892 setit: 1893 if (ifp->if_flags & IFF_ALLMULTI) 1894 sc->sc_opmode |= ATW_NAR_MM; 1895 1896 /* XXX in scan mode, do not filter packets. maybe this is 1897 * unnecessary. 1898 */ 1899 if (ic->ic_state == IEEE80211_S_SCAN) 1900 sc->sc_opmode |= ATW_NAR_PR; 1901 1902 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 1903 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 1904 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1905 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname, 1906 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 1907 1908 DPRINTF(sc, ("%s: atw_filter_setup: returning\n", sc->sc_dev.dv_xname)); 1909} 1910 1911/* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 1912 * a beacon's BSSID and SSID against the preferred BSSID and SSID 1913 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 1914 * no beacon with the preferred BSSID and SSID in the number of 1915 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 1916 */ 1917static void 1918atw_write_bssid(sc) 1919 struct atw_softc *sc; 1920{ 1921 struct ieee80211com *ic = &sc->sc_ic; 1922 u_int8_t *bssid; 1923 1924 bssid = ic->ic_bss->ni_bssid; 1925 1926 ATW_WRITE(sc, ATW_ABDA1, 1927 (ATW_READ(sc, ATW_ABDA1) & 1928 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 1929 LSHIFT(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 1930 LSHIFT(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 1931 1932 ATW_WRITE(sc, ATW_BSSID0, 1933 LSHIFT(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 1934 LSHIFT(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 1935 LSHIFT(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 1936 LSHIFT(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 1937 1938 DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname, 1939 ether_sprintf(sc->sc_bssid))); 1940 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 1941 1942 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 1943} 1944 1945/* Tell the ADM8211 how many beacon intervals must pass without 1946 * receiving a beacon with the preferred BSSID & SSID set by 1947 * atw_write_bssid and atw_write_ssid before ATW_INTR_LINKOFF 1948 * raised. 1949 */ 1950static void 1951atw_write_bcn_thresh(sc) 1952 struct atw_softc *sc; 1953{ 1954 struct ieee80211com *ic = &sc->sc_ic; 1955 int lost_bcn_thresh; 1956 1957 /* Lose link after one second or 7 beacons, whichever comes 1958 * first, but do not lose link before 2 beacons are lost. 1959 * 1960 * In host AP mode, set the lost-beacon threshold to 0. 1961 */ 1962 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 1963 lost_bcn_thresh = 0; 1964 else 1965 lost_bcn_thresh = MAX(2, 1966 MIN(1000000/(IEEE80211_DUR_TU * ic->ic_bss->ni_intval), 7)); 1967 1968 /* XXX resets wake-up status bits */ 1969 ATW_WRITE(sc, ATW_WCSR, 1970 (ATW_READ(sc, ATW_WCSR) & ~ATW_WCSR_BLN_MASK) | 1971 (LSHIFT(lost_bcn_thresh, ATW_WCSR_BLN_MASK) & ATW_WCSR_BLN_MASK)); 1972 1973 DPRINTF(sc, ("%s: lost-beacon threshold %d -> %d\n", 1974 sc->sc_dev.dv_xname, sc->sc_lost_bcn_thresh, lost_bcn_thresh)); 1975 1976 sc->sc_lost_bcn_thresh = lost_bcn_thresh; 1977 1978 DPRINTF(sc, ("%s: atw_write_bcn_thresh reg[WCSR] = %08x\n", 1979 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_WCSR))); 1980} 1981 1982/* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 1983 * 16-bit word. 1984 */ 1985static void 1986atw_write_sram(sc, ofs, buf, buflen) 1987 struct atw_softc *sc; 1988 u_int ofs; 1989 u_int8_t *buf; 1990 u_int buflen; 1991{ 1992 u_int i; 1993 u_int8_t *ptr; 1994 1995 memcpy(&sc->sc_sram[ofs], buf, buflen); 1996 1997 if (ofs % 2 != 0) { 1998 ofs--; 1999 buflen++; 2000 } 2001 2002 if (buflen % 2 != 0) 2003 buflen++; 2004 2005 assert(buflen + ofs <= ATW_SRAM_SIZE); 2006 2007 ptr = &sc->sc_sram[ofs]; 2008 2009 for (i = 0; i < buflen; i += 2) { 2010 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 2011 LSHIFT((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 2012 DELAY(atw_writewep_delay); 2013 2014 ATW_WRITE(sc, ATW_WESK, 2015 LSHIFT((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 2016 DELAY(atw_writewep_delay); 2017 } 2018 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 2019 2020 if (sc->sc_if.if_flags & IFF_DEBUG) { 2021 int n_octets = 0; 2022 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 2023 sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl); 2024 for (i = 0; i < buflen; i++) { 2025 printf(" %02x", ptr[i]); 2026 if (++n_octets % 24 == 0) 2027 printf("\n"); 2028 } 2029 if (n_octets % 24 != 0) 2030 printf("\n"); 2031 } 2032} 2033 2034/* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2035static void 2036atw_write_wep(sc) 2037 struct atw_softc *sc; 2038{ 2039 struct ieee80211com *ic = &sc->sc_ic; 2040 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2041 u_int8_t buf[IEEE80211_WEP_NKID] 2042 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2043 u_int32_t reg; 2044 int i; 2045 2046 sc->sc_wepctl = 0; 2047 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2048 2049 if ((ic->ic_flags & IEEE80211_F_WEPON) == 0) 2050 return; 2051 2052 memset(&buf[0][0], 0, sizeof(buf)); 2053 2054 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2055 if (ic->ic_nw_keys[i].wk_len > 5) { 2056 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2057 } else if (ic->ic_nw_keys[i].wk_len != 0) { 2058 buf[i][1] = ATW_WEP_ENABLED; 2059 } else { 2060 buf[i][1] = 0; 2061 continue; 2062 } 2063 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2064 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2065 ic->ic_nw_keys[i].wk_len - 1); 2066 } 2067 2068 reg = ATW_READ(sc, ATW_MACTEST); 2069 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2070 reg &= ~ATW_MACTEST_KEYID_MASK; 2071 reg |= LSHIFT(ic->ic_wep_txkey, ATW_MACTEST_KEYID_MASK); 2072 ATW_WRITE(sc, ATW_MACTEST, reg); 2073 2074 /* RX bypass WEP if revision != 0x20. (I assume revision != 0x20 2075 * throughout.) 2076 */ 2077 sc->sc_wepctl = ATW_WEPCTL_WEPENABLE | ATW_WEPCTL_WEPRXBYP; 2078 if (sc->sc_if.if_flags & IFF_LINK2) 2079 sc->sc_wepctl &= ~ATW_WEPCTL_WEPRXBYP; 2080 2081 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2082 sizeof(buf)); 2083} 2084 2085const struct timeval atw_beacon_mininterval = {1, 0}; /* 1s */ 2086 2087static void 2088atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2089 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2090{ 2091 struct atw_softc *sc = (struct atw_softc*)ic->ic_softc; 2092 2093 switch (subtype) { 2094 case IEEE80211_FC0_SUBTYPE_PROBE_REQ: 2095 /* do nothing: hardware answers probe request */ 2096 break; 2097 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2098 case IEEE80211_FC0_SUBTYPE_BEACON: 2099 atw_recv_beacon(ic, m, ni, subtype, rssi, rstamp); 2100 break; 2101 default: 2102 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2103 break; 2104 } 2105 return; 2106} 2107 2108/* In ad hoc mode, atw_recv_beacon is responsible for the coalescence 2109 * of IBSSs with like SSID/channel but different BSSID. It joins the 2110 * oldest IBSS (i.e., with greatest TSF time), since that is the WECA 2111 * convention. Possibly the ADMtek chip does this for us; I will have 2112 * to test to find out. 2113 * 2114 * XXX we should add the duration field of the received beacon to 2115 * the TSF time it contains before comparing it with the ADM8211's 2116 * TSF. 2117 */ 2118static void 2119atw_recv_beacon(struct ieee80211com *ic, struct mbuf *m0, 2120 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2121{ 2122 struct atw_softc *sc; 2123 struct ieee80211_frame *wh; 2124 u_int64_t tsft, bcn_tsft; 2125 u_int32_t tsftl, tsfth; 2126 int do_print = 0; 2127 2128 sc = (struct atw_softc*)ic->ic_if.if_softc; 2129 2130 if (ic->ic_if.if_flags & IFF_DEBUG) 2131 do_print = (ic->ic_if.if_flags & IFF_LINK0) 2132 ? 1 : ratecheck(&sc->sc_last_beacon, &atw_beacon_mininterval); 2133 2134 wh = mtod(m0, struct ieee80211_frame *); 2135 2136 (*sc->sc_recv_mgmt)(ic, m0, ni, subtype, rssi, rstamp); 2137 2138 if (ic->ic_state != IEEE80211_S_RUN) { 2139 if (do_print) 2140 printf("%s: atw_recv_beacon: not running\n", 2141 sc->sc_dev.dv_xname); 2142 return; 2143 } 2144 2145 if ((ni = ieee80211_lookup_node(ic, wh->i_addr2, 2146 ic->ic_bss->ni_chan)) == NULL) { 2147 if (do_print) 2148 printf("%s: atw_recv_beacon: no node %s\n", 2149 sc->sc_dev.dv_xname, ether_sprintf(wh->i_addr2)); 2150 return; 2151 } 2152 2153 if (ieee80211_match_bss(ic, ni) != 0) { 2154 if (do_print) 2155 printf("%s: atw_recv_beacon: ssid mismatch %s\n", 2156 sc->sc_dev.dv_xname, ether_sprintf(wh->i_addr2)); 2157 return; 2158 } 2159 2160 if (memcmp(ni->ni_bssid, ic->ic_bss->ni_bssid, IEEE80211_ADDR_LEN) == 0) 2161 return; 2162 2163 if (do_print) 2164 printf("%s: atw_recv_beacon: bssid mismatch %s\n", 2165 sc->sc_dev.dv_xname, ether_sprintf(ni->ni_bssid)); 2166 2167 if (ic->ic_opmode != IEEE80211_M_IBSS) 2168 return; 2169 2170 /* If we read TSFTL right before rollover, we read a TSF timer 2171 * that is too high rather than too low. This prevents a spurious 2172 * synchronization down the line, however, our IBSS could suffer 2173 * from a creeping TSF.... 2174 */ 2175 tsftl = ATW_READ(sc, ATW_TSFTL); 2176 tsfth = ATW_READ(sc, ATW_TSFTH); 2177 2178 tsft = (u_int64_t)tsfth << 32 | tsftl; 2179 bcn_tsft = le64toh(*(u_int64_t*)ni->ni_tstamp); 2180 2181 if (do_print) 2182 printf("%s: my tsft %" PRIu64 " beacon tsft %" PRIu64 "\n", 2183 sc->sc_dev.dv_xname, tsft, bcn_tsft); 2184 2185 /* we are faster, let the other guy catch up */ 2186 if (bcn_tsft < tsft) 2187 return; 2188 2189 if (do_print) 2190 printf("%s: sync TSF with %s\n", sc->sc_dev.dv_xname, 2191 ether_sprintf(wh->i_addr2)); 2192 2193 ic->ic_flags &= ~IEEE80211_F_SIBSS; 2194 2195#if 0 2196 atw_tsf(sc); 2197#endif 2198 2199 /* negotiate rates with new IBSS */ 2200 ieee80211_fix_rate(ic, ni, IEEE80211_F_DOFRATE | 2201 IEEE80211_F_DONEGO | IEEE80211_F_DODEL); 2202 if (ni->ni_rates.rs_nrates == 0) { 2203 printf("%s: rates mismatch, BSSID %s\n", sc->sc_dev.dv_xname, 2204 ether_sprintf(ni->ni_bssid)); 2205 return; 2206 } 2207 2208 if (do_print) { 2209 printf("%s: sync BSSID %s -> ", sc->sc_dev.dv_xname, 2210 ether_sprintf(ic->ic_bss->ni_bssid)); 2211 printf("%s ", ether_sprintf(ni->ni_bssid)); 2212 printf("(from %s)\n", ether_sprintf(wh->i_addr2)); 2213 } 2214 2215 (*ic->ic_node_copy)(ic, ic->ic_bss, ni); 2216 2217 atw_write_bssid(sc); 2218 atw_write_bcn_thresh(sc); 2219 atw_start_beacon(sc, 1); 2220} 2221 2222/* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2223 * In ad hoc mode, the SSID is written to the beacons sent by the 2224 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2225 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2226 * indications. 2227 */ 2228static void 2229atw_write_ssid(sc) 2230 struct atw_softc *sc; 2231{ 2232 struct ieee80211com *ic = &sc->sc_ic; 2233 /* 34 bytes are reserved in ADM8211 SRAM for the SSID */ 2234 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2235 2236 memset(buf, 0, sizeof(buf)); 2237 buf[0] = ic->ic_bss->ni_esslen; 2238 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2239 2240 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, sizeof(buf)); 2241} 2242 2243/* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2244 * In ad hoc mode, the supported rates are written to beacons sent by the 2245 * ADM8211. 2246 */ 2247static void 2248atw_write_sup_rates(sc) 2249 struct atw_softc *sc; 2250{ 2251 struct ieee80211com *ic = &sc->sc_ic; 2252 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2253 * supported rates 2254 */ 2255 u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; 2256 2257 memset(buf, 0, sizeof(buf)); 2258 2259 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2260 2261 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2262 ic->ic_bss->ni_rates.rs_nrates); 2263 2264 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2265} 2266 2267/* Start/stop sending beacons. */ 2268void 2269atw_start_beacon(struct atw_softc *sc, int start) 2270{ 2271 struct ieee80211com *ic = &sc->sc_ic; 2272 u_int32_t len, capinfo, reg_bcnt, reg_cap1; 2273 2274 if (ATW_IS_ENABLED(sc) == 0) 2275 return; 2276 2277 len = capinfo = 0; 2278 2279 /* start beacons */ 2280 len = sizeof(struct ieee80211_frame) + 2281 8 /* timestamp */ + 2 /* beacon interval */ + 2282 2 /* capability info */ + 2283 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2284 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2285 3 /* DS parameters */ + 2286 IEEE80211_CRC_LEN; 2287 2288 reg_bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2289 2290 reg_cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2291 2292 ATW_WRITE(sc, ATW_BCNT, reg_bcnt); 2293 ATW_WRITE(sc, ATW_CAP1, reg_cap1); 2294 2295 if (!start) 2296 return; 2297 2298 /* TBD use ni_capinfo */ 2299 2300 if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2301 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2302 if (ic->ic_flags & IEEE80211_F_WEPON) 2303 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2304 2305 switch (ic->ic_opmode) { 2306 case IEEE80211_M_IBSS: 2307 len += 4; /* IBSS parameters */ 2308 capinfo |= IEEE80211_CAPINFO_IBSS; 2309 break; 2310 case IEEE80211_M_HOSTAP: 2311 /* XXX 6-byte minimum TIM */ 2312 len += atw_beacon_len_adjust; 2313 capinfo |= IEEE80211_CAPINFO_ESS; 2314 break; 2315 default: 2316 return; 2317 } 2318 2319 reg_bcnt |= LSHIFT(len, ATW_BCNT_BCNT_MASK); 2320 reg_cap1 |= LSHIFT(capinfo, ATW_CAP1_CAPI_MASK); 2321 2322 ATW_WRITE(sc, ATW_BCNT, reg_bcnt); 2323 ATW_WRITE(sc, ATW_CAP1, reg_cap1); 2324 2325 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2326 sc->sc_dev.dv_xname, reg_bcnt)); 2327 2328 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2329 sc->sc_dev.dv_xname, reg_cap1)); 2330} 2331 2332/* First beacon was sent at time 0 microseconds, current time is 2333 * tsfth << 32 | tsftl microseconds, and beacon interval is tbtt 2334 * microseconds. Return the expected time in microseconds for the 2335 * beacon after next. 2336 */ 2337static __inline u_int64_t 2338atw_predict_beacon(u_int64_t tsft, u_int32_t tbtt) 2339{ 2340 return tsft + (tbtt - tsft % tbtt); 2341} 2342 2343/* If we've created an IBSS, write the TSF time in the ADM8211 to 2344 * the ieee80211com. 2345 * 2346 * Predict the next target beacon transmission time (TBTT) and 2347 * write it to the ADM8211. 2348 */ 2349static void 2350atw_tsf(struct atw_softc *sc) 2351{ 2352#define TBTTOFS 20 /* TU */ 2353 2354 struct ieee80211com *ic = &sc->sc_ic; 2355 u_int64_t tsft, tbtt; 2356 2357 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2358 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2359 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2360 tsft = ATW_READ(sc, ATW_TSFTH); 2361 tsft <<= 32; 2362 tsft |= ATW_READ(sc, ATW_TSFTL); 2363 *(u_int64_t*)&ic->ic_bss->ni_tstamp[0] = htole64(tsft); 2364 } else 2365 tsft = le64toh(*(u_int64_t*)&ic->ic_bss->ni_tstamp[0]); 2366 2367 tbtt = atw_predict_beacon(tsft, 2368 ic->ic_bss->ni_intval * IEEE80211_DUR_TU); 2369 2370 /* skip one more beacon so that the TBTT cannot pass before 2371 * we've programmed it, and also so that we can subtract a 2372 * few TU so that we wake a little before TBTT. 2373 */ 2374 tbtt += ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2375 2376 /* wake up a little early */ 2377 tbtt -= TBTTOFS * IEEE80211_DUR_TU; 2378 2379 DPRINTF(sc, ("%s: tsft %" PRIu64 " tbtt %" PRIu64 "\n", 2380 sc->sc_dev.dv_xname, tsft, tbtt)); 2381 2382 ATW_WRITE(sc, ATW_TOFS1, 2383 LSHIFT(1, ATW_TOFS1_TSFTOFSR_MASK) | 2384 LSHIFT(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2385 LSHIFT( 2386 MASK_AND_RSHIFT((u_int32_t)tbtt, BITS(25, 10)), 2387 ATW_TOFS1_TBTTPRE_MASK)); 2388#undef TBTTOFS 2389} 2390 2391static void 2392atw_next_scan(void *arg) 2393{ 2394 struct atw_softc *sc = arg; 2395 struct ieee80211com *ic = &sc->sc_ic; 2396 struct ifnet *ifp = &ic->ic_if; 2397 int s; 2398 2399 /* don't call atw_start w/o network interrupts blocked */ 2400 s = splnet(); 2401 if (ic->ic_state == IEEE80211_S_SCAN) 2402 ieee80211_next_scan(ifp); 2403 splx(s); 2404} 2405 2406/* Synchronize the hardware state with the software state. */ 2407static int 2408atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2409{ 2410 struct ifnet *ifp = &ic->ic_if; 2411 struct atw_softc *sc = ifp->if_softc; 2412 enum ieee80211_state ostate; 2413 int error; 2414 2415 ostate = ic->ic_state; 2416 2417 if (nstate == IEEE80211_S_INIT) { 2418 callout_stop(&sc->sc_scan_ch); 2419 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2420 atw_start_beacon(sc, 0); 2421 return (*sc->sc_newstate)(ic, nstate, arg); 2422 } 2423 2424 if ((error = atw_tune(sc)) != 0) 2425 return error; 2426 2427 switch (nstate) { 2428 case IEEE80211_S_ASSOC: 2429 break; 2430 case IEEE80211_S_INIT: 2431 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__); 2432 break; 2433 case IEEE80211_S_SCAN: 2434 memset(sc->sc_bssid, 0, IEEE80211_ADDR_LEN); 2435 atw_write_bssid(sc); 2436 2437 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2438 atw_next_scan, sc); 2439 2440 break; 2441 case IEEE80211_S_RUN: 2442 if (ic->ic_opmode == IEEE80211_M_STA) 2443 break; 2444 /*FALLTHROUGH*/ 2445 case IEEE80211_S_AUTH: 2446 atw_write_bssid(sc); 2447 atw_write_bcn_thresh(sc); 2448 atw_write_ssid(sc); 2449 atw_write_sup_rates(sc); 2450 2451 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2452 ic->ic_opmode == IEEE80211_M_MONITOR) 2453 break; 2454 2455 /* set listen interval 2456 * XXX do software units agree w/ hardware? 2457 */ 2458 ATW_WRITE(sc, ATW_BPLI, 2459 LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2460 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, 2461 ATW_BPLI_LI_MASK)); 2462 2463 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", 2464 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_BPLI))); 2465 2466 atw_tsf(sc); 2467 break; 2468 } 2469 2470 if (nstate != IEEE80211_S_SCAN) 2471 callout_stop(&sc->sc_scan_ch); 2472 2473 if (nstate == IEEE80211_S_RUN && 2474 (ic->ic_opmode == IEEE80211_M_HOSTAP || 2475 ic->ic_opmode == IEEE80211_M_IBSS)) 2476 atw_start_beacon(sc, 1); 2477 else 2478 atw_start_beacon(sc, 0); 2479 2480 return (*sc->sc_newstate)(ic, nstate, arg); 2481} 2482 2483/* 2484 * atw_add_rxbuf: 2485 * 2486 * Add a receive buffer to the indicated descriptor. 2487 */ 2488int 2489atw_add_rxbuf(sc, idx) 2490 struct atw_softc *sc; 2491 int idx; 2492{ 2493 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2494 struct mbuf *m; 2495 int error; 2496 2497 MGETHDR(m, M_DONTWAIT, MT_DATA); 2498 if (m == NULL) 2499 return (ENOBUFS); 2500 2501 MCLGET(m, M_DONTWAIT); 2502 if ((m->m_flags & M_EXT) == 0) { 2503 m_freem(m); 2504 return (ENOBUFS); 2505 } 2506 2507 if (rxs->rxs_mbuf != NULL) 2508 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2509 2510 rxs->rxs_mbuf = m; 2511 2512 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2513 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2514 BUS_DMA_READ|BUS_DMA_NOWAIT); 2515 if (error) { 2516 printf("%s: can't load rx DMA map %d, error = %d\n", 2517 sc->sc_dev.dv_xname, idx, error); 2518 panic("atw_add_rxbuf"); /* XXX */ 2519 } 2520 2521 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2522 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2523 2524 ATW_INIT_RXDESC(sc, idx); 2525 2526 return (0); 2527} 2528 2529/* 2530 * atw_stop: [ ifnet interface function ] 2531 * 2532 * Stop transmission on the interface. 2533 */ 2534void 2535atw_stop(ifp, disable) 2536 struct ifnet *ifp; 2537 int disable; 2538{ 2539 struct atw_softc *sc = ifp->if_softc; 2540 struct ieee80211com *ic = &sc->sc_ic; 2541 struct atw_txsoft *txs; 2542 2543 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2544 2545 /* Disable interrupts. */ 2546 ATW_WRITE(sc, ATW_IER, 0); 2547 2548 /* Stop the transmit and receive processes. */ 2549 sc->sc_opmode = 0; 2550 ATW_WRITE(sc, ATW_NAR, 0); 2551 ATW_WRITE(sc, ATW_TDBD, 0); 2552 ATW_WRITE(sc, ATW_TDBP, 0); 2553 ATW_WRITE(sc, ATW_RDB, 0); 2554 2555 /* 2556 * Release any queued transmit buffers. 2557 */ 2558 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2559 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2560 if (txs->txs_mbuf != NULL) { 2561 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2562 m_freem(txs->txs_mbuf); 2563 txs->txs_mbuf = NULL; 2564 } 2565 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2566 } 2567 2568 if (disable) { 2569 atw_rxdrain(sc); 2570 atw_disable(sc); 2571 } 2572 2573 /* 2574 * Mark the interface down and cancel the watchdog timer. 2575 */ 2576 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2577 ifp->if_timer = 0; 2578 2579 /* XXX */ 2580 atw_reset(sc); 2581} 2582 2583/* 2584 * atw_rxdrain: 2585 * 2586 * Drain the receive queue. 2587 */ 2588void 2589atw_rxdrain(sc) 2590 struct atw_softc *sc; 2591{ 2592 struct atw_rxsoft *rxs; 2593 int i; 2594 2595 for (i = 0; i < ATW_NRXDESC; i++) { 2596 rxs = &sc->sc_rxsoft[i]; 2597 if (rxs->rxs_mbuf == NULL) 2598 continue; 2599 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2600 m_freem(rxs->rxs_mbuf); 2601 rxs->rxs_mbuf = NULL; 2602 } 2603} 2604 2605/* 2606 * atw_detach: 2607 * 2608 * Detach an ADM8211 interface. 2609 */ 2610int 2611atw_detach(sc) 2612 struct atw_softc *sc; 2613{ 2614 struct ifnet *ifp = &sc->sc_ic.ic_if; 2615 struct atw_rxsoft *rxs; 2616 struct atw_txsoft *txs; 2617 int i; 2618 2619 /* 2620 * Succeed now if there isn't any work to do. 2621 */ 2622 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2623 return (0); 2624 2625 ieee80211_ifdetach(ifp); 2626 if_detach(ifp); 2627 2628 for (i = 0; i < ATW_NRXDESC; i++) { 2629 rxs = &sc->sc_rxsoft[i]; 2630 if (rxs->rxs_mbuf != NULL) { 2631 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2632 m_freem(rxs->rxs_mbuf); 2633 rxs->rxs_mbuf = NULL; 2634 } 2635 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2636 } 2637 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2638 txs = &sc->sc_txsoft[i]; 2639 if (txs->txs_mbuf != NULL) { 2640 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2641 m_freem(txs->txs_mbuf); 2642 txs->txs_mbuf = NULL; 2643 } 2644 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2645 } 2646 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2647 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2648 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2649 sizeof(struct atw_control_data)); 2650 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2651 2652 shutdownhook_disestablish(sc->sc_sdhook); 2653 powerhook_disestablish(sc->sc_powerhook); 2654 2655 if (sc->sc_srom) 2656 free(sc->sc_srom, M_DEVBUF); 2657 2658 return (0); 2659} 2660 2661/* atw_shutdown: make sure the interface is stopped at reboot time. */ 2662void 2663atw_shutdown(arg) 2664 void *arg; 2665{ 2666 struct atw_softc *sc = arg; 2667 2668 atw_stop(&sc->sc_ic.ic_if, 1); 2669} 2670 2671int 2672atw_intr(arg) 2673 void *arg; 2674{ 2675 struct atw_softc *sc = arg; 2676 struct ifnet *ifp = &sc->sc_ic.ic_if; 2677 u_int32_t status, rxstatus, txstatus, linkstatus; 2678 int handled = 0, txthresh; 2679 2680#ifdef DEBUG 2681 if (ATW_IS_ENABLED(sc) == 0) 2682 panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname); 2683#endif 2684 2685 /* 2686 * If the interface isn't running, the interrupt couldn't 2687 * possibly have come from us. 2688 */ 2689 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2690 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 2691 return (0); 2692 2693 for (;;) { 2694 status = ATW_READ(sc, ATW_STSR); 2695 2696 if (status) 2697 ATW_WRITE(sc, ATW_STSR, status); 2698 2699 if (sc->sc_intr_ack != NULL) 2700 (*sc->sc_intr_ack)(sc); 2701 2702#ifdef ATW_DEBUG 2703#define PRINTINTR(flag) do { \ 2704 if ((status & flag) != 0) { \ 2705 printf("%s" #flag, delim); \ 2706 delim = ","; \ 2707 } \ 2708} while (0) 2709 2710 if (atw_debug > 1 && status) { 2711 const char *delim = "<"; 2712 2713 printf("%s: reg[STSR] = %x", 2714 sc->sc_dev.dv_xname, status); 2715 2716 PRINTINTR(ATW_INTR_FBE); 2717 PRINTINTR(ATW_INTR_LINKOFF); 2718 PRINTINTR(ATW_INTR_LINKON); 2719 PRINTINTR(ATW_INTR_RCI); 2720 PRINTINTR(ATW_INTR_RDU); 2721 PRINTINTR(ATW_INTR_REIS); 2722 PRINTINTR(ATW_INTR_RPS); 2723 PRINTINTR(ATW_INTR_TCI); 2724 PRINTINTR(ATW_INTR_TDU); 2725 PRINTINTR(ATW_INTR_TLT); 2726 PRINTINTR(ATW_INTR_TPS); 2727 PRINTINTR(ATW_INTR_TRT); 2728 PRINTINTR(ATW_INTR_TUF); 2729 PRINTINTR(ATW_INTR_BCNTC); 2730 PRINTINTR(ATW_INTR_ATIME); 2731 PRINTINTR(ATW_INTR_TBTT); 2732 PRINTINTR(ATW_INTR_TSCZ); 2733 PRINTINTR(ATW_INTR_TSFTF); 2734 printf(">\n"); 2735 } 2736#undef PRINTINTR 2737#endif /* ATW_DEBUG */ 2738 2739 if ((status & sc->sc_inten) == 0) 2740 break; 2741 2742 handled = 1; 2743 2744 rxstatus = status & sc->sc_rxint_mask; 2745 txstatus = status & sc->sc_txint_mask; 2746 linkstatus = status & sc->sc_linkint_mask; 2747 2748 if (linkstatus) { 2749 atw_linkintr(sc, linkstatus); 2750 } 2751 2752 if (rxstatus) { 2753 /* Grab any new packets. */ 2754 atw_rxintr(sc); 2755 2756 if (rxstatus & ATW_INTR_RDU) { 2757 printf("%s: receive ring overrun\n", 2758 sc->sc_dev.dv_xname); 2759 /* Get the receive process going again. */ 2760 ATW_WRITE(sc, ATW_RDR, 0x1); 2761 break; 2762 } 2763 } 2764 2765 if (txstatus) { 2766 /* Sweep up transmit descriptors. */ 2767 atw_txintr(sc); 2768 2769 if (txstatus & ATW_INTR_TLT) 2770 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2771 sc->sc_dev.dv_xname)); 2772 2773 if (txstatus & ATW_INTR_TRT) 2774 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2775 sc->sc_dev.dv_xname)); 2776 2777 /* If Tx under-run, increase our transmit threshold 2778 * if another is available. 2779 */ 2780 txthresh = sc->sc_txthresh + 1; 2781 if ((txstatus & ATW_INTR_TUF) && 2782 sc->sc_txth[txthresh].txth_name != NULL) { 2783 /* Idle the transmit process. */ 2784 atw_idle(sc, ATW_NAR_ST); 2785 2786 sc->sc_txthresh = txthresh; 2787 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2788 sc->sc_opmode |= 2789 sc->sc_txth[txthresh].txth_opmode; 2790 printf("%s: transmit underrun; new " 2791 "threshold: %s\n", sc->sc_dev.dv_xname, 2792 sc->sc_txth[txthresh].txth_name); 2793 2794 /* Set the new threshold and restart 2795 * the transmit process. 2796 */ 2797 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2798 /* XXX Log every Nth underrun from 2799 * XXX now on? 2800 */ 2801 } 2802 } 2803 2804 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2805 if (status & ATW_INTR_TPS) 2806 printf("%s: transmit process stopped\n", 2807 sc->sc_dev.dv_xname); 2808 if (status & ATW_INTR_RPS) 2809 printf("%s: receive process stopped\n", 2810 sc->sc_dev.dv_xname); 2811 (void)atw_init(ifp); 2812 break; 2813 } 2814 2815 if (status & ATW_INTR_FBE) { 2816 printf("%s: fatal bus error\n", sc->sc_dev.dv_xname); 2817 (void)atw_init(ifp); 2818 break; 2819 } 2820 2821 /* 2822 * Not handled: 2823 * 2824 * Transmit buffer unavailable -- normal 2825 * condition, nothing to do, really. 2826 * 2827 * Early receive interrupt -- not available on 2828 * all chips, we just use RI. We also only 2829 * use single-segment receive DMA, so this 2830 * is mostly useless. 2831 * 2832 * TBD others 2833 */ 2834 } 2835 2836 /* Try to get more packets going. */ 2837 atw_start(ifp); 2838 2839 return (handled); 2840} 2841 2842/* 2843 * atw_idle: 2844 * 2845 * Cause the transmit and/or receive processes to go idle. 2846 * 2847 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2848 * process in STSR if I clear SR or ST after the process has already 2849 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2850 * do not seem to be too reliable. Perhaps I have the sense of the 2851 * Rx bits switched with the Tx bits? 2852 */ 2853void 2854atw_idle(sc, bits) 2855 struct atw_softc *sc; 2856 u_int32_t bits; 2857{ 2858 u_int32_t ackmask = 0, opmode, stsr, test0; 2859 int i, s; 2860 2861 /* without this, somehow we run concurrently w/ interrupt handler */ 2862 s = splnet(); 2863 2864 opmode = sc->sc_opmode & ~bits; 2865 2866 if (bits & ATW_NAR_SR) 2867 ackmask |= ATW_INTR_RPS; 2868 2869 if (bits & ATW_NAR_ST) { 2870 ackmask |= ATW_INTR_TPS; 2871 /* set ATW_NAR_HF to flush TX FIFO. */ 2872 opmode |= ATW_NAR_HF; 2873 } 2874 2875 ATW_WRITE(sc, ATW_NAR, opmode); 2876 2877 for (i = 0; i < 1000; i++) { 2878 stsr = ATW_READ(sc, ATW_STSR); 2879 if ((stsr & ackmask) == ackmask) 2880 break; 2881 DELAY(10); 2882 } 2883 2884 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 2885 2886 if ((stsr & ackmask) == ackmask) 2887 goto out; 2888 2889 test0 = ATW_READ(sc, ATW_TEST0); 2890 2891 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 2892 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 2893 printf("%s: transmit process not idle [%s]\n", 2894 sc->sc_dev.dv_xname, 2895 atw_tx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_TS_MASK)]); 2896 printf("%s: bits %08x test0 %08x stsr %08x\n", 2897 sc->sc_dev.dv_xname, bits, test0, stsr); 2898 } 2899 2900 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 2901 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 2902 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 2903 sc->sc_dev.dv_xname, 2904 atw_rx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_RS_MASK)])); 2905 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 2906 sc->sc_dev.dv_xname, bits, test0, stsr)); 2907 } 2908out: 2909 splx(s); 2910 return; 2911} 2912 2913/* 2914 * atw_linkintr: 2915 * 2916 * Helper; handle link-status interrupts. 2917 */ 2918void 2919atw_linkintr(sc, linkstatus) 2920 struct atw_softc *sc; 2921 u_int32_t linkstatus; 2922{ 2923 struct ieee80211com *ic = &sc->sc_ic; 2924 2925 if (ic->ic_state != IEEE80211_S_RUN) 2926 return; 2927 2928 if (linkstatus & ATW_INTR_LINKON) { 2929 DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname)); 2930 sc->sc_rescan_timer = 0; 2931 } else if (linkstatus & ATW_INTR_LINKOFF) { 2932 DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname)); 2933 switch (ic->ic_opmode) { 2934 case IEEE80211_M_HOSTAP: 2935 return; 2936 case IEEE80211_M_IBSS: 2937 if (ic->ic_flags & IEEE80211_F_SIBSS) 2938 return; 2939 /*FALLTHROUGH*/ 2940 case IEEE80211_M_STA: 2941 sc->sc_rescan_timer = 3; 2942 ic->ic_if.if_timer = 1; 2943 break; 2944 default: 2945 break; 2946 } 2947 } 2948} 2949 2950/* 2951 * atw_rxintr: 2952 * 2953 * Helper; handle receive interrupts. 2954 */ 2955void 2956atw_rxintr(sc) 2957 struct atw_softc *sc; 2958{ 2959 static int rate_tbl[] = {2, 4, 11, 22, 44}; 2960 struct ieee80211com *ic = &sc->sc_ic; 2961 struct ieee80211_node *ni; 2962 struct ieee80211_frame *wh; 2963 struct ifnet *ifp = &ic->ic_if; 2964 struct atw_rxsoft *rxs; 2965 struct mbuf *m; 2966 u_int32_t rxstat; 2967 int i, len, rate, rate0, rssi; 2968 2969 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 2970 rxs = &sc->sc_rxsoft[i]; 2971 2972 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2973 2974 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 2975 rssi = le32toh(sc->sc_rxdescs[i].ar_rssi); 2976 rate0 = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_RXDR_MASK); 2977 2978 if (rxstat & ATW_RXSTAT_OWN) 2979 break; /* We have processed all receive buffers. */ 2980 2981 DPRINTF3(sc, 2982 ("%s: rx stat %08x rssi %08x buf1 %08x buf2 %08x\n", 2983 sc->sc_dev.dv_xname, 2984 sc->sc_rxdescs[i].ar_stat, 2985 sc->sc_rxdescs[i].ar_rssi, 2986 sc->sc_rxdescs[i].ar_buf1, 2987 sc->sc_rxdescs[i].ar_buf2)); 2988 2989 /* 2990 * Make sure the packet fit in one buffer. This should 2991 * always be the case. 2992 */ 2993 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 2994 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 2995 printf("%s: incoming packet spilled, resetting\n", 2996 sc->sc_dev.dv_xname); 2997 (void)atw_init(ifp); 2998 return; 2999 } 3000 3001 /* 3002 * If an error occurred, update stats, clear the status 3003 * word, and leave the packet buffer in place. It will 3004 * simply be reused the next time the ring comes around. 3005 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 3006 * error. 3007 */ 3008 3009 if ((rxstat & ATW_RXSTAT_ES) != 0 && 3010 ((sc->sc_ic.ic_ec.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 3011 (rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_SFDE | 3012 ATW_RXSTAT_SIGE | ATW_RXSTAT_CRC16E | 3013 ATW_RXSTAT_RXTOE | ATW_RXSTAT_CRC32E | 3014 ATW_RXSTAT_ICVE)) != 0)) { 3015#define PRINTERR(bit, str) \ 3016 if (rxstat & (bit)) \ 3017 printf("%s: receive error: %s\n", \ 3018 sc->sc_dev.dv_xname, str) 3019 ifp->if_ierrors++; 3020 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 3021 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 3022 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 3023 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 3024 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 3025 PRINTERR(ATW_RXSTAT_CRC32E, "FCS error"); 3026 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 3027#undef PRINTERR 3028 ATW_INIT_RXDESC(sc, i); 3029 continue; 3030 } 3031 3032 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3033 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3034 3035 /* 3036 * No errors; receive the packet. Note the ADM8211 3037 * includes the CRC in promiscuous mode. 3038 */ 3039 len = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_FL_MASK); 3040 3041 /* 3042 * Allocate a new mbuf cluster. If that fails, we are 3043 * out of memory, and must drop the packet and recycle 3044 * the buffer that's already attached to this descriptor. 3045 */ 3046 m = rxs->rxs_mbuf; 3047 if (atw_add_rxbuf(sc, i) != 0) { 3048 ifp->if_ierrors++; 3049 ATW_INIT_RXDESC(sc, i); 3050 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3051 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3052 continue; 3053 } 3054 3055 ifp->if_ipackets++; 3056 if (sc->sc_opmode & ATW_NAR_PR) 3057 m->m_flags |= M_HASFCS; 3058 m->m_pkthdr.rcvif = ifp; 3059 m->m_pkthdr.len = m->m_len = len; 3060 3061 if (rate0 >= sizeof(rate_tbl) / sizeof(rate_tbl[0])) 3062 rate = 0; 3063 else 3064 rate = rate_tbl[rate0]; 3065 3066 #if NBPFILTER > 0 3067 /* Pass this up to any BPF listeners. */ 3068 if (sc->sc_radiobpf != NULL) { 3069 struct mbuf mb; 3070 3071 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3072 3073 tap->ar_rate = rate; 3074 tap->ar_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3075 tap->ar_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3076 3077 /* TBD verify units are dB */ 3078 tap->ar_antsignal = rssi; 3079 /* TBD tap->ar_flags */ 3080 3081 M_COPY_PKTHDR(&mb, m); 3082 mb.m_data = (caddr_t)tap; 3083 mb.m_len = tap->ar_ihdr.it_len; 3084 mb.m_next = m; 3085 mb.m_pkthdr.len += mb.m_len; 3086 bpf_mtap(sc->sc_radiobpf, &mb); 3087 } 3088 #endif /* NPBFILTER > 0 */ 3089 3090 wh = mtod(m, struct ieee80211_frame *); 3091 ni = ieee80211_find_rxnode(ic, wh); 3092 ieee80211_input(ifp, m, ni, rssi, 0); 3093 /* 3094 * The frame may have caused the node to be marked for 3095 * reclamation (e.g. in response to a DEAUTH message) 3096 * so use free_node here instead of unref_node. 3097 */ 3098 if (ni == ic->ic_bss) 3099 ieee80211_unref_node(&ni); 3100 else 3101 ieee80211_free_node(ic, ni); 3102 } 3103 3104 /* Update the receive pointer. */ 3105 sc->sc_rxptr = i; 3106} 3107 3108/* 3109 * atw_txintr: 3110 * 3111 * Helper; handle transmit interrupts. 3112 */ 3113void 3114atw_txintr(sc) 3115 struct atw_softc *sc; 3116{ 3117#define TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | ATW_TXSTAT_TRT | \ 3118 ATW_TXSTAT_TRO | ATW_TXSTAT_SOFBR) 3119#define TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO\33ATW_TXSTAT_TUF" \ 3120 "\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT" 3121 3122 static char txstat_buf[sizeof("ffffffff<>" TXSTAT_FMT)]; 3123 struct ifnet *ifp = &sc->sc_ic.ic_if; 3124 struct atw_txsoft *txs; 3125 u_int32_t txstat; 3126 3127 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3128 sc->sc_dev.dv_xname, sc->sc_flags)); 3129 3130 ifp->if_flags &= ~IFF_OACTIVE; 3131 3132 /* 3133 * Go through our Tx list and free mbufs for those 3134 * frames that have been transmitted. 3135 */ 3136 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3137 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 3138 txs->txs_ndescs, 3139 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3140 3141#ifdef ATW_DEBUG 3142 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3143 int i; 3144 printf(" txsoft %p transmit chain:\n", txs); 3145 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3146 printf(" descriptor %d:\n", i); 3147 printf(" at_status: 0x%08x\n", 3148 le32toh(sc->sc_txdescs[i].at_stat)); 3149 printf(" at_flags: 0x%08x\n", 3150 le32toh(sc->sc_txdescs[i].at_flags)); 3151 printf(" at_buf1: 0x%08x\n", 3152 le32toh(sc->sc_txdescs[i].at_buf1)); 3153 printf(" at_buf2: 0x%08x\n", 3154 le32toh(sc->sc_txdescs[i].at_buf2)); 3155 if (i == txs->txs_lastdesc) 3156 break; 3157 } 3158 } 3159#endif 3160 3161 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3162 if (txstat & ATW_TXSTAT_OWN) 3163 break; 3164 3165 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3166 3167 sc->sc_txfree += txs->txs_ndescs; 3168 3169 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3170 0, txs->txs_dmamap->dm_mapsize, 3171 BUS_DMASYNC_POSTWRITE); 3172 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3173 m_freem(txs->txs_mbuf); 3174 txs->txs_mbuf = NULL; 3175 3176 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3177 3178 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3179 (txstat & TXSTAT_ERRMASK) != 0) { 3180 bitmask_snprintf(txstat & TXSTAT_ERRMASK, TXSTAT_FMT, 3181 txstat_buf, sizeof(txstat_buf)); 3182 printf("%s: txstat %s %d\n", sc->sc_dev.dv_xname, 3183 txstat_buf, 3184 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK)); 3185 } 3186 3187 /* 3188 * Check for errors and collisions. 3189 */ 3190 if (txstat & ATW_TXSTAT_TUF) 3191 sc->sc_stats.ts_tx_tuf++; 3192 if (txstat & ATW_TXSTAT_TLT) 3193 sc->sc_stats.ts_tx_tlt++; 3194 if (txstat & ATW_TXSTAT_TRT) 3195 sc->sc_stats.ts_tx_trt++; 3196 if (txstat & ATW_TXSTAT_TRO) 3197 sc->sc_stats.ts_tx_tro++; 3198 if (txstat & ATW_TXSTAT_SOFBR) { 3199 sc->sc_stats.ts_tx_sofbr++; 3200 } 3201 3202 if ((txstat & ATW_TXSTAT_ES) == 0) 3203 ifp->if_collisions += 3204 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK); 3205 else 3206 ifp->if_oerrors++; 3207 3208 ifp->if_opackets++; 3209 } 3210 3211 /* 3212 * If there are no more pending transmissions, cancel the watchdog 3213 * timer. 3214 */ 3215 if (txs == NULL) 3216 sc->sc_tx_timer = 0; 3217#undef TXSTAT_ERRMASK 3218#undef TXSTAT_FMT 3219} 3220 3221/* 3222 * atw_watchdog: [ifnet interface function] 3223 * 3224 * Watchdog timer handler. 3225 */ 3226void 3227atw_watchdog(ifp) 3228 struct ifnet *ifp; 3229{ 3230 struct atw_softc *sc = ifp->if_softc; 3231 struct ieee80211com *ic = &sc->sc_ic; 3232 3233 ifp->if_timer = 0; 3234 if (ATW_IS_ENABLED(sc) == 0) 3235 return; 3236 3237 if (sc->sc_rescan_timer) { 3238 if (--sc->sc_rescan_timer == 0) 3239 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3240 } 3241 if (sc->sc_tx_timer) { 3242 if (--sc->sc_tx_timer == 0 && 3243 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3244 printf("%s: transmit timeout\n", ifp->if_xname); 3245 ifp->if_oerrors++; 3246 (void)atw_init(ifp); 3247 atw_start(ifp); 3248 } 3249 } 3250 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3251 ifp->if_timer = 1; 3252 ieee80211_watchdog(ifp); 3253} 3254 3255/* Compute the 802.11 Duration field and the PLCP Length fields for 3256 * a len-byte frame (HEADER + PAYLOAD + FCS) sent at rate * 500Kbps. 3257 * Write the fields to the ADM8211 Tx header, frm. 3258 * 3259 * TBD use the fragmentation threshold to find the right duration for 3260 * the first & last fragments. 3261 * 3262 * TBD make certain of the duration fields applied by the ADM8211 to each 3263 * fragment. I think that the ADM8211 knows how to subtract the CTS 3264 * duration when ATW_HDRCTL_RTSCTS is clear; that is why I add it regardless. 3265 * I also think that the ADM8211 does *some* arithmetic for us, because 3266 * otherwise I think we would have to set a first duration for CTS/first 3267 * fragment, a second duration for fragments between the first and the 3268 * last, and a third duration for the last fragment. 3269 * 3270 * TBD make certain that duration fields reflect addition of FCS/WEP 3271 * and correct duration arithmetic as necessary. 3272 */ 3273static void 3274atw_frame_setdurs(struct atw_softc *sc, struct atw_frame *frm, int rate, 3275 int len) 3276{ 3277 int remainder; 3278 3279 /* deal also with encrypted fragments */ 3280 if (frm->atw_hdrctl & htole16(ATW_HDRCTL_WEP)) { 3281 DPRINTF2(sc, ("%s: atw_frame_setdurs len += 8\n", 3282 sc->sc_dev.dv_xname)); 3283 len += IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + 3284 IEEE80211_WEP_CRCLEN; 3285 } 3286 3287 /* 802.11 Duration Field for CTS/Data/ACK sequence minus FCS & WEP 3288 * duration (XXX added by MAC?). 3289 */ 3290 frm->atw_head_dur = (16 * (len - IEEE80211_CRC_LEN)) / rate; 3291 remainder = (16 * (len - IEEE80211_CRC_LEN)) % rate; 3292 3293 if (rate <= 4) 3294 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */ 3295 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3296 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3297 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3298 IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK; 3299 else 3300 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */ 3301 frm->atw_head_dur += 3 * (IEEE80211_DUR_DS_SIFS + 3302 IEEE80211_DUR_DS_SHORT_PREAMBLE + 3303 IEEE80211_DUR_DS_FAST_PLCPHDR) + 3304 IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK; 3305 3306 /* lengthen duration if long preamble */ 3307 if ((sc->sc_flags & ATWF_SHORT_PREAMBLE) == 0) 3308 frm->atw_head_dur += 3309 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE - 3310 IEEE80211_DUR_DS_SHORT_PREAMBLE) + 3311 3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR - 3312 IEEE80211_DUR_DS_FAST_PLCPHDR); 3313 3314 if (remainder != 0) 3315 frm->atw_head_dur++; 3316 3317 if ((atw_voodoo & VOODOO_DUR_2_4_SPECIALCASE) && 3318 (rate == 2 || rate == 4)) { 3319 /* derived from Linux: how could this be right? */ 3320 frm->atw_head_plcplen = frm->atw_head_dur; 3321 } else { 3322 frm->atw_head_plcplen = (16 * len) / rate; 3323 remainder = (80 * len) % (rate * 5); 3324 3325 if (remainder != 0) { 3326 frm->atw_head_plcplen++; 3327 3328 /* XXX magic */ 3329 if ((atw_voodoo & VOODOO_DUR_11_ROUNDING) && 3330 rate == 22 && remainder <= 30) 3331 frm->atw_head_plcplen |= 0x8000; 3332 } 3333 } 3334 frm->atw_tail_plcplen = frm->atw_head_plcplen = 3335 htole16(frm->atw_head_plcplen); 3336 frm->atw_tail_dur = frm->atw_head_dur = htole16(frm->atw_head_dur); 3337} 3338 3339#ifdef ATW_DEBUG 3340static void 3341atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3342{ 3343 struct atw_softc *sc = ifp->if_softc; 3344 struct mbuf *m; 3345 int i, noctets = 0; 3346 3347 printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname, 3348 m0->m_pkthdr.len); 3349 3350 for (m = m0; m; m = m->m_next) { 3351 if (m->m_len == 0) 3352 continue; 3353 for (i = 0; i < m->m_len; i++) { 3354 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3355 if (++noctets % 24 == 0) 3356 printf("\n"); 3357 } 3358 } 3359 printf("%s%s: %d bytes emitted\n", 3360 (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets); 3361} 3362#endif /* ATW_DEBUG */ 3363 3364/* 3365 * atw_start: [ifnet interface function] 3366 * 3367 * Start packet transmission on the interface. 3368 */ 3369void 3370atw_start(ifp) 3371 struct ifnet *ifp; 3372{ 3373 struct atw_softc *sc = ifp->if_softc; 3374 struct ieee80211com *ic = &sc->sc_ic; 3375 struct ieee80211_node *ni; 3376 struct ieee80211_frame *wh; 3377 struct atw_frame *hh; 3378 struct mbuf *m0, *m; 3379 struct atw_txsoft *txs, *last_txs; 3380 struct atw_txdesc *txd; 3381 int do_encrypt, rate; 3382 bus_dmamap_t dmamap; 3383 int ctl, error, firsttx, nexttx, lasttx = -1, first, ofree, seg; 3384 3385 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3386 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 3387 3388 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3389 return; 3390 3391#if 0 /* TBD ??? */ 3392 if ((sc->sc_flags & ATWF_LINK_UP) == 0 && ifp->if_snd.ifq_len < 10) 3393 return; 3394#endif 3395 3396 /* 3397 * Remember the previous number of free descriptors and 3398 * the first descriptor we'll use. 3399 */ 3400 ofree = sc->sc_txfree; 3401 firsttx = sc->sc_txnext; 3402 3403 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3404 sc->sc_dev.dv_xname, ofree, firsttx)); 3405 3406 /* 3407 * Loop through the send queue, setting up transmit descriptors 3408 * until we drain the queue, or use up all available transmit 3409 * descriptors. 3410 */ 3411 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3412 sc->sc_txfree != 0) { 3413 3414 do_encrypt = 0; 3415 /* 3416 * Grab a packet off the management queue, if it 3417 * is not empty. Otherwise, from the data queue. 3418 */ 3419 IF_DEQUEUE(&ic->ic_mgtq, m0); 3420 if (m0 != NULL) { 3421 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 3422 m0->m_pkthdr.rcvif = NULL; 3423 } else { 3424 IFQ_DEQUEUE(&ifp->if_snd, m0); 3425 if (m0 == NULL) 3426 break; 3427#if NBPFILTER > 0 3428 if (ifp->if_bpf != NULL) 3429 bpf_mtap(ifp->if_bpf, m0); 3430#endif /* NBPFILTER > 0 */ 3431 if ((m0 = ieee80211_encap(ifp, m0, &ni)) == NULL) { 3432 ifp->if_oerrors++; 3433 break; 3434 } 3435 } 3436 3437 rate = MAX(ieee80211_get_rate(ic), 2); 3438 3439#if NBPFILTER > 0 3440 /* 3441 * Pass the packet to any BPF listeners. 3442 */ 3443 if (ic->ic_rawbpf != NULL) 3444 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3445 3446 if (sc->sc_radiobpf != NULL) { 3447 struct mbuf mb; 3448 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3449 3450 tap->at_rate = rate; 3451 tap->at_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3452 tap->at_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3453 3454 /* TBD tap->at_flags */ 3455 3456 M_COPY_PKTHDR(&mb, m0); 3457 mb.m_data = (caddr_t)tap; 3458 mb.m_len = tap->at_ihdr.it_len; 3459 mb.m_next = m0; 3460 mb.m_pkthdr.len += mb.m_len; 3461 bpf_mtap(sc->sc_radiobpf, &mb); 3462 } 3463#endif /* NBPFILTER > 0 */ 3464 3465 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3466 3467 if (ni != NULL && ni != ic->ic_bss) 3468 ieee80211_free_node(ic, ni); 3469 3470 if (m0 == NULL) { 3471 ifp->if_oerrors++; 3472 break; 3473 } 3474 3475 /* just to make sure. */ 3476 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3477 3478 if (m0 == NULL) { 3479 ifp->if_oerrors++; 3480 break; 3481 } 3482 3483 hh = mtod(m0, struct atw_frame *); 3484 wh = &hh->atw_ihdr; 3485 3486 do_encrypt = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 3487 3488 /* Copy everything we need from the 802.11 header: 3489 * Frame Control; address 1, address 3, or addresses 3490 * 3 and 4. NIC fills in BSSID, SA. 3491 */ 3492 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3493 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3494 panic("%s: illegal WDS frame", 3495 sc->sc_dev.dv_xname); 3496 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3497 } else 3498 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3499 3500 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3501 3502 /* initialize remaining Tx parameters */ 3503 memset(&hh->u, 0, sizeof(hh->u)); 3504 3505 hh->atw_rate = rate * 5; 3506 /* XXX this could be incorrect if M_FCS. _encap should 3507 * probably strip FCS just in case it sticks around in 3508 * bridged packets. 3509 */ 3510 hh->atw_service = IEEE80211_PLCP_SERVICE; /* XXX guess */ 3511 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3512 sizeof(struct atw_frame)); 3513 3514#if 0 3515 /* this virtually guaranteed that WEP-encrypted frames 3516 * are fragmented. oops. 3517 */ 3518 hh->atw_fragthr = htole16(m0->m_pkthdr.len - 3519 sizeof(struct atw_frame) + sizeof(struct ieee80211_frame)); 3520 hh->atw_fragthr &= htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3521#else 3522 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3523#endif 3524 3525 hh->atw_rtylmt = 3; 3526 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3527 if (do_encrypt) { 3528 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3529 hh->atw_keyid = ic->ic_wep_txkey; 3530 } 3531 3532 /* TBD 4-addr frames */ 3533 atw_frame_setdurs(sc, hh, rate, 3534 m0->m_pkthdr.len - sizeof(struct atw_frame) + 3535 sizeof(struct ieee80211_frame) + IEEE80211_CRC_LEN); 3536 3537 /* never fragment multicast frames */ 3538 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3539 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3540 } else if (sc->sc_flags & ATWF_RTSCTS) { 3541 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3542 } 3543 3544#ifdef ATW_DEBUG 3545 /* experimental stuff */ 3546 if (atw_xrtylmt != ~0) 3547 hh->atw_rtylmt = atw_xrtylmt; 3548 if (atw_xhdrctl != 0) 3549 hh->atw_hdrctl |= htole16(atw_xhdrctl); 3550 if (atw_xservice != IEEE80211_PLCP_SERVICE) 3551 hh->atw_service = atw_xservice; 3552 if (atw_xpaylen != 0) 3553 hh->atw_paylen = htole16(atw_xpaylen); 3554 hh->atw_fragnum = 0; 3555 3556 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3557 printf("%s: dst = %s, rate = 0x%02x, " 3558 "service = 0x%02x, paylen = 0x%04x\n", 3559 sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst), 3560 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3561 3562 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3563 "dur1 = 0x%04x, dur2 = 0x%04x, " 3564 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3565 sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1], 3566 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3567 hh->atw_tail_dur, hh->atw_head_dur); 3568 3569 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3570 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3571 sc->sc_dev.dv_xname, hh->atw_hdrctl, 3572 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3573 3574 printf("%s: keyid = %d\n", 3575 sc->sc_dev.dv_xname, hh->atw_keyid); 3576 3577 atw_dump_pkt(ifp, m0); 3578 } 3579#endif /* ATW_DEBUG */ 3580 3581 dmamap = txs->txs_dmamap; 3582 3583 /* 3584 * Load the DMA map. Copy and try (once) again if the packet 3585 * didn't fit in the alloted number of segments. 3586 */ 3587 for (first = 1; 3588 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3589 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3590 first = 0) { 3591 MGETHDR(m, M_DONTWAIT, MT_DATA); 3592 if (m == NULL) { 3593 printf("%s: unable to allocate Tx mbuf\n", 3594 sc->sc_dev.dv_xname); 3595 break; 3596 } 3597 if (m0->m_pkthdr.len > MHLEN) { 3598 MCLGET(m, M_DONTWAIT); 3599 if ((m->m_flags & M_EXT) == 0) { 3600 printf("%s: unable to allocate Tx " 3601 "cluster\n", sc->sc_dev.dv_xname); 3602 m_freem(m); 3603 break; 3604 } 3605 } 3606 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3607 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3608 m_freem(m0); 3609 m0 = m; 3610 m = NULL; 3611 } 3612 if (error != 0) { 3613 printf("%s: unable to load Tx buffer, " 3614 "error = %d\n", sc->sc_dev.dv_xname, error); 3615 m_freem(m0); 3616 break; 3617 } 3618 3619 /* 3620 * Ensure we have enough descriptors free to describe 3621 * the packet. 3622 */ 3623 if (dmamap->dm_nsegs > sc->sc_txfree) { 3624 /* 3625 * Not enough free descriptors to transmit 3626 * this packet. Unload the DMA map and 3627 * drop the packet. Notify the upper layer 3628 * that there are no more slots left. 3629 * 3630 * XXX We could allocate an mbuf and copy, but 3631 * XXX it is worth it? 3632 */ 3633 ifp->if_flags |= IFF_OACTIVE; 3634 bus_dmamap_unload(sc->sc_dmat, dmamap); 3635 m_freem(m0); 3636 break; 3637 } 3638 3639 /* 3640 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3641 */ 3642 3643 /* Sync the DMA map. */ 3644 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3645 BUS_DMASYNC_PREWRITE); 3646 3647 /* XXX arbitrary retry limit; 8 because I have seen it in 3648 * use already and maybe 0 means "no tries" ! 3649 */ 3650 ctl = htole32(LSHIFT(8, ATW_TXCTL_TL_MASK)); 3651 3652 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3653 sc->sc_dev.dv_xname, rate * 5)); 3654 ctl |= htole32(LSHIFT(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3655 3656 /* 3657 * Initialize the transmit descriptors. 3658 */ 3659 for (nexttx = sc->sc_txnext, seg = 0; 3660 seg < dmamap->dm_nsegs; 3661 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3662 /* 3663 * If this is the first descriptor we're 3664 * enqueueing, don't set the OWN bit just 3665 * yet. That could cause a race condition. 3666 * We'll do it below. 3667 */ 3668 txd = &sc->sc_txdescs[nexttx]; 3669 txd->at_ctl = ctl | 3670 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3671 3672 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3673 txd->at_flags = 3674 htole32(LSHIFT(dmamap->dm_segs[seg].ds_len, 3675 ATW_TXFLAG_TBS1_MASK)) | 3676 ((nexttx == (ATW_NTXDESC - 1)) 3677 ? htole32(ATW_TXFLAG_TER) : 0); 3678 lasttx = nexttx; 3679 } 3680 3681 IASSERT(lasttx != -1, ("bad lastx")); 3682 /* Set `first segment' and `last segment' appropriately. */ 3683 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3684 htole32(ATW_TXFLAG_FS); 3685 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3686 3687#ifdef ATW_DEBUG 3688 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3689 printf(" txsoft %p transmit chain:\n", txs); 3690 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3691 printf(" descriptor %d:\n", seg); 3692 printf(" at_ctl: 0x%08x\n", 3693 le32toh(sc->sc_txdescs[seg].at_ctl)); 3694 printf(" at_flags: 0x%08x\n", 3695 le32toh(sc->sc_txdescs[seg].at_flags)); 3696 printf(" at_buf1: 0x%08x\n", 3697 le32toh(sc->sc_txdescs[seg].at_buf1)); 3698 printf(" at_buf2: 0x%08x\n", 3699 le32toh(sc->sc_txdescs[seg].at_buf2)); 3700 if (seg == lasttx) 3701 break; 3702 } 3703 } 3704#endif 3705 3706 /* Sync the descriptors we're using. */ 3707 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3708 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3709 3710 /* 3711 * Store a pointer to the packet so we can free it later, 3712 * and remember what txdirty will be once the packet is 3713 * done. 3714 */ 3715 txs->txs_mbuf = m0; 3716 txs->txs_firstdesc = sc->sc_txnext; 3717 txs->txs_lastdesc = lasttx; 3718 txs->txs_ndescs = dmamap->dm_nsegs; 3719 3720 /* Advance the tx pointer. */ 3721 sc->sc_txfree -= dmamap->dm_nsegs; 3722 sc->sc_txnext = nexttx; 3723 3724 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3725 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3726 3727 last_txs = txs; 3728 } 3729 3730 if (txs == NULL || sc->sc_txfree == 0) { 3731 /* No more slots left; notify upper layer. */ 3732 ifp->if_flags |= IFF_OACTIVE; 3733 } 3734 3735 if (sc->sc_txfree != ofree) { 3736 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3737 sc->sc_dev.dv_xname, lasttx, firsttx)); 3738 /* 3739 * Cause a transmit interrupt to happen on the 3740 * last packet we enqueued. 3741 */ 3742 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3743 ATW_CDTXSYNC(sc, lasttx, 1, 3744 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3745 3746 /* 3747 * The entire packet chain is set up. Give the 3748 * first descriptor to the chip now. 3749 */ 3750 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3751 ATW_CDTXSYNC(sc, firsttx, 1, 3752 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3753 3754 /* Wake up the transmitter. */ 3755 /* XXX USE AUTOPOLLING? */ 3756 ATW_WRITE(sc, ATW_TDR, 0x1); 3757 3758 /* Set a watchdog timer in case the chip flakes out. */ 3759 sc->sc_tx_timer = 5; 3760 ifp->if_timer = 1; 3761 } 3762} 3763 3764/* 3765 * atw_power: 3766 * 3767 * Power management (suspend/resume) hook. 3768 */ 3769void 3770atw_power(why, arg) 3771 int why; 3772 void *arg; 3773{ 3774 struct atw_softc *sc = arg; 3775 struct ifnet *ifp = &sc->sc_ic.ic_if; 3776 int s; 3777 3778 DPRINTF(sc, ("%s: atw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3779 3780 s = splnet(); 3781 switch (why) { 3782 case PWR_STANDBY: 3783 /* XXX do nothing. */ 3784 break; 3785 case PWR_SUSPEND: 3786 atw_stop(ifp, 0); 3787 if (sc->sc_power != NULL) 3788 (*sc->sc_power)(sc, why); 3789 break; 3790 case PWR_RESUME: 3791 if (ifp->if_flags & IFF_UP) { 3792 if (sc->sc_power != NULL) 3793 (*sc->sc_power)(sc, why); 3794 atw_init(ifp); 3795 } 3796 break; 3797 case PWR_SOFTSUSPEND: 3798 case PWR_SOFTSTANDBY: 3799 case PWR_SOFTRESUME: 3800 break; 3801 } 3802 splx(s); 3803} 3804 3805/* 3806 * atw_ioctl: [ifnet interface function] 3807 * 3808 * Handle control requests from the operator. 3809 */ 3810int 3811atw_ioctl(ifp, cmd, data) 3812 struct ifnet *ifp; 3813 u_long cmd; 3814 caddr_t data; 3815{ 3816 struct atw_softc *sc = ifp->if_softc; 3817 struct ifreq *ifr = (struct ifreq *)data; 3818 int s, error = 0; 3819 3820 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 3821 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 3822 return ENXIO; 3823 3824 s = splnet(); 3825 3826 switch (cmd) { 3827 case SIOCSIFFLAGS: 3828 if (ifp->if_flags & IFF_UP) { 3829 if (ATW_IS_ENABLED(sc)) { 3830 /* 3831 * To avoid rescanning another access point, 3832 * do not call atw_init() here. Instead, 3833 * only reflect media settings. 3834 */ 3835 atw_filter_setup(sc); 3836 } else 3837 error = atw_init(ifp); 3838 } else if (ATW_IS_ENABLED(sc)) 3839 atw_stop(ifp, 1); 3840 break; 3841 case SIOCADDMULTI: 3842 case SIOCDELMULTI: 3843 error = (cmd == SIOCADDMULTI) ? 3844 ether_addmulti(ifr, &sc->sc_ic.ic_ec) : 3845 ether_delmulti(ifr, &sc->sc_ic.ic_ec); 3846 if (error == ENETRESET) { 3847 if (ATW_IS_ENABLED(sc)) 3848 atw_filter_setup(sc); /* do not rescan */ 3849 error = 0; 3850 } 3851 break; 3852 default: 3853 error = ieee80211_ioctl(ifp, cmd, data); 3854 if (error == ENETRESET) { 3855 if (ATW_IS_ENABLED(sc)) 3856 error = atw_init(ifp); 3857 else 3858 error = 0; 3859 } 3860 break; 3861 } 3862 3863 /* Try to get more packets going. */ 3864 if (ATW_IS_ENABLED(sc)) 3865 atw_start(ifp); 3866 3867 splx(s); 3868 return (error); 3869} 3870 3871static int 3872atw_media_change(struct ifnet *ifp) 3873{ 3874 int error; 3875 3876 error = ieee80211_media_change(ifp); 3877 if (error == ENETRESET) { 3878 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 3879 (IFF_RUNNING|IFF_UP)) 3880 atw_init(ifp); /* XXX lose error */ 3881 error = 0; 3882 } 3883 return error; 3884} 3885 3886static void 3887atw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 3888{ 3889 struct atw_softc *sc = ifp->if_softc; 3890 3891 if (ATW_IS_ENABLED(sc) == 0) { 3892 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 3893 imr->ifm_status = 0; 3894 return; 3895 } 3896 ieee80211_media_status(ifp, imr); 3897} 3898