atw.c revision 1.165
1/* $NetBSD: atw.c,v 1.165 2019/02/05 06:17:02 msaitoh Exp $ */ 2 3/*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32/* 33 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 34 */ 35 36#include <sys/cdefs.h> 37__KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.165 2019/02/05 06:17:02 msaitoh Exp $"); 38 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/callout.h> 43#include <sys/mbuf.h> 44#include <sys/malloc.h> 45#include <sys/kernel.h> 46#include <sys/socket.h> 47#include <sys/ioctl.h> 48#include <sys/errno.h> 49#include <sys/device.h> 50#include <sys/kauth.h> 51#include <sys/time.h> 52#include <sys/proc.h> 53#include <sys/atomic.h> 54#include <lib/libkern/libkern.h> 55 56#include <machine/endian.h> 57 58#include <net/if.h> 59#include <net/if_dl.h> 60#include <net/if_media.h> 61#include <net/if_ether.h> 62 63#include <net80211/ieee80211_netbsd.h> 64#include <net80211/ieee80211_var.h> 65#include <net80211/ieee80211_radiotap.h> 66 67#include <net/bpf.h> 68 69#include <sys/bus.h> 70#include <sys/intr.h> 71 72#include <dev/ic/atwreg.h> 73#include <dev/ic/rf3000reg.h> 74#include <dev/ic/si4136reg.h> 75#include <dev/ic/atwvar.h> 76#include <dev/ic/smc93cx6var.h> 77 78/* XXX TBD open questions 79 * 80 * 81 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 82 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 83 * handle this for me? 84 * 85 */ 86/* device attachment 87 * 88 * print TOFS[012] 89 * 90 * device initialization 91 * 92 * clear ATW_FRCTL_MAXPSP to disable max power saving 93 * set ATW_TXBR_ALCUPDATE to enable ALC 94 * set TOFS[012]? (hope not) 95 * disable rx/tx 96 * set ATW_PAR_SWR (software reset) 97 * wait for ATW_PAR_SWR clear 98 * disable interrupts 99 * ack status register 100 * enable interrupts 101 * 102 * rx/tx initialization 103 * 104 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 105 * allocate and init descriptor rings 106 * write ATW_PAR_DSL (descriptor skip length) 107 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 108 * write ATW_NAR_SQ for one/both transmit descriptor rings 109 * write ATW_NAR_SQ for one/both transmit descriptor rings 110 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 111 * 112 * rx/tx end 113 * 114 * stop DMA 115 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 116 * flush tx w/ ATW_NAR_HF 117 * 118 * scan 119 * 120 * initialize rx/tx 121 * 122 * BSS join: (re)association response 123 * 124 * set ATW_FRCTL_AID 125 * 126 * optimizations ??? 127 * 128 */ 129 130#define ATW_REFSLAVE /* slavishly do what the reference driver does */ 131 132int atw_pseudo_milli = 1; 133int atw_magic_delay1 = 100 * 1000; 134int atw_magic_delay2 = 100 * 1000; 135/* more magic multi-millisecond delays (units: microseconds) */ 136int atw_nar_delay = 20 * 1000; 137int atw_magic_delay4 = 10 * 1000; 138int atw_rf_delay1 = 10 * 1000; 139int atw_rf_delay2 = 5 * 1000; 140int atw_plcphd_delay = 2 * 1000; 141int atw_bbp_io_enable_delay = 20 * 1000; 142int atw_bbp_io_disable_delay = 2 * 1000; 143int atw_writewep_delay = 1000; 144int atw_beacon_len_adjust = 4; 145int atw_dwelltime = 200; 146int atw_xindiv2 = 0; 147 148#ifdef ATW_DEBUG 149int atw_debug = 0; 150 151#define ATW_DPRINTF(x) if (atw_debug > 0) printf x 152#define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 153#define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 154#define DPRINTF(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) printf x 155#define DPRINTF2(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 156#define DPRINTF3(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 157 158static void atw_dump_pkt(struct ifnet *, struct mbuf *); 159static void atw_print_regs(struct atw_softc *, const char *); 160 161/* Note well: I never got atw_rf3000_read or atw_si4126_read to work. */ 162# ifdef ATW_BBPDEBUG 163static void atw_rf3000_print(struct atw_softc *); 164static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 165# endif /* ATW_BBPDEBUG */ 166 167# ifdef ATW_SYNDEBUG 168static void atw_si4126_print(struct atw_softc *); 169static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 170# endif /* ATW_SYNDEBUG */ 171#define __atwdebugused /* empty */ 172#else 173#define ATW_DPRINTF(x) 174#define ATW_DPRINTF2(x) 175#define ATW_DPRINTF3(x) 176#define DPRINTF(sc, x) /* nothing */ 177#define DPRINTF2(sc, x) /* nothing */ 178#define DPRINTF3(sc, x) /* nothing */ 179#define __atwdebugused __unused 180#endif 181 182/* ifnet methods */ 183int atw_init(struct ifnet *); 184int atw_ioctl(struct ifnet *, u_long, void *); 185void atw_start(struct ifnet *); 186void atw_stop(struct ifnet *, int); 187void atw_watchdog(struct ifnet *); 188 189/* Device attachment */ 190void atw_attach(struct atw_softc *); 191int atw_detach(struct atw_softc *); 192static void atw_evcnt_attach(struct atw_softc *); 193static void atw_evcnt_detach(struct atw_softc *); 194 195/* Rx/Tx process */ 196int atw_add_rxbuf(struct atw_softc *, int); 197void atw_idle(struct atw_softc *, u_int32_t); 198void atw_rxdrain(struct atw_softc *); 199void atw_txdrain(struct atw_softc *); 200 201/* Device (de)activation and power state */ 202void atw_reset(struct atw_softc *); 203 204/* Interrupt handlers */ 205void atw_softintr(void *); 206void atw_linkintr(struct atw_softc *, u_int32_t); 207void atw_rxintr(struct atw_softc *); 208void atw_txintr(struct atw_softc *, uint32_t); 209 210/* 802.11 state machine */ 211static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 212static void atw_next_scan(void *); 213static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 214 struct ieee80211_node *, int, int, u_int32_t); 215static int atw_tune(struct atw_softc *); 216 217/* Device initialization */ 218static void atw_bbp_io_init(struct atw_softc *); 219static void atw_cfp_init(struct atw_softc *); 220static void atw_cmdr_init(struct atw_softc *); 221static void atw_ifs_init(struct atw_softc *); 222static void atw_nar_init(struct atw_softc *); 223static void atw_response_times_init(struct atw_softc *); 224static void atw_rf_reset(struct atw_softc *); 225static void atw_test1_init(struct atw_softc *); 226static void atw_tofs0_init(struct atw_softc *); 227static void atw_tofs2_init(struct atw_softc *); 228static void atw_txlmt_init(struct atw_softc *); 229static void atw_wcsr_init(struct atw_softc *); 230 231/* Key management */ 232static int atw_key_delete(struct ieee80211com *, const struct ieee80211_key *); 233static int atw_key_set(struct ieee80211com *, const struct ieee80211_key *, 234 const u_int8_t[IEEE80211_ADDR_LEN]); 235static void atw_key_update_begin(struct ieee80211com *); 236static void atw_key_update_end(struct ieee80211com *); 237 238/* RAM/ROM utilities */ 239static void atw_clear_sram(struct atw_softc *); 240static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 241static int atw_read_srom(struct atw_softc *); 242 243/* BSS setup */ 244static void atw_predict_beacon(struct atw_softc *); 245static void atw_start_beacon(struct atw_softc *, int); 246static void atw_write_bssid(struct atw_softc *); 247static void atw_write_ssid(struct atw_softc *); 248static void atw_write_sup_rates(struct atw_softc *); 249static void atw_write_wep(struct atw_softc *); 250 251/* Media */ 252static int atw_media_change(struct ifnet *); 253 254static void atw_filter_setup(struct atw_softc *); 255 256/* 802.11 utilities */ 257static uint64_t atw_get_tsft(struct atw_softc *); 258static inline uint32_t atw_last_even_tsft(uint32_t, uint32_t, 259 uint32_t); 260static struct ieee80211_node *atw_node_alloc(struct ieee80211_node_table *); 261static void atw_node_free(struct ieee80211_node *); 262 263/* 264 * Tuner/transceiver/modem 265 */ 266static void atw_bbp_io_enable(struct atw_softc *, int); 267 268/* RFMD RF3000 Baseband Processor */ 269static int atw_rf3000_init(struct atw_softc *); 270static int atw_rf3000_tune(struct atw_softc *, u_int); 271static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 272 273/* Silicon Laboratories Si4126 RF/IF Synthesizer */ 274static void atw_si4126_tune(struct atw_softc *, u_int); 275static void atw_si4126_write(struct atw_softc *, u_int, u_int); 276 277const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 278const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 279 280const char *atw_tx_state[] = { 281 "STOPPED", 282 "RUNNING - read descriptor", 283 "RUNNING - transmitting", 284 "RUNNING - filling fifo", /* XXX */ 285 "SUSPENDED", 286 "RUNNING -- write descriptor", 287 "RUNNING -- write last descriptor", 288 "RUNNING - fifo full" 289}; 290 291const char *atw_rx_state[] = { 292 "STOPPED", 293 "RUNNING - read descriptor", 294 "RUNNING - check this packet, pre-fetch next", 295 "RUNNING - wait for reception", 296 "SUSPENDED", 297 "RUNNING - write descriptor", 298 "RUNNING - flush fifo", 299 "RUNNING - fifo drain" 300}; 301 302static inline int 303is_running(struct ifnet *ifp) 304{ 305 return (ifp->if_flags & (IFF_RUNNING|IFF_UP)) == (IFF_RUNNING|IFF_UP); 306} 307 308int 309atw_activate(device_t self, enum devact act) 310{ 311 struct atw_softc *sc = device_private(self); 312 313 switch (act) { 314 case DVACT_DEACTIVATE: 315 if_deactivate(&sc->sc_if); 316 return 0; 317 default: 318 return EOPNOTSUPP; 319 } 320} 321 322bool 323atw_suspend(device_t self, const pmf_qual_t *qual) 324{ 325 struct atw_softc *sc = device_private(self); 326 327 atw_rxdrain(sc); 328 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 329 330 return true; 331} 332 333/* Returns -1 on failure. */ 334static int 335atw_read_srom(struct atw_softc *sc) 336{ 337 struct seeprom_descriptor sd; 338 uint32_t test0, fail_bits; 339 340 (void)memset(&sd, 0, sizeof(sd)); 341 342 test0 = ATW_READ(sc, ATW_TEST0); 343 344 switch (sc->sc_rev) { 345 case ATW_REVISION_BA: 346 case ATW_REVISION_CA: 347 fail_bits = ATW_TEST0_EPNE; 348 break; 349 default: 350 fail_bits = ATW_TEST0_EPNE|ATW_TEST0_EPSNM; 351 break; 352 } 353 if ((test0 & fail_bits) != 0) { 354 aprint_error_dev(sc->sc_dev, "bad or missing/bad SROM\n"); 355 return -1; 356 } 357 358 switch (test0 & ATW_TEST0_EPTYP_MASK) { 359 case ATW_TEST0_EPTYP_93c66: 360 ATW_DPRINTF(("%s: 93c66 SROM\n", device_xname(sc->sc_dev))); 361 sc->sc_sromsz = 512; 362 sd.sd_chip = C56_66; 363 break; 364 case ATW_TEST0_EPTYP_93c46: 365 ATW_DPRINTF(("%s: 93c46 SROM\n", device_xname(sc->sc_dev))); 366 sc->sc_sromsz = 128; 367 sd.sd_chip = C46; 368 break; 369 default: 370 printf("%s: unknown SROM type %" __PRIuBITS "\n", 371 device_xname(sc->sc_dev), 372 __SHIFTOUT(test0, ATW_TEST0_EPTYP_MASK)); 373 return -1; 374 } 375 376 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 377 378 if (sc->sc_srom == NULL) { 379 aprint_error_dev(sc->sc_dev, "unable to allocate SROM buffer\n"); 380 return -1; 381 } 382 383 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 384 385 /* ADM8211 has a single 32-bit register for controlling the 386 * 93cx6 SROM. Bit SRS enables the serial port. There is no 387 * "ready" bit. The ADM8211 input/output sense is the reverse 388 * of read_seeprom's. 389 */ 390 sd.sd_tag = sc->sc_st; 391 sd.sd_bsh = sc->sc_sh; 392 sd.sd_regsize = 4; 393 sd.sd_control_offset = ATW_SPR; 394 sd.sd_status_offset = ATW_SPR; 395 sd.sd_dataout_offset = ATW_SPR; 396 sd.sd_CK = ATW_SPR_SCLK; 397 sd.sd_CS = ATW_SPR_SCS; 398 sd.sd_DI = ATW_SPR_SDO; 399 sd.sd_DO = ATW_SPR_SDI; 400 sd.sd_MS = ATW_SPR_SRS; 401 sd.sd_RDY = 0; 402 403 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 404 aprint_error_dev(sc->sc_dev, "could not read SROM\n"); 405 free(sc->sc_srom, M_DEVBUF); 406 return -1; 407 } 408#ifdef ATW_DEBUG 409 { 410 int i; 411 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 412 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 413 if (((i % 8) == 0) && (i != 0)) { 414 ATW_DPRINTF(("\n\t")); 415 } 416 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 417 } 418 ATW_DPRINTF(("\n")); 419 } 420#endif /* ATW_DEBUG */ 421 return 0; 422} 423 424#ifdef ATW_DEBUG 425static void 426atw_print_regs(struct atw_softc *sc, const char *where) 427{ 428#define PRINTREG(sc, reg) \ 429 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 430 device_xname(sc->sc_dev), reg, ATW_READ(sc, reg))) 431 432 ATW_DPRINTF2(("%s: %s\n", device_xname(sc->sc_dev), where)); 433 434 PRINTREG(sc, ATW_PAR); 435 PRINTREG(sc, ATW_FRCTL); 436 PRINTREG(sc, ATW_TDR); 437 PRINTREG(sc, ATW_WTDP); 438 PRINTREG(sc, ATW_RDR); 439 PRINTREG(sc, ATW_WRDP); 440 PRINTREG(sc, ATW_RDB); 441 PRINTREG(sc, ATW_CSR3A); 442 PRINTREG(sc, ATW_TDBD); 443 PRINTREG(sc, ATW_TDBP); 444 PRINTREG(sc, ATW_STSR); 445 PRINTREG(sc, ATW_CSR5A); 446 PRINTREG(sc, ATW_NAR); 447 PRINTREG(sc, ATW_CSR6A); 448 PRINTREG(sc, ATW_IER); 449 PRINTREG(sc, ATW_CSR7A); 450 PRINTREG(sc, ATW_LPC); 451 PRINTREG(sc, ATW_TEST1); 452 PRINTREG(sc, ATW_SPR); 453 PRINTREG(sc, ATW_TEST0); 454 PRINTREG(sc, ATW_WCSR); 455 PRINTREG(sc, ATW_WPDR); 456 PRINTREG(sc, ATW_GPTMR); 457 PRINTREG(sc, ATW_GPIO); 458 PRINTREG(sc, ATW_BBPCTL); 459 PRINTREG(sc, ATW_SYNCTL); 460 PRINTREG(sc, ATW_PLCPHD); 461 PRINTREG(sc, ATW_MMIWADDR); 462 PRINTREG(sc, ATW_MMIRADDR1); 463 PRINTREG(sc, ATW_MMIRADDR2); 464 PRINTREG(sc, ATW_TXBR); 465 PRINTREG(sc, ATW_CSR15A); 466 PRINTREG(sc, ATW_ALCSTAT); 467 PRINTREG(sc, ATW_TOFS2); 468 PRINTREG(sc, ATW_CMDR); 469 PRINTREG(sc, ATW_PCIC); 470 PRINTREG(sc, ATW_PMCSR); 471 PRINTREG(sc, ATW_PAR0); 472 PRINTREG(sc, ATW_PAR1); 473 PRINTREG(sc, ATW_MAR0); 474 PRINTREG(sc, ATW_MAR1); 475 PRINTREG(sc, ATW_ATIMDA0); 476 PRINTREG(sc, ATW_ABDA1); 477 PRINTREG(sc, ATW_BSSID0); 478 PRINTREG(sc, ATW_TXLMT); 479 PRINTREG(sc, ATW_MIBCNT); 480 PRINTREG(sc, ATW_BCNT); 481 PRINTREG(sc, ATW_TSFTH); 482 PRINTREG(sc, ATW_TSC); 483 PRINTREG(sc, ATW_SYNRF); 484 PRINTREG(sc, ATW_BPLI); 485 PRINTREG(sc, ATW_CAP0); 486 PRINTREG(sc, ATW_CAP1); 487 PRINTREG(sc, ATW_RMD); 488 PRINTREG(sc, ATW_CFPP); 489 PRINTREG(sc, ATW_TOFS0); 490 PRINTREG(sc, ATW_TOFS1); 491 PRINTREG(sc, ATW_IFST); 492 PRINTREG(sc, ATW_RSPT); 493 PRINTREG(sc, ATW_TSFTL); 494 PRINTREG(sc, ATW_WEPCTL); 495 PRINTREG(sc, ATW_WESK); 496 PRINTREG(sc, ATW_WEPCNT); 497 PRINTREG(sc, ATW_MACTEST); 498 PRINTREG(sc, ATW_FER); 499 PRINTREG(sc, ATW_FEMR); 500 PRINTREG(sc, ATW_FPSR); 501 PRINTREG(sc, ATW_FFER); 502#undef PRINTREG 503} 504#endif /* ATW_DEBUG */ 505 506/* 507 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 508 */ 509void 510atw_attach(struct atw_softc *sc) 511{ 512 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 513 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 514 }; 515 struct ieee80211com *ic = &sc->sc_ic; 516 struct ifnet *ifp = &sc->sc_if; 517 int country_code, error, i, srom_major; 518 u_int32_t reg; 519 static const char *type_strings[] = {"Intersil (not supported)", 520 "RFMD", "Marvel (not supported)"}; 521 522 pmf_self_suspensor_init(sc->sc_dev, &sc->sc_suspensor, &sc->sc_qual); 523 524 sc->sc_soft_ih = softint_establish(SOFTINT_NET, atw_softintr, sc); 525 if (sc->sc_soft_ih == NULL) { 526 aprint_error_dev(sc->sc_dev, "unable to establish softint\n"); 527 goto fail_0; 528 } 529 530 sc->sc_txth = atw_txthresh_tab_lo; 531 532 SIMPLEQ_INIT(&sc->sc_txfreeq); 533 SIMPLEQ_INIT(&sc->sc_txdirtyq); 534 535#ifdef ATW_DEBUG 536 atw_print_regs(sc, "atw_attach"); 537#endif /* ATW_DEBUG */ 538 539 /* 540 * Allocate the control data structures, and create and load the 541 * DMA map for it. 542 */ 543 if ((error = bus_dmamem_alloc(sc->sc_dmat, 544 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 545 1, &sc->sc_cdnseg, 0)) != 0) { 546 aprint_error_dev(sc->sc_dev, 547 "unable to allocate control data, error = %d\n", 548 error); 549 goto fail_0; 550 } 551 552 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 553 sizeof(struct atw_control_data), (void **)&sc->sc_control_data, 554 BUS_DMA_COHERENT)) != 0) { 555 aprint_error_dev(sc->sc_dev, 556 "unable to map control data, error = %d\n", 557 error); 558 goto fail_1; 559 } 560 561 if ((error = bus_dmamap_create(sc->sc_dmat, 562 sizeof(struct atw_control_data), 1, 563 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 564 aprint_error_dev(sc->sc_dev, 565 "unable to create control data DMA map, error = %d\n", 566 error); 567 goto fail_2; 568 } 569 570 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 571 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 572 0)) != 0) { 573 aprint_error_dev(sc->sc_dev, 574 "unable to load control data DMA map, error = %d\n", error); 575 goto fail_3; 576 } 577 578 /* 579 * Create the transmit buffer DMA maps. 580 */ 581 sc->sc_ntxsegs = ATW_NTXSEGS; 582 for (i = 0; i < ATW_TXQUEUELEN; i++) { 583 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 584 sc->sc_ntxsegs, MCLBYTES, 0, 0, 585 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 586 aprint_error_dev(sc->sc_dev, 587 "unable to create tx DMA map %d, error = %d\n", i, 588 error); 589 goto fail_4; 590 } 591 } 592 593 /* 594 * Create the receive buffer DMA maps. 595 */ 596 for (i = 0; i < ATW_NRXDESC; i++) { 597 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 598 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 599 aprint_error_dev(sc->sc_dev, 600 "unable to create rx DMA map %d, error = %d\n", i, 601 error); 602 goto fail_5; 603 } 604 } 605 for (i = 0; i < ATW_NRXDESC; i++) { 606 sc->sc_rxsoft[i].rxs_mbuf = NULL; 607 } 608 609 switch (sc->sc_rev) { 610 case ATW_REVISION_AB: 611 case ATW_REVISION_AF: 612 sc->sc_sramlen = ATW_SRAM_A_SIZE; 613 break; 614 case ATW_REVISION_BA: 615 case ATW_REVISION_CA: 616 sc->sc_sramlen = ATW_SRAM_B_SIZE; 617 break; 618 } 619 620 /* Reset the chip to a known state. */ 621 atw_reset(sc); 622 623 if (atw_read_srom(sc) == -1) 624 goto fail_5; 625 626 sc->sc_rftype = __SHIFTOUT(sc->sc_srom[ATW_SR_CSR20], 627 ATW_SR_RFTYPE_MASK); 628 629 sc->sc_bbptype = __SHIFTOUT(sc->sc_srom[ATW_SR_CSR20], 630 ATW_SR_BBPTYPE_MASK); 631 632 if (sc->sc_rftype >= __arraycount(type_strings)) { 633 aprint_error_dev(sc->sc_dev, "unknown RF\n"); 634 goto fail_5; 635 } 636 if (sc->sc_bbptype >= __arraycount(type_strings)) { 637 aprint_error_dev(sc->sc_dev, "unknown BBP\n"); 638 goto fail_5; 639 } 640 641 aprint_normal_dev(sc->sc_dev, "%s RF, %s BBP", 642 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 643 644 /* XXX There exists a Linux driver which seems to use RFType = 0 for 645 * MARVEL. My bug, or theirs? 646 */ 647 648 reg = __SHIFTIN(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 649 650 switch (sc->sc_rftype) { 651 case ATW_RFTYPE_INTERSIL: 652 reg |= ATW_SYNCTL_CS1; 653 break; 654 case ATW_RFTYPE_RFMD: 655 reg |= ATW_SYNCTL_CS0; 656 break; 657 case ATW_RFTYPE_MARVEL: 658 break; 659 } 660 661 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 662 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 663 664 reg = __SHIFTIN(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 665 666 switch (sc->sc_bbptype) { 667 case ATW_BBPTYPE_INTERSIL: 668 reg |= ATW_BBPCTL_TWI; 669 break; 670 case ATW_BBPTYPE_RFMD: 671 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 672 ATW_BBPCTL_CCA_ACTLO; 673 break; 674 case ATW_BBPTYPE_MARVEL: 675 break; 676 case ATW_C_BBPTYPE_RFMD: 677 aprint_error_dev(sc->sc_dev, 678 "ADM8211C MAC/RFMD BBP not supported yet.\n"); 679 break; 680 } 681 682 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 683 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 684 685 /* 686 * From this point forward, the attachment cannot fail. A failure 687 * before this point releases all resources that may have been 688 * allocated. 689 */ 690 sc->sc_flags |= ATWF_ATTACHED; 691 692 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 693 htole16(sc->sc_srom[ATW_SR_MAC00]), 694 htole16(sc->sc_srom[ATW_SR_MAC01]), 695 htole16(sc->sc_srom[ATW_SR_MAC10]))); 696 697 srom_major = __SHIFTOUT(sc->sc_srom[ATW_SR_FORMAT_VERSION], 698 ATW_SR_MAJOR_MASK); 699 700 if (srom_major < 2) 701 sc->sc_rf3000_options1 = 0; 702 else if (sc->sc_rev == ATW_REVISION_BA) { 703 sc->sc_rf3000_options1 = 704 __SHIFTOUT(sc->sc_srom[ATW_SR_CR28_CR03], 705 ATW_SR_CR28_MASK); 706 } else 707 sc->sc_rf3000_options1 = 0; 708 709 sc->sc_rf3000_options2 = __SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29], 710 ATW_SR_CR29_MASK); 711 712 country_code = __SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29], 713 ATW_SR_CTRY_MASK); 714 715#define ADD_CHANNEL(_ic, _chan) do { \ 716 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 717 _ic->ic_channels[_chan].ic_freq = \ 718 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 719} while (0) 720 721 /* Find available channels */ 722 switch (country_code) { 723 case COUNTRY_MMK2: /* 1-14 */ 724 ADD_CHANNEL(ic, 14); 725 /*FALLTHROUGH*/ 726 case COUNTRY_ETSI: /* 1-13 */ 727 for (i = 1; i <= 13; i++) 728 ADD_CHANNEL(ic, i); 729 break; 730 case COUNTRY_FCC: /* 1-11 */ 731 case COUNTRY_IC: /* 1-11 */ 732 for (i = 1; i <= 11; i++) 733 ADD_CHANNEL(ic, i); 734 break; 735 case COUNTRY_MMK: /* 14 */ 736 ADD_CHANNEL(ic, 14); 737 break; 738 case COUNTRY_FRANCE: /* 10-13 */ 739 for (i = 10; i <= 13; i++) 740 ADD_CHANNEL(ic, i); 741 break; 742 default: /* assume channels 10-11 */ 743 case COUNTRY_SPAIN: /* 10-11 */ 744 for (i = 10; i <= 11; i++) 745 ADD_CHANNEL(ic, i); 746 break; 747 } 748 749 /* Read the MAC address. */ 750 reg = ATW_READ(sc, ATW_PAR0); 751 ic->ic_myaddr[0] = __SHIFTOUT(reg, ATW_PAR0_PAB0_MASK); 752 ic->ic_myaddr[1] = __SHIFTOUT(reg, ATW_PAR0_PAB1_MASK); 753 ic->ic_myaddr[2] = __SHIFTOUT(reg, ATW_PAR0_PAB2_MASK); 754 ic->ic_myaddr[3] = __SHIFTOUT(reg, ATW_PAR0_PAB3_MASK); 755 reg = ATW_READ(sc, ATW_PAR1); 756 ic->ic_myaddr[4] = __SHIFTOUT(reg, ATW_PAR1_PAB4_MASK); 757 ic->ic_myaddr[5] = __SHIFTOUT(reg, ATW_PAR1_PAB5_MASK); 758 759 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 760 aprint_error_dev(sc->sc_dev, 761 "could not get mac address, attach failed\n"); 762 goto fail_5; 763 } 764 765 aprint_normal(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 766 767 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 768 ifp->if_softc = sc; 769 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 770 ifp->if_ioctl = atw_ioctl; 771 ifp->if_start = atw_start; 772 ifp->if_watchdog = atw_watchdog; 773 ifp->if_init = atw_init; 774 ifp->if_stop = atw_stop; 775 IFQ_SET_READY(&ifp->if_snd); 776 777 ic->ic_ifp = ifp; 778 ic->ic_phytype = IEEE80211_T_DS; 779 ic->ic_opmode = IEEE80211_M_STA; 780 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 781 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR; 782 783 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 784 785 /* 786 * Call MI attach routines. 787 */ 788 789 error = if_initialize(ifp); 790 if (error != 0) { 791 aprint_error_dev(sc->sc_dev, "if_initialize failed(%d)\n", 792 error); 793 goto fail_5; 794 } 795 ieee80211_ifattach(ic); 796 /* Use common softint-based if_input */ 797 ifp->if_percpuq = if_percpuq_create(ifp); 798 if_register(ifp); 799 800 atw_evcnt_attach(sc); 801 802 sc->sc_newstate = ic->ic_newstate; 803 ic->ic_newstate = atw_newstate; 804 805 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 806 ic->ic_recv_mgmt = atw_recv_mgmt; 807 808 sc->sc_node_free = ic->ic_node_free; 809 ic->ic_node_free = atw_node_free; 810 811 sc->sc_node_alloc = ic->ic_node_alloc; 812 ic->ic_node_alloc = atw_node_alloc; 813 814 ic->ic_crypto.cs_key_delete = atw_key_delete; 815 ic->ic_crypto.cs_key_set = atw_key_set; 816 ic->ic_crypto.cs_key_update_begin = atw_key_update_begin; 817 ic->ic_crypto.cs_key_update_end = atw_key_update_end; 818 819 /* possibly we should fill in our own sc_send_prresp, since 820 * the ADM8211 is probably sending probe responses in ad hoc 821 * mode. 822 */ 823 824 /* complete initialization */ 825 ieee80211_media_init(ic, atw_media_change, ieee80211_media_status); 826 callout_init(&sc->sc_scan_ch, 0); 827 828 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 829 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 830 831 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 832 sc->sc_rxtap.ar_ihdr.it_len = htole16(sizeof(sc->sc_rxtapu)); 833 sc->sc_rxtap.ar_ihdr.it_present = htole32(ATW_RX_RADIOTAP_PRESENT); 834 835 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 836 sc->sc_txtap.at_ihdr.it_len = htole16(sizeof(sc->sc_txtapu)); 837 sc->sc_txtap.at_ihdr.it_present = htole32(ATW_TX_RADIOTAP_PRESENT); 838 839 ieee80211_announce(ic); 840 return; 841 842 /* 843 * Free any resources we've allocated during the failed attach 844 * attempt. Do this in reverse order and fall through. 845 */ 846 fail_5: 847 for (i = 0; i < ATW_NRXDESC; i++) { 848 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 849 continue; 850 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 851 } 852 fail_4: 853 for (i = 0; i < ATW_TXQUEUELEN; i++) { 854 if (sc->sc_txsoft[i].txs_dmamap == NULL) 855 continue; 856 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 857 } 858 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 859 fail_3: 860 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 861 fail_2: 862 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 863 sizeof(struct atw_control_data)); 864 fail_1: 865 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 866 fail_0: 867 if (sc->sc_soft_ih != NULL) { 868 softint_disestablish(sc->sc_soft_ih); 869 sc->sc_soft_ih = NULL; 870 } 871} 872 873static struct ieee80211_node * 874atw_node_alloc(struct ieee80211_node_table *nt) 875{ 876 struct atw_softc *sc = (struct atw_softc *)nt->nt_ic->ic_ifp->if_softc; 877 struct ieee80211_node *ni = (*sc->sc_node_alloc)(nt); 878 879 DPRINTF(sc, ("%s: alloc node %p\n", device_xname(sc->sc_dev), ni)); 880 return ni; 881} 882 883static void 884atw_node_free(struct ieee80211_node *ni) 885{ 886 struct atw_softc *sc = (struct atw_softc *)ni->ni_ic->ic_ifp->if_softc; 887 888 DPRINTF(sc, ("%s: freeing node %p %s\n", device_xname(sc->sc_dev), ni, 889 ether_sprintf(ni->ni_bssid))); 890 (*sc->sc_node_free)(ni); 891} 892 893 894static void 895atw_test1_reset(struct atw_softc *sc) 896{ 897 switch (sc->sc_rev) { 898 case ATW_REVISION_BA: 899 if (1 /* XXX condition on transceiver type */) { 900 ATW_SET(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MONITOR); 901 } 902 break; 903 case ATW_REVISION_CA: 904 ATW_CLR(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MASK); 905 break; 906 default: 907 break; 908 } 909} 910 911/* 912 * atw_reset: 913 * 914 * Perform a soft reset on the ADM8211. 915 */ 916void 917atw_reset(struct atw_softc *sc) 918{ 919 int i; 920 uint32_t lpc __atwdebugused; 921 922 ATW_WRITE(sc, ATW_NAR, 0x0); 923 DELAY(atw_nar_delay); 924 925 /* Reference driver has a cryptic remark indicating that this might 926 * power-on the chip. I know that it turns off power-saving.... 927 */ 928 ATW_WRITE(sc, ATW_FRCTL, 0x0); 929 930 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 931 932 for (i = 0; i < 50000 / atw_pseudo_milli; i++) { 933 if ((ATW_READ(sc, ATW_PAR) & ATW_PAR_SWR) == 0) 934 break; 935 DELAY(atw_pseudo_milli); 936 } 937 938 /* ... and then pause 100ms longer for good measure. */ 939 DELAY(atw_magic_delay1); 940 941 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", device_xname(sc->sc_dev), i)); 942 943 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 944 aprint_error_dev(sc->sc_dev, "reset failed to complete\n"); 945 946 /* 947 * Initialize the PCI Access Register. 948 */ 949 sc->sc_busmode = ATW_PAR_PBL_8DW; 950 951 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 952 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", device_xname(sc->sc_dev), 953 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 954 955 atw_test1_reset(sc); 956 957 /* Turn off maximum power saving, etc. */ 958 ATW_WRITE(sc, ATW_FRCTL, 0x0); 959 960 DELAY(atw_magic_delay2); 961 962 /* Recall EEPROM. */ 963 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 964 965 DELAY(atw_magic_delay4); 966 967 lpc = ATW_READ(sc, ATW_LPC); 968 969 DPRINTF(sc, ("%s: ATW_LPC %#08x\n", __func__, lpc)); 970 971 /* A reset seems to affect the SRAM contents, so put them into 972 * a known state. 973 */ 974 atw_clear_sram(sc); 975 976 memset(sc->sc_bssid, 0xff, sizeof(sc->sc_bssid)); 977} 978 979static void 980atw_clear_sram(struct atw_softc *sc) 981{ 982 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 983 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 984 /* XXX not for revision 0x20. */ 985 atw_write_sram(sc, 0, sc->sc_sram, sc->sc_sramlen); 986} 987 988/* TBD atw_init 989 * 990 * set MAC based on ic->ic_bss->myaddr 991 * write WEP keys 992 * set TX rate 993 */ 994 995/* Tell the ADM8211 to raise ATW_INTR_LINKOFF if 7 beacon intervals pass 996 * without receiving a beacon with the preferred BSSID & SSID. 997 * atw_write_bssid & atw_write_ssid set the BSSID & SSID. 998 */ 999static void 1000atw_wcsr_init(struct atw_softc *sc) 1001{ 1002 uint32_t wcsr; 1003 1004 wcsr = ATW_READ(sc, ATW_WCSR); 1005 wcsr &= ~ATW_WCSR_BLN_MASK; 1006 wcsr |= __SHIFTIN(7, ATW_WCSR_BLN_MASK); 1007 /* We always want to wake up on link loss or TSFT out of range */ 1008 wcsr |= ATW_WCSR_LSOE|ATW_WCSR_TSFTWE; 1009 ATW_WRITE(sc, ATW_WCSR, wcsr); 1010 1011 DPRINTF(sc, ("%s: %s reg[WCSR] = %08x\n", 1012 device_xname(sc->sc_dev), __func__, ATW_READ(sc, ATW_WCSR))); 1013} 1014 1015/* Turn off power management. Set Rx store-and-forward mode. */ 1016static void 1017atw_cmdr_init(struct atw_softc *sc) 1018{ 1019 uint32_t cmdr; 1020 cmdr = ATW_READ(sc, ATW_CMDR); 1021 cmdr &= ~ATW_CMDR_APM; 1022 cmdr |= ATW_CMDR_RTE; 1023 cmdr &= ~ATW_CMDR_DRT_MASK; 1024 cmdr |= ATW_CMDR_DRT_SF; 1025 1026 ATW_WRITE(sc, ATW_CMDR, cmdr); 1027} 1028 1029static void 1030atw_tofs2_init(struct atw_softc *sc) 1031{ 1032 uint32_t tofs2; 1033 /* XXX this magic can probably be figured out from the RFMD docs */ 1034#ifndef ATW_REFSLAVE 1035 tofs2 = __SHIFTIN(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1036 __SHIFTIN(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1037 __SHIFTIN(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1038 __SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1039 __SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1040 __SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1041 __SHIFTIN(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1042 __SHIFTIN(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1043#else 1044 /* XXX new magic from reference driver source */ 1045 tofs2 = __SHIFTIN(8, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1046 __SHIFTIN(8, ATW_TOFS2_PWR0PAPE_MASK) | /* 8 us */ 1047 __SHIFTIN(1, ATW_TOFS2_PWR1PAPE_MASK) | /* 1 us */ 1048 __SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1049 __SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1050 __SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1051 __SHIFTIN(1, ATW_TOFS2_PWR1PE2_MASK) | /* 1 us */ 1052 __SHIFTIN(8, ATW_TOFS2_PWR0TXPE_MASK); /* 8 us */ 1053#endif 1054 ATW_WRITE(sc, ATW_TOFS2, tofs2); 1055} 1056 1057static void 1058atw_nar_init(struct atw_softc *sc) 1059{ 1060 ATW_WRITE(sc, ATW_NAR, ATW_NAR_SF|ATW_NAR_PB); 1061} 1062 1063static void 1064atw_txlmt_init(struct atw_softc *sc) 1065{ 1066 ATW_WRITE(sc, ATW_TXLMT, __SHIFTIN(512, ATW_TXLMT_MTMLT_MASK) | 1067 __SHIFTIN(1, ATW_TXLMT_SRTYLIM_MASK)); 1068} 1069 1070static void 1071atw_test1_init(struct atw_softc *sc) 1072{ 1073 uint32_t test1; 1074 1075 test1 = ATW_READ(sc, ATW_TEST1); 1076 test1 &= ~(ATW_TEST1_DBGREAD_MASK|ATW_TEST1_CONTROL); 1077 /* XXX magic 0x1 */ 1078 test1 |= __SHIFTIN(0x1, ATW_TEST1_DBGREAD_MASK) | ATW_TEST1_CONTROL; 1079 ATW_WRITE(sc, ATW_TEST1, test1); 1080} 1081 1082static void 1083atw_rf_reset(struct atw_softc *sc) 1084{ 1085 /* XXX this resets an Intersil RF front-end? */ 1086 /* TBD condition on Intersil RFType? */ 1087 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 1088 DELAY(atw_rf_delay1); 1089 ATW_WRITE(sc, ATW_SYNRF, 0); 1090 DELAY(atw_rf_delay2); 1091} 1092 1093/* Set 16 TU max duration for the contention-free period (CFP). */ 1094static void 1095atw_cfp_init(struct atw_softc *sc) 1096{ 1097 uint32_t cfpp; 1098 1099 cfpp = ATW_READ(sc, ATW_CFPP); 1100 cfpp &= ~ATW_CFPP_CFPMD; 1101 cfpp |= __SHIFTIN(16, ATW_CFPP_CFPMD); 1102 ATW_WRITE(sc, ATW_CFPP, cfpp); 1103} 1104 1105static void 1106atw_tofs0_init(struct atw_softc *sc) 1107{ 1108 /* XXX I guess that the Cardbus clock is 22 MHz? 1109 * I am assuming that the role of ATW_TOFS0_USCNT is 1110 * to divide the bus clock to get a 1 MHz clock---the datasheet is not 1111 * very clear on this point. It says in the datasheet that it is 1112 * possible for the ADM8211 to accommodate bus speeds between 22 MHz 1113 * and 33 MHz; maybe this is the way? I see a binary-only driver write 1114 * these values. These values are also the power-on default. 1115 */ 1116 ATW_WRITE(sc, ATW_TOFS0, 1117 __SHIFTIN(22, ATW_TOFS0_USCNT_MASK) | 1118 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 1119} 1120 1121/* Initialize interframe spacing: 802.11b slot time, SIFS, DIFS, EIFS. */ 1122static void 1123atw_ifs_init(struct atw_softc *sc) 1124{ 1125 uint32_t ifst; 1126 /* XXX EIFS=0x64, SIFS=110 are used by the reference driver. 1127 * Go figure. 1128 */ 1129 ifst = __SHIFTIN(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 1130 __SHIFTIN(22 * 10 /* IEEE80211_DUR_DS_SIFS */ /* # of 22 MHz cycles */, 1131 ATW_IFST_SIFS_MASK) | 1132 __SHIFTIN(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1133 __SHIFTIN(IEEE80211_DUR_DS_EIFS, ATW_IFST_EIFS_MASK); 1134 1135 ATW_WRITE(sc, ATW_IFST, ifst); 1136} 1137 1138static void 1139atw_response_times_init(struct atw_softc *sc) 1140{ 1141 /* XXX More magic. Relates to ACK timing? The datasheet seems to 1142 * indicate that the MAC expects at least SIFS + MIRT microseconds 1143 * to pass after it transmits a frame that requires a response; 1144 * it waits at most SIFS + MART microseconds for the response. 1145 * Surely this is not the ACK timeout? 1146 */ 1147 ATW_WRITE(sc, ATW_RSPT, __SHIFTIN(0xffff, ATW_RSPT_MART_MASK) | 1148 __SHIFTIN(0xff, ATW_RSPT_MIRT_MASK)); 1149} 1150 1151/* Set up the MMI read/write addresses for the baseband. The Tx/Rx 1152 * engines read and write baseband registers after Rx and before 1153 * Tx, respectively. 1154 */ 1155static void 1156atw_bbp_io_init(struct atw_softc *sc) 1157{ 1158 uint32_t mmiraddr2; 1159 1160 /* XXX The reference driver does this, but is it *really* 1161 * necessary? 1162 */ 1163 switch (sc->sc_rev) { 1164 case ATW_REVISION_AB: 1165 case ATW_REVISION_AF: 1166 mmiraddr2 = 0x0; 1167 break; 1168 default: 1169 mmiraddr2 = ATW_READ(sc, ATW_MMIRADDR2); 1170 mmiraddr2 &= 1171 ~(ATW_MMIRADDR2_PROREXT|ATW_MMIRADDR2_PRORLEN_MASK); 1172 break; 1173 } 1174 1175 switch (sc->sc_bbptype) { 1176 case ATW_BBPTYPE_INTERSIL: 1177 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1178 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1179 mmiraddr2 |= ATW_MMIRADDR2_INTERSIL; 1180 break; 1181 case ATW_BBPTYPE_MARVEL: 1182 /* TBD find out the Marvel settings. */ 1183 break; 1184 case ATW_BBPTYPE_RFMD: 1185 default: 1186 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1187 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1188 mmiraddr2 |= ATW_MMIRADDR2_RFMD; 1189 break; 1190 } 1191 ATW_WRITE(sc, ATW_MMIRADDR2, mmiraddr2); 1192 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1193} 1194 1195/* 1196 * atw_init: [ ifnet interface function ] 1197 * 1198 * Initialize the interface. Must be called at splnet(). 1199 */ 1200int 1201atw_init(struct ifnet *ifp) 1202{ 1203 struct atw_softc *sc = ifp->if_softc; 1204 struct ieee80211com *ic = &sc->sc_ic; 1205 struct atw_txsoft *txs; 1206 struct atw_rxsoft *rxs; 1207 int i, error = 0; 1208 1209 if (device_is_active(sc->sc_dev)) { 1210 /* 1211 * Cancel any pending I/O. 1212 */ 1213 atw_stop(ifp, 0); 1214 } else if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 1215 !device_is_active(sc->sc_dev)) 1216 return 0; 1217 1218 /* 1219 * Reset the chip to a known state. 1220 */ 1221 atw_reset(sc); 1222 1223 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 1224 __func__, ieee80211_chan2ieee(ic, ic->ic_curchan), 1225 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags)); 1226 1227 atw_wcsr_init(sc); 1228 1229 atw_cmdr_init(sc); 1230 1231 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 1232 * 1233 * XXX Set transmit power for ATIM, RTS, Beacon. 1234 */ 1235 ATW_WRITE(sc, ATW_PLCPHD, __SHIFTIN(10, ATW_PLCPHD_SIGNAL_MASK) | 1236 __SHIFTIN(0xb0, ATW_PLCPHD_SERVICE_MASK)); 1237 1238 atw_tofs2_init(sc); 1239 1240 atw_nar_init(sc); 1241 1242 atw_txlmt_init(sc); 1243 1244 atw_test1_init(sc); 1245 1246 atw_rf_reset(sc); 1247 1248 atw_cfp_init(sc); 1249 1250 atw_tofs0_init(sc); 1251 1252 atw_ifs_init(sc); 1253 1254 /* XXX Fall asleep after one second of inactivity. 1255 * XXX A frame may only dribble in for 65536us. 1256 */ 1257 ATW_WRITE(sc, ATW_RMD, 1258 __SHIFTIN(1, ATW_RMD_PCNT) | __SHIFTIN(0xffff, ATW_RMD_RMRD_MASK)); 1259 1260 atw_response_times_init(sc); 1261 1262 atw_bbp_io_init(sc); 1263 1264 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1265 1266 if ((error = atw_rf3000_init(sc)) != 0) 1267 goto out; 1268 1269 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1270 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", device_xname(sc->sc_dev), 1271 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1272 1273 /* 1274 * Initialize the transmit descriptor ring. 1275 */ 1276 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1277 for (i = 0; i < ATW_NTXDESC; i++) { 1278 sc->sc_txdescs[i].at_ctl = 0; 1279 /* no transmit chaining */ 1280 sc->sc_txdescs[i].at_flags = 0 /* ATW_TXFLAG_TCH */; 1281 sc->sc_txdescs[i].at_buf2 = 1282 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1283 } 1284 /* use ring mode */ 1285 sc->sc_txdescs[ATW_NTXDESC - 1].at_flags |= htole32(ATW_TXFLAG_TER); 1286 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1287 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1288 sc->sc_txfree = ATW_NTXDESC; 1289 sc->sc_txnext = 0; 1290 1291 /* 1292 * Initialize the transmit job descriptors. 1293 */ 1294 SIMPLEQ_INIT(&sc->sc_txfreeq); 1295 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1296 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1297 txs = &sc->sc_txsoft[i]; 1298 txs->txs_mbuf = NULL; 1299 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1300 } 1301 1302 /* 1303 * Initialize the receive descriptor and receive job 1304 * descriptor rings. 1305 */ 1306 for (i = 0; i < ATW_NRXDESC; i++) { 1307 rxs = &sc->sc_rxsoft[i]; 1308 if (rxs->rxs_mbuf == NULL) { 1309 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1310 aprint_error_dev(sc->sc_dev, 1311 "unable to allocate or map rx buffer %d, " 1312 "error = %d\n", i, error); 1313 /* 1314 * XXX Should attempt to run with fewer receive 1315 * XXX buffers instead of just failing. 1316 */ 1317 atw_rxdrain(sc); 1318 goto out; 1319 } 1320 } else 1321 atw_init_rxdesc(sc, i); 1322 } 1323 sc->sc_rxptr = 0; 1324 1325 /* 1326 * Initialize the interrupt mask and enable interrupts. 1327 */ 1328 /* normal interrupts */ 1329 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1330 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1331 1332 /* abnormal interrupts */ 1333 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1334 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1335 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1336 1337 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1338 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1339 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1340 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1341 ATW_INTR_TRT; 1342 1343 sc->sc_linkint_mask &= sc->sc_inten; 1344 sc->sc_rxint_mask &= sc->sc_inten; 1345 sc->sc_txint_mask &= sc->sc_inten; 1346 1347 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1348 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1349 1350 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1351 device_xname(sc->sc_dev), ATW_READ(sc, ATW_IER), sc->sc_inten)); 1352 1353 /* 1354 * Give the transmit and receive rings to the ADM8211. 1355 */ 1356 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1357 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1358 1359 sc->sc_txthresh = 0; 1360 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1361 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1362 1363 /* common 802.11 configuration */ 1364 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1365 switch (ic->ic_opmode) { 1366 case IEEE80211_M_STA: 1367 break; 1368 case IEEE80211_M_AHDEMO: /* XXX */ 1369 case IEEE80211_M_IBSS: 1370 ic->ic_flags |= IEEE80211_F_IBSSON; 1371 /*FALLTHROUGH*/ 1372 case IEEE80211_M_HOSTAP: /* XXX */ 1373 break; 1374 case IEEE80211_M_MONITOR: /* XXX */ 1375 break; 1376 } 1377 1378 switch (ic->ic_opmode) { 1379 case IEEE80211_M_AHDEMO: 1380 case IEEE80211_M_HOSTAP: 1381#ifndef IEEE80211_NO_HOSTAP 1382 ic->ic_bss->ni_intval = ic->ic_lintval; 1383 ic->ic_bss->ni_rssi = 0; 1384 ic->ic_bss->ni_rstamp = 0; 1385#endif /* !IEEE80211_NO_HOSTAP */ 1386 break; 1387 default: /* XXX */ 1388 break; 1389 } 1390 1391 sc->sc_wepctl = 0; 1392 1393 atw_write_ssid(sc); 1394 atw_write_sup_rates(sc); 1395 atw_write_wep(sc); 1396 1397 ic->ic_state = IEEE80211_S_INIT; 1398 1399 /* 1400 * Set the receive filter. This will start the transmit and 1401 * receive processes. 1402 */ 1403 atw_filter_setup(sc); 1404 1405 /* 1406 * Start the receive process. 1407 */ 1408 ATW_WRITE(sc, ATW_RDR, 0x1); 1409 1410 /* 1411 * Note that the interface is now running. 1412 */ 1413 ifp->if_flags |= IFF_RUNNING; 1414 1415 /* send no beacons, yet. */ 1416 atw_start_beacon(sc, 0); 1417 1418 if (ic->ic_opmode == IEEE80211_M_MONITOR) 1419 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1420 else 1421 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1422 out: 1423 if (error) { 1424 ifp->if_flags &= ~IFF_RUNNING; 1425 sc->sc_tx_timer = 0; 1426 ifp->if_timer = 0; 1427 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1428 } 1429#ifdef ATW_DEBUG 1430 atw_print_regs(sc, "end of init"); 1431#endif /* ATW_DEBUG */ 1432 1433 return (error); 1434} 1435 1436/* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1437 * 0: MAC control of RF3000/Si4126. 1438 * 1439 * Applies power, or selects RF front-end? Sets reset condition. 1440 * 1441 * TBD support non-RFMD BBP, non-SiLabs synth. 1442 */ 1443static void 1444atw_bbp_io_enable(struct atw_softc *sc, int enable) 1445{ 1446 if (enable) { 1447 ATW_WRITE(sc, ATW_SYNRF, 1448 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1449 DELAY(atw_bbp_io_enable_delay); 1450 } else { 1451 ATW_WRITE(sc, ATW_SYNRF, 0); 1452 DELAY(atw_bbp_io_disable_delay); /* shorter for some reason */ 1453 } 1454} 1455 1456static int 1457atw_tune(struct atw_softc *sc) 1458{ 1459 int rc; 1460 u_int chan; 1461 struct ieee80211com *ic = &sc->sc_ic; 1462 1463 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 1464 if (chan == IEEE80211_CHAN_ANY) 1465 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1466 1467 if (chan == sc->sc_cur_chan) 1468 return 0; 1469 1470 DPRINTF(sc, ("%s: chan %d -> %d\n", device_xname(sc->sc_dev), 1471 sc->sc_cur_chan, chan)); 1472 1473 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1474 1475 atw_si4126_tune(sc, chan); 1476 if ((rc = atw_rf3000_tune(sc, chan)) != 0) 1477 printf("%s: failed to tune channel %d\n", device_xname(sc->sc_dev), 1478 chan); 1479 1480 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1481 DELAY(atw_nar_delay); 1482 ATW_WRITE(sc, ATW_RDR, 0x1); 1483 1484 if (rc == 0) { 1485 sc->sc_cur_chan = chan; 1486 sc->sc_rxtap.ar_chan_freq = sc->sc_txtap.at_chan_freq = 1487 htole16(ic->ic_curchan->ic_freq); 1488 sc->sc_rxtap.ar_chan_flags = sc->sc_txtap.at_chan_flags = 1489 htole16(ic->ic_curchan->ic_flags); 1490 } 1491 1492 return rc; 1493} 1494 1495#ifdef ATW_SYNDEBUG 1496static void 1497atw_si4126_print(struct atw_softc *sc) 1498{ 1499 struct ifnet *ifp = &sc->sc_if; 1500 u_int addr, val; 1501 1502 val = 0; 1503 1504 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1505 return; 1506 1507 for (addr = 0; addr <= 8; addr++) { 1508 printf("%s: synth[%d] = ", device_xname(sc->sc_dev), addr); 1509 if (atw_si4126_read(sc, addr, &val) == 0) { 1510 printf("<unknown> (quitting print-out)\n"); 1511 break; 1512 } 1513 printf("%05x\n", val); 1514 } 1515} 1516#endif /* ATW_SYNDEBUG */ 1517 1518/* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1519 * 1520 * The RF/IF synthesizer produces two reference frequencies for 1521 * the RF2948B transceiver. The first frequency the RF2948B requires 1522 * is two times the so-called "intermediate frequency" (IF). Since 1523 * a SAW filter on the radio fixes the IF at 374 MHz, I program the 1524 * Si4126 to generate IF LO = 374 MHz x 2 = 748 MHz. The second 1525 * frequency required by the transceiver is the radio frequency 1526 * (RF). This is a superheterodyne transceiver; for f(chan) the 1527 * center frequency of the channel we are tuning, RF = f(chan) - 1528 * IF. 1529 * 1530 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1531 * of XIN than the 2-25 MHz mentioned by the datasheet, even *without* 1532 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1533 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1534 */ 1535static void 1536atw_si4126_tune(struct atw_softc *sc, u_int chan) 1537{ 1538 u_int mhz; 1539 u_int R; 1540 u_int32_t gpio; 1541 u_int16_t gain; 1542 1543#ifdef ATW_SYNDEBUG 1544 atw_si4126_print(sc); 1545#endif /* ATW_SYNDEBUG */ 1546 1547 if (chan == 14) 1548 mhz = 2484; 1549 else 1550 mhz = 2412 + 5 * (chan - 1); 1551 1552 /* Tune IF to 748 MHz to suit the IF LO input of the 1553 * RF2494B, which is 2 x IF. No need to set an IF divider 1554 * because an IF in 526 MHz - 952 MHz is allowed. 1555 * 1556 * XIN is 44.000 MHz, so divide it by two to get allowable 1557 * range of 2-25 MHz. SiLabs tells me that this is not 1558 * strictly necessary. 1559 */ 1560 1561 if (atw_xindiv2) 1562 R = 44; 1563 else 1564 R = 88; 1565 1566 /* Power-up RF, IF synthesizers. */ 1567 atw_si4126_write(sc, SI4126_POWER, 1568 SI4126_POWER_PDIB|SI4126_POWER_PDRB); 1569 1570 /* set LPWR, too? */ 1571 atw_si4126_write(sc, SI4126_MAIN, 1572 (atw_xindiv2) ? SI4126_MAIN_XINDIV2 : 0); 1573 1574 /* Set the phase-locked loop gain. If RF2 N > 2047, then 1575 * set KP2 to 1. 1576 * 1577 * REFDIF This is different from the reference driver, which 1578 * always sets SI4126_GAIN to 0. 1579 */ 1580 gain = __SHIFTIN(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1581 1582 atw_si4126_write(sc, SI4126_GAIN, gain); 1583 1584 /* XIN = 44 MHz. 1585 * 1586 * If XINDIV2 = 1, IF = N/(2 * R) * XIN. I choose N = 1496, 1587 * R = 44 so that 1496/(2 * 44) * 44 MHz = 748 MHz. 1588 * 1589 * If XINDIV2 = 0, IF = N/R * XIN. I choose N = 1496, R = 88 1590 * so that 1496/88 * 44 MHz = 748 MHz. 1591 */ 1592 atw_si4126_write(sc, SI4126_IFN, 1496); 1593 1594 atw_si4126_write(sc, SI4126_IFR, R); 1595 1596#ifndef ATW_REFSLAVE 1597 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1598 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1599 * which has no RF1! 1600 */ 1601 atw_si4126_write(sc, SI4126_RF1R, R); 1602 1603 atw_si4126_write(sc, SI4126_RF1N, mhz - 374); 1604#endif 1605 1606 /* N/R * XIN = RF. XIN = 44 MHz. We desire RF = mhz - IF, 1607 * where IF = 374 MHz. Let's divide XIN to 1 MHz. So R = 44. 1608 * Now let's multiply it to mhz. So mhz - IF = N. 1609 */ 1610 atw_si4126_write(sc, SI4126_RF2R, R); 1611 1612 atw_si4126_write(sc, SI4126_RF2N, mhz - 374); 1613 1614 /* wait 100us from power-up for RF, IF to settle */ 1615 DELAY(100); 1616 1617 gpio = ATW_READ(sc, ATW_GPIO); 1618 gpio &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1619 gpio |= __SHIFTIN(1, ATW_GPIO_EN_MASK); 1620 1621 if ((sc->sc_if.if_flags & IFF_LINK1) != 0 && chan != 14) { 1622 /* Set a Prism RF front-end to a special mode for channel 14? 1623 * 1624 * Apparently the SMC2635W needs this, although I don't think 1625 * it has a Prism RF. 1626 */ 1627 gpio |= __SHIFTIN(1, ATW_GPIO_O_MASK); 1628 } 1629 ATW_WRITE(sc, ATW_GPIO, gpio); 1630 1631#ifdef ATW_SYNDEBUG 1632 atw_si4126_print(sc); 1633#endif /* ATW_SYNDEBUG */ 1634} 1635 1636/* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1637 * diversity. 1638 * 1639 * !!! 1640 * !!! Call this w/ Tx/Rx suspended, atw_idle(, ATW_NAR_ST|ATW_NAR_SR). 1641 * !!! 1642 */ 1643static int 1644atw_rf3000_init(struct atw_softc *sc) 1645{ 1646 int rc = 0; 1647 1648 atw_bbp_io_enable(sc, 1); 1649 1650 /* CCA is acquisition sensitive */ 1651 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1652 __SHIFTIN(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK)); 1653 1654 if (rc != 0) 1655 goto out; 1656 1657 /* enable diversity */ 1658 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1659 1660 if (rc != 0) 1661 goto out; 1662 1663 /* sensible setting from a binary-only driver */ 1664 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1665 __SHIFTIN(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1666 1667 if (rc != 0) 1668 goto out; 1669 1670 /* magic from a binary-only driver */ 1671 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1672 __SHIFTIN(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1673 1674 if (rc != 0) 1675 goto out; 1676 1677 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1678 1679 if (rc != 0) 1680 goto out; 1681 1682 /* XXX Reference driver remarks that Abocom sets this to 50. 1683 * Meaning 0x50, I think.... 50 = 0x32, which would set a bit 1684 * in the "reserved" area of register RF3000_OPTIONS1. 1685 */ 1686 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, sc->sc_rf3000_options1); 1687 1688 if (rc != 0) 1689 goto out; 1690 1691 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, sc->sc_rf3000_options2); 1692 1693 if (rc != 0) 1694 goto out; 1695 1696out: 1697 atw_bbp_io_enable(sc, 0); 1698 return rc; 1699} 1700 1701#ifdef ATW_BBPDEBUG 1702static void 1703atw_rf3000_print(struct atw_softc *sc) 1704{ 1705 struct ifnet *ifp = &sc->sc_if; 1706 u_int addr, val; 1707 1708 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1709 return; 1710 1711 for (addr = 0x01; addr <= 0x15; addr++) { 1712 printf("%s: bbp[%d] = \n", device_xname(sc->sc_dev), addr); 1713 if (atw_rf3000_read(sc, addr, &val) != 0) { 1714 printf("<unknown> (quitting print-out)\n"); 1715 break; 1716 } 1717 printf("%08x\n", val); 1718 } 1719} 1720#endif /* ATW_BBPDEBUG */ 1721 1722/* Set the power settings on the BBP for channel `chan'. */ 1723static int 1724atw_rf3000_tune(struct atw_softc *sc, u_int chan) 1725{ 1726 int rc = 0; 1727 u_int32_t reg; 1728 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1729 1730 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1731 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1732 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1733 1734 /* odd channels: LSB, even channels: MSB */ 1735 if (chan % 2 == 1) { 1736 txpower &= 0xFF; 1737 lpf_cutoff &= 0xFF; 1738 lna_gs_thresh &= 0xFF; 1739 } else { 1740 txpower >>= 8; 1741 lpf_cutoff >>= 8; 1742 lna_gs_thresh >>= 8; 1743 } 1744 1745#ifdef ATW_BBPDEBUG 1746 atw_rf3000_print(sc); 1747#endif /* ATW_BBPDEBUG */ 1748 1749 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1750 "lna_gs_thresh %02x\n", 1751 device_xname(sc->sc_dev), chan, txpower, lpf_cutoff, lna_gs_thresh)); 1752 1753 atw_bbp_io_enable(sc, 1); 1754 1755 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1756 __SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1757 goto out; 1758 1759 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1760 goto out; 1761 1762 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1763 goto out; 1764 1765 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1766 1767 if (rc != 0) 1768 goto out; 1769 1770 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1771 1772 if (rc != 0) 1773 goto out; 1774 1775#ifdef ATW_BBPDEBUG 1776 atw_rf3000_print(sc); 1777#endif /* ATW_BBPDEBUG */ 1778 1779out: 1780 atw_bbp_io_enable(sc, 0); 1781 1782 /* set beacon, rts, atim transmit power */ 1783 reg = ATW_READ(sc, ATW_PLCPHD); 1784 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1785 reg |= __SHIFTIN(__SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK), 1786 ATW_PLCPHD_SERVICE_MASK); 1787 ATW_WRITE(sc, ATW_PLCPHD, reg); 1788 DELAY(atw_plcphd_delay); 1789 1790 return rc; 1791} 1792 1793/* Write a register on the RF3000 baseband processor using the 1794 * registers provided by the ADM8211 for this purpose. 1795 * 1796 * Return 0 on success. 1797 */ 1798static int 1799atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1800{ 1801 u_int32_t reg; 1802 int i; 1803 1804 reg = sc->sc_bbpctl_wr | 1805 __SHIFTIN(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1806 __SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1807 1808 for (i = 20000 / atw_pseudo_milli; --i >= 0; ) { 1809 ATW_WRITE(sc, ATW_BBPCTL, reg); 1810 DELAY(2 * atw_pseudo_milli); 1811 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1812 break; 1813 } 1814 1815 if (i < 0) { 1816 printf("%s: BBPCTL still busy\n", device_xname(sc->sc_dev)); 1817 return ETIMEDOUT; 1818 } 1819 return 0; 1820} 1821 1822/* Read a register on the RF3000 baseband processor using the registers 1823 * the ADM8211 provides for this purpose. 1824 * 1825 * The 7-bit register address is addr. Record the 8-bit data in the register 1826 * in *val. 1827 * 1828 * Return 0 on success. 1829 * 1830 * XXX This does not seem to work. The ADM8211 must require more or 1831 * different magic to read the chip than to write it. Possibly some 1832 * of the magic I have derived from a binary-only driver concerns 1833 * the "chip address" (see the RF3000 manual). 1834 */ 1835#ifdef ATW_BBPDEBUG 1836static int 1837atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1838{ 1839 u_int32_t reg; 1840 int i; 1841 1842 for (i = 1000; --i >= 0; ) { 1843 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1844 break; 1845 DELAY(100); 1846 } 1847 1848 if (i < 0) { 1849 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1850 device_xname(sc->sc_dev)); 1851 return ETIMEDOUT; 1852 } 1853 1854 reg = sc->sc_bbpctl_rd | __SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1855 1856 ATW_WRITE(sc, ATW_BBPCTL, reg); 1857 1858 for (i = 1000; --i >= 0; ) { 1859 DELAY(100); 1860 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1861 break; 1862 } 1863 1864 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1865 1866 if (i < 0) { 1867 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1868 device_xname(sc->sc_dev), reg); 1869 return ETIMEDOUT; 1870 } 1871 if (val != NULL) 1872 *val = __SHIFTOUT(reg, ATW_BBPCTL_DATA_MASK); 1873 return 0; 1874} 1875#endif /* ATW_BBPDEBUG */ 1876 1877/* Write a register on the Si4126 RF/IF synthesizer using the registers 1878 * provided by the ADM8211 for that purpose. 1879 * 1880 * val is 18 bits of data, and val is the 4-bit address of the register. 1881 * 1882 * Return 0 on success. 1883 */ 1884static void 1885atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1886{ 1887 uint32_t bits, mask, reg; 1888 const int nbits = 22; 1889 1890 KASSERT((addr & ~__SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); 1891 KASSERT((val & ~__SHIFTOUT_MASK(SI4126_TWI_DATA_MASK)) == 0); 1892 1893 bits = __SHIFTIN(val, SI4126_TWI_DATA_MASK) | 1894 __SHIFTIN(addr, SI4126_TWI_ADDR_MASK); 1895 1896 reg = ATW_SYNRF_SELSYN; 1897 /* reference driver: reset Si4126 serial bus to initial 1898 * conditions? 1899 */ 1900 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1901 ATW_WRITE(sc, ATW_SYNRF, reg); 1902 1903 for (mask = __BIT(nbits - 1); mask != 0; mask >>= 1) { 1904 if ((bits & mask) != 0) 1905 reg |= ATW_SYNRF_SYNDATA; 1906 else 1907 reg &= ~ATW_SYNRF_SYNDATA; 1908 ATW_WRITE(sc, ATW_SYNRF, reg); 1909 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_SYNCLK); 1910 ATW_WRITE(sc, ATW_SYNRF, reg); 1911 } 1912 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1913 ATW_WRITE(sc, ATW_SYNRF, 0x0); 1914} 1915 1916/* Read 18-bit data from the 4-bit address addr in Si4126 1917 * RF synthesizer and write the data to *val. Return 0 on success. 1918 * 1919 * XXX This does not seem to work. The ADM8211 must require more or 1920 * different magic to read the chip than to write it. 1921 */ 1922#ifdef ATW_SYNDEBUG 1923static int 1924atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1925{ 1926 u_int32_t reg; 1927 int i; 1928 1929 KASSERT((addr & ~__SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); 1930 1931 for (i = 1000; --i >= 0; ) { 1932 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1933 break; 1934 DELAY(100); 1935 } 1936 1937 if (i < 0) { 1938 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1939 device_xname(sc->sc_dev)); 1940 return ETIMEDOUT; 1941 } 1942 1943 reg = sc->sc_synctl_rd | __SHIFTIN(addr, ATW_SYNCTL_DATA_MASK); 1944 1945 ATW_WRITE(sc, ATW_SYNCTL, reg); 1946 1947 for (i = 1000; --i >= 0; ) { 1948 DELAY(100); 1949 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1950 break; 1951 } 1952 1953 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1954 1955 if (i < 0) { 1956 printf("%s: atw_si4126_read wrote %#08x, SYNCTL still busy\n", 1957 device_xname(sc->sc_dev), reg); 1958 return ETIMEDOUT; 1959 } 1960 if (val != NULL) 1961 *val = __SHIFTOUT(ATW_READ(sc, ATW_SYNCTL), 1962 ATW_SYNCTL_DATA_MASK); 1963 return 0; 1964} 1965#endif /* ATW_SYNDEBUG */ 1966 1967/* XXX is the endianness correct? test. */ 1968#define atw_calchash(addr) \ 1969 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & __BITS(5, 0)) 1970 1971/* 1972 * atw_filter_setup: 1973 * 1974 * Set the ADM8211's receive filter. 1975 */ 1976static void 1977atw_filter_setup(struct atw_softc *sc) 1978{ 1979 struct ieee80211com *ic = &sc->sc_ic; 1980 struct ethercom *ec = &sc->sc_ec; 1981 struct ifnet *ifp = &sc->sc_if; 1982 int hash; 1983 u_int32_t hashes[2]; 1984 struct ether_multi *enm; 1985 struct ether_multistep step; 1986 1987 /* According to comments in tlp_al981_filter_setup 1988 * (dev/ic/tulip.c) the ADMtek AL981 does not like for its 1989 * multicast filter to be set while it is running. Hopefully 1990 * the ADM8211 is not the same! 1991 */ 1992 if ((ifp->if_flags & IFF_RUNNING) != 0) 1993 atw_idle(sc, ATW_NAR_SR); 1994 1995 sc->sc_opmode &= ~(ATW_NAR_PB|ATW_NAR_PR|ATW_NAR_MM); 1996 ifp->if_flags &= ~IFF_ALLMULTI; 1997 1998 /* XXX in scan mode, do not filter packets. Maybe this is 1999 * unnecessary. 2000 */ 2001 if (ic->ic_state == IEEE80211_S_SCAN || 2002 (ifp->if_flags & IFF_PROMISC) != 0) { 2003 sc->sc_opmode |= ATW_NAR_PR | ATW_NAR_PB; 2004 goto allmulti; 2005 } 2006 2007 hashes[0] = hashes[1] = 0x0; 2008 2009 /* 2010 * Program the 64-bit multicast hash filter. 2011 */ 2012 ETHER_FIRST_MULTI(step, ec, enm); 2013 while (enm != NULL) { 2014 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2015 ETHER_ADDR_LEN) != 0) 2016 goto allmulti; 2017 2018 hash = atw_calchash(enm->enm_addrlo); 2019 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2020 ETHER_NEXT_MULTI(step, enm); 2021 sc->sc_opmode |= ATW_NAR_MM; 2022 } 2023 ifp->if_flags &= ~IFF_ALLMULTI; 2024 goto setit; 2025 2026allmulti: 2027 sc->sc_opmode |= ATW_NAR_MM; 2028 ifp->if_flags |= IFF_ALLMULTI; 2029 hashes[0] = hashes[1] = 0xffffffff; 2030 2031setit: 2032 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 2033 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 2034 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2035 DELAY(atw_nar_delay); 2036 ATW_WRITE(sc, ATW_RDR, 0x1); 2037 2038 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", device_xname(sc->sc_dev), 2039 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 2040} 2041 2042/* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 2043 * a beacon's BSSID and SSID against the preferred BSSID and SSID 2044 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 2045 * no beacon with the preferred BSSID and SSID in the number of 2046 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 2047 */ 2048static void 2049atw_write_bssid(struct atw_softc *sc) 2050{ 2051 struct ieee80211com *ic = &sc->sc_ic; 2052 u_int8_t *bssid; 2053 2054 bssid = ic->ic_bss->ni_bssid; 2055 2056 ATW_WRITE(sc, ATW_BSSID0, 2057 __SHIFTIN(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 2058 __SHIFTIN(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 2059 __SHIFTIN(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 2060 __SHIFTIN(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 2061 2062 ATW_WRITE(sc, ATW_ABDA1, 2063 (ATW_READ(sc, ATW_ABDA1) & 2064 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 2065 __SHIFTIN(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 2066 __SHIFTIN(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 2067 2068 DPRINTF(sc, ("%s: BSSID %s -> ", device_xname(sc->sc_dev), 2069 ether_sprintf(sc->sc_bssid))); 2070 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 2071 2072 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 2073} 2074 2075/* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 2076 * 16-bit word. 2077 */ 2078static void 2079atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) 2080{ 2081 u_int i; 2082 u_int8_t *ptr; 2083 2084 memcpy(&sc->sc_sram[ofs], buf, buflen); 2085 2086 KASSERT(ofs % 2 == 0 && buflen % 2 == 0); 2087 2088 KASSERT(buflen + ofs <= sc->sc_sramlen); 2089 2090 ptr = &sc->sc_sram[ofs]; 2091 2092 for (i = 0; i < buflen; i += 2) { 2093 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 2094 __SHIFTIN((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 2095 DELAY(atw_writewep_delay); 2096 2097 ATW_WRITE(sc, ATW_WESK, 2098 __SHIFTIN((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 2099 DELAY(atw_writewep_delay); 2100 } 2101 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 2102 2103 if (sc->sc_if.if_flags & IFF_DEBUG) { 2104 int n_octets = 0; 2105 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 2106 device_xname(sc->sc_dev), buflen, ofs, sc->sc_wepctl); 2107 for (i = 0; i < buflen; i++) { 2108 printf(" %02x", ptr[i]); 2109 if (++n_octets % 24 == 0) 2110 printf("\n"); 2111 } 2112 if (n_octets % 24 != 0) 2113 printf("\n"); 2114 } 2115} 2116 2117static int 2118atw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 2119{ 2120 struct atw_softc *sc = ic->ic_ifp->if_softc; 2121 u_int keyix = k->wk_keyix; 2122 2123 DPRINTF(sc, ("%s: delete key %u\n", __func__, keyix)); 2124 2125 if (keyix >= IEEE80211_WEP_NKID) 2126 return 0; 2127 if (k->wk_keylen != 0) 2128 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2129 2130 return 1; 2131} 2132 2133static int 2134atw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 2135 const u_int8_t mac[IEEE80211_ADDR_LEN]) 2136{ 2137 struct atw_softc *sc = ic->ic_ifp->if_softc; 2138 2139 DPRINTF(sc, ("%s: set key %u\n", __func__, k->wk_keyix)); 2140 2141 if (k->wk_keyix >= IEEE80211_WEP_NKID) 2142 return 0; 2143 2144 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2145 2146 return 1; 2147} 2148 2149static void 2150atw_key_update_begin(struct ieee80211com *ic) 2151{ 2152#ifdef ATW_DEBUG 2153 struct ifnet *ifp = ic->ic_ifp; 2154 struct atw_softc *sc = ifp->if_softc; 2155#endif 2156 2157 DPRINTF(sc, ("%s:\n", __func__)); 2158} 2159 2160static void 2161atw_key_update_end(struct ieee80211com *ic) 2162{ 2163 struct ifnet *ifp = ic->ic_ifp; 2164 struct atw_softc *sc = ifp->if_softc; 2165 2166 DPRINTF(sc, ("%s:\n", __func__)); 2167 2168 if ((sc->sc_flags & ATWF_WEP_SRAM_VALID) != 0) 2169 return; 2170 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 2171 return; 2172 atw_idle(sc, ATW_NAR_SR | ATW_NAR_ST); 2173 atw_write_wep(sc); 2174 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2175 DELAY(atw_nar_delay); 2176 ATW_WRITE(sc, ATW_RDR, 0x1); 2177} 2178 2179/* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2180static void 2181atw_write_wep(struct atw_softc *sc) 2182{ 2183#if 0 2184 struct ieee80211com *ic = &sc->sc_ic; 2185 u_int32_t reg; 2186 int i; 2187#endif 2188 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2189 u_int8_t buf[IEEE80211_WEP_NKID] 2190 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2191 2192 sc->sc_wepctl = 0; 2193 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2194 2195 memset(&buf[0][0], 0, sizeof(buf)); 2196 2197#if 0 2198 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2199 if (ic->ic_nw_keys[i].wk_keylen > 5) { 2200 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2201 } else if (ic->ic_nw_keys[i].wk_keylen != 0) { 2202 buf[i][1] = ATW_WEP_ENABLED; 2203 } else { 2204 buf[i][1] = 0; 2205 continue; 2206 } 2207 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2208 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2209 ic->ic_nw_keys[i].wk_keylen - 1); 2210 } 2211 2212 reg = ATW_READ(sc, ATW_MACTEST); 2213 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2214 reg &= ~ATW_MACTEST_KEYID_MASK; 2215 reg |= __SHIFTIN(ic->ic_def_txkey, ATW_MACTEST_KEYID_MASK); 2216 ATW_WRITE(sc, ATW_MACTEST, reg); 2217 2218 if ((ic->ic_flags & IEEE80211_F_PRIVACY) != 0) 2219 sc->sc_wepctl |= ATW_WEPCTL_WEPENABLE; 2220 2221 switch (sc->sc_rev) { 2222 case ATW_REVISION_AB: 2223 case ATW_REVISION_AF: 2224 /* Bypass WEP on Rx. */ 2225 sc->sc_wepctl |= ATW_WEPCTL_WEPRXBYP; 2226 break; 2227 default: 2228 break; 2229 } 2230#endif 2231 2232 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2233 sizeof(buf)); 2234 2235 sc->sc_flags |= ATWF_WEP_SRAM_VALID; 2236} 2237 2238static void 2239atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2240 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2241{ 2242 struct atw_softc *sc = (struct atw_softc *)ic->ic_ifp->if_softc; 2243 2244 /* The ADM8211A answers probe requests. TBD ADM8211B/C. */ 2245 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_REQ) 2246 return; 2247 2248 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2249 2250 switch (subtype) { 2251 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2252 case IEEE80211_FC0_SUBTYPE_BEACON: 2253 if (ic->ic_opmode == IEEE80211_M_IBSS && 2254 ic->ic_state == IEEE80211_S_RUN) { 2255 if (le64toh(ni->ni_tstamp.tsf) >= atw_get_tsft(sc)) 2256 (void)ieee80211_ibss_merge(ni); 2257 } 2258 break; 2259 default: 2260 break; 2261 } 2262 return; 2263} 2264 2265/* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2266 * In ad hoc mode, the SSID is written to the beacons sent by the 2267 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2268 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2269 * indications. 2270 */ 2271static void 2272atw_write_ssid(struct atw_softc *sc) 2273{ 2274 struct ieee80211com *ic = &sc->sc_ic; 2275 /* 34 bytes are reserved in ADM8211 SRAM for the SSID, but 2276 * it only expects the element length, not its ID. 2277 */ 2278 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2279 2280 memset(buf, 0, sizeof(buf)); 2281 buf[0] = ic->ic_bss->ni_esslen; 2282 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2283 2284 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, 2285 roundup(1 + ic->ic_bss->ni_esslen, 2)); 2286} 2287 2288/* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2289 * In ad hoc mode, the supported rates are written to beacons sent by the 2290 * ADM8211. 2291 */ 2292static void 2293atw_write_sup_rates(struct atw_softc *sc) 2294{ 2295 struct ieee80211com *ic = &sc->sc_ic; 2296 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2297 * supported rates 2298 */ 2299 u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; 2300 2301 memset(buf, 0, sizeof(buf)); 2302 2303 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2304 2305 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2306 ic->ic_bss->ni_rates.rs_nrates); 2307 2308 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2309} 2310 2311/* Start/stop sending beacons. */ 2312void 2313atw_start_beacon(struct atw_softc *sc, int start) 2314{ 2315 struct ieee80211com *ic = &sc->sc_ic; 2316 uint16_t chan; 2317 uint32_t bcnt, bpli, cap0, cap1, capinfo; 2318 size_t len; 2319 2320 if (!device_is_active(sc->sc_dev)) 2321 return; 2322 2323 /* start beacons */ 2324 len = sizeof(struct ieee80211_frame) + 2325 8 /* timestamp */ + 2 /* beacon interval */ + 2326 2 /* capability info */ + 2327 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2328 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2329 3 /* DS parameters */ + 2330 IEEE80211_CRC_LEN; 2331 2332 bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2333 cap0 = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 2334 cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2335 2336 ATW_WRITE(sc, ATW_BCNT, bcnt); 2337 ATW_WRITE(sc, ATW_CAP1, cap1); 2338 2339 if (!start) 2340 return; 2341 2342 /* TBD use ni_capinfo */ 2343 2344 capinfo = 0; 2345 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 2346 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2347 if (ic->ic_flags & IEEE80211_F_PRIVACY) 2348 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2349 2350 switch (ic->ic_opmode) { 2351 case IEEE80211_M_IBSS: 2352 len += 4; /* IBSS parameters */ 2353 capinfo |= IEEE80211_CAPINFO_IBSS; 2354 break; 2355 case IEEE80211_M_HOSTAP: 2356 /* XXX 6-byte minimum TIM */ 2357 len += atw_beacon_len_adjust; 2358 capinfo |= IEEE80211_CAPINFO_ESS; 2359 break; 2360 default: 2361 return; 2362 } 2363 2364 /* set listen interval 2365 * XXX do software units agree w/ hardware? 2366 */ 2367 bpli = __SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2368 __SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK); 2369 2370 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 2371 2372 bcnt |= __SHIFTIN(len, ATW_BCNT_BCNT_MASK); 2373 cap0 |= __SHIFTIN(chan, ATW_CAP0_CHN_MASK); 2374 cap1 |= __SHIFTIN(capinfo, ATW_CAP1_CAPI_MASK); 2375 2376 ATW_WRITE(sc, ATW_BCNT, bcnt); 2377 ATW_WRITE(sc, ATW_BPLI, bpli); 2378 ATW_WRITE(sc, ATW_CAP0, cap0); 2379 ATW_WRITE(sc, ATW_CAP1, cap1); 2380 2381 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2382 device_xname(sc->sc_dev), bcnt)); 2383 2384 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2385 device_xname(sc->sc_dev), cap1)); 2386} 2387 2388/* Return the 32 lsb of the last TSFT divisible by ival. */ 2389static inline uint32_t 2390atw_last_even_tsft(uint32_t tsfth, uint32_t tsftl, uint32_t ival) 2391{ 2392 /* Following the reference driver's lead, I compute 2393 * 2394 * (uint32_t)((((uint64_t)tsfth << 32) | tsftl) % ival) 2395 * 2396 * without using 64-bit arithmetic, using the following 2397 * relationship: 2398 * 2399 * (0x100000000 * H + L) % m 2400 * = ((0x100000000 % m) * H + L) % m 2401 * = (((0xffffffff + 1) % m) * H + L) % m 2402 * = ((0xffffffff % m + 1 % m) * H + L) % m 2403 * = ((0xffffffff % m + 1) * H + L) % m 2404 */ 2405 return ((0xFFFFFFFF % ival + 1) * tsfth + tsftl) % ival; 2406} 2407 2408static uint64_t 2409atw_get_tsft(struct atw_softc *sc) 2410{ 2411 int i; 2412 uint32_t tsfth, tsftl; 2413 for (i = 0; i < 2; i++) { 2414 tsfth = ATW_READ(sc, ATW_TSFTH); 2415 tsftl = ATW_READ(sc, ATW_TSFTL); 2416 if (ATW_READ(sc, ATW_TSFTH) == tsfth) 2417 break; 2418 } 2419 return ((uint64_t)tsfth << 32) | tsftl; 2420} 2421 2422/* If we've created an IBSS, write the TSF time in the ADM8211 to 2423 * the ieee80211com. 2424 * 2425 * Predict the next target beacon transmission time (TBTT) and 2426 * write it to the ADM8211. 2427 */ 2428static void 2429atw_predict_beacon(struct atw_softc *sc) 2430{ 2431#define TBTTOFS 20 /* TU */ 2432 2433 struct ieee80211com *ic = &sc->sc_ic; 2434 uint64_t tsft; 2435 uint32_t ival, past_even, tbtt, tsfth, tsftl; 2436 union { 2437 uint64_t word; 2438 uint8_t tstamp[8]; 2439 } u; 2440 2441 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2442 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2443 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2444 tsft = atw_get_tsft(sc); 2445 u.word = htole64(tsft); 2446 (void)memcpy(&ic->ic_bss->ni_tstamp, &u.tstamp[0], 2447 sizeof(ic->ic_bss->ni_tstamp)); 2448 } else 2449 tsft = le64toh(ic->ic_bss->ni_tstamp.tsf); 2450 2451 ival = ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2452 2453 tsftl = tsft & 0xFFFFFFFF; 2454 tsfth = tsft >> 32; 2455 2456 /* We sent/received the last beacon `past' microseconds 2457 * after the interval divided the TSF timer. 2458 */ 2459 past_even = tsftl - atw_last_even_tsft(tsfth, tsftl, ival); 2460 2461 /* Skip ten beacons so that the TBTT cannot pass before 2462 * we've programmed it. Ten is an arbitrary number. 2463 */ 2464 tbtt = past_even + ival * 10; 2465 2466 ATW_WRITE(sc, ATW_TOFS1, 2467 __SHIFTIN(1, ATW_TOFS1_TSFTOFSR_MASK) | 2468 __SHIFTIN(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2469 __SHIFTIN(__SHIFTOUT(tbtt - TBTTOFS * IEEE80211_DUR_TU, 2470 ATW_TBTTPRE_MASK), ATW_TOFS1_TBTTPRE_MASK)); 2471#undef TBTTOFS 2472} 2473 2474static void 2475atw_next_scan(void *arg) 2476{ 2477 struct atw_softc *sc = arg; 2478 struct ieee80211com *ic = &sc->sc_ic; 2479 int s; 2480 2481 /* don't call atw_start w/o network interrupts blocked */ 2482 s = splnet(); 2483 if (ic->ic_state == IEEE80211_S_SCAN) 2484 ieee80211_next_scan(ic); 2485 splx(s); 2486} 2487 2488/* Synchronize the hardware state with the software state. */ 2489static int 2490atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2491{ 2492 struct ifnet *ifp = ic->ic_ifp; 2493 struct atw_softc *sc = ifp->if_softc; 2494 int error = 0; 2495 2496 callout_stop(&sc->sc_scan_ch); 2497 2498 switch (nstate) { 2499 case IEEE80211_S_AUTH: 2500 case IEEE80211_S_ASSOC: 2501 atw_write_bssid(sc); 2502 error = atw_tune(sc); 2503 break; 2504 case IEEE80211_S_INIT: 2505 callout_stop(&sc->sc_scan_ch); 2506 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2507 atw_start_beacon(sc, 0); 2508 break; 2509 case IEEE80211_S_SCAN: 2510 error = atw_tune(sc); 2511 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2512 atw_next_scan, sc); 2513 break; 2514 case IEEE80211_S_RUN: 2515 error = atw_tune(sc); 2516 atw_write_bssid(sc); 2517 atw_write_ssid(sc); 2518 atw_write_sup_rates(sc); 2519 2520 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2521 ic->ic_opmode == IEEE80211_M_MONITOR) 2522 break; 2523 2524 /* set listen interval 2525 * XXX do software units agree w/ hardware? 2526 */ 2527 ATW_WRITE(sc, ATW_BPLI, 2528 __SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2529 __SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, 2530 ATW_BPLI_LI_MASK)); 2531 2532 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", device_xname(sc->sc_dev), 2533 ATW_READ(sc, ATW_BPLI))); 2534 2535 atw_predict_beacon(sc); 2536 2537 switch (ic->ic_opmode) { 2538 case IEEE80211_M_AHDEMO: 2539 case IEEE80211_M_HOSTAP: 2540 case IEEE80211_M_IBSS: 2541 atw_start_beacon(sc, 1); 2542 break; 2543 case IEEE80211_M_MONITOR: 2544 case IEEE80211_M_STA: 2545 break; 2546 } 2547 2548 break; 2549 } 2550 return (error != 0) ? error : (*sc->sc_newstate)(ic, nstate, arg); 2551} 2552 2553/* 2554 * atw_add_rxbuf: 2555 * 2556 * Add a receive buffer to the indicated descriptor. 2557 */ 2558int 2559atw_add_rxbuf(struct atw_softc *sc, int idx) 2560{ 2561 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2562 struct mbuf *m; 2563 int error; 2564 2565 MGETHDR(m, M_DONTWAIT, MT_DATA); 2566 if (m == NULL) 2567 return (ENOBUFS); 2568 2569 MCLGET(m, M_DONTWAIT); 2570 if ((m->m_flags & M_EXT) == 0) { 2571 m_freem(m); 2572 return (ENOBUFS); 2573 } 2574 2575 if (rxs->rxs_mbuf != NULL) 2576 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2577 2578 rxs->rxs_mbuf = m; 2579 2580 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2581 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2582 BUS_DMA_READ|BUS_DMA_NOWAIT); 2583 if (error) { 2584 aprint_error_dev(sc->sc_dev, "can't load rx DMA map %d, error = %d\n", 2585 idx, error); 2586 panic("atw_add_rxbuf"); /* XXX */ 2587 } 2588 2589 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2590 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2591 2592 atw_init_rxdesc(sc, idx); 2593 2594 return (0); 2595} 2596 2597/* 2598 * Release any queued transmit buffers. 2599 */ 2600void 2601atw_txdrain(struct atw_softc *sc) 2602{ 2603 struct atw_txsoft *txs; 2604 2605 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2606 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2607 if (txs->txs_mbuf != NULL) { 2608 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2609 m_freem(txs->txs_mbuf); 2610 txs->txs_mbuf = NULL; 2611 } 2612 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2613 sc->sc_txfree += txs->txs_ndescs; 2614 } 2615 2616 KASSERT((sc->sc_if.if_flags & IFF_RUNNING) == 0 || 2617 !(SIMPLEQ_EMPTY(&sc->sc_txfreeq) || 2618 sc->sc_txfree != ATW_NTXDESC)); 2619 sc->sc_if.if_flags &= ~IFF_OACTIVE; 2620 sc->sc_tx_timer = 0; 2621} 2622 2623/* 2624 * atw_stop: [ ifnet interface function ] 2625 * 2626 * Stop transmission on the interface. 2627 */ 2628void 2629atw_stop(struct ifnet *ifp, int disable) 2630{ 2631 struct atw_softc *sc = ifp->if_softc; 2632 struct ieee80211com *ic = &sc->sc_ic; 2633 2634 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2635 2636 if (device_is_active(sc->sc_dev)) { 2637 /* Disable interrupts. */ 2638 ATW_WRITE(sc, ATW_IER, 0); 2639 2640 /* Stop the transmit and receive processes. */ 2641 ATW_WRITE(sc, ATW_NAR, 0); 2642 DELAY(atw_nar_delay); 2643 ATW_WRITE(sc, ATW_TDBD, 0); 2644 ATW_WRITE(sc, ATW_TDBP, 0); 2645 ATW_WRITE(sc, ATW_RDB, 0); 2646 } 2647 2648 sc->sc_opmode = 0; 2649 2650 atw_txdrain(sc); 2651 2652 /* 2653 * Mark the interface down and cancel the watchdog timer. 2654 */ 2655 ifp->if_flags &= ~IFF_RUNNING; 2656 ifp->if_timer = 0; 2657 2658 if (disable) 2659 pmf_device_suspend(sc->sc_dev, &sc->sc_qual); 2660} 2661 2662/* 2663 * atw_rxdrain: 2664 * 2665 * Drain the receive queue. 2666 */ 2667void 2668atw_rxdrain(struct atw_softc *sc) 2669{ 2670 struct atw_rxsoft *rxs; 2671 int i; 2672 2673 for (i = 0; i < ATW_NRXDESC; i++) { 2674 rxs = &sc->sc_rxsoft[i]; 2675 if (rxs->rxs_mbuf == NULL) 2676 continue; 2677 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2678 m_freem(rxs->rxs_mbuf); 2679 rxs->rxs_mbuf = NULL; 2680 } 2681} 2682 2683/* 2684 * atw_detach: 2685 * 2686 * Detach an ADM8211 interface. 2687 */ 2688int 2689atw_detach(struct atw_softc *sc) 2690{ 2691 struct ifnet *ifp = &sc->sc_if; 2692 struct atw_rxsoft *rxs; 2693 struct atw_txsoft *txs; 2694 int i; 2695 2696 /* 2697 * Succeed now if there isn't any work to do. 2698 */ 2699 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2700 return (0); 2701 2702 pmf_device_deregister(sc->sc_dev); 2703 2704 callout_stop(&sc->sc_scan_ch); 2705 2706 ieee80211_ifdetach(&sc->sc_ic); 2707 if_detach(ifp); 2708 2709 for (i = 0; i < ATW_NRXDESC; i++) { 2710 rxs = &sc->sc_rxsoft[i]; 2711 if (rxs->rxs_mbuf != NULL) { 2712 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2713 m_freem(rxs->rxs_mbuf); 2714 rxs->rxs_mbuf = NULL; 2715 } 2716 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2717 } 2718 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2719 txs = &sc->sc_txsoft[i]; 2720 if (txs->txs_mbuf != NULL) { 2721 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2722 m_freem(txs->txs_mbuf); 2723 txs->txs_mbuf = NULL; 2724 } 2725 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2726 } 2727 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2728 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2729 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 2730 sizeof(struct atw_control_data)); 2731 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2732 2733 if (sc->sc_srom) 2734 free(sc->sc_srom, M_DEVBUF); 2735 2736 atw_evcnt_detach(sc); 2737 2738 if (sc->sc_soft_ih != NULL) { 2739 softint_disestablish(sc->sc_soft_ih); 2740 sc->sc_soft_ih = NULL; 2741 } 2742 2743 return (0); 2744} 2745 2746/* atw_shutdown: make sure the interface is stopped at reboot time. */ 2747bool 2748atw_shutdown(device_t self, int flags) 2749{ 2750 struct atw_softc *sc = device_private(self); 2751 2752 atw_stop(&sc->sc_if, 1); 2753 return true; 2754} 2755 2756#if 0 2757static void 2758atw_workaround1(struct atw_softc *sc) 2759{ 2760 uint32_t test1; 2761 2762 test1 = ATW_READ(sc, ATW_TEST1); 2763 2764 sc->sc_misc_ev.ev_count++; 2765 2766 if ((test1 & ATW_TEST1_RXPKT1IN) != 0) { 2767 sc->sc_rxpkt1in_ev.ev_count++; 2768 return; 2769 } 2770 if (__SHIFTOUT(test1, ATW_TEST1_RRA_MASK) == 2771 __SHIFTOUT(test1, ATW_TEST1_RWA_MASK)) { 2772 sc->sc_rxamatch_ev.ev_count++; 2773 return; 2774 } 2775 sc->sc_workaround1_ev.ev_count++; 2776 (void)atw_init(&sc->sc_if); 2777} 2778#endif 2779 2780int 2781atw_intr(void *arg) 2782{ 2783 struct atw_softc *sc = arg; 2784 struct ifnet *ifp = &sc->sc_if; 2785 uint32_t status; 2786 2787#ifdef DEBUG 2788 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 2789 panic("%s: atw_intr: not enabled", device_xname(sc->sc_dev)); 2790#endif 2791 2792 /* 2793 * If the interface isn't running, the interrupt couldn't 2794 * possibly have come from us. 2795 */ 2796 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2797 !device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 2798 return (0); 2799 2800 status = ATW_READ(sc, ATW_STSR); 2801 if (status == 0) 2802 return 0; 2803 2804 if ((status & sc->sc_inten) == 0) { 2805 ATW_WRITE(sc, ATW_STSR, status); 2806 return 0; 2807 } 2808 2809 /* Disable interrupts */ 2810 ATW_WRITE(sc, ATW_IER, 0); 2811 2812 softint_schedule(sc->sc_soft_ih); 2813 return 1; 2814} 2815 2816void 2817atw_softintr(void *arg) 2818{ 2819 struct atw_softc *sc = arg; 2820 struct ifnet *ifp = &sc->sc_if; 2821 uint32_t status, rxstatus, txstatus, linkstatus; 2822 int txthresh, s; 2823 2824 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2825 !device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 2826 return; 2827 2828 for (;;) { 2829 status = ATW_READ(sc, ATW_STSR); 2830 2831 if (status) 2832 ATW_WRITE(sc, ATW_STSR, status); 2833 2834#ifdef ATW_DEBUG 2835#define PRINTINTR(flag) do { \ 2836 if ((status & flag) != 0) { \ 2837 printf("%s" #flag, delim); \ 2838 delim = ","; \ 2839 } \ 2840} while (0) 2841 2842 if (atw_debug > 1 && status) { 2843 const char *delim = "<"; 2844 2845 printf("%s: reg[STSR] = %x", 2846 device_xname(sc->sc_dev), status); 2847 2848 PRINTINTR(ATW_INTR_FBE); 2849 PRINTINTR(ATW_INTR_LINKOFF); 2850 PRINTINTR(ATW_INTR_LINKON); 2851 PRINTINTR(ATW_INTR_RCI); 2852 PRINTINTR(ATW_INTR_RDU); 2853 PRINTINTR(ATW_INTR_REIS); 2854 PRINTINTR(ATW_INTR_RPS); 2855 PRINTINTR(ATW_INTR_TCI); 2856 PRINTINTR(ATW_INTR_TDU); 2857 PRINTINTR(ATW_INTR_TLT); 2858 PRINTINTR(ATW_INTR_TPS); 2859 PRINTINTR(ATW_INTR_TRT); 2860 PRINTINTR(ATW_INTR_TUF); 2861 PRINTINTR(ATW_INTR_BCNTC); 2862 PRINTINTR(ATW_INTR_ATIME); 2863 PRINTINTR(ATW_INTR_TBTT); 2864 PRINTINTR(ATW_INTR_TSCZ); 2865 PRINTINTR(ATW_INTR_TSFTF); 2866 printf(">\n"); 2867 } 2868#undef PRINTINTR 2869#endif /* ATW_DEBUG */ 2870 2871 if ((status & sc->sc_inten) == 0) 2872 break; 2873 2874 rxstatus = status & sc->sc_rxint_mask; 2875 txstatus = status & sc->sc_txint_mask; 2876 linkstatus = status & sc->sc_linkint_mask; 2877 2878 if (linkstatus) { 2879 atw_linkintr(sc, linkstatus); 2880 } 2881 2882 if (rxstatus) { 2883 /* Grab any new packets. */ 2884 atw_rxintr(sc); 2885 2886 if (rxstatus & ATW_INTR_RDU) { 2887 printf("%s: receive ring overrun\n", 2888 device_xname(sc->sc_dev)); 2889 /* Get the receive process going again. */ 2890 ATW_WRITE(sc, ATW_RDR, 0x1); 2891 } 2892 } 2893 2894 if (txstatus) { 2895 /* Sweep up transmit descriptors. */ 2896 atw_txintr(sc, txstatus); 2897 2898 if (txstatus & ATW_INTR_TLT) { 2899 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2900 device_xname(sc->sc_dev))); 2901 (void)atw_init(&sc->sc_if); 2902 } 2903 2904 if (txstatus & ATW_INTR_TRT) { 2905 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2906 device_xname(sc->sc_dev))); 2907 } 2908 2909 /* If Tx under-run, increase our transmit threshold 2910 * if another is available. 2911 */ 2912 txthresh = sc->sc_txthresh + 1; 2913 if ((txstatus & ATW_INTR_TUF) && 2914 sc->sc_txth[txthresh].txth_name != NULL) { 2915 /* Idle the transmit process. */ 2916 atw_idle(sc, ATW_NAR_ST); 2917 2918 sc->sc_txthresh = txthresh; 2919 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2920 sc->sc_opmode |= 2921 sc->sc_txth[txthresh].txth_opmode; 2922 printf("%s: transmit underrun; new " 2923 "threshold: %s\n", device_xname(sc->sc_dev), 2924 sc->sc_txth[txthresh].txth_name); 2925 2926 /* Set the new threshold and restart 2927 * the transmit process. 2928 */ 2929 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2930 DELAY(atw_nar_delay); 2931 ATW_WRITE(sc, ATW_TDR, 0x1); 2932 /* XXX Log every Nth underrun from 2933 * XXX now on? 2934 */ 2935 } 2936 } 2937 2938 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2939 if (status & ATW_INTR_TPS) 2940 printf("%s: transmit process stopped\n", 2941 device_xname(sc->sc_dev)); 2942 if (status & ATW_INTR_RPS) 2943 printf("%s: receive process stopped\n", 2944 device_xname(sc->sc_dev)); 2945 s = splnet(); 2946 (void)atw_init(ifp); 2947 splx(s); 2948 break; 2949 } 2950 2951 if (status & ATW_INTR_FBE) { 2952 aprint_error_dev(sc->sc_dev, "fatal bus error\n"); 2953 s = splnet(); 2954 (void)atw_init(ifp); 2955 splx(s); 2956 break; 2957 } 2958 2959 /* 2960 * Not handled: 2961 * 2962 * Transmit buffer unavailable -- normal 2963 * condition, nothing to do, really. 2964 * 2965 * Early receive interrupt -- not available on 2966 * all chips, we just use RI. We also only 2967 * use single-segment receive DMA, so this 2968 * is mostly useless. 2969 * 2970 * TBD others 2971 */ 2972 } 2973 2974 /* Try to get more packets going. */ 2975 s = splnet(); 2976 atw_start(ifp); 2977 splx(s); 2978 2979 /* Enable interrupts */ 2980 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 2981} 2982 2983/* 2984 * atw_idle: 2985 * 2986 * Cause the transmit and/or receive processes to go idle. 2987 * 2988 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2989 * process in STSR if I clear SR or ST after the process has already 2990 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2991 * do not seem to be too reliable. Perhaps I have the sense of the 2992 * Rx bits switched with the Tx bits? 2993 */ 2994void 2995atw_idle(struct atw_softc *sc, u_int32_t bits) 2996{ 2997 u_int32_t ackmask = 0, opmode, stsr, test0; 2998 int i, s; 2999 3000 s = splnet(); 3001 3002 opmode = sc->sc_opmode & ~bits; 3003 3004 if (bits & ATW_NAR_SR) 3005 ackmask |= ATW_INTR_RPS; 3006 3007 if (bits & ATW_NAR_ST) { 3008 ackmask |= ATW_INTR_TPS; 3009 /* set ATW_NAR_HF to flush TX FIFO. */ 3010 opmode |= ATW_NAR_HF; 3011 } 3012 3013 ATW_WRITE(sc, ATW_NAR, opmode); 3014 DELAY(atw_nar_delay); 3015 3016 for (i = 0; i < 1000; i++) { 3017 stsr = ATW_READ(sc, ATW_STSR); 3018 if ((stsr & ackmask) == ackmask) 3019 break; 3020 DELAY(10); 3021 } 3022 3023 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 3024 3025 if ((stsr & ackmask) == ackmask) 3026 goto out; 3027 3028 test0 = ATW_READ(sc, ATW_TEST0); 3029 3030 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 3031 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 3032 printf("%s: transmit process not idle [%s]\n", 3033 device_xname(sc->sc_dev), 3034 atw_tx_state[__SHIFTOUT(test0, ATW_TEST0_TS_MASK)]); 3035 printf("%s: bits %08x test0 %08x stsr %08x\n", 3036 device_xname(sc->sc_dev), bits, test0, stsr); 3037 } 3038 3039 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 3040 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 3041 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 3042 device_xname(sc->sc_dev), 3043 atw_rx_state[__SHIFTOUT(test0, ATW_TEST0_RS_MASK)])); 3044 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 3045 device_xname(sc->sc_dev), bits, test0, stsr)); 3046 } 3047out: 3048 if ((bits & ATW_NAR_ST) != 0) 3049 atw_txdrain(sc); 3050 splx(s); 3051 return; 3052} 3053 3054/* 3055 * atw_linkintr: 3056 * 3057 * Helper; handle link-status interrupts. 3058 */ 3059void 3060atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus) 3061{ 3062 struct ieee80211com *ic = &sc->sc_ic; 3063 3064 if (ic->ic_state != IEEE80211_S_RUN) 3065 return; 3066 3067 if (linkstatus & ATW_INTR_LINKON) { 3068 DPRINTF(sc, ("%s: link on\n", device_xname(sc->sc_dev))); 3069 sc->sc_rescan_timer = 0; 3070 } else if (linkstatus & ATW_INTR_LINKOFF) { 3071 DPRINTF(sc, ("%s: link off\n", device_xname(sc->sc_dev))); 3072 if (ic->ic_opmode != IEEE80211_M_STA) 3073 return; 3074 sc->sc_rescan_timer = 3; 3075 sc->sc_if.if_timer = 1; 3076 } 3077} 3078 3079#if 0 3080static inline int 3081atw_hw_decrypted(struct atw_softc *sc, struct ieee80211_frame_min *wh) 3082{ 3083 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) 3084 return 0; 3085 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3086 return 0; 3087 return (sc->sc_wepctl & ATW_WEPCTL_WEPRXBYP) == 0; 3088} 3089#endif 3090 3091/* 3092 * atw_rxintr: 3093 * 3094 * Helper; handle receive interrupts. 3095 */ 3096void 3097atw_rxintr(struct atw_softc *sc) 3098{ 3099 static int rate_tbl[] = {2, 4, 11, 22, 44}; 3100 struct ieee80211com *ic = &sc->sc_ic; 3101 struct ieee80211_node *ni; 3102 struct ieee80211_frame_min *wh; 3103 struct ifnet *ifp = &sc->sc_if; 3104 struct atw_rxsoft *rxs; 3105 struct mbuf *m; 3106 u_int32_t rxstat; 3107 int i, s, len, rate, rate0; 3108 u_int32_t rssi, ctlrssi; 3109 3110 for (i = sc->sc_rxptr;; i = sc->sc_rxptr) { 3111 rxs = &sc->sc_rxsoft[i]; 3112 3113 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3114 3115 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 3116 ctlrssi = le32toh(sc->sc_rxdescs[i].ar_ctlrssi); 3117 rate0 = __SHIFTOUT(rxstat, ATW_RXSTAT_RXDR_MASK); 3118 3119 if (rxstat & ATW_RXSTAT_OWN) { 3120 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 3121 break; 3122 } 3123 3124 sc->sc_rxptr = ATW_NEXTRX(i); 3125 3126 DPRINTF3(sc, 3127 ("%s: rx stat %08x ctlrssi %08x buf1 %08x buf2 %08x\n", 3128 device_xname(sc->sc_dev), 3129 rxstat, ctlrssi, 3130 le32toh(sc->sc_rxdescs[i].ar_buf1), 3131 le32toh(sc->sc_rxdescs[i].ar_buf2))); 3132 3133 /* 3134 * Make sure the packet fits in one buffer. This should 3135 * always be the case. 3136 */ 3137 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 3138 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 3139 printf("%s: incoming packet spilled, resetting\n", 3140 device_xname(sc->sc_dev)); 3141 (void)atw_init(ifp); 3142 return; 3143 } 3144 3145 /* 3146 * If an error occurred, update stats, clear the status 3147 * word, and leave the packet buffer in place. It will 3148 * simply be reused the next time the ring comes around. 3149 */ 3150 if ((rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_RXTOE)) != 0) { 3151#define PRINTERR(bit, str) \ 3152 if (rxstat & (bit)) \ 3153 aprint_error_dev(sc->sc_dev, "receive error: %s\n", \ 3154 str) 3155 ifp->if_ierrors++; 3156 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 3157 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 3158#if 0 3159 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 3160 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 3161 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 3162 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 3163#endif 3164#undef PRINTERR 3165 atw_init_rxdesc(sc, i); 3166 continue; 3167 } 3168 3169 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3170 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3171 3172 /* 3173 * No errors; receive the packet. Note the ADM8211 3174 * includes the CRC in promiscuous mode. 3175 */ 3176 len = __SHIFTOUT(rxstat, ATW_RXSTAT_FL_MASK); 3177 3178 /* 3179 * Allocate a new mbuf cluster. If that fails, we are 3180 * out of memory, and must drop the packet and recycle 3181 * the buffer that's already attached to this descriptor. 3182 */ 3183 m = rxs->rxs_mbuf; 3184 if (atw_add_rxbuf(sc, i) != 0) { 3185 ifp->if_ierrors++; 3186 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3187 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3188 atw_init_rxdesc(sc, i); 3189 continue; 3190 } 3191 3192 ifp->if_ipackets++; 3193 m_set_rcvif(m, ifp); 3194 m->m_pkthdr.len = m->m_len = MIN(m->m_ext.ext_size, len); 3195 3196 rate = (rate0 < __arraycount(rate_tbl)) ? rate_tbl[rate0] : 0; 3197 3198 /* The RSSI comes straight from a register in the 3199 * baseband processor. I know that for the RF3000, 3200 * the RSSI register also contains the antenna-selection 3201 * bits. Mask those off. 3202 * 3203 * TBD Treat other basebands. 3204 * TBD Use short-preamble bit and such in RF3000_RXSTAT. 3205 */ 3206 if (sc->sc_bbptype == ATW_BBPTYPE_RFMD) 3207 rssi = ctlrssi & RF3000_RSSI_MASK; 3208 else 3209 rssi = ctlrssi; 3210 3211 s = splnet(); 3212 3213 /* Pass this up to any BPF listeners. */ 3214 if (sc->sc_radiobpf != NULL) { 3215 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3216 3217 tap->ar_rate = rate; 3218 3219 /* TBD verify units are dB */ 3220 tap->ar_antsignal = (int)rssi; 3221 if (sc->sc_opmode & ATW_NAR_PR) 3222 tap->ar_flags = IEEE80211_RADIOTAP_F_FCS; 3223 else 3224 tap->ar_flags = 0; 3225 3226 if ((rxstat & ATW_RXSTAT_CRC32E) != 0) 3227 tap->ar_flags |= IEEE80211_RADIOTAP_F_BADFCS; 3228 3229 bpf_mtap2(sc->sc_radiobpf, tap, sizeof(sc->sc_rxtapu), 3230 m, BPF_D_IN); 3231 } 3232 3233 sc->sc_recv_ev.ev_count++; 3234 3235 if ((rxstat & (ATW_RXSTAT_CRC16E|ATW_RXSTAT_CRC32E|ATW_RXSTAT_ICVE|ATW_RXSTAT_SFDE|ATW_RXSTAT_SIGE)) != 0) { 3236 if (rxstat & ATW_RXSTAT_CRC16E) 3237 sc->sc_crc16e_ev.ev_count++; 3238 if (rxstat & ATW_RXSTAT_CRC32E) 3239 sc->sc_crc32e_ev.ev_count++; 3240 if (rxstat & ATW_RXSTAT_ICVE) 3241 sc->sc_icve_ev.ev_count++; 3242 if (rxstat & ATW_RXSTAT_SFDE) 3243 sc->sc_sfde_ev.ev_count++; 3244 if (rxstat & ATW_RXSTAT_SIGE) 3245 sc->sc_sige_ev.ev_count++; 3246 ifp->if_ierrors++; 3247 m_freem(m); 3248 splx(s); 3249 continue; 3250 } 3251 3252 if (sc->sc_opmode & ATW_NAR_PR) 3253 m_adj(m, -IEEE80211_CRC_LEN); 3254 3255 wh = mtod(m, struct ieee80211_frame_min *); 3256 ni = ieee80211_find_rxnode(ic, wh); 3257#if 0 3258 if (atw_hw_decrypted(sc, wh)) { 3259 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 3260 DPRINTF(sc, ("%s: hw decrypted\n", __func__)); 3261 } 3262#endif 3263 ieee80211_input(ic, m, ni, (int)rssi, 0); 3264 ieee80211_free_node(ni); 3265 splx(s); 3266 } 3267} 3268 3269/* 3270 * atw_txintr: 3271 * 3272 * Helper; handle transmit interrupts. 3273 */ 3274void 3275atw_txintr(struct atw_softc *sc, uint32_t status) 3276{ 3277 static char txstat_buf[sizeof("ffffffff<>" ATW_TXSTAT_FMT)]; 3278 struct ifnet *ifp = &sc->sc_if; 3279 struct atw_txsoft *txs; 3280 u_int32_t txstat; 3281 int s; 3282 3283 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3284 device_xname(sc->sc_dev), sc->sc_flags)); 3285 3286 s = splnet(); 3287 3288 /* 3289 * Go through our Tx list and free mbufs for those 3290 * frames that have been transmitted. 3291 */ 3292 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3293 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, 3294 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3295 3296#ifdef ATW_DEBUG 3297 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3298 int i; 3299 printf(" txsoft %p transmit chain:\n", txs); 3300 ATW_CDTXSYNC(sc, txs->txs_firstdesc, 3301 txs->txs_ndescs - 1, 3302 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3303 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3304 printf(" descriptor %d:\n", i); 3305 printf(" at_status: 0x%08x\n", 3306 le32toh(sc->sc_txdescs[i].at_stat)); 3307 printf(" at_flags: 0x%08x\n", 3308 le32toh(sc->sc_txdescs[i].at_flags)); 3309 printf(" at_buf1: 0x%08x\n", 3310 le32toh(sc->sc_txdescs[i].at_buf1)); 3311 printf(" at_buf2: 0x%08x\n", 3312 le32toh(sc->sc_txdescs[i].at_buf2)); 3313 if (i == txs->txs_lastdesc) 3314 break; 3315 } 3316 ATW_CDTXSYNC(sc, txs->txs_firstdesc, 3317 txs->txs_ndescs - 1, BUS_DMASYNC_PREREAD); 3318 } 3319#endif 3320 3321 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3322 if (txstat & ATW_TXSTAT_OWN) { 3323 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, 3324 BUS_DMASYNC_PREREAD); 3325 break; 3326 } 3327 3328 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3329 3330 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3331 0, txs->txs_dmamap->dm_mapsize, 3332 BUS_DMASYNC_POSTWRITE); 3333 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3334 m_freem(txs->txs_mbuf); 3335 txs->txs_mbuf = NULL; 3336 3337 sc->sc_txfree += txs->txs_ndescs; 3338 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3339 3340 KASSERT(!SIMPLEQ_EMPTY(&sc->sc_txfreeq) && sc->sc_txfree != 0); 3341 sc->sc_tx_timer = 0; 3342 ifp->if_flags &= ~IFF_OACTIVE; 3343 3344 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3345 (txstat & ATW_TXSTAT_ERRMASK) != 0) { 3346 snprintb(txstat_buf, sizeof(txstat_buf), 3347 ATW_TXSTAT_FMT, txstat & ATW_TXSTAT_ERRMASK); 3348 printf("%s: txstat %s %" __PRIuBITS "\n", 3349 device_xname(sc->sc_dev), txstat_buf, 3350 __SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK)); 3351 } 3352 3353 sc->sc_xmit_ev.ev_count++; 3354 3355 /* 3356 * Check for errors and collisions. 3357 */ 3358 if (txstat & ATW_TXSTAT_TUF) 3359 sc->sc_tuf_ev.ev_count++; 3360 if (txstat & ATW_TXSTAT_TLT) 3361 sc->sc_tlt_ev.ev_count++; 3362 if (txstat & ATW_TXSTAT_TRT) 3363 sc->sc_trt_ev.ev_count++; 3364 if (txstat & ATW_TXSTAT_TRO) 3365 sc->sc_tro_ev.ev_count++; 3366 if (txstat & ATW_TXSTAT_SOFBR) 3367 sc->sc_sofbr_ev.ev_count++; 3368 3369 if ((txstat & ATW_TXSTAT_ES) == 0) 3370 ifp->if_collisions += 3371 __SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK); 3372 else 3373 ifp->if_oerrors++; 3374 3375 ifp->if_opackets++; 3376 } 3377 3378 KASSERT(txs != NULL || (ifp->if_flags & IFF_OACTIVE) == 0); 3379 3380 splx(s); 3381} 3382 3383/* 3384 * atw_watchdog: [ifnet interface function] 3385 * 3386 * Watchdog timer handler. 3387 */ 3388void 3389atw_watchdog(struct ifnet *ifp) 3390{ 3391 struct atw_softc *sc = ifp->if_softc; 3392 struct ieee80211com *ic = &sc->sc_ic; 3393 3394 ifp->if_timer = 0; 3395 if (!device_is_active(sc->sc_dev)) 3396 return; 3397 3398 if (sc->sc_rescan_timer != 0 && --sc->sc_rescan_timer == 0) 3399 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3400 if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0 && 3401 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3402 printf("%s: transmit timeout\n", ifp->if_xname); 3403 ifp->if_oerrors++; 3404 (void)atw_init(ifp); 3405 atw_start(ifp); 3406 } 3407 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3408 ifp->if_timer = 1; 3409 ieee80211_watchdog(ic); 3410} 3411 3412static void 3413atw_evcnt_detach(struct atw_softc *sc) 3414{ 3415 evcnt_detach(&sc->sc_sige_ev); 3416 evcnt_detach(&sc->sc_sfde_ev); 3417 evcnt_detach(&sc->sc_icve_ev); 3418 evcnt_detach(&sc->sc_crc32e_ev); 3419 evcnt_detach(&sc->sc_crc16e_ev); 3420 evcnt_detach(&sc->sc_recv_ev); 3421 3422 evcnt_detach(&sc->sc_tuf_ev); 3423 evcnt_detach(&sc->sc_tro_ev); 3424 evcnt_detach(&sc->sc_trt_ev); 3425 evcnt_detach(&sc->sc_tlt_ev); 3426 evcnt_detach(&sc->sc_sofbr_ev); 3427 evcnt_detach(&sc->sc_xmit_ev); 3428 3429 evcnt_detach(&sc->sc_rxpkt1in_ev); 3430 evcnt_detach(&sc->sc_rxamatch_ev); 3431 evcnt_detach(&sc->sc_workaround1_ev); 3432 evcnt_detach(&sc->sc_misc_ev); 3433} 3434 3435static void 3436atw_evcnt_attach(struct atw_softc *sc) 3437{ 3438 evcnt_attach_dynamic(&sc->sc_recv_ev, EVCNT_TYPE_MISC, 3439 NULL, sc->sc_if.if_xname, "recv"); 3440 evcnt_attach_dynamic(&sc->sc_crc16e_ev, EVCNT_TYPE_MISC, 3441 &sc->sc_recv_ev, sc->sc_if.if_xname, "CRC16 error"); 3442 evcnt_attach_dynamic(&sc->sc_crc32e_ev, EVCNT_TYPE_MISC, 3443 &sc->sc_recv_ev, sc->sc_if.if_xname, "CRC32 error"); 3444 evcnt_attach_dynamic(&sc->sc_icve_ev, EVCNT_TYPE_MISC, 3445 &sc->sc_recv_ev, sc->sc_if.if_xname, "ICV error"); 3446 evcnt_attach_dynamic(&sc->sc_sfde_ev, EVCNT_TYPE_MISC, 3447 &sc->sc_recv_ev, sc->sc_if.if_xname, "PLCP SFD error"); 3448 evcnt_attach_dynamic(&sc->sc_sige_ev, EVCNT_TYPE_MISC, 3449 &sc->sc_recv_ev, sc->sc_if.if_xname, "PLCP Signal Field error"); 3450 3451 evcnt_attach_dynamic(&sc->sc_xmit_ev, EVCNT_TYPE_MISC, 3452 NULL, sc->sc_if.if_xname, "xmit"); 3453 evcnt_attach_dynamic(&sc->sc_tuf_ev, EVCNT_TYPE_MISC, 3454 &sc->sc_xmit_ev, sc->sc_if.if_xname, "transmit underflow"); 3455 evcnt_attach_dynamic(&sc->sc_tro_ev, EVCNT_TYPE_MISC, 3456 &sc->sc_xmit_ev, sc->sc_if.if_xname, "transmit overrun"); 3457 evcnt_attach_dynamic(&sc->sc_trt_ev, EVCNT_TYPE_MISC, 3458 &sc->sc_xmit_ev, sc->sc_if.if_xname, "retry count exceeded"); 3459 evcnt_attach_dynamic(&sc->sc_tlt_ev, EVCNT_TYPE_MISC, 3460 &sc->sc_xmit_ev, sc->sc_if.if_xname, "lifetime exceeded"); 3461 evcnt_attach_dynamic(&sc->sc_sofbr_ev, EVCNT_TYPE_MISC, 3462 &sc->sc_xmit_ev, sc->sc_if.if_xname, "packet size mismatch"); 3463 3464 evcnt_attach_dynamic(&sc->sc_misc_ev, EVCNT_TYPE_MISC, 3465 NULL, sc->sc_if.if_xname, "misc"); 3466 evcnt_attach_dynamic(&sc->sc_workaround1_ev, EVCNT_TYPE_MISC, 3467 &sc->sc_misc_ev, sc->sc_if.if_xname, "workaround #1"); 3468 evcnt_attach_dynamic(&sc->sc_rxamatch_ev, EVCNT_TYPE_MISC, 3469 &sc->sc_misc_ev, sc->sc_if.if_xname, "rra equals rwa"); 3470 evcnt_attach_dynamic(&sc->sc_rxpkt1in_ev, EVCNT_TYPE_MISC, 3471 &sc->sc_misc_ev, sc->sc_if.if_xname, "rxpkt1in set"); 3472} 3473 3474#ifdef ATW_DEBUG 3475static void 3476atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3477{ 3478 struct atw_softc *sc = ifp->if_softc; 3479 struct mbuf *m; 3480 int i, noctets = 0; 3481 3482 printf("%s: %d-byte packet\n", device_xname(sc->sc_dev), 3483 m0->m_pkthdr.len); 3484 3485 for (m = m0; m; m = m->m_next) { 3486 if (m->m_len == 0) 3487 continue; 3488 for (i = 0; i < m->m_len; i++) { 3489 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3490 if (++noctets % 24 == 0) 3491 printf("\n"); 3492 } 3493 } 3494 printf("%s%s: %d bytes emitted\n", 3495 (noctets % 24 != 0) ? "\n" : "", device_xname(sc->sc_dev), noctets); 3496} 3497#endif /* ATW_DEBUG */ 3498 3499/* 3500 * atw_start: [ifnet interface function] 3501 * 3502 * Start packet transmission on the interface. 3503 */ 3504void 3505atw_start(struct ifnet *ifp) 3506{ 3507 struct atw_softc *sc = ifp->if_softc; 3508 struct ieee80211_key *k; 3509 struct ieee80211com *ic = &sc->sc_ic; 3510 struct ieee80211_node *ni; 3511 struct ieee80211_frame_min *whm; 3512 struct ieee80211_frame *wh; 3513 struct atw_frame *hh; 3514 uint16_t hdrctl; 3515 struct mbuf *m0, *m; 3516 struct atw_txsoft *txs; 3517 struct atw_txdesc *txd; 3518 int npkt, rate; 3519 bus_dmamap_t dmamap; 3520 int ctl, error, firsttx, nexttx, lasttx, first, ofree, seg; 3521 3522 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3523 device_xname(sc->sc_dev), sc->sc_flags, ifp->if_flags)); 3524 3525 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3526 return; 3527 3528 /* 3529 * Remember the previous number of free descriptors and 3530 * the first descriptor we'll use. 3531 */ 3532 ofree = sc->sc_txfree; 3533 firsttx = lasttx = sc->sc_txnext; 3534 3535 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3536 device_xname(sc->sc_dev), ofree, firsttx)); 3537 3538 /* 3539 * Loop through the send queue, setting up transmit descriptors 3540 * until we drain the queue, or use up all available transmit 3541 * descriptors. 3542 */ 3543 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3544 sc->sc_txfree != 0) { 3545 3546 hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3547 3548 /* 3549 * Grab a packet off the management queue, if it 3550 * is not empty. Otherwise, from the data queue. 3551 */ 3552 IF_DEQUEUE(&ic->ic_mgtq, m0); 3553 if (m0 != NULL) { 3554 ni = M_GETCTX(m0, struct ieee80211_node *); 3555 M_CLEARCTX(m0); 3556 } else if (ic->ic_state != IEEE80211_S_RUN) 3557 break; /* send no data until associated */ 3558 else { 3559 IFQ_DEQUEUE(&ifp->if_snd, m0); 3560 if (m0 == NULL) 3561 break; 3562 bpf_mtap(ifp, m0, BPF_D_OUT); 3563 ni = ieee80211_find_txnode(ic, 3564 mtod(m0, struct ether_header *)->ether_dhost); 3565 if (ni == NULL) { 3566 ifp->if_oerrors++; 3567 break; 3568 } 3569 if ((m0 = ieee80211_encap(ic, m0, ni)) == NULL) { 3570 ieee80211_free_node(ni); 3571 ifp->if_oerrors++; 3572 break; 3573 } 3574 } 3575 3576 rate = MAX(ieee80211_get_rate(ni), 2); 3577 3578 whm = mtod(m0, struct ieee80211_frame_min *); 3579 3580 if ((whm->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3581 k = NULL; 3582 else if ((k = ieee80211_crypto_encap(ic, ni, m0)) == NULL) { 3583 m_freem(m0); 3584 ieee80211_free_node(ni); 3585 ifp->if_oerrors++; 3586 break; 3587 } 3588#if 0 3589 if (IEEE80211_IS_MULTICAST(wh->i_addr1) && 3590 m0->m_pkthdr.len > ic->ic_fragthreshold) 3591 hdrctl |= htole16(ATW_HDRCTL_MORE_FRAG); 3592#endif 3593 3594 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN >= ic->ic_rtsthreshold) 3595 hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3596 3597 if (ieee80211_compute_duration(whm, k, m0->m_pkthdr.len, 3598 ic->ic_flags, ic->ic_fragthreshold, rate, 3599 &txs->txs_d0, &txs->txs_dn, &npkt, 0) == -1) { 3600 DPRINTF2(sc, ("%s: fail compute duration\n", __func__)); 3601 m_freem(m0); 3602 break; 3603 } 3604 3605 /* XXX Misleading if fragmentation is enabled. Better 3606 * to fragment in software? 3607 */ 3608 *(uint16_t *)whm->i_dur = htole16(txs->txs_d0.d_rts_dur); 3609 3610 /* 3611 * Pass the packet to any BPF listeners. 3612 */ 3613 bpf_mtap3(ic->ic_rawbpf, m0, BPF_D_OUT); 3614 3615 if (sc->sc_radiobpf != NULL) { 3616 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3617 3618 tap->at_rate = rate; 3619 3620 bpf_mtap2(sc->sc_radiobpf, tap, sizeof(sc->sc_txtapu), 3621 m0, BPF_D_OUT); 3622 } 3623 3624 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3625 3626 if (ni != NULL) 3627 ieee80211_free_node(ni); 3628 3629 if (m0 == NULL) { 3630 ifp->if_oerrors++; 3631 break; 3632 } 3633 3634 /* just to make sure. */ 3635 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3636 3637 if (m0 == NULL) { 3638 ifp->if_oerrors++; 3639 break; 3640 } 3641 3642 hh = mtod(m0, struct atw_frame *); 3643 wh = &hh->atw_ihdr; 3644 3645 /* Copy everything we need from the 802.11 header: 3646 * Frame Control; address 1, address 3, or addresses 3647 * 3 and 4. NIC fills in BSSID, SA. 3648 */ 3649 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3650 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3651 panic("%s: illegal WDS frame", 3652 device_xname(sc->sc_dev)); 3653 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3654 } else 3655 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3656 3657 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3658 3659 /* initialize remaining Tx parameters */ 3660 memset(&hh->u, 0, sizeof(hh->u)); 3661 3662 hh->atw_rate = rate * 5; 3663 /* XXX this could be incorrect if M_FCS. _encap should 3664 * probably strip FCS just in case it sticks around in 3665 * bridged packets. 3666 */ 3667 hh->atw_service = 0x00; /* XXX guess */ 3668 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3669 sizeof(struct atw_frame)); 3670 3671 /* never fragment multicast frames */ 3672 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) 3673 hh->atw_fragthr = htole16(IEEE80211_FRAG_MAX); 3674 else { 3675 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3676 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) 3677 hdrctl |= htole16(ATW_HDRCTL_SHORT_PREAMBLE); 3678 hh->atw_fragthr = htole16(ic->ic_fragthreshold); 3679 } 3680 3681 hh->atw_rtylmt = 3; 3682#if 0 3683 if (do_encrypt) { 3684 hdrctl |= htole16(ATW_HDRCTL_WEP); 3685 hh->atw_keyid = ic->ic_def_txkey; 3686 } 3687#endif 3688 3689 hh->atw_head_plcplen = htole16(txs->txs_d0.d_plcp_len); 3690 hh->atw_tail_plcplen = htole16(txs->txs_dn.d_plcp_len); 3691 if (txs->txs_d0.d_residue) 3692 hh->atw_head_plcplen |= htole16(0x8000); 3693 if (txs->txs_dn.d_residue) 3694 hh->atw_tail_plcplen |= htole16(0x8000); 3695 hh->atw_head_dur = htole16(txs->txs_d0.d_rts_dur); 3696 hh->atw_tail_dur = htole16(txs->txs_dn.d_rts_dur); 3697 3698 hh->atw_hdrctl = hdrctl; 3699 hh->atw_fragnum = npkt << 4; 3700#ifdef ATW_DEBUG 3701 3702 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3703 printf("%s: dst = %s, rate = 0x%02x, " 3704 "service = 0x%02x, paylen = 0x%04x\n", 3705 device_xname(sc->sc_dev), ether_sprintf(hh->atw_dst), 3706 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3707 3708 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3709 "dur1 = 0x%04x, dur2 = 0x%04x, " 3710 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3711 device_xname(sc->sc_dev), hh->atw_fc[0], hh->atw_fc[1], 3712 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3713 hh->atw_tail_dur, hh->atw_head_dur); 3714 3715 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3716 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3717 device_xname(sc->sc_dev), hh->atw_hdrctl, 3718 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3719 3720 printf("%s: keyid = %d\n", 3721 device_xname(sc->sc_dev), hh->atw_keyid); 3722 3723 atw_dump_pkt(ifp, m0); 3724 } 3725#endif /* ATW_DEBUG */ 3726 3727 dmamap = txs->txs_dmamap; 3728 3729 /* 3730 * Load the DMA map. Copy and try (once) again if the packet 3731 * didn't fit in the alloted number of segments. 3732 */ 3733 for (first = 1; 3734 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3735 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3736 first = 0) { 3737 MGETHDR(m, M_DONTWAIT, MT_DATA); 3738 if (m == NULL) { 3739 aprint_error_dev(sc->sc_dev, "unable to allocate Tx mbuf\n"); 3740 break; 3741 } 3742 if (m0->m_pkthdr.len > MHLEN) { 3743 MCLGET(m, M_DONTWAIT); 3744 if ((m->m_flags & M_EXT) == 0) { 3745 aprint_error_dev(sc->sc_dev, "unable to allocate Tx " 3746 "cluster\n"); 3747 m_freem(m); 3748 break; 3749 } 3750 } 3751 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 3752 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3753 m_freem(m0); 3754 m0 = m; 3755 m = NULL; 3756 } 3757 if (error != 0) { 3758 aprint_error_dev(sc->sc_dev, "unable to load Tx buffer, " 3759 "error = %d\n", error); 3760 m_freem(m0); 3761 break; 3762 } 3763 3764 /* 3765 * Ensure we have enough descriptors free to describe 3766 * the packet. 3767 */ 3768 if (dmamap->dm_nsegs > sc->sc_txfree) { 3769 /* 3770 * Not enough free descriptors to transmit 3771 * this packet. Unload the DMA map and 3772 * drop the packet. Notify the upper layer 3773 * that there are no more slots left. 3774 * 3775 * XXX We could allocate an mbuf and copy, but 3776 * XXX it is worth it? 3777 */ 3778 bus_dmamap_unload(sc->sc_dmat, dmamap); 3779 m_freem(m0); 3780 break; 3781 } 3782 3783 /* 3784 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3785 */ 3786 3787 /* Sync the DMA map. */ 3788 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3789 BUS_DMASYNC_PREWRITE); 3790 3791 /* XXX arbitrary retry limit; 8 because I have seen it in 3792 * use already and maybe 0 means "no tries" ! 3793 */ 3794 ctl = htole32(__SHIFTIN(8, ATW_TXCTL_TL_MASK)); 3795 3796 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3797 device_xname(sc->sc_dev), rate * 5)); 3798 ctl |= htole32(__SHIFTIN(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3799 3800 /* 3801 * Initialize the transmit descriptors. 3802 */ 3803 for (nexttx = sc->sc_txnext, seg = 0; 3804 seg < dmamap->dm_nsegs; 3805 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3806 /* 3807 * If this is the first descriptor we're 3808 * enqueueing, don't set the OWN bit just 3809 * yet. That could cause a race condition. 3810 * We'll do it below. 3811 */ 3812 txd = &sc->sc_txdescs[nexttx]; 3813 txd->at_ctl = ctl | 3814 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3815 3816 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3817 txd->at_flags = 3818 htole32(__SHIFTIN(dmamap->dm_segs[seg].ds_len, 3819 ATW_TXFLAG_TBS1_MASK)) | 3820 ((nexttx == (ATW_NTXDESC - 1)) 3821 ? htole32(ATW_TXFLAG_TER) : 0); 3822 lasttx = nexttx; 3823 } 3824 3825 /* Set `first segment' and `last segment' appropriately. */ 3826 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3827 htole32(ATW_TXFLAG_FS); 3828 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3829 3830#ifdef ATW_DEBUG 3831 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3832 printf(" txsoft %p transmit chain:\n", txs); 3833 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3834 printf(" descriptor %d:\n", seg); 3835 printf(" at_ctl: 0x%08x\n", 3836 le32toh(sc->sc_txdescs[seg].at_ctl)); 3837 printf(" at_flags: 0x%08x\n", 3838 le32toh(sc->sc_txdescs[seg].at_flags)); 3839 printf(" at_buf1: 0x%08x\n", 3840 le32toh(sc->sc_txdescs[seg].at_buf1)); 3841 printf(" at_buf2: 0x%08x\n", 3842 le32toh(sc->sc_txdescs[seg].at_buf2)); 3843 if (seg == lasttx) 3844 break; 3845 } 3846 } 3847#endif 3848 3849 /* Sync the descriptors we're using. */ 3850 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3851 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3852 3853 /* 3854 * Store a pointer to the packet so we can free it later, 3855 * and remember what txdirty will be once the packet is 3856 * done. 3857 */ 3858 txs->txs_mbuf = m0; 3859 txs->txs_firstdesc = sc->sc_txnext; 3860 txs->txs_lastdesc = lasttx; 3861 txs->txs_ndescs = dmamap->dm_nsegs; 3862 3863 /* Advance the tx pointer. */ 3864 sc->sc_txfree -= dmamap->dm_nsegs; 3865 sc->sc_txnext = nexttx; 3866 3867 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3868 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3869 } 3870 3871 if (sc->sc_txfree != ofree) { 3872 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3873 device_xname(sc->sc_dev), lasttx, firsttx)); 3874 /* 3875 * Cause a transmit interrupt to happen on the 3876 * last packet we enqueued. 3877 */ 3878 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3879 ATW_CDTXSYNC(sc, lasttx, 1, 3880 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3881 3882 /* 3883 * The entire packet chain is set up. Give the 3884 * first descriptor to the chip now. 3885 */ 3886 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3887 ATW_CDTXSYNC(sc, firsttx, 1, 3888 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3889 3890 /* Wake up the transmitter. */ 3891 ATW_WRITE(sc, ATW_TDR, 0x1); 3892 3893 if (txs == NULL || sc->sc_txfree == 0) 3894 ifp->if_flags |= IFF_OACTIVE; 3895 3896 /* Set a watchdog timer in case the chip flakes out. */ 3897 sc->sc_tx_timer = 5; 3898 ifp->if_timer = 1; 3899 } 3900} 3901 3902/* 3903 * atw_ioctl: [ifnet interface function] 3904 * 3905 * Handle control requests from the operator. 3906 */ 3907int 3908atw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3909{ 3910 struct atw_softc *sc = ifp->if_softc; 3911 struct ieee80211req *ireq; 3912 int s, error = 0; 3913 3914 s = splnet(); 3915 3916 switch (cmd) { 3917 case SIOCSIFFLAGS: 3918 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3919 break; 3920 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 3921 case IFF_UP|IFF_RUNNING: 3922 /* 3923 * To avoid rescanning another access point, 3924 * do not call atw_init() here. Instead, 3925 * only reflect media settings. 3926 */ 3927 if (device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 3928 atw_filter_setup(sc); 3929 break; 3930 case IFF_UP: 3931 error = atw_init(ifp); 3932 break; 3933 case IFF_RUNNING: 3934 atw_stop(ifp, 1); 3935 break; 3936 case 0: 3937 break; 3938 } 3939 break; 3940 case SIOCADDMULTI: 3941 case SIOCDELMULTI: 3942 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 3943 if (ifp->if_flags & IFF_RUNNING) 3944 atw_filter_setup(sc); /* do not rescan */ 3945 error = 0; 3946 } 3947 break; 3948 case SIOCS80211: 3949 ireq = data; 3950 if (ireq->i_type == IEEE80211_IOC_FRAGTHRESHOLD) { 3951 if ((error = kauth_authorize_network(curlwp->l_cred, 3952 KAUTH_NETWORK_INTERFACE, 3953 KAUTH_REQ_NETWORK_INTERFACE_SETPRIV, ifp, 3954 (void *)cmd, NULL)) != 0) 3955 break; 3956 if (!(IEEE80211_FRAG_MIN <= ireq->i_val && 3957 ireq->i_val <= IEEE80211_FRAG_MAX)) 3958 error = EINVAL; 3959 else 3960 sc->sc_ic.ic_fragthreshold = ireq->i_val; 3961 break; 3962 } 3963 /*FALLTHROUGH*/ 3964 default: 3965 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 3966 if (error == ENETRESET || error == ERESTART) { 3967 if (is_running(ifp)) 3968 error = atw_init(ifp); 3969 else 3970 error = 0; 3971 } 3972 break; 3973 } 3974 3975 /* Try to get more packets going. */ 3976 if (device_is_active(sc->sc_dev)) 3977 atw_start(ifp); 3978 3979 splx(s); 3980 return (error); 3981} 3982 3983static int 3984atw_media_change(struct ifnet *ifp) 3985{ 3986 int error; 3987 3988 error = ieee80211_media_change(ifp); 3989 if (error == ENETRESET) { 3990 if (is_running(ifp)) 3991 error = atw_init(ifp); 3992 else 3993 error = 0; 3994 } 3995 return error; 3996} 3997