atw.c revision 1.112
1/* $NetBSD: atw.c,v 1.112 2006/03/08 08:26:50 dyoung Exp $ */ 2 3/*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39/* 40 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 41 */ 42 43#include <sys/cdefs.h> 44__KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.112 2006/03/08 08:26:50 dyoung Exp $"); 45 46#include "bpfilter.h" 47 48#include <sys/param.h> 49#include <sys/systm.h> 50#include <sys/callout.h> 51#include <sys/mbuf.h> 52#include <sys/malloc.h> 53#include <sys/kernel.h> 54#include <sys/socket.h> 55#include <sys/ioctl.h> 56#include <sys/errno.h> 57#include <sys/device.h> 58#include <sys/time.h> 59 60#include <machine/endian.h> 61 62#include <uvm/uvm_extern.h> 63 64#include <net/if.h> 65#include <net/if_dl.h> 66#include <net/if_media.h> 67#include <net/if_ether.h> 68 69#include <net80211/ieee80211_netbsd.h> 70#include <net80211/ieee80211_var.h> 71#include <net80211/ieee80211_radiotap.h> 72 73#if NBPFILTER > 0 74#include <net/bpf.h> 75#endif 76 77#include <machine/bus.h> 78#include <machine/intr.h> 79 80#include <dev/ic/atwreg.h> 81#include <dev/ic/rf3000reg.h> 82#include <dev/ic/si4136reg.h> 83#include <dev/ic/atwvar.h> 84#include <dev/ic/smc93cx6var.h> 85 86/* XXX TBD open questions 87 * 88 * 89 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 90 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 91 * handle this for me? 92 * 93 */ 94/* device attachment 95 * 96 * print TOFS[012] 97 * 98 * device initialization 99 * 100 * clear ATW_FRCTL_MAXPSP to disable max power saving 101 * set ATW_TXBR_ALCUPDATE to enable ALC 102 * set TOFS[012]? (hope not) 103 * disable rx/tx 104 * set ATW_PAR_SWR (software reset) 105 * wait for ATW_PAR_SWR clear 106 * disable interrupts 107 * ack status register 108 * enable interrupts 109 * 110 * rx/tx initialization 111 * 112 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 113 * allocate and init descriptor rings 114 * write ATW_PAR_DSL (descriptor skip length) 115 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 116 * write ATW_NAR_SQ for one/both transmit descriptor rings 117 * write ATW_NAR_SQ for one/both transmit descriptor rings 118 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 119 * 120 * rx/tx end 121 * 122 * stop DMA 123 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 124 * flush tx w/ ATW_NAR_HF 125 * 126 * scan 127 * 128 * initialize rx/tx 129 * 130 * BSS join: (re)association response 131 * 132 * set ATW_FRCTL_AID 133 * 134 * optimizations ??? 135 * 136 */ 137 138#define ATW_REFSLAVE /* slavishly do what the reference driver does */ 139 140#define VOODOO_DUR_11_ROUNDING 0x01 /* necessary */ 141#define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */ 142int atw_voodoo = VOODOO_DUR_11_ROUNDING; 143 144int atw_pseudo_milli = 1; 145int atw_magic_delay1 = 100 * 1000; 146int atw_magic_delay2 = 100 * 1000; 147/* more magic multi-millisecond delays (units: microseconds) */ 148int atw_nar_delay = 20 * 1000; 149int atw_magic_delay4 = 10 * 1000; 150int atw_rf_delay1 = 10 * 1000; 151int atw_rf_delay2 = 5 * 1000; 152int atw_plcphd_delay = 2 * 1000; 153int atw_bbp_io_enable_delay = 20 * 1000; 154int atw_bbp_io_disable_delay = 2 * 1000; 155int atw_writewep_delay = 1000; 156int atw_beacon_len_adjust = 4; 157int atw_dwelltime = 200; 158int atw_xindiv2 = 0; 159 160#ifdef ATW_DEBUG 161int atw_debug = 0; 162 163#define ATW_DPRINTF(x) if (atw_debug > 0) printf x 164#define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 165#define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 166#define DPRINTF(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) printf x 167#define DPRINTF2(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 168#define DPRINTF3(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 169 170static void atw_dump_pkt(struct ifnet *, struct mbuf *); 171static void atw_print_regs(struct atw_softc *, const char *); 172 173/* Note well: I never got atw_rf3000_read or atw_si4126_read to work. */ 174# ifdef ATW_BBPDEBUG 175static void atw_rf3000_print(struct atw_softc *); 176static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 177# endif /* ATW_BBPDEBUG */ 178 179# ifdef ATW_SYNDEBUG 180static void atw_si4126_print(struct atw_softc *); 181static int atw_si4126_read(struct atw_softc *, u_int, u_int *); 182# endif /* ATW_SYNDEBUG */ 183 184#else 185#define ATW_DPRINTF(x) 186#define ATW_DPRINTF2(x) 187#define ATW_DPRINTF3(x) 188#define DPRINTF(sc, x) /* nothing */ 189#define DPRINTF2(sc, x) /* nothing */ 190#define DPRINTF3(sc, x) /* nothing */ 191#endif 192 193/* ifnet methods */ 194int atw_init(struct ifnet *); 195int atw_ioctl(struct ifnet *, u_long, caddr_t); 196void atw_start(struct ifnet *); 197void atw_stop(struct ifnet *, int); 198void atw_watchdog(struct ifnet *); 199 200/* Device attachment */ 201void atw_attach(struct atw_softc *); 202int atw_detach(struct atw_softc *); 203 204/* Rx/Tx process */ 205int atw_add_rxbuf(struct atw_softc *, int); 206void atw_idle(struct atw_softc *, u_int32_t); 207void atw_rxdrain(struct atw_softc *); 208void atw_txdrain(struct atw_softc *); 209 210/* Device (de)activation and power state */ 211void atw_disable(struct atw_softc *); 212int atw_enable(struct atw_softc *); 213void atw_power(int, void *); 214void atw_reset(struct atw_softc *); 215void atw_shutdown(void *); 216 217/* Interrupt handlers */ 218void atw_linkintr(struct atw_softc *, u_int32_t); 219void atw_rxintr(struct atw_softc *); 220void atw_txintr(struct atw_softc *); 221 222/* 802.11 state machine */ 223static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 224static void atw_next_scan(void *); 225static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 226 struct ieee80211_node *, int, int, u_int32_t); 227static int atw_tune(struct atw_softc *); 228 229/* Device initialization */ 230static void atw_bbp_io_init(struct atw_softc *); 231static void atw_cfp_init(struct atw_softc *); 232static void atw_cmdr_init(struct atw_softc *); 233static void atw_ifs_init(struct atw_softc *); 234static void atw_nar_init(struct atw_softc *); 235static void atw_response_times_init(struct atw_softc *); 236static void atw_rf_reset(struct atw_softc *); 237static void atw_test1_init(struct atw_softc *); 238static void atw_tofs0_init(struct atw_softc *); 239static void atw_tofs2_init(struct atw_softc *); 240static void atw_txlmt_init(struct atw_softc *); 241static void atw_wcsr_init(struct atw_softc *); 242 243/* Key management */ 244static int atw_key_delete(struct ieee80211com *, const struct ieee80211_key *); 245static int atw_key_set(struct ieee80211com *, const struct ieee80211_key *, 246 const u_int8_t[IEEE80211_ADDR_LEN]); 247static void atw_key_update_begin(struct ieee80211com *); 248static void atw_key_update_end(struct ieee80211com *); 249 250/* RAM/ROM utilities */ 251static void atw_clear_sram(struct atw_softc *); 252static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 253static int atw_read_srom(struct atw_softc *); 254 255/* BSS setup */ 256static void atw_predict_beacon(struct atw_softc *); 257static void atw_start_beacon(struct atw_softc *, int); 258static void atw_write_bssid(struct atw_softc *); 259static void atw_write_ssid(struct atw_softc *); 260static void atw_write_sup_rates(struct atw_softc *); 261static void atw_write_wep(struct atw_softc *); 262 263/* Media */ 264static int atw_media_change(struct ifnet *); 265 266static void atw_filter_setup(struct atw_softc *); 267 268/* 802.11 utilities */ 269static uint64_t atw_get_tsft(struct atw_softc *); 270static inline uint32_t atw_last_even_tsft(uint32_t, uint32_t, 271 uint32_t); 272static struct ieee80211_node *atw_node_alloc(struct ieee80211_node_table *); 273static void atw_node_free(struct ieee80211_node *); 274 275/* 276 * Tuner/transceiver/modem 277 */ 278static void atw_bbp_io_enable(struct atw_softc *, int); 279 280/* RFMD RF3000 Baseband Processor */ 281static int atw_rf3000_init(struct atw_softc *); 282static int atw_rf3000_tune(struct atw_softc *, u_int); 283static int atw_rf3000_write(struct atw_softc *, u_int, u_int); 284 285/* Silicon Laboratories Si4126 RF/IF Synthesizer */ 286static void atw_si4126_tune(struct atw_softc *, u_int); 287static void atw_si4126_write(struct atw_softc *, u_int, u_int); 288 289const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE; 290const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE; 291 292const char *atw_tx_state[] = { 293 "STOPPED", 294 "RUNNING - read descriptor", 295 "RUNNING - transmitting", 296 "RUNNING - filling fifo", /* XXX */ 297 "SUSPENDED", 298 "RUNNING -- write descriptor", 299 "RUNNING -- write last descriptor", 300 "RUNNING - fifo full" 301}; 302 303const char *atw_rx_state[] = { 304 "STOPPED", 305 "RUNNING - read descriptor", 306 "RUNNING - check this packet, pre-fetch next", 307 "RUNNING - wait for reception", 308 "SUSPENDED", 309 "RUNNING - write descriptor", 310 "RUNNING - flush fifo", 311 "RUNNING - fifo drain" 312}; 313 314static inline int 315is_running(struct ifnet *ifp) 316{ 317 return (ifp->if_flags & (IFF_RUNNING|IFF_UP)) == (IFF_RUNNING|IFF_UP); 318} 319 320int 321atw_activate(struct device *self, enum devact act) 322{ 323 struct atw_softc *sc = (struct atw_softc *)self; 324 int rv = 0, s; 325 326 s = splnet(); 327 switch (act) { 328 case DVACT_ACTIVATE: 329 rv = EOPNOTSUPP; 330 break; 331 332 case DVACT_DEACTIVATE: 333 if_deactivate(&sc->sc_if); 334 break; 335 } 336 splx(s); 337 return rv; 338} 339 340/* 341 * atw_enable: 342 * 343 * Enable the ADM8211 chip. 344 */ 345int 346atw_enable(struct atw_softc *sc) 347{ 348 349 if (ATW_IS_ENABLED(sc) == 0) { 350 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 351 printf("%s: device enable failed\n", 352 sc->sc_dev.dv_xname); 353 return (EIO); 354 } 355 sc->sc_flags |= ATWF_ENABLED; 356 /* Power may have been removed, and WEP keys thus 357 * reset. 358 */ 359 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 360 } 361 return (0); 362} 363 364/* 365 * atw_disable: 366 * 367 * Disable the ADM8211 chip. 368 */ 369void 370atw_disable(struct atw_softc *sc) 371{ 372 if (!ATW_IS_ENABLED(sc)) 373 return; 374 if (sc->sc_disable != NULL) 375 (*sc->sc_disable)(sc); 376 sc->sc_flags &= ~ATWF_ENABLED; 377} 378 379/* Returns -1 on failure. */ 380static int 381atw_read_srom(struct atw_softc *sc) 382{ 383 struct seeprom_descriptor sd; 384 uint32_t test0, fail_bits; 385 386 (void)memset(&sd, 0, sizeof(sd)); 387 388 test0 = ATW_READ(sc, ATW_TEST0); 389 390 switch (sc->sc_rev) { 391 case ATW_REVISION_BA: 392 case ATW_REVISION_CA: 393 fail_bits = ATW_TEST0_EPNE; 394 break; 395 default: 396 fail_bits = ATW_TEST0_EPNE|ATW_TEST0_EPSNM; 397 break; 398 } 399 if ((test0 & fail_bits) != 0) { 400 printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname); 401 return -1; 402 } 403 404 switch (test0 & ATW_TEST0_EPTYP_MASK) { 405 case ATW_TEST0_EPTYP_93c66: 406 ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname)); 407 sc->sc_sromsz = 512; 408 sd.sd_chip = C56_66; 409 break; 410 case ATW_TEST0_EPTYP_93c46: 411 ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname)); 412 sc->sc_sromsz = 128; 413 sd.sd_chip = C46; 414 break; 415 default: 416 printf("%s: unknown SROM type %d\n", sc->sc_dev.dv_xname, 417 SHIFTOUT(test0, ATW_TEST0_EPTYP_MASK)); 418 return -1; 419 } 420 421 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT); 422 423 if (sc->sc_srom == NULL) { 424 printf("%s: unable to allocate SROM buffer\n", 425 sc->sc_dev.dv_xname); 426 return -1; 427 } 428 429 (void)memset(sc->sc_srom, 0, sc->sc_sromsz); 430 431 /* ADM8211 has a single 32-bit register for controlling the 432 * 93cx6 SROM. Bit SRS enables the serial port. There is no 433 * "ready" bit. The ADM8211 input/output sense is the reverse 434 * of read_seeprom's. 435 */ 436 sd.sd_tag = sc->sc_st; 437 sd.sd_bsh = sc->sc_sh; 438 sd.sd_regsize = 4; 439 sd.sd_control_offset = ATW_SPR; 440 sd.sd_status_offset = ATW_SPR; 441 sd.sd_dataout_offset = ATW_SPR; 442 sd.sd_CK = ATW_SPR_SCLK; 443 sd.sd_CS = ATW_SPR_SCS; 444 sd.sd_DI = ATW_SPR_SDO; 445 sd.sd_DO = ATW_SPR_SDI; 446 sd.sd_MS = ATW_SPR_SRS; 447 sd.sd_RDY = 0; 448 449 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 450 printf("%s: could not read SROM\n", sc->sc_dev.dv_xname); 451 free(sc->sc_srom, M_DEVBUF); 452 return -1; 453 } 454#ifdef ATW_DEBUG 455 { 456 int i; 457 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 458 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 459 if (((i % 8) == 0) && (i != 0)) { 460 ATW_DPRINTF(("\n\t")); 461 } 462 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 463 } 464 ATW_DPRINTF(("\n")); 465 } 466#endif /* ATW_DEBUG */ 467 return 0; 468} 469 470#ifdef ATW_DEBUG 471static void 472atw_print_regs(struct atw_softc *sc, const char *where) 473{ 474#define PRINTREG(sc, reg) \ 475 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 476 sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg))) 477 478 ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where)); 479 480 PRINTREG(sc, ATW_PAR); 481 PRINTREG(sc, ATW_FRCTL); 482 PRINTREG(sc, ATW_TDR); 483 PRINTREG(sc, ATW_WTDP); 484 PRINTREG(sc, ATW_RDR); 485 PRINTREG(sc, ATW_WRDP); 486 PRINTREG(sc, ATW_RDB); 487 PRINTREG(sc, ATW_CSR3A); 488 PRINTREG(sc, ATW_TDBD); 489 PRINTREG(sc, ATW_TDBP); 490 PRINTREG(sc, ATW_STSR); 491 PRINTREG(sc, ATW_CSR5A); 492 PRINTREG(sc, ATW_NAR); 493 PRINTREG(sc, ATW_CSR6A); 494 PRINTREG(sc, ATW_IER); 495 PRINTREG(sc, ATW_CSR7A); 496 PRINTREG(sc, ATW_LPC); 497 PRINTREG(sc, ATW_TEST1); 498 PRINTREG(sc, ATW_SPR); 499 PRINTREG(sc, ATW_TEST0); 500 PRINTREG(sc, ATW_WCSR); 501 PRINTREG(sc, ATW_WPDR); 502 PRINTREG(sc, ATW_GPTMR); 503 PRINTREG(sc, ATW_GPIO); 504 PRINTREG(sc, ATW_BBPCTL); 505 PRINTREG(sc, ATW_SYNCTL); 506 PRINTREG(sc, ATW_PLCPHD); 507 PRINTREG(sc, ATW_MMIWADDR); 508 PRINTREG(sc, ATW_MMIRADDR1); 509 PRINTREG(sc, ATW_MMIRADDR2); 510 PRINTREG(sc, ATW_TXBR); 511 PRINTREG(sc, ATW_CSR15A); 512 PRINTREG(sc, ATW_ALCSTAT); 513 PRINTREG(sc, ATW_TOFS2); 514 PRINTREG(sc, ATW_CMDR); 515 PRINTREG(sc, ATW_PCIC); 516 PRINTREG(sc, ATW_PMCSR); 517 PRINTREG(sc, ATW_PAR0); 518 PRINTREG(sc, ATW_PAR1); 519 PRINTREG(sc, ATW_MAR0); 520 PRINTREG(sc, ATW_MAR1); 521 PRINTREG(sc, ATW_ATIMDA0); 522 PRINTREG(sc, ATW_ABDA1); 523 PRINTREG(sc, ATW_BSSID0); 524 PRINTREG(sc, ATW_TXLMT); 525 PRINTREG(sc, ATW_MIBCNT); 526 PRINTREG(sc, ATW_BCNT); 527 PRINTREG(sc, ATW_TSFTH); 528 PRINTREG(sc, ATW_TSC); 529 PRINTREG(sc, ATW_SYNRF); 530 PRINTREG(sc, ATW_BPLI); 531 PRINTREG(sc, ATW_CAP0); 532 PRINTREG(sc, ATW_CAP1); 533 PRINTREG(sc, ATW_RMD); 534 PRINTREG(sc, ATW_CFPP); 535 PRINTREG(sc, ATW_TOFS0); 536 PRINTREG(sc, ATW_TOFS1); 537 PRINTREG(sc, ATW_IFST); 538 PRINTREG(sc, ATW_RSPT); 539 PRINTREG(sc, ATW_TSFTL); 540 PRINTREG(sc, ATW_WEPCTL); 541 PRINTREG(sc, ATW_WESK); 542 PRINTREG(sc, ATW_WEPCNT); 543 PRINTREG(sc, ATW_MACTEST); 544 PRINTREG(sc, ATW_FER); 545 PRINTREG(sc, ATW_FEMR); 546 PRINTREG(sc, ATW_FPSR); 547 PRINTREG(sc, ATW_FFER); 548#undef PRINTREG 549} 550#endif /* ATW_DEBUG */ 551 552/* 553 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 554 */ 555void 556atw_attach(struct atw_softc *sc) 557{ 558 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 559 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 560 }; 561 struct ieee80211com *ic = &sc->sc_ic; 562 struct ifnet *ifp = &sc->sc_if; 563 int country_code, error, i, nrate, srom_major; 564 u_int32_t reg; 565 static const char *type_strings[] = {"Intersil (not supported)", 566 "RFMD", "Marvel (not supported)"}; 567 568 sc->sc_txth = atw_txthresh_tab_lo; 569 570 SIMPLEQ_INIT(&sc->sc_txfreeq); 571 SIMPLEQ_INIT(&sc->sc_txdirtyq); 572 573#ifdef ATW_DEBUG 574 atw_print_regs(sc, "atw_attach"); 575#endif /* ATW_DEBUG */ 576 577 /* 578 * Allocate the control data structures, and create and load the 579 * DMA map for it. 580 */ 581 if ((error = bus_dmamem_alloc(sc->sc_dmat, 582 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 583 1, &sc->sc_cdnseg, 0)) != 0) { 584 printf("%s: unable to allocate control data, error = %d\n", 585 sc->sc_dev.dv_xname, error); 586 goto fail_0; 587 } 588 589 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 590 sizeof(struct atw_control_data), (caddr_t *)&sc->sc_control_data, 591 BUS_DMA_COHERENT)) != 0) { 592 printf("%s: unable to map control data, error = %d\n", 593 sc->sc_dev.dv_xname, error); 594 goto fail_1; 595 } 596 597 if ((error = bus_dmamap_create(sc->sc_dmat, 598 sizeof(struct atw_control_data), 1, 599 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 600 printf("%s: unable to create control data DMA map, " 601 "error = %d\n", sc->sc_dev.dv_xname, error); 602 goto fail_2; 603 } 604 605 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 606 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 607 0)) != 0) { 608 printf("%s: unable to load control data DMA map, error = %d\n", 609 sc->sc_dev.dv_xname, error); 610 goto fail_3; 611 } 612 613 /* 614 * Create the transmit buffer DMA maps. 615 */ 616 sc->sc_ntxsegs = ATW_NTXSEGS; 617 for (i = 0; i < ATW_TXQUEUELEN; i++) { 618 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 619 sc->sc_ntxsegs, MCLBYTES, 0, 0, 620 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 621 printf("%s: unable to create tx DMA map %d, " 622 "error = %d\n", sc->sc_dev.dv_xname, i, error); 623 goto fail_4; 624 } 625 } 626 627 /* 628 * Create the receive buffer DMA maps. 629 */ 630 for (i = 0; i < ATW_NRXDESC; i++) { 631 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 632 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 633 printf("%s: unable to create rx DMA map %d, " 634 "error = %d\n", sc->sc_dev.dv_xname, i, error); 635 goto fail_5; 636 } 637 } 638 for (i = 0; i < ATW_NRXDESC; i++) { 639 sc->sc_rxsoft[i].rxs_mbuf = NULL; 640 } 641 642 switch (sc->sc_rev) { 643 case ATW_REVISION_AB: 644 case ATW_REVISION_AF: 645 sc->sc_sramlen = ATW_SRAM_A_SIZE; 646 break; 647 case ATW_REVISION_BA: 648 case ATW_REVISION_CA: 649 sc->sc_sramlen = ATW_SRAM_B_SIZE; 650 break; 651 } 652 653 /* Reset the chip to a known state. */ 654 atw_reset(sc); 655 656 if (atw_read_srom(sc) == -1) 657 return; 658 659 sc->sc_rftype = SHIFTOUT(sc->sc_srom[ATW_SR_CSR20], 660 ATW_SR_RFTYPE_MASK); 661 662 sc->sc_bbptype = SHIFTOUT(sc->sc_srom[ATW_SR_CSR20], 663 ATW_SR_BBPTYPE_MASK); 664 665 if (sc->sc_rftype > sizeof(type_strings)/sizeof(type_strings[0])) { 666 printf("%s: unknown RF\n", sc->sc_dev.dv_xname); 667 return; 668 } 669 if (sc->sc_bbptype > sizeof(type_strings)/sizeof(type_strings[0])) { 670 printf("%s: unknown BBP\n", sc->sc_dev.dv_xname); 671 return; 672 } 673 674 printf("%s: %s RF, %s BBP", sc->sc_dev.dv_xname, 675 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]); 676 677 /* XXX There exists a Linux driver which seems to use RFType = 0 for 678 * MARVEL. My bug, or theirs? 679 */ 680 681 reg = SHIFTIN(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 682 683 switch (sc->sc_rftype) { 684 case ATW_RFTYPE_INTERSIL: 685 reg |= ATW_SYNCTL_CS1; 686 break; 687 case ATW_RFTYPE_RFMD: 688 reg |= ATW_SYNCTL_CS0; 689 break; 690 case ATW_RFTYPE_MARVEL: 691 break; 692 } 693 694 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 695 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 696 697 reg = SHIFTIN(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 698 699 switch (sc->sc_bbptype) { 700 case ATW_BBPTYPE_INTERSIL: 701 reg |= ATW_BBPCTL_TWI; 702 break; 703 case ATW_BBPTYPE_RFMD: 704 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 705 ATW_BBPCTL_CCA_ACTLO; 706 break; 707 case ATW_BBPTYPE_MARVEL: 708 break; 709 case ATW_C_BBPTYPE_RFMD: 710 printf("%s: ADM8211C MAC/RFMD BBP not supported yet.\n", 711 sc->sc_dev.dv_xname); 712 break; 713 } 714 715 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 716 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 717 718 /* 719 * From this point forward, the attachment cannot fail. A failure 720 * before this point releases all resources that may have been 721 * allocated. 722 */ 723 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 724 725 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 726 htole16(sc->sc_srom[ATW_SR_MAC00]), 727 htole16(sc->sc_srom[ATW_SR_MAC01]), 728 htole16(sc->sc_srom[ATW_SR_MAC10]))); 729 730 srom_major = SHIFTOUT(sc->sc_srom[ATW_SR_FORMAT_VERSION], 731 ATW_SR_MAJOR_MASK); 732 733 if (srom_major < 2) 734 sc->sc_rf3000_options1 = 0; 735 else if (sc->sc_rev == ATW_REVISION_BA) { 736 sc->sc_rf3000_options1 = 737 SHIFTOUT(sc->sc_srom[ATW_SR_CR28_CR03], 738 ATW_SR_CR28_MASK); 739 } else 740 sc->sc_rf3000_options1 = 0; 741 742 sc->sc_rf3000_options2 = SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29], 743 ATW_SR_CR29_MASK); 744 745 country_code = SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29], 746 ATW_SR_CTRY_MASK); 747 748#define ADD_CHANNEL(_ic, _chan) do { \ 749 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 750 _ic->ic_channels[_chan].ic_freq = \ 751 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 752} while (0) 753 754 /* Find available channels */ 755 switch (country_code) { 756 case COUNTRY_MMK2: /* 1-14 */ 757 ADD_CHANNEL(ic, 14); 758 /*FALLTHROUGH*/ 759 case COUNTRY_ETSI: /* 1-13 */ 760 for (i = 1; i <= 13; i++) 761 ADD_CHANNEL(ic, i); 762 break; 763 case COUNTRY_FCC: /* 1-11 */ 764 case COUNTRY_IC: /* 1-11 */ 765 for (i = 1; i <= 11; i++) 766 ADD_CHANNEL(ic, i); 767 break; 768 case COUNTRY_MMK: /* 14 */ 769 ADD_CHANNEL(ic, 14); 770 break; 771 case COUNTRY_FRANCE: /* 10-13 */ 772 for (i = 10; i <= 13; i++) 773 ADD_CHANNEL(ic, i); 774 break; 775 default: /* assume channels 10-11 */ 776 case COUNTRY_SPAIN: /* 10-11 */ 777 for (i = 10; i <= 11; i++) 778 ADD_CHANNEL(ic, i); 779 break; 780 } 781 782 /* Read the MAC address. */ 783 reg = ATW_READ(sc, ATW_PAR0); 784 ic->ic_myaddr[0] = SHIFTOUT(reg, ATW_PAR0_PAB0_MASK); 785 ic->ic_myaddr[1] = SHIFTOUT(reg, ATW_PAR0_PAB1_MASK); 786 ic->ic_myaddr[2] = SHIFTOUT(reg, ATW_PAR0_PAB2_MASK); 787 ic->ic_myaddr[3] = SHIFTOUT(reg, ATW_PAR0_PAB3_MASK); 788 reg = ATW_READ(sc, ATW_PAR1); 789 ic->ic_myaddr[4] = SHIFTOUT(reg, ATW_PAR1_PAB4_MASK); 790 ic->ic_myaddr[5] = SHIFTOUT(reg, ATW_PAR1_PAB5_MASK); 791 792 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 793 printf(" could not get mac address, attach failed\n"); 794 return; 795 } 796 797 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr)); 798 799 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 800 ifp->if_softc = sc; 801 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 802 IFF_NOTRAILERS; 803 ifp->if_ioctl = atw_ioctl; 804 ifp->if_start = atw_start; 805 ifp->if_watchdog = atw_watchdog; 806 ifp->if_init = atw_init; 807 ifp->if_stop = atw_stop; 808 IFQ_SET_READY(&ifp->if_snd); 809 810 ic->ic_ifp = ifp; 811 ic->ic_phytype = IEEE80211_T_DS; 812 ic->ic_opmode = IEEE80211_M_STA; 813 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS | 814 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR; 815 816 nrate = 0; 817 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2; 818 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4; 819 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11; 820 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22; 821 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate; 822 823 /* 824 * Call MI attach routines. 825 */ 826 827 if_attach(ifp); 828 ieee80211_ifattach(ic); 829 830 sc->sc_newstate = ic->ic_newstate; 831 ic->ic_newstate = atw_newstate; 832 833 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 834 ic->ic_recv_mgmt = atw_recv_mgmt; 835 836 sc->sc_node_free = ic->ic_node_free; 837 ic->ic_node_free = atw_node_free; 838 839 sc->sc_node_alloc = ic->ic_node_alloc; 840 ic->ic_node_alloc = atw_node_alloc; 841 842 ic->ic_crypto.cs_key_delete = atw_key_delete; 843 ic->ic_crypto.cs_key_set = atw_key_set; 844 ic->ic_crypto.cs_key_update_begin = atw_key_update_begin; 845 ic->ic_crypto.cs_key_update_end = atw_key_update_end; 846 847 /* possibly we should fill in our own sc_send_prresp, since 848 * the ADM8211 is probably sending probe responses in ad hoc 849 * mode. 850 */ 851 852 /* complete initialization */ 853 ieee80211_media_init(ic, atw_media_change, ieee80211_media_status); 854 callout_init(&sc->sc_scan_ch); 855 856#if NBPFILTER > 0 857 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 858 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf); 859#endif 860 861 /* 862 * Make sure the interface is shutdown during reboot. 863 */ 864 sc->sc_sdhook = shutdownhook_establish(atw_shutdown, sc); 865 if (sc->sc_sdhook == NULL) 866 printf("%s: WARNING: unable to establish shutdown hook\n", 867 sc->sc_dev.dv_xname); 868 869 /* 870 * Add a suspend hook to make sure we come back up after a 871 * resume. 872 */ 873 sc->sc_powerhook = powerhook_establish(atw_power, sc); 874 if (sc->sc_powerhook == NULL) 875 printf("%s: WARNING: unable to establish power hook\n", 876 sc->sc_dev.dv_xname); 877 878 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 879 sc->sc_rxtap.ar_ihdr.it_len = sizeof(sc->sc_rxtapu); 880 sc->sc_rxtap.ar_ihdr.it_present = ATW_RX_RADIOTAP_PRESENT; 881 882 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 883 sc->sc_txtap.at_ihdr.it_len = sizeof(sc->sc_txtapu); 884 sc->sc_txtap.at_ihdr.it_present = ATW_TX_RADIOTAP_PRESENT; 885 886 ieee80211_announce(ic); 887 return; 888 889 /* 890 * Free any resources we've allocated during the failed attach 891 * attempt. Do this in reverse order and fall through. 892 */ 893 fail_5: 894 for (i = 0; i < ATW_NRXDESC; i++) { 895 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 896 continue; 897 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 898 } 899 fail_4: 900 for (i = 0; i < ATW_TXQUEUELEN; i++) { 901 if (sc->sc_txsoft[i].txs_dmamap == NULL) 902 continue; 903 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 904 } 905 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 906 fail_3: 907 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 908 fail_2: 909 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 910 sizeof(struct atw_control_data)); 911 fail_1: 912 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 913 fail_0: 914 return; 915} 916 917static struct ieee80211_node * 918atw_node_alloc(struct ieee80211_node_table *nt) 919{ 920 struct atw_softc *sc = (struct atw_softc *)nt->nt_ic->ic_ifp->if_softc; 921 struct ieee80211_node *ni = (*sc->sc_node_alloc)(nt); 922 923 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 924 return ni; 925} 926 927static void 928atw_node_free(struct ieee80211_node *ni) 929{ 930 struct atw_softc *sc = (struct atw_softc *)ni->ni_ic->ic_ifp->if_softc; 931 932 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 933 ether_sprintf(ni->ni_bssid))); 934 (*sc->sc_node_free)(ni); 935} 936 937 938static void 939atw_test1_reset(struct atw_softc *sc) 940{ 941 switch (sc->sc_rev) { 942 case ATW_REVISION_BA: 943 if (1 /* XXX condition on transceiver type */) { 944 ATW_SET(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MONITOR); 945 } 946 break; 947 case ATW_REVISION_CA: 948 ATW_CLR(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MASK); 949 break; 950 default: 951 break; 952 } 953} 954 955/* 956 * atw_reset: 957 * 958 * Perform a soft reset on the ADM8211. 959 */ 960void 961atw_reset(struct atw_softc *sc) 962{ 963 int i; 964 uint32_t lpc; 965 966 ATW_WRITE(sc, ATW_NAR, 0x0); 967 DELAY(atw_nar_delay); 968 969 /* Reference driver has a cryptic remark indicating that this might 970 * power-on the chip. I know that it turns off power-saving.... 971 */ 972 ATW_WRITE(sc, ATW_FRCTL, 0x0); 973 974 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 975 976 for (i = 0; i < 50000 / atw_pseudo_milli; i++) { 977 if ((ATW_READ(sc, ATW_PAR) & ATW_PAR_SWR) == 0) 978 break; 979 DELAY(atw_pseudo_milli); 980 } 981 982 /* ... and then pause 100ms longer for good measure. */ 983 DELAY(atw_magic_delay1); 984 985 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i)); 986 987 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 988 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 989 990 /* 991 * Initialize the PCI Access Register. 992 */ 993 sc->sc_busmode = ATW_PAR_PBL_8DW; 994 995 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 996 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 997 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 998 999 atw_test1_reset(sc); 1000 1001 /* Turn off maximum power saving, etc. */ 1002 ATW_WRITE(sc, ATW_FRCTL, 0x0); 1003 1004 DELAY(atw_magic_delay2); 1005 1006 /* Recall EEPROM. */ 1007 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 1008 1009 DELAY(atw_magic_delay4); 1010 1011 lpc = ATW_READ(sc, ATW_LPC); 1012 1013 DPRINTF(sc, ("%s: ATW_LPC %#08x\n", __func__, lpc)); 1014 1015 /* A reset seems to affect the SRAM contents, so put them into 1016 * a known state. 1017 */ 1018 atw_clear_sram(sc); 1019 1020 memset(sc->sc_bssid, 0xff, sizeof(sc->sc_bssid)); 1021} 1022 1023static void 1024atw_clear_sram(struct atw_softc *sc) 1025{ 1026 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 1027 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 1028 /* XXX not for revision 0x20. */ 1029 atw_write_sram(sc, 0, sc->sc_sram, sc->sc_sramlen); 1030} 1031 1032/* TBD atw_init 1033 * 1034 * set MAC based on ic->ic_bss->myaddr 1035 * write WEP keys 1036 * set TX rate 1037 */ 1038 1039/* Tell the ADM8211 to raise ATW_INTR_LINKOFF if 7 beacon intervals pass 1040 * without receiving a beacon with the preferred BSSID & SSID. 1041 * atw_write_bssid & atw_write_ssid set the BSSID & SSID. 1042 */ 1043static void 1044atw_wcsr_init(struct atw_softc *sc) 1045{ 1046 uint32_t wcsr; 1047 1048 wcsr = ATW_READ(sc, ATW_WCSR); 1049 wcsr &= ~(ATW_WCSR_BLN_MASK|ATW_WCSR_LSOE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1050 wcsr |= SHIFTIN(7, ATW_WCSR_BLN_MASK); 1051 ATW_WRITE(sc, ATW_WCSR, wcsr); /* XXX resets wake-up status bits */ 1052 1053 DPRINTF(sc, ("%s: %s reg[WCSR] = %08x\n", 1054 sc->sc_dev.dv_xname, __func__, ATW_READ(sc, ATW_WCSR))); 1055} 1056 1057/* Turn off power management. Set Rx store-and-forward mode. */ 1058static void 1059atw_cmdr_init(struct atw_softc *sc) 1060{ 1061 uint32_t cmdr; 1062 cmdr = ATW_READ(sc, ATW_CMDR); 1063 cmdr &= ~ATW_CMDR_APM; 1064 cmdr |= ATW_CMDR_RTE; 1065 cmdr &= ~ATW_CMDR_DRT_MASK; 1066 cmdr |= ATW_CMDR_DRT_SF; 1067 1068 ATW_WRITE(sc, ATW_CMDR, cmdr); 1069} 1070 1071static void 1072atw_tofs2_init(struct atw_softc *sc) 1073{ 1074 uint32_t tofs2; 1075 /* XXX this magic can probably be figured out from the RFMD docs */ 1076#ifndef ATW_REFSLAVE 1077 tofs2 = SHIFTIN(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1078 SHIFTIN(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1079 SHIFTIN(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1080 SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1081 SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1082 SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1083 SHIFTIN(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1084 SHIFTIN(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1085#else 1086 /* XXX new magic from reference driver source */ 1087 tofs2 = SHIFTIN(8, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1088 SHIFTIN(8, ATW_TOFS2_PWR0PAPE_MASK) | /* 8 us */ 1089 SHIFTIN(1, ATW_TOFS2_PWR1PAPE_MASK) | /* 1 us */ 1090 SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1091 SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1092 SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1093 SHIFTIN(1, ATW_TOFS2_PWR1PE2_MASK) | /* 1 us */ 1094 SHIFTIN(8, ATW_TOFS2_PWR0TXPE_MASK); /* 8 us */ 1095#endif 1096 ATW_WRITE(sc, ATW_TOFS2, tofs2); 1097} 1098 1099static void 1100atw_nar_init(struct atw_softc *sc) 1101{ 1102 ATW_WRITE(sc, ATW_NAR, ATW_NAR_SF|ATW_NAR_PB); 1103} 1104 1105static void 1106atw_txlmt_init(struct atw_softc *sc) 1107{ 1108 ATW_WRITE(sc, ATW_TXLMT, SHIFTIN(512, ATW_TXLMT_MTMLT_MASK) | 1109 SHIFTIN(1, ATW_TXLMT_SRTYLIM_MASK)); 1110} 1111 1112static void 1113atw_test1_init(struct atw_softc *sc) 1114{ 1115 uint32_t test1; 1116 1117 test1 = ATW_READ(sc, ATW_TEST1); 1118 test1 &= ~(ATW_TEST1_DBGREAD_MASK|ATW_TEST1_CONTROL); 1119 /* XXX magic 0x1 */ 1120 test1 |= SHIFTIN(0x1, ATW_TEST1_DBGREAD_MASK) | ATW_TEST1_CONTROL; 1121 ATW_WRITE(sc, ATW_TEST1, test1); 1122} 1123 1124static void 1125atw_rf_reset(struct atw_softc *sc) 1126{ 1127 /* XXX this resets an Intersil RF front-end? */ 1128 /* TBD condition on Intersil RFType? */ 1129 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 1130 DELAY(atw_rf_delay1); 1131 ATW_WRITE(sc, ATW_SYNRF, 0); 1132 DELAY(atw_rf_delay2); 1133} 1134 1135/* Set 16 TU max duration for the contention-free period (CFP). */ 1136static void 1137atw_cfp_init(struct atw_softc *sc) 1138{ 1139 uint32_t cfpp; 1140 1141 cfpp = ATW_READ(sc, ATW_CFPP); 1142 cfpp &= ~ATW_CFPP_CFPMD; 1143 cfpp |= SHIFTIN(16, ATW_CFPP_CFPMD); 1144 ATW_WRITE(sc, ATW_CFPP, cfpp); 1145} 1146 1147static void 1148atw_tofs0_init(struct atw_softc *sc) 1149{ 1150 /* XXX I guess that the Cardbus clock is 22MHz? 1151 * I am assuming that the role of ATW_TOFS0_USCNT is 1152 * to divide the bus clock to get a 1MHz clock---the datasheet is not 1153 * very clear on this point. It says in the datasheet that it is 1154 * possible for the ADM8211 to accomodate bus speeds between 22MHz 1155 * and 33MHz; maybe this is the way? I see a binary-only driver write 1156 * these values. These values are also the power-on default. 1157 */ 1158 ATW_WRITE(sc, ATW_TOFS0, 1159 SHIFTIN(22, ATW_TOFS0_USCNT_MASK) | 1160 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 1161} 1162 1163/* Initialize interframe spacing: 802.11b slot time, SIFS, DIFS, EIFS. */ 1164static void 1165atw_ifs_init(struct atw_softc *sc) 1166{ 1167 uint32_t ifst; 1168 /* XXX EIFS=0x64, SIFS=110 are used by the reference driver. 1169 * Go figure. 1170 */ 1171 ifst = SHIFTIN(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 1172 SHIFTIN(22 * 5 /* IEEE80211_DUR_DS_SIFS */ /* # of 22MHz cycles */, 1173 ATW_IFST_SIFS_MASK) | 1174 SHIFTIN(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1175 SHIFTIN(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 1176 1177 ATW_WRITE(sc, ATW_IFST, ifst); 1178} 1179 1180static void 1181atw_response_times_init(struct atw_softc *sc) 1182{ 1183 /* XXX More magic. Relates to ACK timing? The datasheet seems to 1184 * indicate that the MAC expects at least SIFS + MIRT microseconds 1185 * to pass after it transmits a frame that requires a response; 1186 * it waits at most SIFS + MART microseconds for the response. 1187 * Surely this is not the ACK timeout? 1188 */ 1189 ATW_WRITE(sc, ATW_RSPT, SHIFTIN(0xffff, ATW_RSPT_MART_MASK) | 1190 SHIFTIN(0xff, ATW_RSPT_MIRT_MASK)); 1191} 1192 1193/* Set up the MMI read/write addresses for the baseband. The Tx/Rx 1194 * engines read and write baseband registers after Rx and before 1195 * Tx, respectively. 1196 */ 1197static void 1198atw_bbp_io_init(struct atw_softc *sc) 1199{ 1200 uint32_t mmiraddr2; 1201 1202 /* XXX The reference driver does this, but is it *really* 1203 * necessary? 1204 */ 1205 switch (sc->sc_rev) { 1206 case ATW_REVISION_AB: 1207 case ATW_REVISION_AF: 1208 mmiraddr2 = 0x0; 1209 break; 1210 default: 1211 mmiraddr2 = ATW_READ(sc, ATW_MMIRADDR2); 1212 mmiraddr2 &= 1213 ~(ATW_MMIRADDR2_PROREXT|ATW_MMIRADDR2_PRORLEN_MASK); 1214 break; 1215 } 1216 1217 switch (sc->sc_bbptype) { 1218 case ATW_BBPTYPE_INTERSIL: 1219 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1220 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1221 mmiraddr2 |= ATW_MMIRADDR2_INTERSIL; 1222 break; 1223 case ATW_BBPTYPE_MARVEL: 1224 /* TBD find out the Marvel settings. */ 1225 break; 1226 case ATW_BBPTYPE_RFMD: 1227 default: 1228 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1229 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1230 mmiraddr2 |= ATW_MMIRADDR2_RFMD; 1231 break; 1232 } 1233 ATW_WRITE(sc, ATW_MMIRADDR2, mmiraddr2); 1234 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1235} 1236 1237/* 1238 * atw_init: [ ifnet interface function ] 1239 * 1240 * Initialize the interface. Must be called at splnet(). 1241 */ 1242int 1243atw_init(struct ifnet *ifp) 1244{ 1245 struct atw_softc *sc = ifp->if_softc; 1246 struct ieee80211com *ic = &sc->sc_ic; 1247 struct atw_txsoft *txs; 1248 struct atw_rxsoft *rxs; 1249 int i, error = 0; 1250 1251 if ((error = atw_enable(sc)) != 0) 1252 goto out; 1253 1254 /* 1255 * Cancel any pending I/O. This also resets. 1256 */ 1257 atw_stop(ifp, 0); 1258 1259 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 1260 __func__, ieee80211_chan2ieee(ic, ic->ic_curchan), 1261 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags)); 1262 1263 atw_wcsr_init(sc); 1264 1265 atw_cmdr_init(sc); 1266 1267 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 1268 * 1269 * XXX Set transmit power for ATIM, RTS, Beacon. 1270 */ 1271 ATW_WRITE(sc, ATW_PLCPHD, SHIFTIN(10, ATW_PLCPHD_SIGNAL_MASK) | 1272 SHIFTIN(0xb0, ATW_PLCPHD_SERVICE_MASK)); 1273 1274 atw_tofs2_init(sc); 1275 1276 atw_nar_init(sc); 1277 1278 atw_txlmt_init(sc); 1279 1280 atw_test1_init(sc); 1281 1282 atw_rf_reset(sc); 1283 1284 atw_cfp_init(sc); 1285 1286 atw_tofs0_init(sc); 1287 1288 atw_ifs_init(sc); 1289 1290 /* XXX Fall asleep after one second of inactivity. 1291 * XXX A frame may only dribble in for 65536us. 1292 */ 1293 ATW_WRITE(sc, ATW_RMD, 1294 SHIFTIN(1, ATW_RMD_PCNT) | SHIFTIN(0xffff, ATW_RMD_RMRD_MASK)); 1295 1296 atw_response_times_init(sc); 1297 1298 atw_bbp_io_init(sc); 1299 1300 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1301 1302 if ((error = atw_rf3000_init(sc)) != 0) 1303 goto out; 1304 1305 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1306 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 1307 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1308 1309 /* 1310 * Initialize the transmit descriptor ring. 1311 */ 1312 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1313 for (i = 0; i < ATW_NTXDESC; i++) { 1314 sc->sc_txdescs[i].at_ctl = 0; 1315 /* no transmit chaining */ 1316 sc->sc_txdescs[i].at_flags = 0 /* ATW_TXFLAG_TCH */; 1317 sc->sc_txdescs[i].at_buf2 = 1318 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1319 } 1320 /* use ring mode */ 1321 sc->sc_txdescs[ATW_NTXDESC - 1].at_flags |= htole32(ATW_TXFLAG_TER); 1322 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1323 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1324 sc->sc_txfree = ATW_NTXDESC; 1325 sc->sc_txnext = 0; 1326 1327 /* 1328 * Initialize the transmit job descriptors. 1329 */ 1330 SIMPLEQ_INIT(&sc->sc_txfreeq); 1331 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1332 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1333 txs = &sc->sc_txsoft[i]; 1334 txs->txs_mbuf = NULL; 1335 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1336 } 1337 1338 /* 1339 * Initialize the receive descriptor and receive job 1340 * descriptor rings. 1341 */ 1342 for (i = 0; i < ATW_NRXDESC; i++) { 1343 rxs = &sc->sc_rxsoft[i]; 1344 if (rxs->rxs_mbuf == NULL) { 1345 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1346 printf("%s: unable to allocate or map rx " 1347 "buffer %d, error = %d\n", 1348 sc->sc_dev.dv_xname, i, error); 1349 /* 1350 * XXX Should attempt to run with fewer receive 1351 * XXX buffers instead of just failing. 1352 */ 1353 atw_rxdrain(sc); 1354 goto out; 1355 } 1356 } else 1357 ATW_INIT_RXDESC(sc, i); 1358 } 1359 sc->sc_rxptr = 0; 1360 1361 /* 1362 * Initialize the interrupt mask and enable interrupts. 1363 */ 1364 /* normal interrupts */ 1365 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1366 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1367 1368 /* abnormal interrupts */ 1369 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1370 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1371 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1372 1373 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1374 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1375 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1376 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1377 ATW_INTR_TRT; 1378 1379 sc->sc_linkint_mask &= sc->sc_inten; 1380 sc->sc_rxint_mask &= sc->sc_inten; 1381 sc->sc_txint_mask &= sc->sc_inten; 1382 1383 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1384 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1385 1386 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1387 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten)); 1388 1389 /* 1390 * Give the transmit and receive rings to the ADM8211. 1391 */ 1392 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1393 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1394 1395 sc->sc_txthresh = 0; 1396 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1397 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1398 1399 /* common 802.11 configuration */ 1400 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1401 switch (ic->ic_opmode) { 1402 case IEEE80211_M_STA: 1403 break; 1404 case IEEE80211_M_AHDEMO: /* XXX */ 1405 case IEEE80211_M_IBSS: 1406 ic->ic_flags |= IEEE80211_F_IBSSON; 1407 /*FALLTHROUGH*/ 1408 case IEEE80211_M_HOSTAP: /* XXX */ 1409 break; 1410 case IEEE80211_M_MONITOR: /* XXX */ 1411 break; 1412 } 1413 1414 switch (ic->ic_opmode) { 1415 case IEEE80211_M_AHDEMO: 1416 case IEEE80211_M_HOSTAP: 1417#ifndef IEEE80211_NO_HOSTAP 1418 ic->ic_bss->ni_intval = ic->ic_lintval; 1419 ic->ic_bss->ni_rssi = 0; 1420 ic->ic_bss->ni_rstamp = 0; 1421#endif /* !IEEE80211_NO_HOSTAP */ 1422 break; 1423 default: /* XXX */ 1424 break; 1425 } 1426 1427 sc->sc_wepctl = 0; 1428 1429 atw_write_ssid(sc); 1430 atw_write_sup_rates(sc); 1431 atw_write_wep(sc); 1432 1433 ic->ic_state = IEEE80211_S_INIT; 1434 1435 /* 1436 * Set the receive filter. This will start the transmit and 1437 * receive processes. 1438 */ 1439 atw_filter_setup(sc); 1440 1441 /* 1442 * Start the receive process. 1443 */ 1444 ATW_WRITE(sc, ATW_RDR, 0x1); 1445 1446 /* 1447 * Note that the interface is now running. 1448 */ 1449 ifp->if_flags |= IFF_RUNNING; 1450 ifp->if_flags &= ~IFF_OACTIVE; 1451 1452 /* send no beacons, yet. */ 1453 atw_start_beacon(sc, 0); 1454 1455 if (ic->ic_opmode == IEEE80211_M_MONITOR) 1456 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1457 else 1458 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1459 out: 1460 if (error) { 1461 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1462 sc->sc_tx_timer = 0; 1463 ifp->if_timer = 0; 1464 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1465 } 1466#ifdef ATW_DEBUG 1467 atw_print_regs(sc, "end of init"); 1468#endif /* ATW_DEBUG */ 1469 1470 return (error); 1471} 1472 1473/* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1474 * 0: MAC control of RF3000/Si4126. 1475 * 1476 * Applies power, or selects RF front-end? Sets reset condition. 1477 * 1478 * TBD support non-RFMD BBP, non-SiLabs synth. 1479 */ 1480static void 1481atw_bbp_io_enable(struct atw_softc *sc, int enable) 1482{ 1483 if (enable) { 1484 ATW_WRITE(sc, ATW_SYNRF, 1485 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1486 DELAY(atw_bbp_io_enable_delay); 1487 } else { 1488 ATW_WRITE(sc, ATW_SYNRF, 0); 1489 DELAY(atw_bbp_io_disable_delay); /* shorter for some reason */ 1490 } 1491} 1492 1493static int 1494atw_tune(struct atw_softc *sc) 1495{ 1496 int rc; 1497 u_int chan; 1498 struct ieee80211com *ic = &sc->sc_ic; 1499 1500 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 1501 if (chan == IEEE80211_CHAN_ANY) 1502 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__); 1503 1504 if (chan == sc->sc_cur_chan) 1505 return 0; 1506 1507 DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname, 1508 sc->sc_cur_chan, chan)); 1509 1510 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1511 1512 atw_si4126_tune(sc, chan); 1513 if ((rc = atw_rf3000_tune(sc, chan)) != 0) 1514 printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname, 1515 chan); 1516 1517 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1518 DELAY(atw_nar_delay); 1519 ATW_WRITE(sc, ATW_RDR, 0x1); 1520 1521 if (rc == 0) 1522 sc->sc_cur_chan = chan; 1523 1524 return rc; 1525} 1526 1527#ifdef ATW_SYNDEBUG 1528static void 1529atw_si4126_print(struct atw_softc *sc) 1530{ 1531 struct ifnet *ifp = &sc->sc_if; 1532 u_int addr, val; 1533 1534 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1535 return; 1536 1537 for (addr = 0; addr <= 8; addr++) { 1538 printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr); 1539 if (atw_si4126_read(sc, addr, &val) == 0) { 1540 printf("<unknown> (quitting print-out)\n"); 1541 break; 1542 } 1543 printf("%05x\n", val); 1544 } 1545} 1546#endif /* ATW_SYNDEBUG */ 1547 1548/* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1549 * 1550 * The RF/IF synthesizer produces two reference frequencies for 1551 * the RF2948B transceiver. The first frequency the RF2948B requires 1552 * is two times the so-called "intermediate frequency" (IF). Since 1553 * a SAW filter on the radio fixes the IF at 374MHz, I program the 1554 * Si4126 to generate IF LO = 374MHz x 2 = 748MHz. The second 1555 * frequency required by the transceiver is the radio frequency 1556 * (RF). This is a superheterodyne transceiver; for f(chan) the 1557 * center frequency of the channel we are tuning, RF = f(chan) - 1558 * IF. 1559 * 1560 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1561 * of XIN than the 2-25MHz mentioned by the datasheet, even *without* 1562 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1563 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1564 */ 1565static void 1566atw_si4126_tune(struct atw_softc *sc, u_int chan) 1567{ 1568 u_int mhz; 1569 u_int R; 1570 u_int32_t gpio; 1571 u_int16_t gain; 1572 1573#ifdef ATW_SYNDEBUG 1574 atw_si4126_print(sc); 1575#endif /* ATW_SYNDEBUG */ 1576 1577 if (chan == 14) 1578 mhz = 2484; 1579 else 1580 mhz = 2412 + 5 * (chan - 1); 1581 1582 /* Tune IF to 748MHz to suit the IF LO input of the 1583 * RF2494B, which is 2 x IF. No need to set an IF divider 1584 * because an IF in 526MHz - 952MHz is allowed. 1585 * 1586 * XIN is 44.000MHz, so divide it by two to get allowable 1587 * range of 2-25MHz. SiLabs tells me that this is not 1588 * strictly necessary. 1589 */ 1590 1591 if (atw_xindiv2) 1592 R = 44; 1593 else 1594 R = 88; 1595 1596 /* Power-up RF, IF synthesizers. */ 1597 atw_si4126_write(sc, SI4126_POWER, 1598 SI4126_POWER_PDIB|SI4126_POWER_PDRB); 1599 1600 /* set LPWR, too? */ 1601 atw_si4126_write(sc, SI4126_MAIN, 1602 (atw_xindiv2) ? SI4126_MAIN_XINDIV2 : 0); 1603 1604 /* Set the phase-locked loop gain. If RF2 N > 2047, then 1605 * set KP2 to 1. 1606 * 1607 * REFDIF This is different from the reference driver, which 1608 * always sets SI4126_GAIN to 0. 1609 */ 1610 gain = SHIFTIN(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1611 1612 atw_si4126_write(sc, SI4126_GAIN, gain); 1613 1614 /* XIN = 44MHz. 1615 * 1616 * If XINDIV2 = 1, IF = N/(2 * R) * XIN. I choose N = 1496, 1617 * R = 44 so that 1496/(2 * 44) * 44MHz = 748MHz. 1618 * 1619 * If XINDIV2 = 0, IF = N/R * XIN. I choose N = 1496, R = 88 1620 * so that 1496/88 * 44MHz = 748MHz. 1621 */ 1622 atw_si4126_write(sc, SI4126_IFN, 1496); 1623 1624 atw_si4126_write(sc, SI4126_IFR, R); 1625 1626#ifndef ATW_REFSLAVE 1627 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1628 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1629 * which has no RF1! 1630 */ 1631 atw_si4126_write(sc, SI4126_RF1R, R); 1632 1633 atw_si4126_write(sc, SI4126_RF1N, mhz - 374); 1634#endif 1635 1636 /* N/R * XIN = RF. XIN = 44MHz. We desire RF = mhz - IF, 1637 * where IF = 374MHz. Let's divide XIN to 1MHz. So R = 44. 1638 * Now let's multiply it to mhz. So mhz - IF = N. 1639 */ 1640 atw_si4126_write(sc, SI4126_RF2R, R); 1641 1642 atw_si4126_write(sc, SI4126_RF2N, mhz - 374); 1643 1644 /* wait 100us from power-up for RF, IF to settle */ 1645 DELAY(100); 1646 1647 gpio = ATW_READ(sc, ATW_GPIO); 1648 gpio &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1649 gpio |= SHIFTIN(1, ATW_GPIO_EN_MASK); 1650 1651 if ((sc->sc_if.if_flags & IFF_LINK1) != 0 && chan != 14) { 1652 /* Set a Prism RF front-end to a special mode for channel 14? 1653 * 1654 * Apparently the SMC2635W needs this, although I don't think 1655 * it has a Prism RF. 1656 */ 1657 gpio |= SHIFTIN(1, ATW_GPIO_O_MASK); 1658 } 1659 ATW_WRITE(sc, ATW_GPIO, gpio); 1660 1661#ifdef ATW_SYNDEBUG 1662 atw_si4126_print(sc); 1663#endif /* ATW_SYNDEBUG */ 1664} 1665 1666/* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1667 * diversity. 1668 * 1669 * !!! 1670 * !!! Call this w/ Tx/Rx suspended, atw_idle(, ATW_NAR_ST|ATW_NAR_SR). 1671 * !!! 1672 */ 1673static int 1674atw_rf3000_init(struct atw_softc *sc) 1675{ 1676 int rc = 0; 1677 1678 atw_bbp_io_enable(sc, 1); 1679 1680 /* CCA is acquisition sensitive */ 1681 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1682 SHIFTIN(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK)); 1683 1684 if (rc != 0) 1685 goto out; 1686 1687 /* enable diversity */ 1688 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1689 1690 if (rc != 0) 1691 goto out; 1692 1693 /* sensible setting from a binary-only driver */ 1694 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1695 SHIFTIN(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1696 1697 if (rc != 0) 1698 goto out; 1699 1700 /* magic from a binary-only driver */ 1701 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1702 SHIFTIN(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1703 1704 if (rc != 0) 1705 goto out; 1706 1707 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1708 1709 if (rc != 0) 1710 goto out; 1711 1712 /* XXX Reference driver remarks that Abocom sets this to 50. 1713 * Meaning 0x50, I think.... 50 = 0x32, which would set a bit 1714 * in the "reserved" area of register RF3000_OPTIONS1. 1715 */ 1716 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, sc->sc_rf3000_options1); 1717 1718 if (rc != 0) 1719 goto out; 1720 1721 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, sc->sc_rf3000_options2); 1722 1723 if (rc != 0) 1724 goto out; 1725 1726out: 1727 atw_bbp_io_enable(sc, 0); 1728 return rc; 1729} 1730 1731#ifdef ATW_BBPDEBUG 1732static void 1733atw_rf3000_print(struct atw_softc *sc) 1734{ 1735 struct ifnet *ifp = &sc->sc_if; 1736 u_int addr, val; 1737 1738 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1739 return; 1740 1741 for (addr = 0x01; addr <= 0x15; addr++) { 1742 printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr); 1743 if (atw_rf3000_read(sc, addr, &val) != 0) { 1744 printf("<unknown> (quitting print-out)\n"); 1745 break; 1746 } 1747 printf("%08x\n", val); 1748 } 1749} 1750#endif /* ATW_BBPDEBUG */ 1751 1752/* Set the power settings on the BBP for channel `chan'. */ 1753static int 1754atw_rf3000_tune(struct atw_softc *sc, u_int chan) 1755{ 1756 int rc = 0; 1757 u_int32_t reg; 1758 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1759 1760 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1761 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1762 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1763 1764 /* odd channels: LSB, even channels: MSB */ 1765 if (chan % 2 == 1) { 1766 txpower &= 0xFF; 1767 lpf_cutoff &= 0xFF; 1768 lna_gs_thresh &= 0xFF; 1769 } else { 1770 txpower >>= 8; 1771 lpf_cutoff >>= 8; 1772 lna_gs_thresh >>= 8; 1773 } 1774 1775#ifdef ATW_BBPDEBUG 1776 atw_rf3000_print(sc); 1777#endif /* ATW_BBPDEBUG */ 1778 1779 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1780 "lna_gs_thresh %02x\n", 1781 sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh)); 1782 1783 atw_bbp_io_enable(sc, 1); 1784 1785 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1786 SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1787 goto out; 1788 1789 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1790 goto out; 1791 1792 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1793 goto out; 1794 1795 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0); 1796 1797 if (rc != 0) 1798 goto out; 1799 1800 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1801 1802 if (rc != 0) 1803 goto out; 1804 1805#ifdef ATW_BBPDEBUG 1806 atw_rf3000_print(sc); 1807#endif /* ATW_BBPDEBUG */ 1808 1809out: 1810 atw_bbp_io_enable(sc, 0); 1811 1812 /* set beacon, rts, atim transmit power */ 1813 reg = ATW_READ(sc, ATW_PLCPHD); 1814 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1815 reg |= SHIFTIN(SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK), 1816 ATW_PLCPHD_SERVICE_MASK); 1817 ATW_WRITE(sc, ATW_PLCPHD, reg); 1818 DELAY(atw_plcphd_delay); 1819 1820 return rc; 1821} 1822 1823/* Write a register on the RF3000 baseband processor using the 1824 * registers provided by the ADM8211 for this purpose. 1825 * 1826 * Return 0 on success. 1827 */ 1828static int 1829atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1830{ 1831 u_int32_t reg; 1832 int i; 1833 1834 reg = sc->sc_bbpctl_wr | 1835 SHIFTIN(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1836 SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1837 1838 for (i = 20000 / atw_pseudo_milli; --i >= 0; ) { 1839 ATW_WRITE(sc, ATW_BBPCTL, reg); 1840 DELAY(2 * atw_pseudo_milli); 1841 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1842 break; 1843 } 1844 1845 if (i < 0) { 1846 printf("%s: BBPCTL still busy\n", sc->sc_dev.dv_xname); 1847 return ETIMEDOUT; 1848 } 1849 return 0; 1850} 1851 1852/* Read a register on the RF3000 baseband processor using the registers 1853 * the ADM8211 provides for this purpose. 1854 * 1855 * The 7-bit register address is addr. Record the 8-bit data in the register 1856 * in *val. 1857 * 1858 * Return 0 on success. 1859 * 1860 * XXX This does not seem to work. The ADM8211 must require more or 1861 * different magic to read the chip than to write it. Possibly some 1862 * of the magic I have derived from a binary-only driver concerns 1863 * the "chip address" (see the RF3000 manual). 1864 */ 1865#ifdef ATW_BBPDEBUG 1866static int 1867atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1868{ 1869 u_int32_t reg; 1870 int i; 1871 1872 for (i = 1000; --i >= 0; ) { 1873 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1874 break; 1875 DELAY(100); 1876 } 1877 1878 if (i < 0) { 1879 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1880 sc->sc_dev.dv_xname); 1881 return ETIMEDOUT; 1882 } 1883 1884 reg = sc->sc_bbpctl_rd | SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1885 1886 ATW_WRITE(sc, ATW_BBPCTL, reg); 1887 1888 for (i = 1000; --i >= 0; ) { 1889 DELAY(100); 1890 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1891 break; 1892 } 1893 1894 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1895 1896 if (i < 0) { 1897 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1898 sc->sc_dev.dv_xname, reg); 1899 return ETIMEDOUT; 1900 } 1901 if (val != NULL) 1902 *val = SHIFTOUT(reg, ATW_BBPCTL_DATA_MASK); 1903 return 0; 1904} 1905#endif /* ATW_BBPDEBUG */ 1906 1907/* Write a register on the Si4126 RF/IF synthesizer using the registers 1908 * provided by the ADM8211 for that purpose. 1909 * 1910 * val is 18 bits of data, and val is the 4-bit address of the register. 1911 * 1912 * Return 0 on success. 1913 */ 1914static void 1915atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1916{ 1917 uint32_t bits, mask, reg; 1918 const int nbits = 22; 1919 1920 KASSERT((addr & ~SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); 1921 KASSERT((val & ~SHIFTOUT_MASK(SI4126_TWI_DATA_MASK)) == 0); 1922 1923 bits = SHIFTIN(val, SI4126_TWI_DATA_MASK) | 1924 SHIFTIN(addr, SI4126_TWI_ADDR_MASK); 1925 1926 reg = ATW_SYNRF_SELSYN; 1927 /* reference driver: reset Si4126 serial bus to initial 1928 * conditions? 1929 */ 1930 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1931 ATW_WRITE(sc, ATW_SYNRF, reg); 1932 1933 for (mask = __BIT(nbits - 1); mask != 0; mask >>= 1) { 1934 if ((bits & mask) != 0) 1935 reg |= ATW_SYNRF_SYNDATA; 1936 else 1937 reg &= ~ATW_SYNRF_SYNDATA; 1938 ATW_WRITE(sc, ATW_SYNRF, reg); 1939 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_SYNCLK); 1940 ATW_WRITE(sc, ATW_SYNRF, reg); 1941 } 1942 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1943 ATW_WRITE(sc, ATW_SYNRF, 0x0); 1944} 1945 1946/* Read 18-bit data from the 4-bit address addr in Si4126 1947 * RF synthesizer and write the data to *val. Return 0 on success. 1948 * 1949 * XXX This does not seem to work. The ADM8211 must require more or 1950 * different magic to read the chip than to write it. 1951 */ 1952#ifdef ATW_SYNDEBUG 1953static int 1954atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1955{ 1956 u_int32_t reg; 1957 int i; 1958 1959 KASSERT((addr & ~SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0); 1960 1961 for (i = 1000; --i >= 0; ) { 1962 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1963 break; 1964 DELAY(100); 1965 } 1966 1967 if (i < 0) { 1968 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1969 sc->sc_dev.dv_xname); 1970 return ETIMEDOUT; 1971 } 1972 1973 reg = sc->sc_synctl_rd | SHIFTIN(addr, ATW_SYNCTL_DATA_MASK); 1974 1975 ATW_WRITE(sc, ATW_SYNCTL, reg); 1976 1977 for (i = 1000; --i >= 0; ) { 1978 DELAY(100); 1979 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1980 break; 1981 } 1982 1983 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1984 1985 if (i < 0) { 1986 printf("%s: atw_si4126_read wrote %#08x, SYNCTL still busy\n", 1987 sc->sc_dev.dv_xname, reg); 1988 return ETIMEDOUT; 1989 } 1990 if (val != NULL) 1991 *val = SHIFTOUT(ATW_READ(sc, ATW_SYNCTL), 1992 ATW_SYNCTL_DATA_MASK); 1993 return 0; 1994} 1995#endif /* ATW_SYNDEBUG */ 1996 1997/* XXX is the endianness correct? test. */ 1998#define atw_calchash(addr) \ 1999 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & __BITS(5, 0)) 2000 2001/* 2002 * atw_filter_setup: 2003 * 2004 * Set the ADM8211's receive filter. 2005 */ 2006static void 2007atw_filter_setup(struct atw_softc *sc) 2008{ 2009 struct ieee80211com *ic = &sc->sc_ic; 2010 struct ethercom *ec = &sc->sc_ec; 2011 struct ifnet *ifp = &sc->sc_if; 2012 int hash; 2013 u_int32_t hashes[2]; 2014 struct ether_multi *enm; 2015 struct ether_multistep step; 2016 2017 /* According to comments in tlp_al981_filter_setup 2018 * (dev/ic/tulip.c) the ADMtek AL981 does not like for its 2019 * multicast filter to be set while it is running. Hopefully 2020 * the ADM8211 is not the same! 2021 */ 2022 if ((ifp->if_flags & IFF_RUNNING) != 0) 2023 atw_idle(sc, ATW_NAR_SR); 2024 2025 sc->sc_opmode &= ~(ATW_NAR_PR|ATW_NAR_MM); 2026 ifp->if_flags &= ~IFF_ALLMULTI; 2027 2028 /* XXX in scan mode, do not filter packets. Maybe this is 2029 * unnecessary. 2030 */ 2031 if (ic->ic_state == IEEE80211_S_SCAN || 2032 (ifp->if_flags & IFF_PROMISC) != 0) { 2033 sc->sc_opmode |= ATW_NAR_PR; 2034 goto allmulti; 2035 } 2036 2037 hashes[0] = hashes[1] = 0x0; 2038 2039 /* 2040 * Program the 64-bit multicast hash filter. 2041 */ 2042 ETHER_FIRST_MULTI(step, ec, enm); 2043 while (enm != NULL) { 2044 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2045 ETHER_ADDR_LEN) != 0) 2046 goto allmulti; 2047 2048 hash = atw_calchash(enm->enm_addrlo); 2049 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2050 ETHER_NEXT_MULTI(step, enm); 2051 sc->sc_opmode |= ATW_NAR_MM; 2052 } 2053 ifp->if_flags &= ~IFF_ALLMULTI; 2054 goto setit; 2055 2056allmulti: 2057 sc->sc_opmode |= ATW_NAR_MM; 2058 ifp->if_flags |= IFF_ALLMULTI; 2059 hashes[0] = hashes[1] = 0xffffffff; 2060 2061setit: 2062 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 2063 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 2064 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2065 DELAY(atw_nar_delay); 2066 ATW_WRITE(sc, ATW_RDR, 0x1); 2067 2068 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname, 2069 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 2070} 2071 2072/* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 2073 * a beacon's BSSID and SSID against the preferred BSSID and SSID 2074 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 2075 * no beacon with the preferred BSSID and SSID in the number of 2076 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 2077 */ 2078static void 2079atw_write_bssid(struct atw_softc *sc) 2080{ 2081 struct ieee80211com *ic = &sc->sc_ic; 2082 u_int8_t *bssid; 2083 2084 bssid = ic->ic_bss->ni_bssid; 2085 2086 ATW_WRITE(sc, ATW_BSSID0, 2087 SHIFTIN(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 2088 SHIFTIN(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 2089 SHIFTIN(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 2090 SHIFTIN(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 2091 2092 ATW_WRITE(sc, ATW_ABDA1, 2093 (ATW_READ(sc, ATW_ABDA1) & 2094 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 2095 SHIFTIN(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 2096 SHIFTIN(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 2097 2098 DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname, 2099 ether_sprintf(sc->sc_bssid))); 2100 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 2101 2102 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 2103} 2104 2105/* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 2106 * 16-bit word. 2107 */ 2108static void 2109atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) 2110{ 2111 u_int i; 2112 u_int8_t *ptr; 2113 2114 memcpy(&sc->sc_sram[ofs], buf, buflen); 2115 2116 KASSERT(ofs % 2 == 0 && buflen % 2 == 0); 2117 2118 KASSERT(buflen + ofs <= sc->sc_sramlen); 2119 2120 ptr = &sc->sc_sram[ofs]; 2121 2122 for (i = 0; i < buflen; i += 2) { 2123 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 2124 SHIFTIN((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 2125 DELAY(atw_writewep_delay); 2126 2127 ATW_WRITE(sc, ATW_WESK, 2128 SHIFTIN((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 2129 DELAY(atw_writewep_delay); 2130 } 2131 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 2132 2133 if (sc->sc_if.if_flags & IFF_DEBUG) { 2134 int n_octets = 0; 2135 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 2136 sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl); 2137 for (i = 0; i < buflen; i++) { 2138 printf(" %02x", ptr[i]); 2139 if (++n_octets % 24 == 0) 2140 printf("\n"); 2141 } 2142 if (n_octets % 24 != 0) 2143 printf("\n"); 2144 } 2145} 2146 2147static int 2148atw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 2149{ 2150 struct atw_softc *sc = ic->ic_ifp->if_softc; 2151 u_int keyix = k->wk_keyix; 2152 2153 DPRINTF(sc, ("%s: delete key %u\n", __func__, keyix)); 2154 2155 if (keyix >= IEEE80211_WEP_NKID) 2156 return 0; 2157 if (k->wk_keylen != 0) 2158 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2159 2160 return 1; 2161} 2162 2163static int 2164atw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 2165 const u_int8_t mac[IEEE80211_ADDR_LEN]) 2166{ 2167 struct atw_softc *sc = ic->ic_ifp->if_softc; 2168 2169 DPRINTF(sc, ("%s: set key %u\n", __func__, k->wk_keyix)); 2170 2171 if (k->wk_keyix >= IEEE80211_WEP_NKID) 2172 return 0; 2173 2174 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID; 2175 2176 return 1; 2177} 2178 2179static void 2180atw_key_update_begin(struct ieee80211com *ic) 2181{ 2182#ifdef ATW_DEBUG 2183 struct ifnet *ifp = ic->ic_ifp; 2184 struct atw_softc *sc = ifp->if_softc; 2185#endif 2186 2187 DPRINTF(sc, ("%s:\n", __func__)); 2188} 2189 2190static void 2191atw_key_update_end(struct ieee80211com *ic) 2192{ 2193 struct ifnet *ifp = ic->ic_ifp; 2194 struct atw_softc *sc = ifp->if_softc; 2195 2196 DPRINTF(sc, ("%s:\n", __func__)); 2197 2198 if ((sc->sc_flags & ATWF_WEP_SRAM_VALID) != 0) 2199 return; 2200 if (ATW_IS_ENABLED(sc) == 0) 2201 return; 2202 atw_idle(sc, ATW_NAR_SR | ATW_NAR_ST); 2203 atw_write_wep(sc); 2204 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2205 DELAY(atw_nar_delay); 2206 ATW_WRITE(sc, ATW_RDR, 0x1); 2207} 2208 2209/* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2210static void 2211atw_write_wep(struct atw_softc *sc) 2212{ 2213#if 0 2214 struct ieee80211com *ic = &sc->sc_ic; 2215 u_int32_t reg; 2216 int i; 2217#endif 2218 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2219 u_int8_t buf[IEEE80211_WEP_NKID] 2220 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2221 2222 sc->sc_wepctl = 0; 2223 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2224 2225 memset(&buf[0][0], 0, sizeof(buf)); 2226 2227#if 0 2228 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2229 if (ic->ic_nw_keys[i].wk_keylen > 5) { 2230 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2231 } else if (ic->ic_nw_keys[i].wk_keylen != 0) { 2232 buf[i][1] = ATW_WEP_ENABLED; 2233 } else { 2234 buf[i][1] = 0; 2235 continue; 2236 } 2237 buf[i][0] = ic->ic_nw_keys[i].wk_key[0]; 2238 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1], 2239 ic->ic_nw_keys[i].wk_keylen - 1); 2240 } 2241 2242 reg = ATW_READ(sc, ATW_MACTEST); 2243 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2244 reg &= ~ATW_MACTEST_KEYID_MASK; 2245 reg |= SHIFTIN(ic->ic_def_txkey, ATW_MACTEST_KEYID_MASK); 2246 ATW_WRITE(sc, ATW_MACTEST, reg); 2247 2248 if ((ic->ic_flags & IEEE80211_F_PRIVACY) != 0) 2249 sc->sc_wepctl |= ATW_WEPCTL_WEPENABLE; 2250 2251 switch (sc->sc_rev) { 2252 case ATW_REVISION_AB: 2253 case ATW_REVISION_AF: 2254 /* Bypass WEP on Rx. */ 2255 sc->sc_wepctl |= ATW_WEPCTL_WEPRXBYP; 2256 break; 2257 default: 2258 break; 2259 } 2260#endif 2261 2262 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2263 sizeof(buf)); 2264 2265 sc->sc_flags |= ATWF_WEP_SRAM_VALID; 2266} 2267 2268static void 2269atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2270 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 2271{ 2272 struct atw_softc *sc = (struct atw_softc *)ic->ic_ifp->if_softc; 2273 2274 /* The ADM8211A answers probe requests. TBD ADM8211B/C. */ 2275 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_REQ) 2276 return; 2277 2278 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 2279 2280 switch (subtype) { 2281 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2282 case IEEE80211_FC0_SUBTYPE_BEACON: 2283 if (ic->ic_opmode == IEEE80211_M_IBSS && 2284 ic->ic_state == IEEE80211_S_RUN) { 2285 if (le64toh(ni->ni_tstamp.tsf) >= atw_get_tsft(sc)) 2286 (void)ieee80211_ibss_merge(ni); 2287 } 2288 break; 2289 default: 2290 break; 2291 } 2292 return; 2293} 2294 2295/* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2296 * In ad hoc mode, the SSID is written to the beacons sent by the 2297 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2298 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2299 * indications. 2300 */ 2301static void 2302atw_write_ssid(struct atw_softc *sc) 2303{ 2304 struct ieee80211com *ic = &sc->sc_ic; 2305 /* 34 bytes are reserved in ADM8211 SRAM for the SSID, but 2306 * it only expects the element length, not its ID. 2307 */ 2308 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2309 2310 memset(buf, 0, sizeof(buf)); 2311 buf[0] = ic->ic_bss->ni_esslen; 2312 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2313 2314 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, 2315 roundup(1 + ic->ic_bss->ni_esslen, 2)); 2316} 2317 2318/* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2319 * In ad hoc mode, the supported rates are written to beacons sent by the 2320 * ADM8211. 2321 */ 2322static void 2323atw_write_sup_rates(struct atw_softc *sc) 2324{ 2325 struct ieee80211com *ic = &sc->sc_ic; 2326 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for 2327 * supported rates 2328 */ 2329 u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)]; 2330 2331 memset(buf, 0, sizeof(buf)); 2332 2333 buf[0] = ic->ic_bss->ni_rates.rs_nrates; 2334 2335 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, 2336 ic->ic_bss->ni_rates.rs_nrates); 2337 2338 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2339} 2340 2341/* Start/stop sending beacons. */ 2342void 2343atw_start_beacon(struct atw_softc *sc, int start) 2344{ 2345 struct ieee80211com *ic = &sc->sc_ic; 2346 uint16_t chan; 2347 uint32_t bcnt, bpli, cap0, cap1, capinfo; 2348 size_t len; 2349 2350 if (ATW_IS_ENABLED(sc) == 0) 2351 return; 2352 2353 /* start beacons */ 2354 len = sizeof(struct ieee80211_frame) + 2355 8 /* timestamp */ + 2 /* beacon interval */ + 2356 2 /* capability info */ + 2357 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2358 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2359 3 /* DS parameters */ + 2360 IEEE80211_CRC_LEN; 2361 2362 bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2363 cap0 = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 2364 cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2365 2366 ATW_WRITE(sc, ATW_BCNT, bcnt); 2367 ATW_WRITE(sc, ATW_CAP1, cap1); 2368 2369 if (!start) 2370 return; 2371 2372 /* TBD use ni_capinfo */ 2373 2374 capinfo = 0; 2375 if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2376 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2377 if (ic->ic_flags & IEEE80211_F_PRIVACY) 2378 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2379 2380 switch (ic->ic_opmode) { 2381 case IEEE80211_M_IBSS: 2382 len += 4; /* IBSS parameters */ 2383 capinfo |= IEEE80211_CAPINFO_IBSS; 2384 break; 2385 case IEEE80211_M_HOSTAP: 2386 /* XXX 6-byte minimum TIM */ 2387 len += atw_beacon_len_adjust; 2388 capinfo |= IEEE80211_CAPINFO_ESS; 2389 break; 2390 default: 2391 return; 2392 } 2393 2394 /* set listen interval 2395 * XXX do software units agree w/ hardware? 2396 */ 2397 bpli = SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2398 SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK); 2399 2400 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 2401 2402 bcnt |= SHIFTIN(len, ATW_BCNT_BCNT_MASK); 2403 cap0 |= SHIFTIN(chan, ATW_CAP0_CHN_MASK); 2404 cap1 |= SHIFTIN(capinfo, ATW_CAP1_CAPI_MASK); 2405 2406 ATW_WRITE(sc, ATW_BCNT, bcnt); 2407 ATW_WRITE(sc, ATW_BPLI, bpli); 2408 ATW_WRITE(sc, ATW_CAP0, cap0); 2409 ATW_WRITE(sc, ATW_CAP1, cap1); 2410 2411 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2412 sc->sc_dev.dv_xname, bcnt)); 2413 2414 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2415 sc->sc_dev.dv_xname, cap1)); 2416} 2417 2418/* Return the 32 lsb of the last TSFT divisible by ival. */ 2419static inline uint32_t 2420atw_last_even_tsft(uint32_t tsfth, uint32_t tsftl, uint32_t ival) 2421{ 2422 /* Following the reference driver's lead, I compute 2423 * 2424 * (uint32_t)((((uint64_t)tsfth << 32) | tsftl) % ival) 2425 * 2426 * without using 64-bit arithmetic, using the following 2427 * relationship: 2428 * 2429 * (0x100000000 * H + L) % m 2430 * = ((0x100000000 % m) * H + L) % m 2431 * = (((0xffffffff + 1) % m) * H + L) % m 2432 * = ((0xffffffff % m + 1 % m) * H + L) % m 2433 * = ((0xffffffff % m + 1) * H + L) % m 2434 */ 2435 return ((0xFFFFFFFF % ival + 1) * tsfth + tsftl) % ival; 2436} 2437 2438static uint64_t 2439atw_get_tsft(struct atw_softc *sc) 2440{ 2441 int i; 2442 uint32_t tsfth, tsftl; 2443 for (i = 0; i < 2; i++) { 2444 tsfth = ATW_READ(sc, ATW_TSFTH); 2445 tsftl = ATW_READ(sc, ATW_TSFTL); 2446 if (ATW_READ(sc, ATW_TSFTH) == tsfth) 2447 break; 2448 } 2449 return ((uint64_t)tsfth << 32) | tsftl; 2450} 2451 2452/* If we've created an IBSS, write the TSF time in the ADM8211 to 2453 * the ieee80211com. 2454 * 2455 * Predict the next target beacon transmission time (TBTT) and 2456 * write it to the ADM8211. 2457 */ 2458static void 2459atw_predict_beacon(struct atw_softc *sc) 2460{ 2461#define TBTTOFS 20 /* TU */ 2462 2463 struct ieee80211com *ic = &sc->sc_ic; 2464 uint64_t tsft; 2465 uint32_t ival, past_even, tbtt, tsfth, tsftl; 2466 union { 2467 uint64_t word; 2468 uint8_t tstamp[8]; 2469 } u; 2470 2471 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) || 2472 ((ic->ic_opmode == IEEE80211_M_IBSS) && 2473 (ic->ic_flags & IEEE80211_F_SIBSS))) { 2474 tsft = atw_get_tsft(sc); 2475 u.word = htole64(tsft); 2476 (void)memcpy(&ic->ic_bss->ni_tstamp, &u.tstamp[0], 2477 sizeof(ic->ic_bss->ni_tstamp)); 2478 } else 2479 tsft = le64toh(ic->ic_bss->ni_tstamp.tsf); 2480 2481 ival = ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2482 2483 tsftl = tsft & 0xFFFFFFFF; 2484 tsfth = tsft >> 32; 2485 2486 /* We sent/received the last beacon `past' microseconds 2487 * after the interval divided the TSF timer. 2488 */ 2489 past_even = tsftl - atw_last_even_tsft(tsfth, tsftl, ival); 2490 2491 /* Skip ten beacons so that the TBTT cannot pass before 2492 * we've programmed it. Ten is an arbitrary number. 2493 */ 2494 tbtt = past_even + ival * 10; 2495 2496 ATW_WRITE(sc, ATW_TOFS1, 2497 SHIFTIN(1, ATW_TOFS1_TSFTOFSR_MASK) | 2498 SHIFTIN(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2499 SHIFTIN(SHIFTOUT(tbtt - TBTTOFS * IEEE80211_DUR_TU, 2500 ATW_TBTTPRE_MASK), ATW_TOFS1_TBTTPRE_MASK)); 2501#undef TBTTOFS 2502} 2503 2504static void 2505atw_next_scan(void *arg) 2506{ 2507 struct atw_softc *sc = arg; 2508 struct ieee80211com *ic = &sc->sc_ic; 2509 int s; 2510 2511 /* don't call atw_start w/o network interrupts blocked */ 2512 s = splnet(); 2513 if (ic->ic_state == IEEE80211_S_SCAN) 2514 ieee80211_next_scan(ic); 2515 splx(s); 2516} 2517 2518/* Synchronize the hardware state with the software state. */ 2519static int 2520atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2521{ 2522 struct ifnet *ifp = ic->ic_ifp; 2523 struct atw_softc *sc = ifp->if_softc; 2524 enum ieee80211_state ostate; 2525 int error = 0; 2526 2527 ostate = ic->ic_state; 2528 callout_stop(&sc->sc_scan_ch); 2529 2530 switch (nstate) { 2531 case IEEE80211_S_AUTH: 2532 case IEEE80211_S_ASSOC: 2533 atw_write_bssid(sc); 2534 error = atw_tune(sc); 2535 break; 2536 case IEEE80211_S_INIT: 2537 callout_stop(&sc->sc_scan_ch); 2538 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2539 atw_start_beacon(sc, 0); 2540 break; 2541 case IEEE80211_S_SCAN: 2542 error = atw_tune(sc); 2543 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000, 2544 atw_next_scan, sc); 2545 break; 2546 case IEEE80211_S_RUN: 2547 error = atw_tune(sc); 2548 atw_write_bssid(sc); 2549 atw_write_ssid(sc); 2550 atw_write_sup_rates(sc); 2551 2552 if (ic->ic_opmode == IEEE80211_M_AHDEMO || 2553 ic->ic_opmode == IEEE80211_M_MONITOR) 2554 break; 2555 2556 /* set listen interval 2557 * XXX do software units agree w/ hardware? 2558 */ 2559 ATW_WRITE(sc, ATW_BPLI, 2560 SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2561 SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, 2562 ATW_BPLI_LI_MASK)); 2563 2564 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", sc->sc_dev.dv_xname, 2565 ATW_READ(sc, ATW_BPLI))); 2566 2567 atw_predict_beacon(sc); 2568 2569 switch (ic->ic_opmode) { 2570 case IEEE80211_M_AHDEMO: 2571 case IEEE80211_M_HOSTAP: 2572 case IEEE80211_M_IBSS: 2573 atw_start_beacon(sc, 1); 2574 break; 2575 case IEEE80211_M_MONITOR: 2576 case IEEE80211_M_STA: 2577 break; 2578 } 2579 2580 break; 2581 } 2582 return (error != 0) ? error : (*sc->sc_newstate)(ic, nstate, arg); 2583} 2584 2585/* 2586 * atw_add_rxbuf: 2587 * 2588 * Add a receive buffer to the indicated descriptor. 2589 */ 2590int 2591atw_add_rxbuf(struct atw_softc *sc, int idx) 2592{ 2593 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2594 struct mbuf *m; 2595 int error; 2596 2597 MGETHDR(m, M_DONTWAIT, MT_DATA); 2598 if (m == NULL) 2599 return (ENOBUFS); 2600 2601 MCLGET(m, M_DONTWAIT); 2602 if ((m->m_flags & M_EXT) == 0) { 2603 m_freem(m); 2604 return (ENOBUFS); 2605 } 2606 2607 if (rxs->rxs_mbuf != NULL) 2608 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2609 2610 rxs->rxs_mbuf = m; 2611 2612 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2613 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2614 BUS_DMA_READ|BUS_DMA_NOWAIT); 2615 if (error) { 2616 printf("%s: can't load rx DMA map %d, error = %d\n", 2617 sc->sc_dev.dv_xname, idx, error); 2618 panic("atw_add_rxbuf"); /* XXX */ 2619 } 2620 2621 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2622 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2623 2624 ATW_INIT_RXDESC(sc, idx); 2625 2626 return (0); 2627} 2628 2629/* 2630 * Release any queued transmit buffers. 2631 */ 2632void 2633atw_txdrain(struct atw_softc *sc) 2634{ 2635 struct atw_txsoft *txs; 2636 2637 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2638 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2639 if (txs->txs_mbuf != NULL) { 2640 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2641 m_freem(txs->txs_mbuf); 2642 txs->txs_mbuf = NULL; 2643 } 2644 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2645 sc->sc_txfree += txs->txs_ndescs; 2646 } 2647 2648 KASSERT((sc->sc_if.if_flags & IFF_RUNNING) == 0 || 2649 !(SIMPLEQ_EMPTY(&sc->sc_txfreeq) || 2650 sc->sc_txfree != ATW_NTXDESC)); 2651 sc->sc_if.if_flags &= ~IFF_OACTIVE; 2652 sc->sc_tx_timer = 0; 2653} 2654 2655/* 2656 * atw_stop: [ ifnet interface function ] 2657 * 2658 * Stop transmission on the interface. 2659 */ 2660void 2661atw_stop(struct ifnet *ifp, int disable) 2662{ 2663 struct atw_softc *sc = ifp->if_softc; 2664 struct ieee80211com *ic = &sc->sc_ic; 2665 2666 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2667 2668 /* Disable interrupts. */ 2669 ATW_WRITE(sc, ATW_IER, 0); 2670 2671 /* Stop the transmit and receive processes. */ 2672 sc->sc_opmode = 0; 2673 ATW_WRITE(sc, ATW_NAR, 0); 2674 DELAY(atw_nar_delay); 2675 ATW_WRITE(sc, ATW_TDBD, 0); 2676 ATW_WRITE(sc, ATW_TDBP, 0); 2677 ATW_WRITE(sc, ATW_RDB, 0); 2678 2679 atw_txdrain(sc); 2680 2681 if (disable) { 2682 atw_rxdrain(sc); 2683 atw_disable(sc); 2684 } 2685 2686 /* 2687 * Mark the interface down and cancel the watchdog timer. 2688 */ 2689 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2690 sc->sc_tx_timer = 0; 2691 ifp->if_timer = 0; 2692 2693 if (!disable) 2694 atw_reset(sc); 2695} 2696 2697/* 2698 * atw_rxdrain: 2699 * 2700 * Drain the receive queue. 2701 */ 2702void 2703atw_rxdrain(struct atw_softc *sc) 2704{ 2705 struct atw_rxsoft *rxs; 2706 int i; 2707 2708 for (i = 0; i < ATW_NRXDESC; i++) { 2709 rxs = &sc->sc_rxsoft[i]; 2710 if (rxs->rxs_mbuf == NULL) 2711 continue; 2712 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2713 m_freem(rxs->rxs_mbuf); 2714 rxs->rxs_mbuf = NULL; 2715 } 2716} 2717 2718/* 2719 * atw_detach: 2720 * 2721 * Detach an ADM8211 interface. 2722 */ 2723int 2724atw_detach(struct atw_softc *sc) 2725{ 2726 struct ifnet *ifp = &sc->sc_if; 2727 struct atw_rxsoft *rxs; 2728 struct atw_txsoft *txs; 2729 int i; 2730 2731 /* 2732 * Succeed now if there isn't any work to do. 2733 */ 2734 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2735 return (0); 2736 2737 callout_stop(&sc->sc_scan_ch); 2738 2739 ieee80211_ifdetach(&sc->sc_ic); 2740 if_detach(ifp); 2741 2742 for (i = 0; i < ATW_NRXDESC; i++) { 2743 rxs = &sc->sc_rxsoft[i]; 2744 if (rxs->rxs_mbuf != NULL) { 2745 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2746 m_freem(rxs->rxs_mbuf); 2747 rxs->rxs_mbuf = NULL; 2748 } 2749 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2750 } 2751 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2752 txs = &sc->sc_txsoft[i]; 2753 if (txs->txs_mbuf != NULL) { 2754 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2755 m_freem(txs->txs_mbuf); 2756 txs->txs_mbuf = NULL; 2757 } 2758 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2759 } 2760 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2761 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2762 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2763 sizeof(struct atw_control_data)); 2764 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2765 2766 shutdownhook_disestablish(sc->sc_sdhook); 2767 powerhook_disestablish(sc->sc_powerhook); 2768 2769 if (sc->sc_srom) 2770 free(sc->sc_srom, M_DEVBUF); 2771 2772 return (0); 2773} 2774 2775/* atw_shutdown: make sure the interface is stopped at reboot time. */ 2776void 2777atw_shutdown(void *arg) 2778{ 2779 struct atw_softc *sc = arg; 2780 2781 atw_stop(&sc->sc_if, 1); 2782} 2783 2784int 2785atw_intr(void *arg) 2786{ 2787 struct atw_softc *sc = arg; 2788 struct ifnet *ifp = &sc->sc_if; 2789 u_int32_t status, rxstatus, txstatus, linkstatus; 2790 int handled = 0, txthresh; 2791 2792#ifdef DEBUG 2793 if (ATW_IS_ENABLED(sc) == 0) 2794 panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname); 2795#endif 2796 2797 /* 2798 * If the interface isn't running, the interrupt couldn't 2799 * possibly have come from us. 2800 */ 2801 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2802 !device_is_active(&sc->sc_dev)) 2803 return (0); 2804 2805 for (;;) { 2806 status = ATW_READ(sc, ATW_STSR); 2807 2808 if (status) 2809 ATW_WRITE(sc, ATW_STSR, status); 2810 2811#ifdef ATW_DEBUG 2812#define PRINTINTR(flag) do { \ 2813 if ((status & flag) != 0) { \ 2814 printf("%s" #flag, delim); \ 2815 delim = ","; \ 2816 } \ 2817} while (0) 2818 2819 if (atw_debug > 1 && status) { 2820 const char *delim = "<"; 2821 2822 printf("%s: reg[STSR] = %x", 2823 sc->sc_dev.dv_xname, status); 2824 2825 PRINTINTR(ATW_INTR_FBE); 2826 PRINTINTR(ATW_INTR_LINKOFF); 2827 PRINTINTR(ATW_INTR_LINKON); 2828 PRINTINTR(ATW_INTR_RCI); 2829 PRINTINTR(ATW_INTR_RDU); 2830 PRINTINTR(ATW_INTR_REIS); 2831 PRINTINTR(ATW_INTR_RPS); 2832 PRINTINTR(ATW_INTR_TCI); 2833 PRINTINTR(ATW_INTR_TDU); 2834 PRINTINTR(ATW_INTR_TLT); 2835 PRINTINTR(ATW_INTR_TPS); 2836 PRINTINTR(ATW_INTR_TRT); 2837 PRINTINTR(ATW_INTR_TUF); 2838 PRINTINTR(ATW_INTR_BCNTC); 2839 PRINTINTR(ATW_INTR_ATIME); 2840 PRINTINTR(ATW_INTR_TBTT); 2841 PRINTINTR(ATW_INTR_TSCZ); 2842 PRINTINTR(ATW_INTR_TSFTF); 2843 printf(">\n"); 2844 } 2845#undef PRINTINTR 2846#endif /* ATW_DEBUG */ 2847 2848 if ((status & sc->sc_inten) == 0) 2849 break; 2850 2851 handled = 1; 2852 2853 rxstatus = status & sc->sc_rxint_mask; 2854 txstatus = status & sc->sc_txint_mask; 2855 linkstatus = status & sc->sc_linkint_mask; 2856 2857 if (linkstatus) { 2858 atw_linkintr(sc, linkstatus); 2859 } 2860 2861 if (rxstatus) { 2862 /* Grab any new packets. */ 2863 atw_rxintr(sc); 2864 2865 if (rxstatus & ATW_INTR_RDU) { 2866 printf("%s: receive ring overrun\n", 2867 sc->sc_dev.dv_xname); 2868 /* Get the receive process going again. */ 2869 ATW_WRITE(sc, ATW_RDR, 0x1); 2870 break; 2871 } 2872 } 2873 2874 if (txstatus) { 2875 /* Sweep up transmit descriptors. */ 2876 atw_txintr(sc); 2877 2878 if (txstatus & ATW_INTR_TLT) 2879 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2880 sc->sc_dev.dv_xname)); 2881 2882 if (txstatus & ATW_INTR_TRT) 2883 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2884 sc->sc_dev.dv_xname)); 2885 2886 /* If Tx under-run, increase our transmit threshold 2887 * if another is available. 2888 */ 2889 txthresh = sc->sc_txthresh + 1; 2890 if ((txstatus & ATW_INTR_TUF) && 2891 sc->sc_txth[txthresh].txth_name != NULL) { 2892 /* Idle the transmit process. */ 2893 atw_idle(sc, ATW_NAR_ST); 2894 2895 sc->sc_txthresh = txthresh; 2896 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2897 sc->sc_opmode |= 2898 sc->sc_txth[txthresh].txth_opmode; 2899 printf("%s: transmit underrun; new " 2900 "threshold: %s\n", sc->sc_dev.dv_xname, 2901 sc->sc_txth[txthresh].txth_name); 2902 2903 /* Set the new threshold and restart 2904 * the transmit process. 2905 */ 2906 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2907 DELAY(atw_nar_delay); 2908 ATW_WRITE(sc, ATW_RDR, 0x1); 2909 /* XXX Log every Nth underrun from 2910 * XXX now on? 2911 */ 2912 } 2913 } 2914 2915 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2916 if (status & ATW_INTR_TPS) 2917 printf("%s: transmit process stopped\n", 2918 sc->sc_dev.dv_xname); 2919 if (status & ATW_INTR_RPS) 2920 printf("%s: receive process stopped\n", 2921 sc->sc_dev.dv_xname); 2922 (void)atw_init(ifp); 2923 break; 2924 } 2925 2926 if (status & ATW_INTR_FBE) { 2927 printf("%s: fatal bus error\n", sc->sc_dev.dv_xname); 2928 (void)atw_init(ifp); 2929 break; 2930 } 2931 2932 /* 2933 * Not handled: 2934 * 2935 * Transmit buffer unavailable -- normal 2936 * condition, nothing to do, really. 2937 * 2938 * Early receive interrupt -- not available on 2939 * all chips, we just use RI. We also only 2940 * use single-segment receive DMA, so this 2941 * is mostly useless. 2942 * 2943 * TBD others 2944 */ 2945 } 2946 2947 /* Try to get more packets going. */ 2948 atw_start(ifp); 2949 2950 return (handled); 2951} 2952 2953/* 2954 * atw_idle: 2955 * 2956 * Cause the transmit and/or receive processes to go idle. 2957 * 2958 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2959 * process in STSR if I clear SR or ST after the process has already 2960 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2961 * do not seem to be too reliable. Perhaps I have the sense of the 2962 * Rx bits switched with the Tx bits? 2963 */ 2964void 2965atw_idle(struct atw_softc *sc, u_int32_t bits) 2966{ 2967 u_int32_t ackmask = 0, opmode, stsr, test0; 2968 int i, s; 2969 2970 s = splnet(); 2971 2972 opmode = sc->sc_opmode & ~bits; 2973 2974 if (bits & ATW_NAR_SR) 2975 ackmask |= ATW_INTR_RPS; 2976 2977 if (bits & ATW_NAR_ST) { 2978 ackmask |= ATW_INTR_TPS; 2979 /* set ATW_NAR_HF to flush TX FIFO. */ 2980 opmode |= ATW_NAR_HF; 2981 } 2982 2983 ATW_WRITE(sc, ATW_NAR, opmode); 2984 DELAY(atw_nar_delay); 2985 2986 for (i = 0; i < 1000; i++) { 2987 stsr = ATW_READ(sc, ATW_STSR); 2988 if ((stsr & ackmask) == ackmask) 2989 break; 2990 DELAY(10); 2991 } 2992 2993 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 2994 2995 if ((stsr & ackmask) == ackmask) 2996 goto out; 2997 2998 test0 = ATW_READ(sc, ATW_TEST0); 2999 3000 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 3001 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 3002 printf("%s: transmit process not idle [%s]\n", 3003 sc->sc_dev.dv_xname, 3004 atw_tx_state[SHIFTOUT(test0, ATW_TEST0_TS_MASK)]); 3005 printf("%s: bits %08x test0 %08x stsr %08x\n", 3006 sc->sc_dev.dv_xname, bits, test0, stsr); 3007 } 3008 3009 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 3010 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 3011 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 3012 sc->sc_dev.dv_xname, 3013 atw_rx_state[SHIFTOUT(test0, ATW_TEST0_RS_MASK)])); 3014 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 3015 sc->sc_dev.dv_xname, bits, test0, stsr)); 3016 } 3017out: 3018 if ((bits & ATW_NAR_ST) != 0) 3019 atw_txdrain(sc); 3020 splx(s); 3021 return; 3022} 3023 3024/* 3025 * atw_linkintr: 3026 * 3027 * Helper; handle link-status interrupts. 3028 */ 3029void 3030atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus) 3031{ 3032 struct ieee80211com *ic = &sc->sc_ic; 3033 3034 if (ic->ic_state != IEEE80211_S_RUN) 3035 return; 3036 3037 if (linkstatus & ATW_INTR_LINKON) { 3038 DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname)); 3039 sc->sc_rescan_timer = 0; 3040 } else if (linkstatus & ATW_INTR_LINKOFF) { 3041 DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname)); 3042 if (ic->ic_opmode != IEEE80211_M_STA) 3043 return; 3044 sc->sc_rescan_timer = 3; 3045 sc->sc_if.if_timer = 1; 3046 } 3047} 3048 3049static inline int 3050atw_hw_decrypted(struct atw_softc *sc, struct ieee80211_frame_min *wh) 3051{ 3052 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0) 3053 return 0; 3054 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3055 return 0; 3056 return (sc->sc_wepctl & ATW_WEPCTL_WEPRXBYP) == 0; 3057} 3058 3059/* 3060 * atw_rxintr: 3061 * 3062 * Helper; handle receive interrupts. 3063 */ 3064void 3065atw_rxintr(struct atw_softc *sc) 3066{ 3067 static int rate_tbl[] = {2, 4, 11, 22, 44}; 3068 struct ieee80211com *ic = &sc->sc_ic; 3069 struct ieee80211_node *ni; 3070 struct ieee80211_frame_min *wh; 3071 struct ifnet *ifp = &sc->sc_if; 3072 struct atw_rxsoft *rxs; 3073 struct mbuf *m; 3074 u_int32_t rxstat; 3075 int i, len, rate, rate0; 3076 u_int32_t rssi, rssi0; 3077 3078 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 3079 rxs = &sc->sc_rxsoft[i]; 3080 3081 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3082 3083 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat); 3084 rssi0 = le32toh(sc->sc_rxdescs[i].ar_rssi); 3085 rate0 = SHIFTOUT(rxstat, ATW_RXSTAT_RXDR_MASK); 3086 3087 if (rxstat & ATW_RXSTAT_OWN) 3088 break; /* We have processed all receive buffers. */ 3089 3090 DPRINTF3(sc, 3091 ("%s: rx stat %08x rssi0 %08x buf1 %08x buf2 %08x\n", 3092 sc->sc_dev.dv_xname, 3093 rxstat, rssi0, 3094 le32toh(sc->sc_rxdescs[i].ar_buf1), 3095 le32toh(sc->sc_rxdescs[i].ar_buf2))); 3096 3097 /* 3098 * Make sure the packet fits in one buffer. This should 3099 * always be the case. 3100 */ 3101 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 3102 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 3103 printf("%s: incoming packet spilled, resetting\n", 3104 sc->sc_dev.dv_xname); 3105 (void)atw_init(ifp); 3106 return; 3107 } 3108 3109 /* 3110 * If an error occurred, update stats, clear the status 3111 * word, and leave the packet buffer in place. It will 3112 * simply be reused the next time the ring comes around. 3113 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 3114 * error. 3115 */ 3116 3117 if ((rxstat & ATW_RXSTAT_ES) != 0 && 3118 ((sc->sc_ec.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 3119 (rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_SFDE | 3120 ATW_RXSTAT_SIGE | ATW_RXSTAT_CRC16E | 3121 ATW_RXSTAT_RXTOE | ATW_RXSTAT_CRC32E | 3122 ATW_RXSTAT_ICVE)) != 0)) { 3123#define PRINTERR(bit, str) \ 3124 if (rxstat & (bit)) \ 3125 printf("%s: receive error: %s\n", \ 3126 sc->sc_dev.dv_xname, str) 3127 ifp->if_ierrors++; 3128 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 3129 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 3130 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 3131 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 3132 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 3133 PRINTERR(ATW_RXSTAT_CRC32E, "FCS error"); 3134 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 3135#undef PRINTERR 3136 ATW_INIT_RXDESC(sc, i); 3137 continue; 3138 } 3139 3140 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3141 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3142 3143 /* 3144 * No errors; receive the packet. Note the ADM8211 3145 * includes the CRC in promiscuous mode. 3146 */ 3147 len = SHIFTOUT(rxstat, ATW_RXSTAT_FL_MASK); 3148 3149 /* 3150 * Allocate a new mbuf cluster. If that fails, we are 3151 * out of memory, and must drop the packet and recycle 3152 * the buffer that's already attached to this descriptor. 3153 */ 3154 m = rxs->rxs_mbuf; 3155 if (atw_add_rxbuf(sc, i) != 0) { 3156 ifp->if_ierrors++; 3157 ATW_INIT_RXDESC(sc, i); 3158 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3159 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3160 continue; 3161 } 3162 3163 ifp->if_ipackets++; 3164 if (sc->sc_opmode & ATW_NAR_PR) 3165 len -= IEEE80211_CRC_LEN; 3166 m->m_pkthdr.rcvif = ifp; 3167 m->m_pkthdr.len = m->m_len = MIN(m->m_ext.ext_size, len); 3168 3169 if (rate0 >= sizeof(rate_tbl) / sizeof(rate_tbl[0])) 3170 rate = 0; 3171 else 3172 rate = rate_tbl[rate0]; 3173 3174 /* The RSSI comes straight from a register in the 3175 * baseband processor. I know that for the RF3000, 3176 * the RSSI register also contains the antenna-selection 3177 * bits. Mask those off. 3178 * 3179 * TBD Treat other basebands. 3180 */ 3181 if (sc->sc_bbptype == ATW_BBPTYPE_RFMD) 3182 rssi = rssi0 & RF3000_RSSI_MASK; 3183 else 3184 rssi = rssi0; 3185 3186 #if NBPFILTER > 0 3187 /* Pass this up to any BPF listeners. */ 3188 if (sc->sc_radiobpf != NULL) { 3189 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3190 3191 tap->ar_rate = rate; 3192 tap->ar_chan_freq = ic->ic_curchan->ic_freq; 3193 tap->ar_chan_flags = ic->ic_curchan->ic_flags; 3194 3195 /* TBD verify units are dB */ 3196 tap->ar_antsignal = (int)rssi; 3197 /* TBD tap->ar_flags */ 3198 3199 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3200 tap->ar_ihdr.it_len, m); 3201 } 3202 #endif /* NPBFILTER > 0 */ 3203 3204 wh = mtod(m, struct ieee80211_frame_min *); 3205 ni = ieee80211_find_rxnode(ic, wh); 3206#if 0 3207 if (atw_hw_decrypted(sc, wh)) { 3208 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 3209 DPRINTF(sc, ("%s: hw decrypted\n", __func__)); 3210 } 3211#endif 3212 ieee80211_input(ic, m, ni, (int)rssi, 0); 3213 ieee80211_free_node(ni); 3214 } 3215 3216 /* Update the receive pointer. */ 3217 sc->sc_rxptr = i; 3218} 3219 3220/* 3221 * atw_txintr: 3222 * 3223 * Helper; handle transmit interrupts. 3224 */ 3225void 3226atw_txintr(struct atw_softc *sc) 3227{ 3228#define TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | ATW_TXSTAT_TRT | \ 3229 ATW_TXSTAT_TRO | ATW_TXSTAT_SOFBR) 3230#define TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO\33ATW_TXSTAT_TUF" \ 3231 "\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT" 3232 3233 static char txstat_buf[sizeof("ffffffff<>" TXSTAT_FMT)]; 3234 struct ifnet *ifp = &sc->sc_if; 3235 struct atw_txsoft *txs; 3236 u_int32_t txstat; 3237 3238 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3239 sc->sc_dev.dv_xname, sc->sc_flags)); 3240 3241 /* 3242 * Go through our Tx list and free mbufs for those 3243 * frames that have been transmitted. 3244 */ 3245 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3246 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, 3247 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3248 3249#ifdef ATW_DEBUG 3250 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3251 int i; 3252 printf(" txsoft %p transmit chain:\n", txs); 3253 ATW_CDTXSYNC(sc, txs->txs_firstdesc, 3254 txs->txs_ndescs - 1, 3255 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3256 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3257 printf(" descriptor %d:\n", i); 3258 printf(" at_status: 0x%08x\n", 3259 le32toh(sc->sc_txdescs[i].at_stat)); 3260 printf(" at_flags: 0x%08x\n", 3261 le32toh(sc->sc_txdescs[i].at_flags)); 3262 printf(" at_buf1: 0x%08x\n", 3263 le32toh(sc->sc_txdescs[i].at_buf1)); 3264 printf(" at_buf2: 0x%08x\n", 3265 le32toh(sc->sc_txdescs[i].at_buf2)); 3266 if (i == txs->txs_lastdesc) 3267 break; 3268 } 3269 } 3270#endif 3271 3272 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3273 if (txstat & ATW_TXSTAT_OWN) 3274 break; 3275 3276 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3277 3278 sc->sc_txfree += txs->txs_ndescs; 3279 3280 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3281 0, txs->txs_dmamap->dm_mapsize, 3282 BUS_DMASYNC_POSTWRITE); 3283 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3284 m_freem(txs->txs_mbuf); 3285 txs->txs_mbuf = NULL; 3286 3287 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3288 3289 KASSERT(!(SIMPLEQ_EMPTY(&sc->sc_txfreeq) || 3290 sc->sc_txfree == 0)); 3291 ifp->if_flags &= ~IFF_OACTIVE; 3292 3293 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3294 (txstat & TXSTAT_ERRMASK) != 0) { 3295 bitmask_snprintf(txstat & TXSTAT_ERRMASK, TXSTAT_FMT, 3296 txstat_buf, sizeof(txstat_buf)); 3297 printf("%s: txstat %s %d\n", sc->sc_dev.dv_xname, 3298 txstat_buf, 3299 SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK)); 3300 } 3301 3302 /* 3303 * Check for errors and collisions. 3304 */ 3305 if (txstat & ATW_TXSTAT_TUF) 3306 sc->sc_stats.ts_tx_tuf++; 3307 if (txstat & ATW_TXSTAT_TLT) 3308 sc->sc_stats.ts_tx_tlt++; 3309 if (txstat & ATW_TXSTAT_TRT) 3310 sc->sc_stats.ts_tx_trt++; 3311 if (txstat & ATW_TXSTAT_TRO) 3312 sc->sc_stats.ts_tx_tro++; 3313 if (txstat & ATW_TXSTAT_SOFBR) { 3314 sc->sc_stats.ts_tx_sofbr++; 3315 } 3316 3317 if ((txstat & ATW_TXSTAT_ES) == 0) 3318 ifp->if_collisions += 3319 SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK); 3320 else 3321 ifp->if_oerrors++; 3322 3323 ifp->if_opackets++; 3324 } 3325 3326 /* 3327 * If there are no more pending transmissions, cancel the watchdog 3328 * timer. 3329 */ 3330 if (txs == NULL) { 3331 KASSERT((ifp->if_flags & IFF_OACTIVE) == 0); 3332 sc->sc_tx_timer = 0; 3333 } 3334#undef TXSTAT_ERRMASK 3335#undef TXSTAT_FMT 3336} 3337 3338/* 3339 * atw_watchdog: [ifnet interface function] 3340 * 3341 * Watchdog timer handler. 3342 */ 3343void 3344atw_watchdog(struct ifnet *ifp) 3345{ 3346 struct atw_softc *sc = ifp->if_softc; 3347 struct ieee80211com *ic = &sc->sc_ic; 3348 3349 ifp->if_timer = 0; 3350 if (ATW_IS_ENABLED(sc) == 0) 3351 return; 3352 3353 if (sc->sc_rescan_timer) { 3354 if (--sc->sc_rescan_timer == 0) 3355 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3356 } 3357 if (sc->sc_tx_timer) { 3358 if (--sc->sc_tx_timer == 0 && 3359 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3360 printf("%s: transmit timeout\n", ifp->if_xname); 3361 ifp->if_oerrors++; 3362 (void)atw_init(ifp); 3363 atw_start(ifp); 3364 } 3365 } 3366 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3367 ifp->if_timer = 1; 3368 ieee80211_watchdog(ic); 3369} 3370 3371#ifdef ATW_DEBUG 3372static void 3373atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3374{ 3375 struct atw_softc *sc = ifp->if_softc; 3376 struct mbuf *m; 3377 int i, noctets = 0; 3378 3379 printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname, 3380 m0->m_pkthdr.len); 3381 3382 for (m = m0; m; m = m->m_next) { 3383 if (m->m_len == 0) 3384 continue; 3385 for (i = 0; i < m->m_len; i++) { 3386 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3387 if (++noctets % 24 == 0) 3388 printf("\n"); 3389 } 3390 } 3391 printf("%s%s: %d bytes emitted\n", 3392 (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets); 3393} 3394#endif /* ATW_DEBUG */ 3395 3396/* 3397 * atw_start: [ifnet interface function] 3398 * 3399 * Start packet transmission on the interface. 3400 */ 3401void 3402atw_start(struct ifnet *ifp) 3403{ 3404 struct atw_softc *sc = ifp->if_softc; 3405 struct ieee80211_key *k; 3406 struct ieee80211com *ic = &sc->sc_ic; 3407 struct ieee80211_node *ni; 3408 struct ieee80211_frame_min *whm; 3409 struct ieee80211_frame *wh; 3410 struct atw_frame *hh; 3411 struct mbuf *m0, *m; 3412 struct atw_txsoft *txs, *last_txs; 3413 struct atw_txdesc *txd; 3414 int npkt, rate; 3415 bus_dmamap_t dmamap; 3416 int ctl, error, firsttx, nexttx, lasttx = -1, first, ofree, seg; 3417 3418 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3419 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 3420 3421 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3422 return; 3423 3424 /* 3425 * Remember the previous number of free descriptors and 3426 * the first descriptor we'll use. 3427 */ 3428 ofree = sc->sc_txfree; 3429 firsttx = sc->sc_txnext; 3430 3431 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3432 sc->sc_dev.dv_xname, ofree, firsttx)); 3433 3434 /* 3435 * Loop through the send queue, setting up transmit descriptors 3436 * until we drain the queue, or use up all available transmit 3437 * descriptors. 3438 */ 3439 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3440 sc->sc_txfree != 0) { 3441 3442 /* 3443 * Grab a packet off the management queue, if it 3444 * is not empty. Otherwise, from the data queue. 3445 */ 3446 IF_DEQUEUE(&ic->ic_mgtq, m0); 3447 if (m0 != NULL) { 3448 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 3449 m0->m_pkthdr.rcvif = NULL; 3450 } else if (ic->ic_state != IEEE80211_S_RUN) 3451 break; /* send no data until associated */ 3452 else { 3453 IFQ_DEQUEUE(&ifp->if_snd, m0); 3454 if (m0 == NULL) 3455 break; 3456#if NBPFILTER > 0 3457 if (ifp->if_bpf != NULL) 3458 bpf_mtap(ifp->if_bpf, m0); 3459#endif /* NBPFILTER > 0 */ 3460 ni = ieee80211_find_txnode(ic, 3461 mtod(m0, struct ether_header *)->ether_dhost); 3462 if (ni == NULL) { 3463 ifp->if_oerrors++; 3464 break; 3465 } 3466 if ((m0 = ieee80211_encap(ic, m0, ni)) == NULL) { 3467 ieee80211_free_node(ni); 3468 ifp->if_oerrors++; 3469 break; 3470 } 3471 } 3472 3473 rate = MAX(ieee80211_get_rate(ic), 2); 3474 3475 whm = mtod(m0, struct ieee80211_frame_min *); 3476 3477 if ((whm->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3478 k = NULL; 3479 else if ((k = ieee80211_crypto_encap(ic, ni, m0)) == NULL) { 3480 m_freem(m0); 3481 ieee80211_free_node(ni); 3482 ifp->if_oerrors++; 3483 break; 3484 } 3485 3486 if (ieee80211_compute_duration(whm, k, m0->m_pkthdr.len, 3487 ic->ic_flags, ic->ic_fragthreshold, rate, 3488 &txs->txs_d0, &txs->txs_dn, &npkt, 0) == -1) { 3489 DPRINTF2(sc, ("%s: fail compute duration\n", __func__)); 3490 m_freem(m0); 3491 break; 3492 } 3493 3494 /* XXX Misleading if fragmentation is enabled. Better 3495 * to fragment in software? 3496 */ 3497 *(uint16_t *)whm->i_dur = htole16(txs->txs_d0.d_rts_dur); 3498 3499#if NBPFILTER > 0 3500 /* 3501 * Pass the packet to any BPF listeners. 3502 */ 3503 if (ic->ic_rawbpf != NULL) 3504 bpf_mtap((caddr_t)ic->ic_rawbpf, m0); 3505 3506 if (sc->sc_radiobpf != NULL) { 3507 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3508 3509 tap->at_rate = rate; 3510 tap->at_chan_freq = ic->ic_curchan->ic_freq; 3511 tap->at_chan_flags = ic->ic_curchan->ic_flags; 3512 3513 /* TBD tap->at_flags */ 3514 3515 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap, 3516 tap->at_ihdr.it_len, m0); 3517 } 3518#endif /* NBPFILTER > 0 */ 3519 3520 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3521 3522 if (ni != NULL) 3523 ieee80211_free_node(ni); 3524 3525 if (m0 == NULL) { 3526 ifp->if_oerrors++; 3527 break; 3528 } 3529 3530 /* just to make sure. */ 3531 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3532 3533 if (m0 == NULL) { 3534 ifp->if_oerrors++; 3535 break; 3536 } 3537 3538 hh = mtod(m0, struct atw_frame *); 3539 wh = &hh->atw_ihdr; 3540 3541 /* Copy everything we need from the 802.11 header: 3542 * Frame Control; address 1, address 3, or addresses 3543 * 3 and 4. NIC fills in BSSID, SA. 3544 */ 3545 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3546 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3547 panic("%s: illegal WDS frame", 3548 sc->sc_dev.dv_xname); 3549 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3550 } else 3551 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3552 3553 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3554 3555 /* initialize remaining Tx parameters */ 3556 memset(&hh->u, 0, sizeof(hh->u)); 3557 3558 hh->atw_rate = rate * 5; 3559 /* XXX this could be incorrect if M_FCS. _encap should 3560 * probably strip FCS just in case it sticks around in 3561 * bridged packets. 3562 */ 3563 hh->atw_service = 0x00; /* XXX guess */ 3564 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3565 sizeof(struct atw_frame)); 3566 3567 hh->atw_fragthr = htole16(ic->ic_fragthreshold); 3568 hh->atw_rtylmt = 3; 3569 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3570#if 0 3571 if (do_encrypt) { 3572 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3573 hh->atw_keyid = ic->ic_def_txkey; 3574 } 3575#endif 3576 3577 hh->atw_head_plcplen = htole16(txs->txs_d0.d_plcp_len); 3578 hh->atw_tail_plcplen = htole16(txs->txs_dn.d_plcp_len); 3579 if (txs->txs_d0.d_residue) 3580 hh->atw_head_plcplen |= htole16(0x8000); 3581 if (txs->txs_dn.d_residue) 3582 hh->atw_tail_plcplen |= htole16(0x8000); 3583 hh->atw_head_dur = htole16(txs->txs_d0.d_rts_dur); 3584 hh->atw_tail_dur = htole16(txs->txs_dn.d_rts_dur); 3585 3586 /* never fragment multicast frames */ 3587 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3588 hh->atw_fragthr = htole16(ic->ic_fragthreshold); 3589 } else if (sc->sc_flags & ATWF_RTSCTS) { 3590 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3591 } 3592 3593#ifdef ATW_DEBUG 3594 hh->atw_fragnum = 0; 3595 3596 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3597 printf("%s: dst = %s, rate = 0x%02x, " 3598 "service = 0x%02x, paylen = 0x%04x\n", 3599 sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst), 3600 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3601 3602 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3603 "dur1 = 0x%04x, dur2 = 0x%04x, " 3604 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3605 sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1], 3606 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3607 hh->atw_tail_dur, hh->atw_head_dur); 3608 3609 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3610 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3611 sc->sc_dev.dv_xname, hh->atw_hdrctl, 3612 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3613 3614 printf("%s: keyid = %d\n", 3615 sc->sc_dev.dv_xname, hh->atw_keyid); 3616 3617 atw_dump_pkt(ifp, m0); 3618 } 3619#endif /* ATW_DEBUG */ 3620 3621 dmamap = txs->txs_dmamap; 3622 3623 /* 3624 * Load the DMA map. Copy and try (once) again if the packet 3625 * didn't fit in the alloted number of segments. 3626 */ 3627 for (first = 1; 3628 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3629 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3630 first = 0) { 3631 MGETHDR(m, M_DONTWAIT, MT_DATA); 3632 if (m == NULL) { 3633 printf("%s: unable to allocate Tx mbuf\n", 3634 sc->sc_dev.dv_xname); 3635 break; 3636 } 3637 if (m0->m_pkthdr.len > MHLEN) { 3638 MCLGET(m, M_DONTWAIT); 3639 if ((m->m_flags & M_EXT) == 0) { 3640 printf("%s: unable to allocate Tx " 3641 "cluster\n", sc->sc_dev.dv_xname); 3642 m_freem(m); 3643 break; 3644 } 3645 } 3646 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3647 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3648 m_freem(m0); 3649 m0 = m; 3650 m = NULL; 3651 } 3652 if (error != 0) { 3653 printf("%s: unable to load Tx buffer, " 3654 "error = %d\n", sc->sc_dev.dv_xname, error); 3655 m_freem(m0); 3656 break; 3657 } 3658 3659 /* 3660 * Ensure we have enough descriptors free to describe 3661 * the packet. 3662 */ 3663 if (dmamap->dm_nsegs > sc->sc_txfree) { 3664 /* 3665 * Not enough free descriptors to transmit 3666 * this packet. Unload the DMA map and 3667 * drop the packet. Notify the upper layer 3668 * that there are no more slots left. 3669 * 3670 * XXX We could allocate an mbuf and copy, but 3671 * XXX it is worth it? 3672 */ 3673 bus_dmamap_unload(sc->sc_dmat, dmamap); 3674 m_freem(m0); 3675 break; 3676 } 3677 3678 /* 3679 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3680 */ 3681 3682 /* Sync the DMA map. */ 3683 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3684 BUS_DMASYNC_PREWRITE); 3685 3686 /* XXX arbitrary retry limit; 8 because I have seen it in 3687 * use already and maybe 0 means "no tries" ! 3688 */ 3689 ctl = htole32(SHIFTIN(8, ATW_TXCTL_TL_MASK)); 3690 3691 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3692 sc->sc_dev.dv_xname, rate * 5)); 3693 ctl |= htole32(SHIFTIN(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3694 3695 /* 3696 * Initialize the transmit descriptors. 3697 */ 3698 for (nexttx = sc->sc_txnext, seg = 0; 3699 seg < dmamap->dm_nsegs; 3700 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3701 /* 3702 * If this is the first descriptor we're 3703 * enqueueing, don't set the OWN bit just 3704 * yet. That could cause a race condition. 3705 * We'll do it below. 3706 */ 3707 txd = &sc->sc_txdescs[nexttx]; 3708 txd->at_ctl = ctl | 3709 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3710 3711 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3712 txd->at_flags = 3713 htole32(SHIFTIN(dmamap->dm_segs[seg].ds_len, 3714 ATW_TXFLAG_TBS1_MASK)) | 3715 ((nexttx == (ATW_NTXDESC - 1)) 3716 ? htole32(ATW_TXFLAG_TER) : 0); 3717 lasttx = nexttx; 3718 } 3719 3720 IASSERT(lasttx != -1, ("bad lastx")); 3721 /* Set `first segment' and `last segment' appropriately. */ 3722 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3723 htole32(ATW_TXFLAG_FS); 3724 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3725 3726#ifdef ATW_DEBUG 3727 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3728 printf(" txsoft %p transmit chain:\n", txs); 3729 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3730 printf(" descriptor %d:\n", seg); 3731 printf(" at_ctl: 0x%08x\n", 3732 le32toh(sc->sc_txdescs[seg].at_ctl)); 3733 printf(" at_flags: 0x%08x\n", 3734 le32toh(sc->sc_txdescs[seg].at_flags)); 3735 printf(" at_buf1: 0x%08x\n", 3736 le32toh(sc->sc_txdescs[seg].at_buf1)); 3737 printf(" at_buf2: 0x%08x\n", 3738 le32toh(sc->sc_txdescs[seg].at_buf2)); 3739 if (seg == lasttx) 3740 break; 3741 } 3742 } 3743#endif 3744 3745 /* Sync the descriptors we're using. */ 3746 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3747 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3748 3749 /* 3750 * Store a pointer to the packet so we can free it later, 3751 * and remember what txdirty will be once the packet is 3752 * done. 3753 */ 3754 txs->txs_mbuf = m0; 3755 txs->txs_firstdesc = sc->sc_txnext; 3756 txs->txs_lastdesc = lasttx; 3757 txs->txs_ndescs = dmamap->dm_nsegs; 3758 3759 /* Advance the tx pointer. */ 3760 sc->sc_txfree -= dmamap->dm_nsegs; 3761 sc->sc_txnext = nexttx; 3762 3763 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3764 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3765 3766 last_txs = txs; 3767 } 3768 3769 if (sc->sc_txfree != ofree) { 3770 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3771 sc->sc_dev.dv_xname, lasttx, firsttx)); 3772 /* 3773 * Cause a transmit interrupt to happen on the 3774 * last packet we enqueued. 3775 */ 3776 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3777 ATW_CDTXSYNC(sc, lasttx, 1, 3778 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3779 3780 /* 3781 * The entire packet chain is set up. Give the 3782 * first descriptor to the chip now. 3783 */ 3784 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3785 ATW_CDTXSYNC(sc, firsttx, 1, 3786 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3787 3788 /* Wake up the transmitter. */ 3789 ATW_WRITE(sc, ATW_TDR, 0x1); 3790 3791 if (txs == NULL || sc->sc_txfree == 0) 3792 ifp->if_flags |= IFF_OACTIVE; 3793 3794 /* Set a watchdog timer in case the chip flakes out. */ 3795 sc->sc_tx_timer = 5; 3796 ifp->if_timer = 1; 3797 } 3798} 3799 3800/* 3801 * atw_power: 3802 * 3803 * Power management (suspend/resume) hook. 3804 */ 3805void 3806atw_power(int why, void *arg) 3807{ 3808 struct atw_softc *sc = arg; 3809 struct ifnet *ifp = &sc->sc_if; 3810 int s; 3811 3812 DPRINTF(sc, ("%s: atw_power(%d,)\n", sc->sc_dev.dv_xname, why)); 3813 3814 s = splnet(); 3815 switch (why) { 3816 case PWR_STANDBY: 3817 /* XXX do nothing. */ 3818 break; 3819 case PWR_SUSPEND: 3820 atw_stop(ifp, 0); 3821 if (sc->sc_power != NULL) 3822 (*sc->sc_power)(sc, why); 3823 break; 3824 case PWR_RESUME: 3825 if (ifp->if_flags & IFF_UP) { 3826 if (sc->sc_power != NULL) 3827 (*sc->sc_power)(sc, why); 3828 atw_init(ifp); 3829 } 3830 break; 3831 case PWR_SOFTSUSPEND: 3832 case PWR_SOFTSTANDBY: 3833 case PWR_SOFTRESUME: 3834 break; 3835 } 3836 splx(s); 3837} 3838 3839/* 3840 * atw_ioctl: [ifnet interface function] 3841 * 3842 * Handle control requests from the operator. 3843 */ 3844int 3845atw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3846{ 3847 struct atw_softc *sc = ifp->if_softc; 3848 struct ifreq *ifr = (struct ifreq *)data; 3849 int s, error = 0; 3850 3851 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 3852 if (!device_is_active(&sc->sc_dev)) 3853 return ENXIO; 3854 3855 s = splnet(); 3856 3857 switch (cmd) { 3858 case SIOCSIFFLAGS: 3859 if (ifp->if_flags & IFF_UP) { 3860 if (ATW_IS_ENABLED(sc)) { 3861 /* 3862 * To avoid rescanning another access point, 3863 * do not call atw_init() here. Instead, 3864 * only reflect media settings. 3865 */ 3866 atw_filter_setup(sc); 3867 } else 3868 error = atw_init(ifp); 3869 } else if (ATW_IS_ENABLED(sc)) 3870 atw_stop(ifp, 1); 3871 break; 3872 case SIOCADDMULTI: 3873 case SIOCDELMULTI: 3874 error = (cmd == SIOCADDMULTI) ? 3875 ether_addmulti(ifr, &sc->sc_ec) : 3876 ether_delmulti(ifr, &sc->sc_ec); 3877 if (error == ENETRESET) { 3878 if (ifp->if_flags & IFF_RUNNING) 3879 atw_filter_setup(sc); /* do not rescan */ 3880 error = 0; 3881 } 3882 break; 3883 default: 3884 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 3885 if (error == ENETRESET || error == ERESTART) { 3886 if (is_running(ifp)) 3887 error = atw_init(ifp); 3888 else 3889 error = 0; 3890 } 3891 break; 3892 } 3893 3894 /* Try to get more packets going. */ 3895 if (ATW_IS_ENABLED(sc)) 3896 atw_start(ifp); 3897 3898 splx(s); 3899 return (error); 3900} 3901 3902static int 3903atw_media_change(struct ifnet *ifp) 3904{ 3905 int error; 3906 3907 error = ieee80211_media_change(ifp); 3908 if (error == ENETRESET) { 3909 if (is_running(ifp)) 3910 error = atw_init(ifp); 3911 else 3912 error = 0; 3913 } 3914 return error; 3915} 3916