1/* $NetBSD: ds1307.c,v 1.40 2023/01/24 07:09:48 mlelstv Exp $ */ 2 3/* 4 * Copyright (c) 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38#include <sys/cdefs.h> 39__KERNEL_RCSID(0, "$NetBSD: ds1307.c,v 1.40 2023/01/24 07:09:48 mlelstv Exp $"); 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/device.h> 44#include <sys/kernel.h> 45#include <sys/fcntl.h> 46#include <sys/uio.h> 47#include <sys/conf.h> 48#include <sys/event.h> 49 50#include <dev/clock_subr.h> 51 52#include <dev/i2c/i2cvar.h> 53#include <dev/i2c/ds1307reg.h> 54#include <dev/sysmon/sysmonvar.h> 55 56#include "ioconf.h" 57#include "opt_dsrtc.h" 58 59struct dsrtc_model { 60 const i2c_addr_t *dm_valid_addrs; 61 uint16_t dm_model; 62 uint8_t dm_ch_reg; 63 uint8_t dm_ch_value; 64 uint8_t dm_vbaten_reg; 65 uint8_t dm_vbaten_value; 66 uint8_t dm_rtc_start; 67 uint8_t dm_rtc_size; 68 uint8_t dm_nvram_start; 69 uint8_t dm_nvram_size; 70 uint8_t dm_flags; 71#define DSRTC_FLAG_CLOCK_HOLD 0x01 72#define DSRTC_FLAG_BCD 0x02 73#define DSRTC_FLAG_TEMP 0x04 74#define DSRTC_FLAG_VBATEN 0x08 75#define DSRTC_FLAG_YEAR_START_2K 0x10 76#define DSRTC_FLAG_CLOCK_HOLD_REVERSED 0x20 77}; 78 79static const i2c_addr_t ds1307_valid_addrs[] = { DS1307_ADDR, 0 }; 80static const struct dsrtc_model ds1307_model = { 81 .dm_valid_addrs = ds1307_valid_addrs, 82 .dm_model = 1307, 83 .dm_ch_reg = DSXXXX_SECONDS, 84 .dm_ch_value = DS1307_SECONDS_CH, 85 .dm_rtc_start = DS1307_RTC_START, 86 .dm_rtc_size = DS1307_RTC_SIZE, 87 .dm_nvram_start = DS1307_NVRAM_START, 88 .dm_nvram_size = DS1307_NVRAM_SIZE, 89 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_CLOCK_HOLD, 90}; 91 92static const struct dsrtc_model ds1339_model = { 93 .dm_valid_addrs = ds1307_valid_addrs, 94 .dm_model = 1339, 95 .dm_rtc_start = DS1339_RTC_START, 96 .dm_rtc_size = DS1339_RTC_SIZE, 97 .dm_flags = DSRTC_FLAG_BCD, 98}; 99 100static const struct dsrtc_model ds1340_model = { 101 .dm_valid_addrs = ds1307_valid_addrs, 102 .dm_model = 1340, 103 .dm_ch_reg = DSXXXX_SECONDS, 104 .dm_ch_value = DS1340_SECONDS_EOSC, 105 .dm_rtc_start = DS1340_RTC_START, 106 .dm_rtc_size = DS1340_RTC_SIZE, 107 .dm_flags = DSRTC_FLAG_BCD, 108}; 109 110static const struct dsrtc_model ds1672_model = { 111 .dm_valid_addrs = ds1307_valid_addrs, 112 .dm_model = 1672, 113 .dm_rtc_start = DS1672_RTC_START, 114 .dm_rtc_size = DS1672_RTC_SIZE, 115 .dm_ch_reg = DS1672_CONTROL, 116 .dm_ch_value = DS1672_CONTROL_CH, 117 .dm_flags = 0, 118}; 119 120static const struct dsrtc_model ds3231_model = { 121 .dm_valid_addrs = ds1307_valid_addrs, 122 .dm_model = 3231, 123 .dm_rtc_start = DS3232_RTC_START, 124 .dm_rtc_size = DS3232_RTC_SIZE, 125 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_TEMP, 126}; 127 128static const struct dsrtc_model ds3232_model = { 129 .dm_valid_addrs = ds1307_valid_addrs, 130 .dm_model = 3232, 131 .dm_rtc_start = DS3232_RTC_START, 132 .dm_rtc_size = DS3232_RTC_SIZE, 133 .dm_nvram_start = DS3232_NVRAM_START, 134 .dm_nvram_size = DS3232_NVRAM_SIZE, 135 /* 136 * XXX 137 * the DS3232 likely has the temperature sensor too but I can't 138 * easily verify or test that right now 139 */ 140 .dm_flags = DSRTC_FLAG_BCD, 141}; 142 143static const i2c_addr_t mcp7940_valid_addrs[] = { MCP7940_ADDR, 0 }; 144static const struct dsrtc_model mcp7940_model = { 145 .dm_valid_addrs = mcp7940_valid_addrs, 146 .dm_model = 7940, 147 .dm_rtc_start = DS1307_RTC_START, 148 .dm_rtc_size = DS1307_RTC_SIZE, 149 .dm_ch_reg = DSXXXX_SECONDS, 150 .dm_ch_value = DS1307_SECONDS_CH, 151 .dm_vbaten_reg = DSXXXX_DAY, 152 .dm_vbaten_value = MCP7940_TOD_DAY_VBATEN, 153 .dm_nvram_start = MCP7940_NVRAM_START, 154 .dm_nvram_size = MCP7940_NVRAM_SIZE, 155 .dm_flags = DSRTC_FLAG_BCD | DSRTC_FLAG_CLOCK_HOLD | 156 DSRTC_FLAG_VBATEN | DSRTC_FLAG_CLOCK_HOLD_REVERSED, 157}; 158 159static const struct device_compatible_entry compat_data[] = { 160 { .compat = "dallas,ds1307", .data = &ds1307_model }, 161 { .compat = "maxim,ds1307", .data = &ds1307_model }, 162 { .compat = "i2c-ds1307", .data = &ds1307_model }, 163 164 { .compat = "dallas,ds1339", .data = &ds1339_model }, 165 { .compat = "maxim,ds1339", .data = &ds1339_model }, 166 167 { .compat = "dallas,ds1340", .data = &ds1340_model }, 168 { .compat = "maxim,ds1340", .data = &ds1340_model }, 169 170 { .compat = "dallas,ds1672", .data = &ds1672_model }, 171 { .compat = "maxim,ds1672", .data = &ds1672_model }, 172 173 { .compat = "dallas,ds3231", .data = &ds3231_model }, 174 { .compat = "maxim,ds3231", .data = &ds3231_model }, 175 176 { .compat = "dallas,ds3232", .data = &ds3232_model }, 177 { .compat = "maxim,ds3232", .data = &ds3232_model }, 178 179 { .compat = "microchip,mcp7940", .data = &mcp7940_model }, 180 181 DEVICE_COMPAT_EOL 182}; 183 184struct dsrtc_softc { 185 device_t sc_dev; 186 i2c_tag_t sc_tag; 187 uint8_t sc_address; 188 bool sc_open; 189 struct dsrtc_model sc_model; 190 struct todr_chip_handle sc_todr; 191 struct sysmon_envsys *sc_sme; 192 envsys_data_t sc_sensor; 193}; 194 195static void dsrtc_attach(device_t, device_t, void *); 196static int dsrtc_match(device_t, cfdata_t, void *); 197 198CFATTACH_DECL_NEW(dsrtc, sizeof(struct dsrtc_softc), 199 dsrtc_match, dsrtc_attach, NULL, NULL); 200 201dev_type_open(dsrtc_open); 202dev_type_close(dsrtc_close); 203dev_type_read(dsrtc_read); 204dev_type_write(dsrtc_write); 205 206const struct cdevsw dsrtc_cdevsw = { 207 .d_open = dsrtc_open, 208 .d_close = dsrtc_close, 209 .d_read = dsrtc_read, 210 .d_write = dsrtc_write, 211 .d_ioctl = noioctl, 212 .d_stop = nostop, 213 .d_tty = notty, 214 .d_poll = nopoll, 215 .d_mmap = nommap, 216 .d_kqfilter = nokqfilter, 217 .d_discard = nodiscard, 218 .d_flag = D_OTHER 219}; 220 221static int dsrtc_gettime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 222static int dsrtc_settime_ymdhms(struct todr_chip_handle *, struct clock_ymdhms *); 223static int dsrtc_clock_read_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 224static int dsrtc_clock_write_ymdhms(struct dsrtc_softc *, struct clock_ymdhms *); 225 226static int dsrtc_gettime_timeval(struct todr_chip_handle *, struct timeval *); 227static int dsrtc_settime_timeval(struct todr_chip_handle *, struct timeval *); 228static int dsrtc_clock_read_timeval(struct dsrtc_softc *, time_t *); 229static int dsrtc_clock_write_timeval(struct dsrtc_softc *, time_t); 230 231static int dsrtc_read_temp(struct dsrtc_softc *, uint32_t *); 232static void dsrtc_refresh(struct sysmon_envsys *, envsys_data_t *); 233 234static const struct dsrtc_model * 235dsrtc_model_by_number(u_int model) 236{ 237 const struct device_compatible_entry *dce; 238 const struct dsrtc_model *dm; 239 240 /* no model given, assume it's a DS1307 */ 241 if (model == 0) 242 return &ds1307_model; 243 244 for (dce = compat_data; dce->compat != NULL; dce++) { 245 dm = dce->data; 246 if (dm->dm_model == model) 247 return dm; 248 } 249 return NULL; 250} 251 252static const struct dsrtc_model * 253dsrtc_model_by_compat(const struct i2c_attach_args *ia) 254{ 255 const struct dsrtc_model *dm = NULL; 256 const struct device_compatible_entry *dce; 257 258 if ((dce = iic_compatible_lookup(ia, compat_data)) != NULL) 259 dm = dce->data; 260 261 return dm; 262} 263 264static bool 265dsrtc_is_valid_addr_for_model(const struct dsrtc_model *dm, i2c_addr_t addr) 266{ 267 268 for (int i = 0; dm->dm_valid_addrs[i] != 0; i++) { 269 if (addr == dm->dm_valid_addrs[i]) 270 return true; 271 } 272 return false; 273} 274 275static int 276dsrtc_match(device_t parent, cfdata_t cf, void *arg) 277{ 278 struct i2c_attach_args *ia = arg; 279 const struct dsrtc_model *dm; 280 int match_result; 281 282 if (iic_use_direct_match(ia, cf, compat_data, &match_result)) 283 return match_result; 284 285 dm = dsrtc_model_by_number(cf->cf_flags & 0xffff); 286 if (dm == NULL) 287 return 0; 288 289 if (dsrtc_is_valid_addr_for_model(dm, ia->ia_addr)) 290 return I2C_MATCH_ADDRESS_ONLY; 291 292 return 0; 293} 294 295static void 296dsrtc_attach(device_t parent, device_t self, void *arg) 297{ 298 struct dsrtc_softc *sc = device_private(self); 299 struct i2c_attach_args *ia = arg; 300 const struct dsrtc_model *dm; 301 prop_dictionary_t dict = device_properties(self); 302 bool base_2k = FALSE; 303 304 if ((dm = dsrtc_model_by_compat(ia)) == NULL) 305 dm = dsrtc_model_by_number(device_cfdata(self)->cf_flags); 306 307 if (dm == NULL) { 308 aprint_error(": unable to determine model!\n"); 309 return; 310 } 311 312 aprint_naive(": Real-time Clock%s\n", 313 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 314 aprint_normal(": DS%u Real-time Clock%s\n", dm->dm_model, 315 dm->dm_nvram_size > 0 ? "/NVRAM" : ""); 316 317 sc->sc_tag = ia->ia_tag; 318 sc->sc_address = ia->ia_addr; 319 sc->sc_model = *dm; 320 sc->sc_dev = self; 321 sc->sc_open = 0; 322 sc->sc_todr.cookie = sc; 323 324 if (dm->dm_flags & DSRTC_FLAG_BCD) { 325 sc->sc_todr.todr_gettime_ymdhms = dsrtc_gettime_ymdhms; 326 sc->sc_todr.todr_settime_ymdhms = dsrtc_settime_ymdhms; 327 } else { 328 sc->sc_todr.todr_gettime = dsrtc_gettime_timeval; 329 sc->sc_todr.todr_settime = dsrtc_settime_timeval; 330 } 331 sc->sc_todr.todr_setwen = NULL; 332 333#ifdef DSRTC_YEAR_START_2K 334 sc->sc_model.dm_flags |= DSRTC_FLAG_YEAR_START_2K; 335#endif 336 337 prop_dictionary_get_bool(dict, "base_year_is_2000", &base_2k); 338 if (base_2k) sc->sc_model.dm_flags |= DSRTC_FLAG_YEAR_START_2K; 339 340 341 todr_attach(&sc->sc_todr); 342 if ((sc->sc_model.dm_flags & DSRTC_FLAG_TEMP) != 0) { 343 int error; 344 345 sc->sc_sme = sysmon_envsys_create(); 346 sc->sc_sme->sme_name = device_xname(self); 347 sc->sc_sme->sme_cookie = sc; 348 sc->sc_sme->sme_refresh = dsrtc_refresh; 349 350 sc->sc_sensor.units = ENVSYS_STEMP; 351 sc->sc_sensor.state = ENVSYS_SINVALID; 352 sc->sc_sensor.flags = 0; 353 (void)strlcpy(sc->sc_sensor.desc, "temperature", 354 sizeof(sc->sc_sensor.desc)); 355 356 if (sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor)) { 357 aprint_error_dev(self, "unable to attach sensor\n"); 358 goto bad; 359 } 360 361 error = sysmon_envsys_register(sc->sc_sme); 362 if (error) { 363 aprint_error_dev(self, 364 "error %d registering with sysmon\n", error); 365 goto bad; 366 } 367 } 368 return; 369bad: 370 sysmon_envsys_destroy(sc->sc_sme); 371} 372 373/*ARGSUSED*/ 374int 375dsrtc_open(dev_t dev, int flag, int fmt, struct lwp *l) 376{ 377 struct dsrtc_softc *sc; 378 379 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 380 return ENXIO; 381 382 /* XXX: Locking */ 383 if (sc->sc_open) 384 return EBUSY; 385 386 sc->sc_open = true; 387 return 0; 388} 389 390/*ARGSUSED*/ 391int 392dsrtc_close(dev_t dev, int flag, int fmt, struct lwp *l) 393{ 394 struct dsrtc_softc *sc; 395 396 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 397 return ENXIO; 398 399 sc->sc_open = false; 400 return 0; 401} 402 403/*ARGSUSED*/ 404int 405dsrtc_read(dev_t dev, struct uio *uio, int flags) 406{ 407 struct dsrtc_softc *sc; 408 int error; 409 410 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 411 return ENXIO; 412 413 const struct dsrtc_model * const dm = &sc->sc_model; 414 if (uio->uio_offset < 0 || uio->uio_offset >= dm->dm_nvram_size) 415 return EINVAL; 416 417 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 418 return error; 419 420 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 421 uint8_t ch, cmd; 422 const u_int a = uio->uio_offset; 423 cmd = a + dm->dm_nvram_start; 424 if ((error = iic_exec(sc->sc_tag, 425 uio->uio_resid > 1 ? I2C_OP_READ : I2C_OP_READ_WITH_STOP, 426 sc->sc_address, &cmd, 1, &ch, 1, 0)) != 0) { 427 iic_release_bus(sc->sc_tag, 0); 428 aprint_error_dev(sc->sc_dev, 429 "%s: read failed at 0x%x: %d\n", 430 __func__, a, error); 431 return error; 432 } 433 if ((error = uiomove(&ch, 1, uio)) != 0) { 434 iic_release_bus(sc->sc_tag, 0); 435 return error; 436 } 437 } 438 439 iic_release_bus(sc->sc_tag, 0); 440 441 return 0; 442} 443 444/*ARGSUSED*/ 445int 446dsrtc_write(dev_t dev, struct uio *uio, int flags) 447{ 448 struct dsrtc_softc *sc; 449 int error; 450 451 if ((sc = device_lookup_private(&dsrtc_cd, minor(dev))) == NULL) 452 return ENXIO; 453 454 const struct dsrtc_model * const dm = &sc->sc_model; 455 if (uio->uio_offset >= dm->dm_nvram_size) 456 return EINVAL; 457 458 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) 459 return error; 460 461 while (uio->uio_resid && uio->uio_offset < dm->dm_nvram_size) { 462 uint8_t cmdbuf[2]; 463 const u_int a = (int)uio->uio_offset; 464 cmdbuf[0] = a + dm->dm_nvram_start; 465 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0) 466 break; 467 468 if ((error = iic_exec(sc->sc_tag, 469 uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP, 470 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 471 aprint_error_dev(sc->sc_dev, 472 "%s: write failed at 0x%x: %d\n", 473 __func__, a, error); 474 break; 475 } 476 } 477 478 iic_release_bus(sc->sc_tag, 0); 479 480 return error; 481} 482 483static int 484dsrtc_gettime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 485{ 486 struct dsrtc_softc *sc = ch->cookie; 487 struct clock_ymdhms check; 488 int retries; 489 490 memset(dt, 0, sizeof(*dt)); 491 memset(&check, 0, sizeof(check)); 492 493 /* 494 * Since we don't support Burst Read, we have to read the clock twice 495 * until we get two consecutive identical results. 496 */ 497 retries = 5; 498 do { 499 dsrtc_clock_read_ymdhms(sc, dt); 500 dsrtc_clock_read_ymdhms(sc, &check); 501 } while (memcmp(dt, &check, sizeof(check)) != 0 && --retries); 502 503 return 0; 504} 505 506static int 507dsrtc_settime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt) 508{ 509 struct dsrtc_softc *sc = ch->cookie; 510 511 if (dsrtc_clock_write_ymdhms(sc, dt) == 0) 512 return -1; 513 514 return 0; 515} 516 517static int 518dsrtc_clock_read_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 519{ 520 struct dsrtc_model * const dm = &sc->sc_model; 521 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[1]; 522 int error; 523 524 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 525 526 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) { 527 aprint_error_dev(sc->sc_dev, 528 "%s: failed to acquire I2C bus: %d\n", 529 __func__, error); 530 return 0; 531 } 532 533 /* Read each RTC register in order. */ 534 for (u_int i = 0; !error && i < dm->dm_rtc_size; i++) { 535 cmdbuf[0] = dm->dm_rtc_start + i; 536 537 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, 538 sc->sc_address, cmdbuf, 1, &bcd[i], 1, 0); 539 } 540 541 /* Done with I2C */ 542 iic_release_bus(sc->sc_tag, 0); 543 544 if (error != 0) { 545 aprint_error_dev(sc->sc_dev, 546 "%s: failed to read rtc at 0x%x: %d\n", 547 __func__, cmdbuf[0], error); 548 return 0; 549 } 550 551 /* 552 * Convert the RTC's register values into something useable 553 */ 554 dt->dt_sec = bcdtobin(bcd[DSXXXX_SECONDS] & DSXXXX_SECONDS_MASK); 555 dt->dt_min = bcdtobin(bcd[DSXXXX_MINUTES] & DSXXXX_MINUTES_MASK); 556 557 if ((bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_MODE) != 0) { 558 dt->dt_hour = bcdtobin(bcd[DSXXXX_HOURS] & 559 DSXXXX_HOURS_12MASK) % 12; /* 12AM -> 0, 12PM -> 12 */ 560 if (bcd[DSXXXX_HOURS] & DSXXXX_HOURS_12HRS_PM) 561 dt->dt_hour += 12; 562 } else 563 dt->dt_hour = bcdtobin(bcd[DSXXXX_HOURS] & 564 DSXXXX_HOURS_24MASK); 565 566 dt->dt_day = bcdtobin(bcd[DSXXXX_DATE] & DSXXXX_DATE_MASK); 567 dt->dt_mon = bcdtobin(bcd[DSXXXX_MONTH] & DSXXXX_MONTH_MASK); 568 569 /* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */ 570 if (sc->sc_model.dm_flags & DSRTC_FLAG_YEAR_START_2K) 571 dt->dt_year = bcdtobin(bcd[DSXXXX_YEAR]) + 2000; 572 else { 573 dt->dt_year = bcdtobin(bcd[DSXXXX_YEAR]) + POSIX_BASE_YEAR; 574 if (bcd[DSXXXX_MONTH] & DSXXXX_MONTH_CENTURY) 575 dt->dt_year += 100; 576 } 577 578 return 1; 579} 580 581static int 582dsrtc_clock_write_ymdhms(struct dsrtc_softc *sc, struct clock_ymdhms *dt) 583{ 584 struct dsrtc_model * const dm = &sc->sc_model; 585 uint8_t bcd[DSXXXX_RTC_SIZE], cmdbuf[2]; 586 int error, offset; 587 588 KASSERT(DSXXXX_RTC_SIZE >= dm->dm_rtc_size); 589 590 /* 591 * Convert our time representation into something the DSXXXX 592 * can understand. 593 */ 594 bcd[DSXXXX_SECONDS] = bintobcd(dt->dt_sec); 595 bcd[DSXXXX_MINUTES] = bintobcd(dt->dt_min); 596 bcd[DSXXXX_HOURS] = bintobcd(dt->dt_hour); /* DSXXXX_HOURS_12HRS_MODE=0 */ 597 bcd[DSXXXX_DATE] = bintobcd(dt->dt_day); 598 bcd[DSXXXX_DAY] = bintobcd(dt->dt_wday); 599 bcd[DSXXXX_MONTH] = bintobcd(dt->dt_mon); 600 601 if (sc->sc_model.dm_flags & DSRTC_FLAG_YEAR_START_2K) { 602 offset = 2000; 603 } else { 604 offset = POSIX_BASE_YEAR; 605 } 606 607 bcd[DSXXXX_YEAR] = bintobcd((dt->dt_year - offset) % 100); 608 if (dt->dt_year - offset >= 100) 609 bcd[DSXXXX_MONTH] |= DSXXXX_MONTH_CENTURY; 610 611 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) { 612 aprint_error_dev(sc->sc_dev, 613 "%s: failed to acquire I2C bus: %d\n", 614 __func__, error); 615 return 0; 616 } 617 618 /* Stop the clock */ 619 cmdbuf[0] = dm->dm_ch_reg; 620 621 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address, 622 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 623 iic_release_bus(sc->sc_tag, 0); 624 aprint_error_dev(sc->sc_dev, 625 "%s: failed to read Hold Clock: %d\n", 626 __func__, error); 627 return 0; 628 } 629 630 if (sc->sc_model.dm_flags & DSRTC_FLAG_CLOCK_HOLD_REVERSED) 631 cmdbuf[1] &= ~dm->dm_ch_value; 632 else 633 cmdbuf[1] |= dm->dm_ch_value; 634 635 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address, 636 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 637 iic_release_bus(sc->sc_tag, 0); 638 aprint_error_dev(sc->sc_dev, 639 "%s: failed to write Hold Clock: %d\n", 640 __func__, error); 641 return 0; 642 } 643 644 /* 645 * Write registers in reverse order. The last write (to the Seconds 646 * register) will undo the Clock Hold, above. 647 */ 648 uint8_t op = I2C_OP_WRITE; 649 for (signed int i = dm->dm_rtc_size - 1; i >= 0; i--) { 650 cmdbuf[0] = dm->dm_rtc_start + i; 651 if ((dm->dm_flags & DSRTC_FLAG_VBATEN) && 652 dm->dm_rtc_start + i == dm->dm_vbaten_reg) 653 bcd[i] |= dm->dm_vbaten_value; 654 if (dm->dm_rtc_start + i == dm->dm_ch_reg) { 655 op = I2C_OP_WRITE_WITH_STOP; 656 if (dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD_REVERSED) 657 bcd[i] |= dm->dm_ch_value; 658 } 659 if ((error = iic_exec(sc->sc_tag, op, sc->sc_address, 660 cmdbuf, 1, &bcd[i], 1, 0)) != 0) { 661 iic_release_bus(sc->sc_tag, 0); 662 aprint_error_dev(sc->sc_dev, 663 "%s: failed to write rtc at 0x%x: %d\n", 664 __func__, i, error); 665 /* XXX: Clock Hold is likely still asserted! */ 666 return 0; 667 } 668 } 669 /* 670 * If the clock hold register isn't the same register as seconds, 671 * we need to reenable the clock. 672 */ 673 if (op != I2C_OP_WRITE_WITH_STOP) { 674 cmdbuf[0] = dm->dm_ch_reg; 675 if (dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD_REVERSED) 676 cmdbuf[1] |= dm->dm_ch_value; 677 else 678 cmdbuf[1] &= ~dm->dm_ch_value; 679 680 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 681 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) { 682 iic_release_bus(sc->sc_tag, 0); 683 aprint_error_dev(sc->sc_dev, 684 "%s: failed to Hold Clock: %d\n", 685 __func__, error); 686 return 0; 687 } 688 } 689 690 iic_release_bus(sc->sc_tag, 0); 691 692 return 1; 693} 694 695static int 696dsrtc_gettime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 697{ 698 struct dsrtc_softc *sc = ch->cookie; 699 struct timeval check; 700 int retries; 701 702 memset(tv, 0, sizeof(*tv)); 703 memset(&check, 0, sizeof(check)); 704 705 /* 706 * Since we don't support Burst Read, we have to read the clock twice 707 * until we get two consecutive identical results. 708 */ 709 retries = 5; 710 do { 711 dsrtc_clock_read_timeval(sc, &tv->tv_sec); 712 dsrtc_clock_read_timeval(sc, &check.tv_sec); 713 } while (memcmp(tv, &check, sizeof(check)) != 0 && --retries); 714 715 return 0; 716} 717 718static int 719dsrtc_settime_timeval(struct todr_chip_handle *ch, struct timeval *tv) 720{ 721 struct dsrtc_softc *sc = ch->cookie; 722 723 if (dsrtc_clock_write_timeval(sc, tv->tv_sec) == 0) 724 return -1; 725 726 return 0; 727} 728 729/* 730 * The RTC probably has a nice Clock Burst Read/Write command, but we can't use 731 * it, since some I2C controllers don't support anything other than single-byte 732 * transfers. 733 */ 734static int 735dsrtc_clock_read_timeval(struct dsrtc_softc *sc, time_t *tp) 736{ 737 const struct dsrtc_model * const dm = &sc->sc_model; 738 uint8_t buf[4]; 739 int error; 740 741 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) { 742 aprint_error_dev(sc->sc_dev, 743 "%s: failed to acquire I2C bus: %d\n", 744 __func__, error); 745 return 0; 746 } 747 748 /* read all registers: */ 749 uint8_t reg = dm->dm_rtc_start; 750 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 751 ®, 1, buf, 4, 0); 752 753 /* Done with I2C */ 754 iic_release_bus(sc->sc_tag, 0); 755 756 if (error != 0) { 757 aprint_error_dev(sc->sc_dev, 758 "%s: failed to read rtc at 0x%x: %d\n", 759 __func__, reg, error); 760 return 0; 761 } 762 763 uint32_t v = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; 764 *tp = v; 765 766 aprint_debug_dev(sc->sc_dev, "%s: cntr=0x%08"PRIx32"\n", 767 __func__, v); 768 769 return 1; 770} 771 772static int 773dsrtc_clock_write_timeval(struct dsrtc_softc *sc, time_t t) 774{ 775 const struct dsrtc_model * const dm = &sc->sc_model; 776 size_t buflen = dm->dm_rtc_size + 2; 777 /* XXX: the biggest dm_rtc_size we have now is 7, so we should be ok */ 778 uint8_t buf[16]; 779 int error; 780 781 KASSERT((dm->dm_flags & DSRTC_FLAG_CLOCK_HOLD) == 0); 782 KASSERT(dm->dm_ch_reg == dm->dm_rtc_start + 4); 783 784 buf[0] = dm->dm_rtc_start; 785 buf[1] = (t >> 0) & 0xff; 786 buf[2] = (t >> 8) & 0xff; 787 buf[3] = (t >> 16) & 0xff; 788 buf[4] = (t >> 24) & 0xff; 789 buf[5] = 0; 790 791 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) { 792 aprint_error_dev(sc->sc_dev, 793 "%s: failed to acquire I2C bus: %d\n", 794 __func__, error); 795 return 0; 796 } 797 798 error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address, 799 &buf, buflen, NULL, 0, 0); 800 801 /* Done with I2C */ 802 iic_release_bus(sc->sc_tag, 0); 803 804 /* send data */ 805 if (error != 0) { 806 aprint_error_dev(sc->sc_dev, 807 "%s: failed to set time: %d\n", 808 __func__, error); 809 return 0; 810 } 811 812 return 1; 813} 814 815static int 816dsrtc_read_temp(struct dsrtc_softc *sc, uint32_t *temp) 817{ 818 int error, tc; 819 uint8_t reg = DS3232_TEMP_MSB; 820 uint8_t buf[2]; 821 822 if ((sc->sc_model.dm_flags & DSRTC_FLAG_TEMP) == 0) 823 return ENOTSUP; 824 825 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) { 826 aprint_error_dev(sc->sc_dev, 827 "%s: failed to acquire I2C bus: %d\n", 828 __func__, error); 829 return 0; 830 } 831 832 /* read temperature registers: */ 833 error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address, 834 ®, 1, buf, 2, 0); 835 836 /* Done with I2C */ 837 iic_release_bus(sc->sc_tag, 0); 838 839 if (error != 0) { 840 aprint_error_dev(sc->sc_dev, 841 "%s: failed to read temperature: %d\n", 842 __func__, error); 843 return 0; 844 } 845 846 /* convert to microkelvin */ 847 tc = buf[0] * 1000000 + (buf[1] >> 6) * 250000; 848 *temp = tc + 273150000; 849 return 1; 850} 851 852static void 853dsrtc_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 854{ 855 struct dsrtc_softc *sc = sme->sme_cookie; 856 uint32_t temp = 0; /* XXX gcc */ 857 858 if (dsrtc_read_temp(sc, &temp) == 0) { 859 edata->state = ENVSYS_SINVALID; 860 return; 861 } 862 863 edata->value_cur = temp; 864 865 edata->state = ENVSYS_SVALID; 866} 867