arasan_sdhc_fdt.c revision 1.11 
1/* $NetBSD: arasan_sdhc_fdt.c,v 1.11 2022/10/26 20:54:52 jmcneill Exp $ */
2
3/*-
4 * Copyright (c) 2019 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
30__KERNEL_RCSID(0, "$NetBSD: arasan_sdhc_fdt.c,v 1.11 2022/10/26 20:54:52 jmcneill Exp $");
31
32#include <sys/param.h>
33#include <sys/bus.h>
34#include <sys/device.h>
35#include <sys/systm.h>
36#include <sys/sysctl.h>
37#include <sys/kmem.h>
38
39#include <dev/sdmmc/sdhcreg.h>
40#include <dev/sdmmc/sdhcvar.h>
41#include <dev/sdmmc/sdmmcvar.h>
42
43#include <dev/clk/clk_backend.h>
44
45#include <dev/fdt/fdtvar.h>
46#include <dev/fdt/syscon.h>
47
48#define	RK3399_GRF_EMMCCORE_CON0	0xf000
49#define	 RK3399_CORECFG_BASECLKFREQ		__BITS(15,8)
50#define	 RK3399_CORECFG_TIMEOUTCLKUNIT		__BIT(7)
51#define	 RK3399_CORECFG_TUNINGCOUNT		__BITS(5,0)
52#define	RK3399_GRF_EMMCCORE_CON11	0xf02c
53#define	 RK3399_CORECFG_CLOCKMULTIPLIER		__BITS(7,0)
54
55enum arasan_sdhc_type {
56	AS_TYPE_GENERIC = 0,
57	AS_TYPE_RK3399 = 1,
58};
59
60struct arasan_sdhc_softc {
61	struct sdhc_softc	sc_base;
62	struct sdhc_host	*sc_host[1];
63	bus_space_tag_t		sc_bst;
64	bus_space_handle_t	sc_bsh;
65	bus_size_t		sc_bsz;
66	int			sc_phandle;
67	struct fdtbus_phy	*sc_phy;
68	struct syscon		*sc_syscon;
69	struct clk		*sc_clk_xin;
70	struct clk		*sc_clk_ahb;
71	enum arasan_sdhc_type	sc_type;
72	struct clk_domain	sc_clkdom;
73	struct clk		sc_clk_card;
74};
75
76static const struct device_compatible_entry compat_data[] = {
77	{ .compat = "rockchip,rk3399-sdhci-5.1",
78	  .value = AS_TYPE_RK3399 },
79
80	{ .compat = "arasan,sdhci-8.9a",
81	  .value = AS_TYPE_GENERIC },
82
83	DEVICE_COMPAT_EOL
84};
85
86static const struct device_compatible_entry sdhci_5_1_compat[] = {
87	{ .compat = "arasan,sdhci-5.1" },
88	DEVICE_COMPAT_EOL
89};
90
91static struct clk *
92arasan_sdhc_clk_decode(device_t dev, int cc_phandle, const void *data, size_t len)
93{
94	struct arasan_sdhc_softc * const sc = device_private(dev);
95
96	if (len != 0)
97		return NULL;
98
99	return &sc->sc_clk_card;
100}
101
102static const struct fdtbus_clock_controller_func arasan_sdhc_fdt_clk_funcs = {
103	.decode = arasan_sdhc_clk_decode,
104};
105
106static struct clk *
107arasan_sdhc_clk_get(void *priv, const char *name)
108{
109	struct arasan_sdhc_softc * const sc = priv;
110
111	if (strcmp(name, sc->sc_clk_card.name) != 0)
112		return NULL;
113
114	return &sc->sc_clk_card;
115}
116
117static u_int
118arasan_sdhc_clk_get_rate(void *priv, struct clk *clk)
119{
120	struct arasan_sdhc_softc * const sc = priv;
121
122	return clk_get_rate(sc->sc_clk_xin);
123}
124
125static const struct clk_funcs arasan_sdhc_clk_funcs = {
126	.get = arasan_sdhc_clk_get,
127	.get_rate = arasan_sdhc_clk_get_rate,
128};
129
130static int
131arasan_sdhc_signal_voltage(struct sdhc_softc *sdhc, int signal_voltage)
132{
133	if (signal_voltage == SDMMC_SIGNAL_VOLTAGE_180)
134		return 0;
135
136	return EINVAL;
137}
138
139static int
140arasan_sdhc_bus_clock_pre(struct sdhc_softc *sdhc, int freq)
141{
142	struct arasan_sdhc_softc * const sc = device_private(sdhc->sc_dev);
143	int error;
144
145	if (sc->sc_phy != NULL) {
146		error = fdtbus_phy_enable(sc->sc_phy, false);
147		if (error != 0)
148			return error;
149	}
150
151	return 0;
152}
153
154static int
155arasan_sdhc_bus_clock_post(struct sdhc_softc *sdhc, int freq)
156{
157	struct arasan_sdhc_softc * const sc = device_private(sdhc->sc_dev);
158	int error;
159
160	if (sc->sc_phy != NULL) {
161		error = fdtbus_phy_enable(sc->sc_phy, true);
162		if (error != 0)
163			return error;
164	}
165
166	return 0;
167}
168
169static void
170arasan_sdhc_init_rk3399(struct arasan_sdhc_softc *sc)
171{
172	uint32_t mask, val;
173
174	if (sc->sc_syscon == NULL)
175		return;
176
177	syscon_lock(sc->sc_syscon);
178
179	/* Disable clock multiplier */
180	mask = RK3399_CORECFG_CLOCKMULTIPLIER;
181	val = 0;
182	syscon_write_4(sc->sc_syscon, RK3399_GRF_EMMCCORE_CON11, (mask << 16) | val);
183
184	/* Set base clock frequency */
185	const u_int xin_rate = clk_get_rate(sc->sc_clk_xin);
186	mask = RK3399_CORECFG_BASECLKFREQ;
187	val = __SHIFTIN((xin_rate + (1000000 / 2)) / 1000000, RK3399_CORECFG_BASECLKFREQ);
188	syscon_write_4(sc->sc_syscon, RK3399_GRF_EMMCCORE_CON0, (mask << 16) | val);
189
190	syscon_unlock(sc->sc_syscon);
191}
192
193static void
194arasan_sdhc_init(device_t dev)
195{
196	struct arasan_sdhc_softc * const sc = device_private(dev);
197	int error;
198
199	if (sc->sc_type == AS_TYPE_RK3399)
200		arasan_sdhc_init_rk3399(sc);
201
202	if (of_compatible_match(sc->sc_phandle, sdhci_5_1_compat)) {
203		sc->sc_phy = fdtbus_phy_get(sc->sc_phandle, "phy_arasan");
204		if (sc->sc_phy == NULL) {
205			aprint_error_dev(dev, "couldn't get PHY\n");
206			return;
207		}
208		sc->sc_base.sc_vendor_signal_voltage = arasan_sdhc_signal_voltage;
209	}
210
211	error = sdhc_host_found(&sc->sc_base, sc->sc_bst, sc->sc_bsh, sc->sc_bsz);
212	if (error != 0) {
213		aprint_error_dev(dev, "couldn't initialize host, error = %d\n", error);
214		return;
215	}
216}
217
218static int
219arasan_sdhc_match(device_t parent, cfdata_t cf, void *aux)
220{
221	struct fdt_attach_args * const faa = aux;
222
223	return of_compatible_match(faa->faa_phandle, compat_data);
224}
225
226static void
227arasan_sdhc_attach(device_t parent, device_t self, void *aux)
228{
229	struct arasan_sdhc_softc * const sc = device_private(self);
230	struct fdt_attach_args * const faa = aux;
231	const int phandle = faa->faa_phandle;
232	char intrstr[128];
233	const char *clkname;
234	bus_addr_t addr;
235	bus_size_t size;
236	u_int bus_width;
237	void *ih;
238
239	fdtbus_clock_assign(phandle);
240
241	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
242		aprint_error(": couldn't get registers\n");
243		return;
244	}
245
246	if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
247		aprint_error(": couldn't decode interrupt\n");
248		return;
249	}
250
251	sc->sc_clk_xin = fdtbus_clock_get(phandle, "clk_xin");
252	sc->sc_clk_ahb = fdtbus_clock_get(phandle, "clk_ahb");
253	if (sc->sc_clk_xin == NULL || sc->sc_clk_ahb == NULL) {
254		aprint_error(": couldn't get clocks\n");
255		return;
256	}
257	if (clk_enable(sc->sc_clk_xin) != 0 || clk_enable(sc->sc_clk_ahb) != 0) {
258		aprint_error(": couldn't enable clocks\n");
259		return;
260	}
261
262	sc->sc_syscon = fdtbus_syscon_acquire(phandle, "arasan,soc-ctl-syscon");
263
264	if (of_getprop_uint32(phandle, "bus-width", &bus_width) != 0)
265		bus_width = 4;
266
267	sc->sc_phandle = phandle;
268	sc->sc_bst = faa->faa_bst;
269	if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
270		aprint_error(": couldn't map registers\n");
271		return;
272	}
273	sc->sc_bsz = size;
274	sc->sc_type = of_compatible_lookup(phandle, compat_data)->value;
275
276#ifdef _LP64
277	const uint32_t caps = bus_space_read_4(sc->sc_bst, sc->sc_bsh, SDHC_CAPABILITIES);
278	if ((caps & (SDHC_ADMA2_SUPP|SDHC_64BIT_SYS_BUS)) == SDHC_ADMA2_SUPP) {
279		int error = bus_dmatag_subregion(faa->faa_dmat, 0, __MASK(32),
280		    &sc->sc_base.sc_dmat, BUS_DMA_WAITOK);
281		if (error != 0) {
282			aprint_error(": couldn't create DMA tag: %d\n", error);
283			return;
284		}
285	} else {
286		sc->sc_base.sc_dmat = faa->faa_dmat;
287	}
288#else
289	sc->sc_base.sc_dmat = faa->faa_dmat;
290#endif
291
292	sc->sc_base.sc_dev = self;
293	sc->sc_base.sc_host = sc->sc_host;
294	sc->sc_base.sc_flags = SDHC_FLAG_NO_CLKBASE |
295			       SDHC_FLAG_SINGLE_POWER_WRITE |
296			       SDHC_FLAG_32BIT_ACCESS |
297			       SDHC_FLAG_USE_DMA |
298			       SDHC_FLAG_STOP_WITH_TC;
299	if (bus_width == 8)
300		sc->sc_base.sc_flags |= SDHC_FLAG_8BIT_MODE;
301	sc->sc_base.sc_clkbase = clk_get_rate(sc->sc_clk_xin) / 1000;
302	sc->sc_base.sc_vendor_bus_clock = arasan_sdhc_bus_clock_pre;
303	sc->sc_base.sc_vendor_bus_clock_post = arasan_sdhc_bus_clock_post;
304
305	aprint_naive("\n");
306	aprint_normal(": Arasan SDHCI controller\n");
307
308	clkname = fdtbus_get_string(phandle, "clock-output-names");
309	if (clkname == NULL)
310		clkname = faa->faa_name;
311
312	sc->sc_clkdom.name = device_xname(self);
313	sc->sc_clkdom.funcs = &arasan_sdhc_clk_funcs;
314	sc->sc_clkdom.priv = sc;
315	sc->sc_clk_card.domain = &sc->sc_clkdom;
316	sc->sc_clk_card.name = kmem_asprintf("%s", clkname);
317	clk_attach(&sc->sc_clk_card);
318
319	fdtbus_register_clock_controller(self, phandle, &arasan_sdhc_fdt_clk_funcs);
320
321	ih = fdtbus_intr_establish_xname(phandle, 0, IPL_SDMMC, 0,
322	    sdhc_intr, &sc->sc_base, device_xname(self));
323	if (ih == NULL) {
324		aprint_error_dev(self, "couldn't establish interrupt on %s\n", intrstr);
325		return;
326	}
327	aprint_normal_dev(self, "interrupting on %s\n", intrstr);
328
329	arasan_sdhc_init(self);
330}
331
332CFATTACH_DECL_NEW(arasan_sdhc_fdt, sizeof(struct arasan_sdhc_softc),
333	arasan_sdhc_match, arasan_sdhc_attach, NULL, NULL);
334