ahbreg.h revision 1.1 
1typedef u_long physaddr;
2typedef u_long physlen;
3
4/*
5 * AHA1740 EISA board mode registers (Offset from slot base)
6 */
7#define PORTADDR	0xCC0
8#define	 PORTADDR_ENHANCED	0x80
9#define BIOSADDR	0xCC1
10#define	INTDEF		0xCC2
11#define	SCSIDEF		0xCC3
12#define	BUSDEF		0xCC4
13#define	RESV0		0xCC5
14#define	RESV1		0xCC6
15#define	RESV2		0xCC7
16/**** bit definitions for INTDEF ****/
17#define	INT9	0x00
18#define	INT10	0x01
19#define	INT11	0x02
20#define	INT12	0x03
21#define	INT14	0x05
22#define	INT15	0x06
23#define INTHIGH 0x08		/* int high=ACTIVE (else edge) */
24#define	INTEN	0x10
25/**** bit definitions for SCSIDEF ****/
26#define	HSCSIID	0x0F		/* our SCSI ID */
27#define	RSTPWR	0x10		/* reset scsi bus on power up or reset */
28/**** bit definitions for BUSDEF ****/
29#define	B0uS	0x00		/* give up bus immediatly */
30#define	B4uS	0x01		/* delay 4uSec. */
31#define	B8uS	0x02
32
33/*
34 * AHA1740 ENHANCED mode mailbox control regs (Offset from slot base)
35 */
36#define MBOXOUT0	0xCD0
37#define MBOXOUT1	0xCD1
38#define MBOXOUT2	0xCD2
39#define MBOXOUT3	0xCD3
40
41#define	ATTN		0xCD4
42#define	G2CNTRL		0xCD5
43#define	G2INTST		0xCD6
44#define G2STAT		0xCD7
45
46#define	MBOXIN0		0xCD8
47#define	MBOXIN1		0xCD9
48#define	MBOXIN2		0xCDA
49#define	MBOXIN3		0xCDB
50
51#define G2STAT2		0xCDC
52
53/*
54 * Bit definitions for the 5 control/status registers
55 */
56#define	ATTN_TARGET		0x0F
57#define	ATTN_OPCODE		0xF0
58#define  OP_IMMED		0x10
59#define	  AHB_TARG_RESET	0x80
60#define  OP_START_ECB		0x40
61#define  OP_ABORT_ECB		0x50
62
63#define	G2CNTRL_SET_HOST_READY	0x20
64#define	G2CNTRL_CLEAR_EISA_INT	0x40
65#define	G2CNTRL_HARD_RESET	0x80
66
67#define	G2INTST_TARGET		0x0F
68#define	G2INTST_INT_STAT	0xF0
69#define	 AHB_ECB_OK		0x10
70#define	 AHB_ECB_RECOVERED	0x50
71#define	 AHB_HW_ERR		0x70
72#define	 AHB_IMMED_OK		0xA0
73#define	 AHB_ECB_ERR		0xC0
74#define	 AHB_ASN		0xD0	/* for target mode */
75#define	 AHB_IMMED_ERR		0xE0
76
77#define	G2STAT_BUSY		0x01
78#define	G2STAT_INT_PEND		0x02
79#define	G2STAT_MBOX_EMPTY	0x04
80
81#define	G2STAT2_HOST_READY	0x01
82
83#define	AHB_NSEG	33	/* number of dma segments supported */
84
85struct ahb_dma_seg {
86	physaddr seg_addr;
87	physlen seg_len;
88};
89
90struct ahb_ecb_status {
91	u_short status;
92#define	ST_DON	0x0001
93#define	ST_DU	0x0002
94#define	ST_QF	0x0008
95#define	ST_SC	0x0010
96#define	ST_DO	0x0020
97#define	ST_CH	0x0040
98#define	ST_INT	0x0080
99#define	ST_ASA	0x0100
100#define	ST_SNS	0x0200
101#define	ST_INI	0x0800
102#define	ST_ME	0x1000
103#define	ST_ECA	0x4000
104	u_char  host_stat;
105#define	HS_OK			0x00
106#define	HS_CMD_ABORTED_HOST	0x04
107#define	HS_CMD_ABORTED_ADAPTER	0x05
108#define	HS_TIMED_OUT		0x11
109#define	HS_HARDWARE_ERR		0x20
110#define	HS_SCSI_RESET_ADAPTER	0x22
111#define	HS_SCSI_RESET_INCOMING	0x23
112	u_char  target_stat;
113	u_long  resid_count;
114	u_long  resid_addr;
115	u_short addit_status;
116	u_char  sense_len;
117	u_char  unused[9];
118	u_char  cdb[6];
119};
120
121struct ahb_ecb {
122	u_char  opcode;
123#define	ECB_SCSI_OP	0x01
124	        u_char:4;
125	u_char  options:3;
126	        u_char:1;
127	short   opt1;
128#define	ECB_CNE	0x0001
129#define	ECB_DI	0x0080
130#define	ECB_SES	0x0400
131#define	ECB_S_G	0x1000
132#define	ECB_DSB	0x4000
133#define	ECB_ARS	0x8000
134	short   opt2;
135#define	ECB_LUN	0x0007
136#define	ECB_TAG	0x0008
137#define	ECB_TT	0x0030
138#define	ECB_ND	0x0040
139#define	ECB_DAT	0x0100
140#define	ECB_DIR	0x0200
141#define	ECB_ST	0x0400
142#define	ECB_CHK	0x0800
143#define	ECB_REC	0x4000
144#define	ECB_NRB	0x8000
145	u_short unused1;
146	physaddr data_addr;
147	physlen  data_length;
148	physaddr status;
149	physaddr link_addr;
150	short   unused2;
151	short   unused3;
152	physaddr sense_ptr;
153	u_char  req_sense_length;
154	u_char  scsi_cmd_length;
155	short   cksum;
156	struct scsi_generic scsi_cmd;
157
158	struct ahb_dma_seg ahb_dma[AHB_NSEG];
159	struct ahb_ecb_status ecb_status;
160	struct scsi_sense_data ecb_sense;
161	/*-----------------end of hardware supported fields----------------*/
162	TAILQ_ENTRY(ahb_ecb) chain;
163	struct ahb_ecb *nexthash;
164	long hashkey;
165	struct scsi_xfer *xs;	/* the scsi_xfer for this cmd */
166	int flags;
167#define	ECB_ALLOC	0x01
168#define	ECB_ABORT	0x02
169#define	ECB_IMMED	0x04
170#define	ECB_IMMED_FAIL	0x08
171	int timeout;
172};
173