acpi_cpu_cstate.c revision 1.45 
1/* $NetBSD: acpi_cpu_cstate.c,v 1.45 2011/02/25 12:08:35 jruoho Exp $ */
2
3/*-
4 * Copyright (c) 2010, 2011 Jukka Ruohonen <jruohonen@iki.fi>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29#include <sys/cdefs.h>
30__KERNEL_RCSID(0, "$NetBSD: acpi_cpu_cstate.c,v 1.45 2011/02/25 12:08:35 jruoho Exp $");
31
32#include <sys/param.h>
33#include <sys/cpu.h>
34#include <sys/device.h>
35#include <sys/evcnt.h>
36#include <sys/kernel.h>
37#include <sys/once.h>
38#include <sys/mutex.h>
39#include <sys/timetc.h>
40
41#include <dev/acpi/acpireg.h>
42#include <dev/acpi/acpivar.h>
43#include <dev/acpi/acpi_cpu.h>
44#include <dev/acpi/acpi_timer.h>
45
46#include <machine/acpi_machdep.h>
47
48#define _COMPONENT	 ACPI_BUS_COMPONENT
49ACPI_MODULE_NAME	 ("acpi_cpu_cstate")
50
51static void		 acpicpu_cstate_attach_print(struct acpicpu_softc *);
52static void		 acpicpu_cstate_attach_evcnt(struct acpicpu_softc *);
53static void		 acpicpu_cstate_detach_evcnt(struct acpicpu_softc *);
54static ACPI_STATUS	 acpicpu_cstate_cst(struct acpicpu_softc *);
55static ACPI_STATUS	 acpicpu_cstate_cst_add(struct acpicpu_softc *,
56						ACPI_OBJECT *, int );
57static void		 acpicpu_cstate_cst_bios(void);
58static void		 acpicpu_cstate_memset(struct acpicpu_softc *);
59static void		 acpicpu_cstate_fadt(struct acpicpu_softc *);
60static void		 acpicpu_cstate_quirks(struct acpicpu_softc *);
61static int		 acpicpu_cstate_latency(struct acpicpu_softc *);
62static bool		 acpicpu_cstate_bm_check(void);
63static void		 acpicpu_cstate_idle_enter(struct acpicpu_softc *,int);
64
65extern struct acpicpu_softc **acpicpu_sc;
66
67/*
68 * XXX:	The local APIC timer (as well as TSC) is typically stopped in C3.
69 *	For now, we cannot but disable C3. But there appears to be timer-
70 *	related interrupt issues also in C2. The only entirely safe option
71 *	at the moment is to use C1.
72 */
73#ifdef ACPICPU_ENABLE_C3
74static int cs_state_max = ACPI_STATE_C3;
75#else
76static int cs_state_max = ACPI_STATE_C1;
77#endif
78
79void
80acpicpu_cstate_attach(device_t self)
81{
82	struct acpicpu_softc *sc = device_private(self);
83	ACPI_STATUS rv;
84
85	/*
86	 * Either use the preferred _CST or resort to FADT.
87	 */
88	rv = acpicpu_cstate_cst(sc);
89
90	switch (rv) {
91
92	case AE_OK:
93		acpicpu_cstate_cst_bios();
94		break;
95
96	default:
97		sc->sc_flags |= ACPICPU_FLAG_C_FADT;
98		acpicpu_cstate_fadt(sc);
99		break;
100	}
101
102	sc->sc_flags |= ACPICPU_FLAG_C;
103
104	acpicpu_cstate_quirks(sc);
105	acpicpu_cstate_attach_evcnt(sc);
106	acpicpu_cstate_attach_print(sc);
107}
108
109void
110acpicpu_cstate_attach_print(struct acpicpu_softc *sc)
111{
112	struct acpicpu_cstate *cs;
113	static bool once = false;
114	const char *str;
115	int i;
116
117	if (once != false)
118		return;
119
120	for (i = 0; i < ACPI_C_STATE_COUNT; i++) {
121
122		cs = &sc->sc_cstate[i];
123
124		if (cs->cs_method == 0)
125			continue;
126
127		switch (cs->cs_method) {
128
129		case ACPICPU_C_STATE_HALT:
130			str = "HLT";
131			break;
132
133		case ACPICPU_C_STATE_FFH:
134			str = "FFH";
135			break;
136
137		case ACPICPU_C_STATE_SYSIO:
138			str = "I/O";
139			break;
140
141		default:
142			panic("NOTREACHED");
143		}
144
145		aprint_verbose_dev(sc->sc_dev, "C%d: %3s, "
146		    "lat %3u us, pow %5u mW, flags 0x%02x\n", i, str,
147		    cs->cs_latency, cs->cs_power, cs->cs_flags);
148	}
149
150	once = true;
151}
152
153static void
154acpicpu_cstate_attach_evcnt(struct acpicpu_softc *sc)
155{
156	struct acpicpu_cstate *cs;
157	const char *str;
158	int i;
159
160	for (i = 0; i < ACPI_C_STATE_COUNT; i++) {
161
162		cs = &sc->sc_cstate[i];
163
164		if (cs->cs_method == 0)
165			continue;
166
167		str = "HALT";
168
169		if (cs->cs_method == ACPICPU_C_STATE_FFH)
170			str = "MWAIT";
171
172		if (cs->cs_method == ACPICPU_C_STATE_SYSIO)
173			str = "I/O";
174
175		(void)snprintf(cs->cs_name, sizeof(cs->cs_name),
176		    "C%d (%s)", i, str);
177
178		evcnt_attach_dynamic(&cs->cs_evcnt, EVCNT_TYPE_MISC,
179		    NULL, device_xname(sc->sc_dev), cs->cs_name);
180	}
181}
182
183int
184acpicpu_cstate_detach(device_t self)
185{
186	struct acpicpu_softc *sc = device_private(self);
187	static ONCE_DECL(once_detach);
188	int rv;
189
190	rv = RUN_ONCE(&once_detach, acpicpu_md_cstate_stop);
191
192	if (rv != 0)
193		return rv;
194
195	sc->sc_flags &= ~ACPICPU_FLAG_C;
196	acpicpu_cstate_detach_evcnt(sc);
197
198	return 0;
199}
200
201static void
202acpicpu_cstate_detach_evcnt(struct acpicpu_softc *sc)
203{
204	struct acpicpu_cstate *cs;
205	int i;
206
207	for (i = 0; i < ACPI_C_STATE_COUNT; i++) {
208
209		cs = &sc->sc_cstate[i];
210
211		if (cs->cs_method != 0)
212			evcnt_detach(&cs->cs_evcnt);
213	}
214}
215
216void
217acpicpu_cstate_start(device_t self)
218{
219	struct acpicpu_softc *sc = device_private(self);
220
221	(void)acpicpu_md_cstate_start(sc);
222}
223
224bool
225acpicpu_cstate_suspend(device_t self)
226{
227	return true;
228}
229
230bool
231acpicpu_cstate_resume(device_t self)
232{
233	static const ACPI_OSD_EXEC_CALLBACK func = acpicpu_cstate_callback;
234	struct acpicpu_softc *sc = device_private(self);
235
236	if ((sc->sc_flags & ACPICPU_FLAG_C_FADT) == 0)
237		(void)AcpiOsExecute(OSL_NOTIFY_HANDLER, func, sc->sc_dev);
238
239	return true;
240}
241
242void
243acpicpu_cstate_callback(void *aux)
244{
245	struct acpicpu_softc *sc;
246	device_t self = aux;
247
248	sc = device_private(self);
249
250	if ((sc->sc_flags & ACPICPU_FLAG_C_FADT) != 0)
251		return;
252
253	mutex_enter(&sc->sc_mtx);
254	(void)acpicpu_cstate_cst(sc);
255	mutex_exit(&sc->sc_mtx);
256}
257
258static ACPI_STATUS
259acpicpu_cstate_cst(struct acpicpu_softc *sc)
260{
261	ACPI_OBJECT *elm, *obj;
262	ACPI_BUFFER buf;
263	ACPI_STATUS rv;
264	uint32_t i, n;
265	uint8_t count;
266
267	rv = acpi_eval_struct(sc->sc_node->ad_handle, "_CST", &buf);
268
269	if (ACPI_FAILURE(rv))
270		return rv;
271
272	obj = buf.Pointer;
273
274	if (obj->Type != ACPI_TYPE_PACKAGE) {
275		rv = AE_TYPE;
276		goto out;
277	}
278
279	if (obj->Package.Count < 2) {
280		rv = AE_LIMIT;
281		goto out;
282	}
283
284	elm = obj->Package.Elements;
285
286	if (elm[0].Type != ACPI_TYPE_INTEGER) {
287		rv = AE_TYPE;
288		goto out;
289	}
290
291	n = elm[0].Integer.Value;
292
293	if (n != obj->Package.Count - 1) {
294		rv = AE_BAD_VALUE;
295		goto out;
296	}
297
298	if (n > ACPI_C_STATES_MAX) {
299		rv = AE_LIMIT;
300		goto out;
301	}
302
303	acpicpu_cstate_memset(sc);
304
305	CTASSERT(ACPI_STATE_C0 == 0 && ACPI_STATE_C1 == 1);
306	CTASSERT(ACPI_STATE_C2 == 2 && ACPI_STATE_C3 == 3);
307
308	for (count = 0, i = 1; i <= n; i++) {
309
310		elm = &obj->Package.Elements[i];
311		rv = acpicpu_cstate_cst_add(sc, elm, i);
312
313		if (ACPI_SUCCESS(rv))
314			count++;
315	}
316
317	rv = (count != 0) ? AE_OK : AE_NOT_EXIST;
318
319out:
320	if (buf.Pointer != NULL)
321		ACPI_FREE(buf.Pointer);
322
323	return rv;
324}
325
326static ACPI_STATUS
327acpicpu_cstate_cst_add(struct acpicpu_softc *sc, ACPI_OBJECT *elm, int i)
328{
329	struct acpicpu_cstate *cs = sc->sc_cstate;
330	struct acpicpu_cstate state;
331	struct acpicpu_reg *reg;
332	ACPI_STATUS rv = AE_OK;
333	ACPI_OBJECT *obj;
334	uint32_t type;
335
336	(void)memset(&state, 0, sizeof(*cs));
337
338	state.cs_flags = ACPICPU_FLAG_C_BM_STS;
339
340	if (elm->Type != ACPI_TYPE_PACKAGE) {
341		rv = AE_TYPE;
342		goto out;
343	}
344
345	if (elm->Package.Count != 4) {
346		rv = AE_LIMIT;
347		goto out;
348	}
349
350	/*
351	 * Type.
352	 */
353	obj = &elm->Package.Elements[1];
354
355	if (obj->Type != ACPI_TYPE_INTEGER) {
356		rv = AE_TYPE;
357		goto out;
358	}
359
360	type = obj->Integer.Value;
361
362	if (type < ACPI_STATE_C1 || type > ACPI_STATE_C3) {
363		rv = AE_TYPE;
364		goto out;
365	}
366
367	/*
368	 * Latency.
369	 */
370	obj = &elm->Package.Elements[2];
371
372	if (obj->Type != ACPI_TYPE_INTEGER) {
373		rv = AE_TYPE;
374		goto out;
375	}
376
377	state.cs_latency = obj->Integer.Value;
378
379	/*
380	 * Power.
381	 */
382	obj = &elm->Package.Elements[3];
383
384	if (obj->Type != ACPI_TYPE_INTEGER) {
385		rv = AE_TYPE;
386		goto out;
387	}
388
389	state.cs_power = obj->Integer.Value;
390
391	/*
392	 * Register.
393	 */
394	obj = &elm->Package.Elements[0];
395
396	if (obj->Type != ACPI_TYPE_BUFFER) {
397		rv = AE_TYPE;
398		goto out;
399	}
400
401	CTASSERT(sizeof(struct acpicpu_reg) == 15);
402
403	if (obj->Buffer.Length < sizeof(struct acpicpu_reg)) {
404		rv = AE_LIMIT;
405		goto out;
406	}
407
408	reg = (struct acpicpu_reg *)obj->Buffer.Pointer;
409
410	switch (reg->reg_spaceid) {
411
412	case ACPI_ADR_SPACE_SYSTEM_IO:
413		state.cs_method = ACPICPU_C_STATE_SYSIO;
414
415		if (reg->reg_addr == 0) {
416			rv = AE_AML_ILLEGAL_ADDRESS;
417			goto out;
418		}
419
420		if (reg->reg_bitwidth != 8) {
421			rv = AE_AML_BAD_RESOURCE_LENGTH;
422			goto out;
423		}
424
425		state.cs_addr = reg->reg_addr;
426		break;
427
428	case ACPI_ADR_SPACE_FIXED_HARDWARE:
429		state.cs_method = ACPICPU_C_STATE_FFH;
430
431		switch (type) {
432
433		case ACPI_STATE_C1:
434
435			if ((sc->sc_flags & ACPICPU_FLAG_C_FFH) == 0)
436				state.cs_method = ACPICPU_C_STATE_HALT;
437
438			break;
439
440		default:
441
442			if ((sc->sc_flags & ACPICPU_FLAG_C_FFH) == 0) {
443				rv = AE_SUPPORT;
444				goto out;
445			}
446		}
447
448		if (sc->sc_cap != 0) {
449
450			/*
451			 * The _CST FFH GAS encoding may contain
452			 * additional hints on Intel processors.
453			 * Use these to determine whether we can
454			 * avoid the bus master activity check.
455			 */
456			if ((reg->reg_accesssize & ACPICPU_PDC_GAS_BM) == 0)
457				state.cs_flags &= ~ACPICPU_FLAG_C_BM_STS;
458		}
459
460		break;
461
462	default:
463		rv = AE_AML_INVALID_SPACE_ID;
464		goto out;
465	}
466
467	/*
468	 * As some systems define the type arbitrarily,
469	 * we use a sequential counter instead of the
470	 * BIOS data. For instance, AMD family 14h is
471	 * instructed to only use the value 2; see
472	 *
473	 *	Advanced Micro Devices: BIOS and Kernel
474	 *	Developer's Guide (BKDG) for AMD Family
475	 *	14h Models 00h-0Fh Processors. Revision
476	 *	3.00, January 4, 2011.
477	 */
478	if (i != (int)type) {
479
480		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
481			"C%d != C%u from BIOS", i, type));
482	}
483
484	KASSERT(cs[i].cs_method == 0);
485
486	cs[i].cs_addr = state.cs_addr;
487	cs[i].cs_power = state.cs_power;
488	cs[i].cs_flags = state.cs_flags;
489	cs[i].cs_method = state.cs_method;
490	cs[i].cs_latency = state.cs_latency;
491
492out:
493	if (ACPI_FAILURE(rv))
494		aprint_error_dev(sc->sc_dev, "failed to add "
495		    "C-state: %s\n", AcpiFormatException(rv));
496
497	i++;
498
499	return rv;
500}
501
502static void
503acpicpu_cstate_cst_bios(void)
504{
505	const uint8_t val = AcpiGbl_FADT.CstControl;
506	const uint32_t addr = AcpiGbl_FADT.SmiCommand;
507
508	if (addr == 0 || val == 0)
509		return;
510
511	(void)AcpiOsWritePort(addr, val, 8);
512}
513
514static void
515acpicpu_cstate_memset(struct acpicpu_softc *sc)
516{
517	int i = 0;
518
519	while (i < ACPI_C_STATE_COUNT) {
520
521		sc->sc_cstate[i].cs_addr = 0;
522		sc->sc_cstate[i].cs_power = 0;
523		sc->sc_cstate[i].cs_flags = 0;
524		sc->sc_cstate[i].cs_method = 0;
525		sc->sc_cstate[i].cs_latency = 0;
526
527		i++;
528	}
529}
530
531static void
532acpicpu_cstate_fadt(struct acpicpu_softc *sc)
533{
534	struct acpicpu_cstate *cs = sc->sc_cstate;
535
536	acpicpu_cstate_memset(sc);
537
538	/*
539	 * All x86 processors should support C1 (a.k.a. HALT).
540	 */
541	cs[ACPI_STATE_C1].cs_method = ACPICPU_C_STATE_HALT;
542
543	if ((AcpiGbl_FADT.Flags & ACPI_FADT_C1_SUPPORTED) == 0)
544		aprint_debug_dev(sc->sc_dev, "HALT not supported?\n");
545
546	if (sc->sc_object.ao_pblkaddr == 0)
547		return;
548
549	if (acpi_md_ncpus() > 1) {
550
551		if ((AcpiGbl_FADT.Flags & ACPI_FADT_C2_MP_SUPPORTED) == 0)
552			return;
553	}
554
555	cs[ACPI_STATE_C2].cs_method = ACPICPU_C_STATE_SYSIO;
556	cs[ACPI_STATE_C3].cs_method = ACPICPU_C_STATE_SYSIO;
557
558	cs[ACPI_STATE_C2].cs_latency = AcpiGbl_FADT.C2Latency;
559	cs[ACPI_STATE_C3].cs_latency = AcpiGbl_FADT.C3Latency;
560
561	cs[ACPI_STATE_C2].cs_addr = sc->sc_object.ao_pblkaddr + 4;
562	cs[ACPI_STATE_C3].cs_addr = sc->sc_object.ao_pblkaddr + 5;
563
564	/*
565	 * The P_BLK length should always be 6. If it
566	 * is not, reduce functionality accordingly.
567	 */
568	if (sc->sc_object.ao_pblklen < 5)
569		cs[ACPI_STATE_C2].cs_method = 0;
570
571	if (sc->sc_object.ao_pblklen < 6)
572		cs[ACPI_STATE_C3].cs_method = 0;
573
574	/*
575	 * Sanity check the latency levels in FADT.
576	 * Values above the thresholds are used to
577	 * inform that C-states are not supported.
578	 */
579	CTASSERT(ACPICPU_C_C2_LATENCY_MAX == 100);
580	CTASSERT(ACPICPU_C_C3_LATENCY_MAX == 1000);
581
582	if (AcpiGbl_FADT.C2Latency > ACPICPU_C_C2_LATENCY_MAX)
583		cs[ACPI_STATE_C2].cs_method = 0;
584
585	if (AcpiGbl_FADT.C3Latency > ACPICPU_C_C3_LATENCY_MAX)
586		cs[ACPI_STATE_C3].cs_method = 0;
587}
588
589static void
590acpicpu_cstate_quirks(struct acpicpu_softc *sc)
591{
592	const uint32_t reg = AcpiGbl_FADT.Pm2ControlBlock;
593	const uint32_t len = AcpiGbl_FADT.Pm2ControlLength;
594
595	/*
596	 * Disable C3 for PIIX4.
597	 */
598	if ((sc->sc_flags & ACPICPU_FLAG_PIIX4) != 0) {
599		sc->sc_cstate[ACPI_STATE_C3].cs_method = 0;
600		return;
601	}
602
603	/*
604	 * Check bus master arbitration. If ARB_DIS
605	 * is not available, processor caches must be
606	 * flushed before C3 (ACPI 4.0, section 8.2).
607	 */
608	if (reg != 0 && len != 0) {
609		sc->sc_flags |= ACPICPU_FLAG_C_ARB;
610		return;
611	}
612
613	/*
614	 * Disable C3 entirely if WBINVD is not present.
615	 */
616	if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD) == 0)
617		sc->sc_cstate[ACPI_STATE_C3].cs_method = 0;
618	else {
619		/*
620		 * If WBINVD is present and functioning properly,
621		 * flush all processor caches before entering C3.
622		 */
623		if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD_FLUSH) == 0)
624			sc->sc_flags &= ~ACPICPU_FLAG_C_BM;
625		else
626			sc->sc_cstate[ACPI_STATE_C3].cs_method = 0;
627	}
628}
629
630static int
631acpicpu_cstate_latency(struct acpicpu_softc *sc)
632{
633	static const uint32_t cs_factor = 3;
634	struct acpicpu_cstate *cs;
635	int i;
636
637	for (i = cs_state_max; i > 0; i--) {
638
639		cs = &sc->sc_cstate[i];
640
641		if (__predict_false(cs->cs_method == 0))
642			continue;
643
644		/*
645		 * Choose a state if we have previously slept
646		 * longer than the worst case latency of the
647		 * state times an arbitrary multiplier.
648		 */
649		if (sc->sc_cstate_sleep > cs->cs_latency * cs_factor)
650			return i;
651	}
652
653	return ACPI_STATE_C1;
654}
655
656/*
657 * The main idle loop.
658 */
659void
660acpicpu_cstate_idle(void)
661{
662	struct cpu_info *ci = curcpu();
663	struct acpicpu_softc *sc;
664	int state;
665
666	acpi_md_OsDisableInterrupt();
667
668	if (__predict_false(ci->ci_want_resched != 0))
669		goto out;
670
671	KASSERT(acpicpu_sc != NULL);
672	KASSERT(ci->ci_acpiid < maxcpus);
673
674	sc = acpicpu_sc[ci->ci_acpiid];
675
676	if (__predict_false(sc == NULL))
677		goto out;
678
679	KASSERT(ci->ci_ilevel == IPL_NONE);
680	KASSERT((sc->sc_flags & ACPICPU_FLAG_C) != 0);
681
682	if (__predict_false(sc->sc_cold != false))
683		goto out;
684
685	if (__predict_false(mutex_tryenter(&sc->sc_mtx) == 0))
686		goto out;
687
688	mutex_exit(&sc->sc_mtx);
689	state = acpicpu_cstate_latency(sc);
690
691	/*
692	 * Apply AMD C1E quirk.
693	 */
694	if ((sc->sc_flags & ACPICPU_FLAG_C_C1E) != 0)
695		acpicpu_md_quirk_c1e();
696
697	/*
698	 * Check for bus master activity. Note that particularly usb(4)
699	 * causes high activity, which may prevent the use of C3 states.
700	 */
701	if ((sc->sc_cstate[state].cs_flags & ACPICPU_FLAG_C_BM_STS) != 0) {
702
703		if (acpicpu_cstate_bm_check() != false)
704			state--;
705
706		if (__predict_false(sc->sc_cstate[state].cs_method == 0))
707			state = ACPI_STATE_C1;
708	}
709
710	KASSERT(state != ACPI_STATE_C0);
711
712	if (state != ACPI_STATE_C3) {
713		acpicpu_cstate_idle_enter(sc, state);
714		return;
715	}
716
717	/*
718	 * On all recent (Intel) CPUs caches are shared
719	 * by CPUs and bus master control is required to
720	 * keep these coherent while in C3. Flushing the
721	 * CPU caches is only the last resort.
722	 */
723	if ((sc->sc_flags & ACPICPU_FLAG_C_BM) == 0)
724		ACPI_FLUSH_CPU_CACHE();
725
726	/*
727	 * Allow the bus master to request that any given
728	 * CPU should return immediately to C0 from C3.
729	 */
730	if ((sc->sc_flags & ACPICPU_FLAG_C_BM) != 0)
731		(void)AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 1);
732
733	/*
734	 * It may be necessary to disable bus master arbitration
735	 * to ensure that bus master cycles do not occur while
736	 * sleeping in C3 (see ACPI 4.0, section 8.1.4).
737	 */
738	if ((sc->sc_flags & ACPICPU_FLAG_C_ARB) != 0)
739		(void)AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 1);
740
741	acpicpu_cstate_idle_enter(sc, state);
742
743	/*
744	 * Disable bus master wake and re-enable the arbiter.
745	 */
746	if ((sc->sc_flags & ACPICPU_FLAG_C_BM) != 0)
747		(void)AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0);
748
749	if ((sc->sc_flags & ACPICPU_FLAG_C_ARB) != 0)
750		(void)AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 0);
751
752	return;
753
754out:
755	acpi_md_OsEnableInterrupt();
756}
757
758static void
759acpicpu_cstate_idle_enter(struct acpicpu_softc *sc, int state)
760{
761	struct acpicpu_cstate *cs = &sc->sc_cstate[state];
762	uint32_t end, start, val;
763
764	start = acpitimer_read_fast(NULL);
765
766	switch (cs->cs_method) {
767
768	case ACPICPU_C_STATE_FFH:
769	case ACPICPU_C_STATE_HALT:
770		acpicpu_md_cstate_enter(cs->cs_method, state);
771		break;
772
773	case ACPICPU_C_STATE_SYSIO:
774		(void)AcpiOsReadPort(cs->cs_addr, &val, 8);
775		break;
776	}
777
778	acpi_md_OsEnableInterrupt();
779
780	cs->cs_evcnt.ev_count++;
781	end = acpitimer_read_fast(NULL);
782	sc->sc_cstate_sleep = hztoms(acpitimer_delta(end, start)) * 1000;
783}
784
785static bool
786acpicpu_cstate_bm_check(void)
787{
788	uint32_t val = 0;
789	ACPI_STATUS rv;
790
791	rv = AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, &val);
792
793	if (ACPI_FAILURE(rv) || val == 0)
794		return false;
795
796	(void)AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1);
797
798	return true;
799}
800