acpi_cpu_cstate.c revision 1.29
1/* $NetBSD: acpi_cpu_cstate.c,v 1.29 2010/08/16 17:58:42 jruoho Exp $ */ 2 3/*- 4 * Copyright (c) 2010 Jukka Ruohonen <jruohonen@iki.fi> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29#include <sys/cdefs.h> 30__KERNEL_RCSID(0, "$NetBSD: acpi_cpu_cstate.c,v 1.29 2010/08/16 17:58:42 jruoho Exp $"); 31 32#include <sys/param.h> 33#include <sys/cpu.h> 34#include <sys/device.h> 35#include <sys/evcnt.h> 36#include <sys/kernel.h> 37#include <sys/once.h> 38#include <sys/mutex.h> 39#include <sys/timetc.h> 40 41#include <dev/acpi/acpireg.h> 42#include <dev/acpi/acpivar.h> 43#include <dev/acpi/acpi_cpu.h> 44#include <dev/acpi/acpi_timer.h> 45 46#include <machine/acpi_machdep.h> 47 48#define _COMPONENT ACPI_BUS_COMPONENT 49ACPI_MODULE_NAME ("acpi_cpu_cstate") 50 51static void acpicpu_cstate_attach_print(struct acpicpu_softc *); 52static void acpicpu_cstate_attach_evcnt(struct acpicpu_softc *); 53static void acpicpu_cstate_detach_evcnt(struct acpicpu_softc *); 54static ACPI_STATUS acpicpu_cstate_cst(struct acpicpu_softc *); 55static ACPI_STATUS acpicpu_cstate_cst_add(struct acpicpu_softc *, 56 ACPI_OBJECT *); 57static void acpicpu_cstate_cst_bios(void); 58static void acpicpu_cstate_memset(struct acpicpu_softc *); 59static void acpicpu_cstate_fadt(struct acpicpu_softc *); 60static void acpicpu_cstate_quirks(struct acpicpu_softc *); 61static int acpicpu_cstate_latency(struct acpicpu_softc *); 62static bool acpicpu_cstate_bm_check(void); 63static void acpicpu_cstate_idle_enter(struct acpicpu_softc *,int); 64 65extern struct acpicpu_softc **acpicpu_sc; 66 67/* 68 * XXX: The local APIC timer (as well as TSC) is typically stopped in C3. 69 * For now, we cannot but disable C3. But there appears to be timer- 70 * related interrupt issues also in C2. The only entirely safe option 71 * at the moment is to use C1. 72 */ 73#ifdef ACPICPU_ENABLE_C3 74static int cs_state_max = ACPI_STATE_C3; 75#else 76static int cs_state_max = ACPI_STATE_C1; 77#endif 78 79void 80acpicpu_cstate_attach(device_t self) 81{ 82 struct acpicpu_softc *sc = device_private(self); 83 ACPI_STATUS rv; 84 85 /* 86 * Either use the preferred _CST or resort to FADT. 87 */ 88 rv = acpicpu_cstate_cst(sc); 89 90 switch (rv) { 91 92 case AE_OK: 93 acpicpu_cstate_cst_bios(); 94 break; 95 96 default: 97 sc->sc_flags |= ACPICPU_FLAG_C_FADT; 98 acpicpu_cstate_fadt(sc); 99 break; 100 } 101 102 sc->sc_flags |= ACPICPU_FLAG_C; 103 104 acpicpu_cstate_quirks(sc); 105 acpicpu_cstate_attach_evcnt(sc); 106 acpicpu_cstate_attach_print(sc); 107} 108 109void 110acpicpu_cstate_attach_print(struct acpicpu_softc *sc) 111{ 112 struct acpicpu_cstate *cs; 113 static bool once = false; 114 const char *str; 115 int i; 116 117 if (once != false) 118 return; 119 120 for (i = 0; i < ACPI_C_STATE_COUNT; i++) { 121 122 cs = &sc->sc_cstate[i]; 123 124 if (cs->cs_method == 0) 125 continue; 126 127 switch (cs->cs_method) { 128 129 case ACPICPU_C_STATE_HALT: 130 str = "HLT"; 131 break; 132 133 case ACPICPU_C_STATE_FFH: 134 str = "FFH"; 135 break; 136 137 case ACPICPU_C_STATE_SYSIO: 138 str = "I/O"; 139 break; 140 141 default: 142 panic("NOTREACHED"); 143 } 144 145 aprint_debug_dev(sc->sc_dev, "C%d: %3s, " 146 "lat %3u us, pow %5u mW, flags 0x%02x\n", i, str, 147 cs->cs_latency, cs->cs_power, cs->cs_flags); 148 } 149 150 once = true; 151} 152 153static void 154acpicpu_cstate_attach_evcnt(struct acpicpu_softc *sc) 155{ 156 struct acpicpu_cstate *cs; 157 const char *str; 158 int i; 159 160 for (i = 0; i < ACPI_C_STATE_COUNT; i++) { 161 162 cs = &sc->sc_cstate[i]; 163 164 if (cs->cs_method == 0) 165 continue; 166 167 str = "HALT"; 168 169 if (cs->cs_method == ACPICPU_C_STATE_FFH) 170 str = "MWAIT"; 171 172 if (cs->cs_method == ACPICPU_C_STATE_SYSIO) 173 str = "I/O"; 174 175 (void)snprintf(cs->cs_name, sizeof(cs->cs_name), 176 "C%d (%s)", i, str); 177 178 evcnt_attach_dynamic(&cs->cs_evcnt, EVCNT_TYPE_MISC, 179 NULL, device_xname(sc->sc_dev), cs->cs_name); 180 } 181} 182 183int 184acpicpu_cstate_detach(device_t self) 185{ 186 struct acpicpu_softc *sc = device_private(self); 187 static ONCE_DECL(once_detach); 188 int rv; 189 190 rv = RUN_ONCE(&once_detach, acpicpu_md_idle_stop); 191 192 if (rv != 0) 193 return rv; 194 195 sc->sc_flags &= ~ACPICPU_FLAG_C; 196 acpicpu_cstate_detach_evcnt(sc); 197 198 return 0; 199} 200 201static void 202acpicpu_cstate_detach_evcnt(struct acpicpu_softc *sc) 203{ 204 struct acpicpu_cstate *cs; 205 int i; 206 207 for (i = 0; i < ACPI_C_STATE_COUNT; i++) { 208 209 cs = &sc->sc_cstate[i]; 210 211 if (cs->cs_method != 0) 212 evcnt_detach(&cs->cs_evcnt); 213 } 214} 215 216void 217acpicpu_cstate_start(device_t self) 218{ 219 220 (void)acpicpu_md_idle_start(); 221} 222 223bool 224acpicpu_cstate_suspend(device_t self) 225{ 226 227 return true; 228} 229 230bool 231acpicpu_cstate_resume(device_t self) 232{ 233 struct acpicpu_softc *sc = device_private(self); 234 235 if ((sc->sc_flags & ACPICPU_FLAG_C_FADT) == 0) 236 acpicpu_cstate_callback(self); 237 238 return true; 239} 240 241void 242acpicpu_cstate_callback(void *aux) 243{ 244 struct acpicpu_softc *sc; 245 device_t self = aux; 246 247 sc = device_private(self); 248 249 if ((sc->sc_flags & ACPICPU_FLAG_C_FADT) != 0) 250 return; 251 252 mutex_enter(&sc->sc_mtx); 253 (void)acpicpu_cstate_cst(sc); 254 mutex_exit(&sc->sc_mtx); 255} 256 257static ACPI_STATUS 258acpicpu_cstate_cst(struct acpicpu_softc *sc) 259{ 260 ACPI_OBJECT *elm, *obj; 261 ACPI_BUFFER buf; 262 ACPI_STATUS rv; 263 uint32_t i, n; 264 uint8_t count; 265 266 rv = acpi_eval_struct(sc->sc_node->ad_handle, "_CST", &buf); 267 268 if (ACPI_FAILURE(rv)) 269 return rv; 270 271 obj = buf.Pointer; 272 273 if (obj->Type != ACPI_TYPE_PACKAGE) { 274 rv = AE_TYPE; 275 goto out; 276 } 277 278 if (obj->Package.Count < 2) { 279 rv = AE_LIMIT; 280 goto out; 281 } 282 283 elm = obj->Package.Elements; 284 285 if (elm[0].Type != ACPI_TYPE_INTEGER) { 286 rv = AE_TYPE; 287 goto out; 288 } 289 290 n = elm[0].Integer.Value; 291 292 if (n != obj->Package.Count - 1) { 293 rv = AE_BAD_VALUE; 294 goto out; 295 } 296 297 if (n > ACPI_C_STATES_MAX) { 298 rv = AE_LIMIT; 299 goto out; 300 } 301 302 acpicpu_cstate_memset(sc); 303 304 CTASSERT(ACPI_STATE_C0 == 0 && ACPI_STATE_C1 == 1); 305 CTASSERT(ACPI_STATE_C2 == 2 && ACPI_STATE_C3 == 3); 306 307 for (count = 0, i = 1; i <= n; i++) { 308 309 elm = &obj->Package.Elements[i]; 310 rv = acpicpu_cstate_cst_add(sc, elm); 311 312 if (ACPI_SUCCESS(rv)) 313 count++; 314 } 315 316 rv = (count != 0) ? AE_OK : AE_NOT_EXIST; 317 318out: 319 if (buf.Pointer != NULL) 320 ACPI_FREE(buf.Pointer); 321 322 return rv; 323} 324 325static ACPI_STATUS 326acpicpu_cstate_cst_add(struct acpicpu_softc *sc, ACPI_OBJECT *elm) 327{ 328 const struct acpicpu_object *ao = &sc->sc_object; 329 struct acpicpu_cstate *cs = sc->sc_cstate; 330 struct acpicpu_cstate state; 331 struct acpicpu_reg *reg; 332 ACPI_STATUS rv = AE_OK; 333 ACPI_OBJECT *obj; 334 uint32_t type; 335 336 (void)memset(&state, 0, sizeof(*cs)); 337 338 state.cs_flags = ACPICPU_FLAG_C_BM_STS; 339 340 if (elm->Type != ACPI_TYPE_PACKAGE) { 341 rv = AE_TYPE; 342 goto out; 343 } 344 345 if (elm->Package.Count != 4) { 346 rv = AE_LIMIT; 347 goto out; 348 } 349 350 /* 351 * Type. 352 */ 353 obj = &elm->Package.Elements[1]; 354 355 if (obj->Type != ACPI_TYPE_INTEGER) { 356 rv = AE_TYPE; 357 goto out; 358 } 359 360 type = obj->Integer.Value; 361 362 if (type < ACPI_STATE_C1 || type > ACPI_STATE_C3) { 363 rv = AE_TYPE; 364 goto out; 365 } 366 367 /* 368 * Latency. 369 */ 370 obj = &elm->Package.Elements[2]; 371 372 if (obj->Type != ACPI_TYPE_INTEGER) { 373 rv = AE_TYPE; 374 goto out; 375 } 376 377 state.cs_latency = obj->Integer.Value; 378 379 /* 380 * Power. 381 */ 382 obj = &elm->Package.Elements[3]; 383 384 if (obj->Type != ACPI_TYPE_INTEGER) { 385 rv = AE_TYPE; 386 goto out; 387 } 388 389 state.cs_power = obj->Integer.Value; 390 391 /* 392 * Register. 393 */ 394 obj = &elm->Package.Elements[0]; 395 396 if (obj->Type != ACPI_TYPE_BUFFER) { 397 rv = AE_TYPE; 398 goto out; 399 } 400 401 CTASSERT(sizeof(struct acpicpu_reg) == 15); 402 403 if (obj->Buffer.Length < sizeof(struct acpicpu_reg)) { 404 rv = AE_LIMIT; 405 goto out; 406 } 407 408 reg = (struct acpicpu_reg *)obj->Buffer.Pointer; 409 410 switch (reg->reg_spaceid) { 411 412 case ACPI_ADR_SPACE_SYSTEM_IO: 413 state.cs_method = ACPICPU_C_STATE_SYSIO; 414 415 if (reg->reg_addr == 0) { 416 rv = AE_AML_ILLEGAL_ADDRESS; 417 goto out; 418 } 419 420 if (reg->reg_bitwidth != 8) { 421 rv = AE_AML_BAD_RESOURCE_LENGTH; 422 goto out; 423 } 424 425 /* 426 * Check only that the address is in the mapped space. 427 * Systems are allowed to change it when operating 428 * with _CST (see ACPI 4.0, pp. 94-95). For instance, 429 * the offset of P_LVL3 may change depending on whether 430 * acpiacad(4) is connected or disconnected. 431 */ 432 if (reg->reg_addr > ao->ao_pblkaddr + ao->ao_pblklen) { 433 rv = AE_BAD_ADDRESS; 434 goto out; 435 } 436 437 state.cs_addr = reg->reg_addr; 438 break; 439 440 case ACPI_ADR_SPACE_FIXED_HARDWARE: 441 state.cs_method = ACPICPU_C_STATE_FFH; 442 443 switch (type) { 444 445 case ACPI_STATE_C1: 446 447 if ((sc->sc_flags & ACPICPU_FLAG_C_FFH) == 0) 448 state.cs_method = ACPICPU_C_STATE_HALT; 449 450 break; 451 452 default: 453 454 if ((sc->sc_flags & ACPICPU_FLAG_C_FFH) == 0) { 455 rv = AE_SUPPORT; 456 goto out; 457 } 458 } 459 460 if (sc->sc_cap != 0) { 461 462 /* 463 * The _CST FFH GAS encoding may contain 464 * additional hints on Intel processors. 465 * Use these to determine whether we can 466 * avoid the bus master activity check. 467 */ 468 if ((reg->reg_accesssize & ACPICPU_PDC_GAS_BM) == 0) 469 state.cs_flags &= ~ACPICPU_FLAG_C_BM_STS; 470 } 471 472 break; 473 474 default: 475 rv = AE_AML_INVALID_SPACE_ID; 476 goto out; 477 } 478 479 if (cs[type].cs_method != 0) { 480 rv = AE_ALREADY_EXISTS; 481 goto out; 482 } 483 484 cs[type].cs_addr = state.cs_addr; 485 cs[type].cs_power = state.cs_power; 486 cs[type].cs_flags = state.cs_flags; 487 cs[type].cs_method = state.cs_method; 488 cs[type].cs_latency = state.cs_latency; 489 490out: 491 if (ACPI_FAILURE(rv)) 492 aprint_debug_dev(sc->sc_dev, "invalid " 493 "_CST: %s\n", AcpiFormatException(rv)); 494 495 return rv; 496} 497 498static void 499acpicpu_cstate_cst_bios(void) 500{ 501 const uint8_t val = AcpiGbl_FADT.CstControl; 502 const uint32_t addr = AcpiGbl_FADT.SmiCommand; 503 504 if (addr == 0 || val == 0) 505 return; 506 507 (void)AcpiOsWritePort(addr, val, 8); 508} 509 510static void 511acpicpu_cstate_memset(struct acpicpu_softc *sc) 512{ 513 int i = 0; 514 515 while (i < ACPI_C_STATE_COUNT) { 516 517 sc->sc_cstate[i].cs_addr = 0; 518 sc->sc_cstate[i].cs_power = 0; 519 sc->sc_cstate[i].cs_flags = 0; 520 sc->sc_cstate[i].cs_method = 0; 521 sc->sc_cstate[i].cs_latency = 0; 522 523 i++; 524 } 525} 526 527static void 528acpicpu_cstate_fadt(struct acpicpu_softc *sc) 529{ 530 struct acpicpu_cstate *cs = sc->sc_cstate; 531 532 acpicpu_cstate_memset(sc); 533 534 /* 535 * All x86 processors should support C1 (a.k.a. HALT). 536 */ 537 if ((AcpiGbl_FADT.Flags & ACPI_FADT_C1_SUPPORTED) != 0) 538 cs[ACPI_STATE_C1].cs_method = ACPICPU_C_STATE_HALT; 539 540 if (sc->sc_object.ao_pblkaddr == 0) 541 return; 542 543 if (acpicpu_md_cpus_running() > 1) { 544 545 if ((AcpiGbl_FADT.Flags & ACPI_FADT_C2_MP_SUPPORTED) == 0) 546 return; 547 } 548 549 cs[ACPI_STATE_C2].cs_method = ACPICPU_C_STATE_SYSIO; 550 cs[ACPI_STATE_C3].cs_method = ACPICPU_C_STATE_SYSIO; 551 552 cs[ACPI_STATE_C2].cs_latency = AcpiGbl_FADT.C2Latency; 553 cs[ACPI_STATE_C3].cs_latency = AcpiGbl_FADT.C3Latency; 554 555 cs[ACPI_STATE_C2].cs_addr = sc->sc_object.ao_pblkaddr + 4; 556 cs[ACPI_STATE_C3].cs_addr = sc->sc_object.ao_pblkaddr + 5; 557 558 /* 559 * The P_BLK length should always be 6. If it 560 * is not, reduce functionality accordingly. 561 */ 562 if (sc->sc_object.ao_pblklen < 5) 563 cs[ACPI_STATE_C2].cs_method = 0; 564 565 if (sc->sc_object.ao_pblklen < 6) 566 cs[ACPI_STATE_C3].cs_method = 0; 567 568 /* 569 * Sanity check the latency levels in FADT. 570 * Values above the thresholds are used to 571 * inform that C-states are not supported. 572 */ 573 CTASSERT(ACPICPU_C_C2_LATENCY_MAX == 100); 574 CTASSERT(ACPICPU_C_C3_LATENCY_MAX == 1000); 575 576 if (AcpiGbl_FADT.C2Latency > ACPICPU_C_C2_LATENCY_MAX) 577 cs[ACPI_STATE_C2].cs_method = 0; 578 579 if (AcpiGbl_FADT.C3Latency > ACPICPU_C_C3_LATENCY_MAX) 580 cs[ACPI_STATE_C3].cs_method = 0; 581} 582 583static void 584acpicpu_cstate_quirks(struct acpicpu_softc *sc) 585{ 586 const uint32_t reg = AcpiGbl_FADT.Pm2ControlBlock; 587 const uint32_t len = AcpiGbl_FADT.Pm2ControlLength; 588 589 /* 590 * Disable C3 for PIIX4. 591 */ 592 if ((sc->sc_flags & ACPICPU_FLAG_PIIX4) != 0) { 593 sc->sc_cstate[ACPI_STATE_C3].cs_method = 0; 594 return; 595 } 596 597 /* 598 * Check bus master arbitration. If ARB_DIS 599 * is not available, processor caches must be 600 * flushed before C3 (ACPI 4.0, section 8.2). 601 */ 602 if (reg != 0 && len != 0) { 603 sc->sc_flags |= ACPICPU_FLAG_C_ARB; 604 return; 605 } 606 607 /* 608 * Disable C3 entirely if WBINVD is not present. 609 */ 610 if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD) == 0) 611 sc->sc_cstate[ACPI_STATE_C3].cs_method = 0; 612 else { 613 /* 614 * If WBINVD is present and functioning properly, 615 * flush all processor caches before entering C3. 616 */ 617 if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD_FLUSH) == 0) 618 sc->sc_flags &= ~ACPICPU_FLAG_C_BM; 619 else 620 sc->sc_cstate[ACPI_STATE_C3].cs_method = 0; 621 } 622} 623 624static int 625acpicpu_cstate_latency(struct acpicpu_softc *sc) 626{ 627 static const uint32_t cs_factor = 3; 628 struct acpicpu_cstate *cs; 629 int i; 630 631 for (i = cs_state_max; i > 0; i--) { 632 633 cs = &sc->sc_cstate[i]; 634 635 if (__predict_false(cs->cs_method == 0)) 636 continue; 637 638 /* 639 * Choose a state if we have previously slept 640 * longer than the worst case latency of the 641 * state times an arbitrary multiplier. 642 */ 643 if (sc->sc_cstate_sleep > cs->cs_latency * cs_factor) 644 return i; 645 } 646 647 return ACPI_STATE_C1; 648} 649 650/* 651 * The main idle loop. 652 */ 653void 654acpicpu_cstate_idle(void) 655{ 656 struct cpu_info *ci = curcpu(); 657 struct acpicpu_softc *sc; 658 int state; 659 660 if (__predict_false(ci->ci_want_resched) != 0) 661 return; 662 663 acpi_md_OsDisableInterrupt(); 664 665 KASSERT(acpicpu_sc != NULL); 666 KASSERT(ci->ci_acpiid < maxcpus); 667 KASSERT(ci->ci_ilevel == IPL_NONE); 668 KASSERT((sc->sc_flags & ACPICPU_FLAG_C) != 0); 669 670 sc = acpicpu_sc[ci->ci_acpiid]; 671 672 if (__predict_false(sc == NULL)) 673 goto halt; 674 675 if (__predict_false(sc->sc_cold != false)) 676 goto halt; 677 678 if (__predict_false(mutex_tryenter(&sc->sc_mtx) == 0)) 679 goto halt; 680 681 mutex_exit(&sc->sc_mtx); 682 state = acpicpu_cstate_latency(sc); 683 684 /* 685 * Check for bus master activity. Note that particularly usb(4) 686 * causes high activity, which may prevent the use of C3 states. 687 */ 688 if ((sc->sc_cstate[state].cs_flags & ACPICPU_FLAG_C_BM_STS) != 0) { 689 690 if (acpicpu_cstate_bm_check() != false) 691 state--; 692 693 if (__predict_false(sc->sc_cstate[state].cs_method == 0)) 694 state = ACPI_STATE_C1; 695 } 696 697 KASSERT(state != ACPI_STATE_C0); 698 699 if (state != ACPI_STATE_C3) { 700 acpicpu_cstate_idle_enter(sc, state); 701 return; 702 } 703 704 /* 705 * On all recent (Intel) CPUs caches are shared 706 * by CPUs and bus master control is required to 707 * keep these coherent while in C3. Flushing the 708 * CPU caches is only the last resort. 709 */ 710 if ((sc->sc_flags & ACPICPU_FLAG_C_BM) == 0) 711 ACPI_FLUSH_CPU_CACHE(); 712 713 /* 714 * Allow the bus master to request that any given 715 * CPU should return immediately to C0 from C3. 716 */ 717 if ((sc->sc_flags & ACPICPU_FLAG_C_BM) != 0) 718 (void)AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 1); 719 720 /* 721 * It may be necessary to disable bus master arbitration 722 * to ensure that bus master cycles do not occur while 723 * sleeping in C3 (see ACPI 4.0, section 8.1.4). 724 */ 725 if ((sc->sc_flags & ACPICPU_FLAG_C_ARB) != 0) 726 (void)AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 1); 727 728 acpicpu_cstate_idle_enter(sc, state); 729 730 /* 731 * Disable bus master wake and re-enable the arbiter. 732 */ 733 if ((sc->sc_flags & ACPICPU_FLAG_C_BM) != 0) 734 (void)AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 735 736 if ((sc->sc_flags & ACPICPU_FLAG_C_ARB) != 0) 737 (void)AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 0); 738 739 return; 740 741halt: 742 acpicpu_md_idle_enter(ACPICPU_C_STATE_HALT, ACPI_STATE_C1); 743} 744 745static void 746acpicpu_cstate_idle_enter(struct acpicpu_softc *sc, int state) 747{ 748 struct acpicpu_cstate *cs = &sc->sc_cstate[state]; 749 uint32_t end, start, val; 750 751 start = acpitimer_read_safe(NULL); 752 753 switch (cs->cs_method) { 754 755 case ACPICPU_C_STATE_FFH: 756 case ACPICPU_C_STATE_HALT: 757 acpicpu_md_idle_enter(cs->cs_method, state); 758 break; 759 760 case ACPICPU_C_STATE_SYSIO: 761 (void)AcpiOsReadPort(cs->cs_addr, &val, 8); 762 break; 763 764 default: 765 acpicpu_md_idle_enter(ACPICPU_C_STATE_HALT, ACPI_STATE_C1); 766 break; 767 } 768 769 cs->cs_evcnt.ev_count++; 770 771 end = acpitimer_read_safe(NULL); 772 sc->sc_cstate_sleep = hztoms(acpitimer_delta(end, start)) * 1000; 773 774 acpi_md_OsEnableInterrupt(); 775} 776 777static bool 778acpicpu_cstate_bm_check(void) 779{ 780 uint32_t val = 0; 781 ACPI_STATUS rv; 782 783 rv = AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, &val); 784 785 if (ACPI_FAILURE(rv) || val == 0) 786 return false; 787 788 (void)AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1); 789 790 return true; 791} 792