acpi_cpu.h revision 1.7 
1/* $NetBSD: acpi_cpu.h,v 1.7 2010/07/29 22:42:58 jruoho Exp $ */
2
3/*-
4 * Copyright (c) 2010 Jukka Ruohonen <jruohonen@iki.fi>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30#ifndef _SYS_DEV_ACPI_ACPI_CPU_H
31#define _SYS_DEV_ACPI_ACPI_CPU_H
32
33/*
34 * The following _PDC values are based on:
35 *
36 *   Intel Processor-Specific ACPI Interface
37 *   Specification, September 2006, Revision 005.
38 */
39#define ACPICPU_PDC_REVID         0x1
40#define ACPICPU_PDC_SMP           0xA
41#define ACPICPU_PDC_MSR           0x1
42
43#define ACPICPU_PDC_P_FFH         __BIT(0)	/* SpeedStep MSRs            */
44#define ACPICPU_PDC_C_C1_HALT     __BIT(1)	/* C1 "I/O then halt"        */
45#define ACPICPU_PDC_T_FFH         __BIT(2)	/* OnDemand throttling MSRs  */
46#define ACPICPU_PDC_C_C1PT        __BIT(3)	/* SMP C1, Px, and Tx (same) */
47#define ACPICPU_PDC_C_C2C3        __BIT(4)	/* SMP C2 and C3 (same)      */
48#define ACPICPU_PDC_P_SW          __BIT(5)	/* SMP Px (different)        */
49#define ACPICPU_PDC_C_SW          __BIT(6)	/* SMP Cx (different)        */
50#define ACPICPU_PDC_T_SW          __BIT(7)	/* SMP Tx (different)        */
51#define ACPICPU_PDC_C_C1_FFH      __BIT(8)	/* SMP C1 native beyond halt */
52#define ACPICPU_PDC_C_C2C3_FFH    __BIT(9)	/* SMP C2 and C2 native      */
53#define ACPICPU_PDC_P_HW          __BIT(11)	/* Px hardware coordination  */
54
55#define ACPICPU_PDC_GAS_HW	  __BIT(0)	/* HW-coordinated state      */
56#define ACPICPU_PDC_GAS_BM	  __BIT(1)	/* Bus master check required */
57
58/*
59 * Notify values.
60 */
61#define ACPICPU_P_NOTIFY	 0x80		/* _PPC */
62#define ACPICPU_C_NOTIFY	 0x81		/* _CST */
63#define ACPICPU_T_NOTIFY	 0x82		/* _TPC */
64
65/*
66 * C-states.
67 */
68#define ACPICPU_C_C2_LATENCY_MAX 100		/* us */
69#define ACPICPU_C_C3_LATENCY_MAX 1000		/* us */
70
71#define ACPICPU_C_STATE_HALT	 0x01
72#define ACPICPU_C_STATE_FFH	 0x02
73#define ACPICPU_C_STATE_SYSIO	 0x03
74
75/*
76 * Cross-CPU dependency coordination.
77 */
78#define ACPICPU_DEP_SW_ALL	 0xFC
79#define ACPICPU_DEP_SW_ANY	 0xFD
80#define ACPICPU_DEP_HW_ALL	 0xFE
81
82/*
83 * Flags.
84 */
85#define ACPICPU_FLAG_C		 __BIT(0)	/* C-states supported        */
86#define ACPICPU_FLAG_P		 __BIT(1)	/* P-states supported        */
87#define ACPICPU_FLAG_T		 __BIT(2)	/* T-states supported        */
88
89#define ACPICPU_FLAG_C_CST	 __BIT(3)	/* C-states with _CST	     */
90#define ACPICPU_FLAG_C_FADT	 __BIT(4)	/* C-states with FADT        */
91#define ACPICPU_FLAG_C_BM	 __BIT(5)	/* Bus master control        */
92#define ACPICPU_FLAG_C_BM_STS	 __BIT(6)	/* Bus master check required */
93#define ACPICPU_FLAG_C_ARB	 __BIT(7)	/* Bus master arbitration    */
94#define ACPICPU_FLAG_C_NOC3	 __BIT(8)	/* C3 disabled (quirk)       */
95#define ACPICPU_FLAG_C_MWAIT	 __BIT(9)	/* MONITOR/MWAIT supported   */
96#define ACPICPU_FLAG_C_C1E	 __BIT(10)	/* AMD C1E detected	     */
97
98struct acpicpu_cstate {
99	uint64_t		 cs_stat;
100	uint64_t		 cs_addr;
101	uint32_t		 cs_power;	/* mW */
102	uint32_t		 cs_latency;	/* us */
103	int			 cs_method;
104	int			 cs_flags;
105};
106
107struct acpicpu_dep {
108	uint32_t		 dep_domain;
109	uint32_t		 dep_coord;
110	uint32_t		 dep_ncpu;
111	uint32_t		 dep_index;
112};
113
114struct acpicpu_object {
115	uint32_t		 ao_procid;
116	uint32_t		 ao_pblklen;
117	uint32_t		 ao_pblkaddr;
118};
119
120struct acpicpu_softc {
121	device_t		 sc_dev;
122	struct acpi_devnode	*sc_node;
123	struct acpicpu_object	 sc_object;
124	struct acpicpu_cstate	 sc_cstate[ACPI_C_STATE_COUNT];
125	kmutex_t		 sc_cstate_mtx;
126	bus_space_tag_t		 sc_iot;
127	bus_space_handle_t	 sc_ioh;
128	uint32_t		 sc_sleep;
129	uint32_t		 sc_cpuid;
130	uint32_t		 sc_cap;
131	uint32_t		 sc_flags;
132	bool			 sc_cold;
133};
134
135/*
136 * This is AML_RESOURCE_GENERIC_REGISTER,
137 * included here separately for convenience.
138 */
139struct acpicpu_reg {
140	uint8_t			 reg_desc;
141	uint16_t		 reg_reslen;
142	uint8_t			 reg_spaceid;
143	uint8_t			 reg_bitwidth;
144	uint8_t			 reg_bitoffset;
145	uint8_t			 reg_accesssize;
146	uint64_t		 reg_addr;
147} __packed;
148
149void		acpicpu_cstate_attach(device_t);
150int		acpicpu_cstate_detach(device_t);
151int		acpicpu_cstate_start(device_t);
152bool		acpicpu_cstate_suspend(device_t);
153bool		acpicpu_cstate_resume(device_t);
154void		acpicpu_cstate_callback(void *);
155void		acpicpu_cstate_idle(void);
156
157uint32_t	acpicpu_md_cap(void);
158uint32_t	acpicpu_md_quirks(void);
159uint32_t	acpicpu_md_cpus_running(void);
160int		acpicpu_md_idle_init(void);
161int		acpicpu_md_idle_start(void);
162int		acpicpu_md_idle_stop(void);
163void		acpicpu_md_idle_enter(int, int);
164
165#endif	/* !_SYS_DEV_ACPI_ACPI_CPU_H */
166