acpi_cpu.h revision 1.43
1/* $NetBSD: acpi_cpu.h,v 1.43 2011/10/18 05:08:24 jruoho Exp $ */ 2 3/*- 4 * Copyright (c) 2010, 2011 Jukka Ruohonen <jruohonen@iki.fi> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30#ifndef _SYS_DEV_ACPI_ACPI_CPU_H 31#define _SYS_DEV_ACPI_ACPI_CPU_H 32 33/* 34 * The following _PDC values are based on: 35 * 36 * Intel Corporation: Intel Processor-Specific ACPI 37 * Interface Specification, September 2006, Revision 005. 38 */ 39#define ACPICPU_PDC_REVID 0x1 40#define ACPICPU_PDC_SMP 0xA 41#define ACPICPU_PDC_MSR 0x1 42 43#define ACPICPU_PDC_P_FFH __BIT(0) /* SpeedStep MSRs */ 44#define ACPICPU_PDC_C_C1_HALT __BIT(1) /* C1 "I/O then halt" */ 45#define ACPICPU_PDC_T_FFH __BIT(2) /* OnDemand throttling MSRs */ 46#define ACPICPU_PDC_C_C1PT __BIT(3) /* SMP C1, Px, and Tx (same) */ 47#define ACPICPU_PDC_C_C2C3 __BIT(4) /* SMP C2 and C3 (same) */ 48#define ACPICPU_PDC_P_SW __BIT(5) /* SMP Px (different) */ 49#define ACPICPU_PDC_C_SW __BIT(6) /* SMP Cx (different) */ 50#define ACPICPU_PDC_T_SW __BIT(7) /* SMP Tx (different) */ 51#define ACPICPU_PDC_C_C1_FFH __BIT(8) /* SMP C1 native beyond halt */ 52#define ACPICPU_PDC_C_C2C3_FFH __BIT(9) /* SMP C2 and C2 native */ 53#define ACPICPU_PDC_P_HWF __BIT(11) /* Px hardware feedback */ 54 55#define ACPICPU_PDC_GAS_HW __BIT(0) /* HW-coordinated state */ 56#define ACPICPU_PDC_GAS_BM __BIT(1) /* Bus master check required */ 57 58/* 59 * Notify values. 60 */ 61#define ACPICPU_P_NOTIFY 0x80 /* _PPC */ 62#define ACPICPU_C_NOTIFY 0x81 /* _CST */ 63#define ACPICPU_T_NOTIFY 0x82 /* _TPC */ 64 65/* 66 * Dependency coordination. 67 */ 68#define ACPICPU_DEP_SW_ALL 0xFC /* All CPUs must set a state */ 69#define ACPICPU_DEP_SW_ANY 0xFD /* Any CPU can set a state */ 70#define ACPICPU_DEP_HW_ALL 0xFE /* HW does the coordination */ 71 72/* 73 * C-states. 74 */ 75#define ACPICPU_C_C2_LATENCY_MAX 100 /* us */ 76#define ACPICPU_C_C3_LATENCY_MAX 1000 /* us */ 77 78#define ACPICPU_C_STATE_HALT 0x01 79#define ACPICPU_C_STATE_FFH 0x02 80#define ACPICPU_C_STATE_SYSIO 0x03 81 82/* 83 * P-states. 84 */ 85#define ACPICPU_P_STATE_MAX 255 /* Arbitrary upper limit */ 86#define ACPICPU_P_STATE_RETRY 100 87 88/* 89 * T-states. 90 */ 91#define ACPICPU_T_STATE_MAX 0x8 92#define ACPICPU_T_STATE_RETRY 0xA 93#define ACPICPU_T_STATE_UNKNOWN 255 94 95/* 96 * Flags. 97 */ 98#define ACPICPU_FLAG_C __BIT(0) /* C-states supported */ 99#define ACPICPU_FLAG_P __BIT(1) /* P-states supported */ 100#define ACPICPU_FLAG_T __BIT(2) /* T-states supported */ 101 102#define ACPICPU_FLAG_PIIX4 __BIT(3) /* Broken (quirk) */ 103 104#define ACPICPU_FLAG_C_FFH __BIT(4) /* Native C-states */ 105#define ACPICPU_FLAG_C_FADT __BIT(5) /* C-states with FADT */ 106#define ACPICPU_FLAG_C_DEP __BIT(6) /* C-state CPU coordination */ 107#define ACPICPU_FLAG_C_BM __BIT(7) /* Bus master control */ 108#define ACPICPU_FLAG_C_BM_STS __BIT(8) /* Bus master check required */ 109#define ACPICPU_FLAG_C_ARB __BIT(9) /* Bus master arbitration */ 110#define ACPICPU_FLAG_C_TSC __BIT(10) /* TSC broken, > C1, Px, Tx */ 111#define ACPICPU_FLAG_C_APIC __BIT(11) /* APIC timer broken, > C1 */ 112#define ACPICPU_FLAG_C_C1E __BIT(12) /* AMD C1E detected */ 113 114#define ACPICPU_FLAG_P_FFH __BIT(13) /* Native P-states */ 115#define ACPICPU_FLAG_P_DEP __BIT(14) /* P-state CPU coordination */ 116#define ACPICPU_FLAG_P_HWF __BIT(15) /* HW feedback supported */ 117#define ACPICPU_FLAG_P_XPSS __BIT(16) /* Microsoft XPSS in use */ 118#define ACPICPU_FLAG_P_TURBO __BIT(17) /* Turbo Boost / Turbo Core */ 119#define ACPICPU_FLAG_P_FIDVID __BIT(18) /* AMD "FID/VID algorithm" */ 120 121#define ACPICPU_FLAG_T_FFH __BIT(19) /* Native throttling */ 122#define ACPICPU_FLAG_T_FADT __BIT(20) /* Throttling with FADT */ 123#define ACPICPU_FLAG_T_DEP __BIT(21) /* T-state CPU coordination */ 124 125/* 126 * This is AML_RESOURCE_GENERIC_REGISTER, 127 * included here separately for convenience. 128 */ 129struct acpicpu_reg { 130 uint8_t reg_desc; 131 uint16_t reg_reslen; 132 uint8_t reg_spaceid; 133 uint8_t reg_bitwidth; 134 uint8_t reg_bitoffset; 135 uint8_t reg_accesssize; 136 uint64_t reg_addr; 137} __packed; 138 139struct acpicpu_dep { 140 uint32_t dep_domain; 141 uint32_t dep_type; 142 uint32_t dep_ncpus; 143 uint32_t dep_index; 144}; 145 146struct acpicpu_cstate { 147 struct evcnt cs_evcnt; 148 char cs_name[EVCNT_STRING_MAX]; 149 uint64_t cs_addr; 150 uint32_t cs_power; 151 uint32_t cs_latency; 152 int cs_method; 153 int cs_flags; 154}; 155 156/* 157 * This structure supports both the conventional _PSS and the 158 * so-called extended _PSS (XPSS). For the latter, refer to: 159 * 160 * Microsoft Corporation: Extended PSS ACPI 161 * Method Specification, April 2, 2007. 162 */ 163struct acpicpu_pstate { 164 struct evcnt ps_evcnt; 165 char ps_name[EVCNT_STRING_MAX]; 166 uint32_t ps_freq; 167 uint32_t ps_power; 168 uint32_t ps_latency; 169 uint32_t ps_latency_bm; 170 uint64_t ps_control; 171 uint64_t ps_control_addr; 172 uint64_t ps_control_mask; 173 uint64_t ps_status; 174 uint64_t ps_status_addr; 175 uint64_t ps_status_mask; 176 int ps_flags; 177}; 178 179struct acpicpu_tstate { 180 struct evcnt ts_evcnt; 181 char ts_name[EVCNT_STRING_MAX]; 182 uint32_t ts_percent; 183 uint32_t ts_power; 184 uint32_t ts_latency; 185 uint32_t ts_control; 186 uint32_t ts_status; 187}; 188 189struct acpicpu_object { 190 uint32_t ao_procid; 191 uint32_t ao_pblklen; 192 uint32_t ao_pblkaddr; 193}; 194 195struct acpicpu_softc { 196 device_t sc_dev; 197 struct cpu_info *sc_ci; 198 struct acpi_devnode *sc_node; 199 struct acpicpu_object sc_object; 200 201 struct acpicpu_cstate sc_cstate[ACPI_C_STATE_COUNT]; 202 struct acpicpu_dep sc_cstate_dep; 203 uint32_t sc_cstate_sleep; 204 205 struct acpicpu_pstate *sc_pstate; 206 struct acpicpu_dep sc_pstate_dep; 207 struct acpicpu_reg sc_pstate_control; 208 struct acpicpu_reg sc_pstate_status; 209 uint64_t sc_pstate_aperf; /* ACPICPU_FLAG_P_HW */ 210 uint64_t sc_pstate_mperf; /* ACPICPU_FLAG_P_HW*/ 211 uint32_t sc_pstate_current; 212 uint32_t sc_pstate_saved; 213 uint32_t sc_pstate_count; 214 uint32_t sc_pstate_max; 215 uint32_t sc_pstate_min; 216 217 struct acpicpu_tstate *sc_tstate; 218 struct acpicpu_dep sc_tstate_dep; 219 struct acpicpu_reg sc_tstate_control; 220 struct acpicpu_reg sc_tstate_status; 221 uint32_t sc_tstate_current; 222 uint32_t sc_tstate_count; 223 uint32_t sc_tstate_max; 224 uint32_t sc_tstate_min; 225 226 kmutex_t sc_mtx; 227 uint32_t sc_cap; 228 uint32_t sc_ncpus; 229 uint32_t sc_flags; 230 bool sc_cold; 231}; 232 233void acpicpu_cstate_attach(device_t); 234void acpicpu_cstate_detach(device_t); 235void acpicpu_cstate_start(device_t); 236void acpicpu_cstate_suspend(void *); 237void acpicpu_cstate_resume(void *); 238void acpicpu_cstate_callback(void *); 239void acpicpu_cstate_idle(void); 240 241void acpicpu_pstate_attach(device_t); 242void acpicpu_pstate_detach(device_t); 243void acpicpu_pstate_start(device_t); 244void acpicpu_pstate_suspend(void *); 245void acpicpu_pstate_resume(void *); 246void acpicpu_pstate_callback(void *); 247void acpicpu_pstate_get(void *, void *); 248void acpicpu_pstate_set(void *, void *); 249 250void acpicpu_tstate_attach(device_t); 251void acpicpu_tstate_detach(device_t); 252void acpicpu_tstate_start(device_t); 253void acpicpu_tstate_suspend(void *); 254void acpicpu_tstate_resume(void *); 255void acpicpu_tstate_callback(void *); 256int acpicpu_tstate_get(struct cpu_info *, uint32_t *); 257void acpicpu_tstate_set(struct cpu_info *, uint32_t); 258 259struct cpu_info *acpicpu_md_match(device_t, cfdata_t, void *); 260struct cpu_info *acpicpu_md_attach(device_t, device_t, void *); 261 262uint32_t acpicpu_md_flags(void); 263void acpicpu_md_quirk_c1e(void); 264int acpicpu_md_cstate_start(struct acpicpu_softc *); 265int acpicpu_md_cstate_stop(void); 266void acpicpu_md_cstate_enter(int, int); 267int acpicpu_md_pstate_start(struct acpicpu_softc *); 268int acpicpu_md_pstate_stop(void); 269int acpicpu_md_pstate_init(struct acpicpu_softc *); 270uint8_t acpicpu_md_pstate_hwf(struct cpu_info *); 271int acpicpu_md_pstate_get(struct acpicpu_softc *, uint32_t *); 272int acpicpu_md_pstate_set(struct acpicpu_pstate *); 273int acpicpu_md_tstate_get(struct acpicpu_softc *, uint32_t *); 274int acpicpu_md_tstate_set(struct acpicpu_tstate *); 275 276#endif /* !_SYS_DEV_ACPI_ACPI_CPU_H */ 277