acpi_cpu.h revision 1.15
1/* $NetBSD: acpi_cpu.h,v 1.15 2010/08/14 05:13:21 jruoho Exp $ */ 2 3/*- 4 * Copyright (c) 2010 Jukka Ruohonen <jruohonen@iki.fi> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30#ifndef _SYS_DEV_ACPI_ACPI_CPU_H 31#define _SYS_DEV_ACPI_ACPI_CPU_H 32 33/* 34 * The following _PDC values are based on: 35 * 36 * Intel Corporation: Intel Processor-Specific ACPI 37 * Interface Specification, September 2006, Revision 005. 38 */ 39#define ACPICPU_PDC_REVID 0x1 40#define ACPICPU_PDC_SMP 0xA 41#define ACPICPU_PDC_MSR 0x1 42 43#define ACPICPU_PDC_P_FFH __BIT(0) /* SpeedStep MSRs */ 44#define ACPICPU_PDC_C_C1_HALT __BIT(1) /* C1 "I/O then halt" */ 45#define ACPICPU_PDC_T_FFH __BIT(2) /* OnDemand throttling MSRs */ 46#define ACPICPU_PDC_C_C1PT __BIT(3) /* SMP C1, Px, and Tx (same) */ 47#define ACPICPU_PDC_C_C2C3 __BIT(4) /* SMP C2 and C3 (same) */ 48#define ACPICPU_PDC_P_SW __BIT(5) /* SMP Px (different) */ 49#define ACPICPU_PDC_C_SW __BIT(6) /* SMP Cx (different) */ 50#define ACPICPU_PDC_T_SW __BIT(7) /* SMP Tx (different) */ 51#define ACPICPU_PDC_C_C1_FFH __BIT(8) /* SMP C1 native beyond halt */ 52#define ACPICPU_PDC_C_C2C3_FFH __BIT(9) /* SMP C2 and C2 native */ 53#define ACPICPU_PDC_P_HW __BIT(11) /* Px hardware coordination */ 54 55#define ACPICPU_PDC_GAS_HW __BIT(0) /* HW-coordinated state */ 56#define ACPICPU_PDC_GAS_BM __BIT(1) /* Bus master check required */ 57 58/* 59 * Notify values. 60 */ 61#define ACPICPU_P_NOTIFY 0x80 /* _PPC */ 62#define ACPICPU_C_NOTIFY 0x81 /* _CST */ 63#define ACPICPU_T_NOTIFY 0x82 /* _TPC */ 64 65/* 66 * C-states. 67 */ 68#define ACPICPU_C_C2_LATENCY_MAX 100 /* us */ 69#define ACPICPU_C_C3_LATENCY_MAX 1000 /* us */ 70 71#define ACPICPU_C_STATE_HALT 0x01 72#define ACPICPU_C_STATE_FFH 0x02 73#define ACPICPU_C_STATE_SYSIO 0x03 74 75/* 76 * P-states. 77 */ 78#define ACPICPU_P_STATE_MAX 255 /* Arbitrary upper limit */ 79#define ACPICPU_P_STATE_RETRY 100 80#define ACPICPU_P_STATE_UNKNOWN 0x0 81 82/* 83 * T-states. 84 */ 85#define ACPICPU_T_STATE_MAX 0x8 86#define ACPICPU_T_STATE_RETRY 0xA 87#define ACPICPU_T_STATE_UNKNOWN 255 88 89/* 90 * Flags. 91 */ 92#define ACPICPU_FLAG_C __BIT(0) /* C-states supported */ 93#define ACPICPU_FLAG_P __BIT(1) /* P-states supported */ 94#define ACPICPU_FLAG_T __BIT(2) /* T-states supported */ 95 96#define ACPICPU_FLAG_PIIX4 __BIT(3) /* Broken (quirk) */ 97 98#define ACPICPU_FLAG_C_FFH __BIT(4) /* Native C-states */ 99#define ACPICPU_FLAG_C_FADT __BIT(5) /* C-states with FADT */ 100#define ACPICPU_FLAG_C_BM __BIT(6) /* Bus master control */ 101#define ACPICPU_FLAG_C_BM_STS __BIT(7) /* Bus master check required */ 102#define ACPICPU_FLAG_C_ARB __BIT(8) /* Bus master arbitration */ 103#define ACPICPU_FLAG_C_C1E __BIT(9) /* AMD C1E detected */ 104 105#define ACPICPU_FLAG_P_FFH __BIT(10) /* Native P-states */ 106 107#define ACPICPU_FLAG_T_FFH __BIT(11) /* Native throttling */ 108#define ACPICPU_FLAG_T_FADT __BIT(12) /* Throttling with FADT */ 109 110/* 111 * This is AML_RESOURCE_GENERIC_REGISTER, 112 * included here separately for convenience. 113 */ 114struct acpicpu_reg { 115 uint8_t reg_desc; 116 uint16_t reg_reslen; 117 uint8_t reg_spaceid; 118 uint8_t reg_bitwidth; 119 uint8_t reg_bitoffset; 120 uint8_t reg_accesssize; 121 uint64_t reg_addr; 122} __packed; 123 124struct acpicpu_cstate { 125 struct evcnt cs_evcnt; 126 char cs_name[EVCNT_STRING_MAX]; 127 uint64_t cs_addr; 128 uint32_t cs_power; /* mW */ 129 uint32_t cs_latency; /* us */ 130 int cs_method; 131 int cs_flags; 132}; 133 134struct acpicpu_pstate { 135 struct evcnt ps_evcnt; 136 char ps_name[EVCNT_STRING_MAX]; 137 uint32_t ps_freq; /* MHz */ 138 uint32_t ps_power; /* mW */ 139 uint32_t ps_latency; /* us */ 140 uint32_t ps_latency_bm; /* us */ 141 uint32_t ps_control; 142 uint32_t ps_status; 143}; 144 145struct acpicpu_tstate { 146 struct evcnt ts_evcnt; 147 char ts_name[EVCNT_STRING_MAX]; 148 uint32_t ts_percent; /* % */ 149 uint32_t ts_power; /* mW */ 150 uint32_t ts_latency; /* us */ 151 uint32_t ts_control; 152 uint32_t ts_status; 153}; 154 155struct acpicpu_object { 156 uint32_t ao_procid; 157 uint32_t ao_pblklen; 158 uint32_t ao_pblkaddr; 159}; 160 161struct acpicpu_softc { 162 device_t sc_dev; 163 struct acpi_devnode *sc_node; 164 struct acpicpu_object sc_object; 165 166 struct acpicpu_cstate sc_cstate[ACPI_C_STATE_COUNT]; 167 uint32_t sc_cstate_sleep; 168 169 struct acpicpu_pstate *sc_pstate; 170 struct acpicpu_reg sc_pstate_control; 171 struct acpicpu_reg sc_pstate_status; 172 uint32_t sc_pstate_current; 173 uint32_t sc_pstate_count; 174 uint32_t sc_pstate_max; 175 176 struct acpicpu_tstate *sc_tstate; 177 struct acpicpu_reg sc_tstate_control; 178 struct acpicpu_reg sc_tstate_status; 179 uint32_t sc_tstate_current; 180 uint32_t sc_tstate_count; 181 uint32_t sc_tstate_max; 182 uint32_t sc_tstate_min; 183 184 kmutex_t sc_mtx; 185 bus_space_tag_t sc_iot; 186 bus_space_handle_t sc_ioh; 187 188 uint32_t sc_cap; 189 uint32_t sc_flags; 190 cpuid_t sc_cpuid; 191 bool sc_cold; 192 bool sc_mapped; 193}; 194 195void acpicpu_cstate_attach(device_t); 196int acpicpu_cstate_detach(device_t); 197int acpicpu_cstate_start(device_t); 198bool acpicpu_cstate_suspend(device_t); 199bool acpicpu_cstate_resume(device_t); 200void acpicpu_cstate_callback(void *); 201void acpicpu_cstate_idle(void); 202 203void acpicpu_pstate_attach(device_t); 204int acpicpu_pstate_detach(device_t); 205int acpicpu_pstate_start(device_t); 206bool acpicpu_pstate_suspend(device_t); 207bool acpicpu_pstate_resume(device_t); 208void acpicpu_pstate_callback(void *); 209int acpicpu_pstate_get(struct acpicpu_softc *, uint32_t *); 210int acpicpu_pstate_set(struct acpicpu_softc *, uint32_t); 211 212void acpicpu_tstate_attach(device_t); 213int acpicpu_tstate_detach(device_t); 214int acpicpu_tstate_start(device_t); 215bool acpicpu_tstate_suspend(device_t); 216bool acpicpu_tstate_resume(device_t); 217void acpicpu_tstate_callback(void *); 218int acpicpu_tstate_get(struct acpicpu_softc *, uint32_t *); 219int acpicpu_tstate_set(struct acpicpu_softc *, uint32_t); 220 221uint32_t acpicpu_md_cap(void); 222uint32_t acpicpu_md_quirks(void); 223uint32_t acpicpu_md_cpus_running(void); 224int acpicpu_md_idle_start(void); 225int acpicpu_md_idle_stop(void); 226void acpicpu_md_idle_enter(int, int); 227int acpicpu_md_pstate_start(void); 228int acpicpu_md_pstate_stop(void); 229int acpicpu_md_pstate_get(struct acpicpu_softc *, uint32_t *); 230int acpicpu_md_pstate_set(struct acpicpu_pstate *); 231int acpicpu_md_tstate_get(struct acpicpu_softc *, uint32_t *); 232int acpicpu_md_tstate_set(struct acpicpu_tstate *); 233 234#endif /* !_SYS_DEV_ACPI_ACPI_CPU_H */ 235