acpi_cpu.h revision 1.11 
1/* $NetBSD: acpi_cpu.h,v 1.11 2010/08/09 13:41:38 jruoho Exp $ */
2
3/*-
4 * Copyright (c) 2010 Jukka Ruohonen <jruohonen@iki.fi>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30#ifndef _SYS_DEV_ACPI_ACPI_CPU_H
31#define _SYS_DEV_ACPI_ACPI_CPU_H
32
33/*
34 * The following _PDC values are based on:
35 *
36 * 	Intel Corporation: Intel Processor-Specific ACPI
37 *	Interface Specification, September 2006, Revision 005.
38 *
39 *	http://download.intel.com/technology/IAPC/acpi/downloads/30222305.pdf
40 *
41 * For other relevant reading, see for instance:
42 *
43 *	Advanced Micro Devices: Using ACPI to Report APML P-State
44 *	Limit Changes to Operating Systems and VMM's. August 7, 2009.
45 *
46 *	http://developer.amd.com/Assets/ACPI-APML-PState-rev12.pdf
47 */
48#define ACPICPU_PDC_REVID         0x1
49#define ACPICPU_PDC_SMP           0xA
50#define ACPICPU_PDC_MSR           0x1
51
52#define ACPICPU_PDC_P_FFH         __BIT(0)	/* SpeedStep MSRs            */
53#define ACPICPU_PDC_C_C1_HALT     __BIT(1)	/* C1 "I/O then halt"        */
54#define ACPICPU_PDC_T_FFH         __BIT(2)	/* OnDemand throttling MSRs  */
55#define ACPICPU_PDC_C_C1PT        __BIT(3)	/* SMP C1, Px, and Tx (same) */
56#define ACPICPU_PDC_C_C2C3        __BIT(4)	/* SMP C2 and C3 (same)      */
57#define ACPICPU_PDC_P_SW          __BIT(5)	/* SMP Px (different)        */
58#define ACPICPU_PDC_C_SW          __BIT(6)	/* SMP Cx (different)        */
59#define ACPICPU_PDC_T_SW          __BIT(7)	/* SMP Tx (different)        */
60#define ACPICPU_PDC_C_C1_FFH      __BIT(8)	/* SMP C1 native beyond halt */
61#define ACPICPU_PDC_C_C2C3_FFH    __BIT(9)	/* SMP C2 and C2 native      */
62#define ACPICPU_PDC_P_HW          __BIT(11)	/* Px hardware coordination  */
63
64#define ACPICPU_PDC_GAS_HW	  __BIT(0)	/* HW-coordinated state      */
65#define ACPICPU_PDC_GAS_BM	  __BIT(1)	/* Bus master check required */
66
67/*
68 * Notify values.
69 */
70#define ACPICPU_P_NOTIFY	 0x80		/* _PPC */
71#define ACPICPU_C_NOTIFY	 0x81		/* _CST */
72#define ACPICPU_T_NOTIFY	 0x82		/* _TPC */
73
74/*
75 * C-states.
76 */
77#define ACPICPU_C_C2_LATENCY_MAX 100		/* us */
78#define ACPICPU_C_C3_LATENCY_MAX 1000		/* us */
79
80#define ACPICPU_C_STATE_HALT	 0x01
81#define ACPICPU_C_STATE_FFH	 0x02
82#define ACPICPU_C_STATE_SYSIO	 0x03
83
84/*
85 * P-states.
86 */
87#define ACPICPU_P_STATE_RETRY	 100
88#define ACPICPU_P_STATE_UNKNOWN	 0x0
89
90/*
91 * Flags.
92 */
93#define ACPICPU_FLAG_C		 __BIT(0)	/* C-states supported        */
94#define ACPICPU_FLAG_P		 __BIT(1)	/* P-states supported        */
95#define ACPICPU_FLAG_T		 __BIT(2)	/* T-states supported        */
96
97#define ACPICPU_FLAG_C_CST	 __BIT(3)	/* C-states with _CST	     */
98#define ACPICPU_FLAG_C_FADT	 __BIT(4)	/* C-states with FADT        */
99#define ACPICPU_FLAG_C_BM	 __BIT(5)	/* Bus master control        */
100#define ACPICPU_FLAG_C_BM_STS	 __BIT(6)	/* Bus master check required */
101#define ACPICPU_FLAG_C_ARB	 __BIT(7)	/* Bus master arbitration    */
102#define ACPICPU_FLAG_C_NOC3	 __BIT(8)	/* C3 disabled (quirk)       */
103#define ACPICPU_FLAG_C_FFH	 __BIT(9)	/* MONITOR/MWAIT supported   */
104#define ACPICPU_FLAG_C_C1E	 __BIT(10)	/* AMD C1E detected	     */
105
106#define ACPICPU_FLAG_P_PPC	 __BIT(11)	/* Dynamic freq. with _PPC   */
107#define ACPICPU_FLAG_P_FFH	 __BIT(12)	/* EST etc. supported        */
108
109/*
110 * This is AML_RESOURCE_GENERIC_REGISTER,
111 * included here separately for convenience.
112 */
113struct acpicpu_reg {
114	uint8_t			 reg_desc;
115	uint16_t		 reg_reslen;
116	uint8_t			 reg_spaceid;
117	uint8_t			 reg_bitwidth;
118	uint8_t			 reg_bitoffset;
119	uint8_t			 reg_accesssize;
120	uint64_t		 reg_addr;
121} __packed;
122
123struct acpicpu_cstate {
124	uint64_t		 cs_stat;
125	uint64_t		 cs_addr;
126	uint32_t		 cs_power;	/* mW */
127	uint32_t		 cs_latency;	/* us */
128	int			 cs_method;
129	int			 cs_flags;
130};
131
132struct acpicpu_pstate {
133	uint64_t		 ps_stat;
134	uint32_t		 ps_freq;	/* MHz */
135	uint32_t		 ps_power;	/* mW */
136	uint32_t		 ps_latency;	/* us */
137	uint32_t		 ps_latency_bm; /* us */
138	uint32_t		 ps_control;
139	uint32_t		 ps_status;
140};
141
142struct acpicpu_object {
143	uint32_t		 ao_procid;
144	uint32_t		 ao_pblklen;
145	uint32_t		 ao_pblkaddr;
146};
147
148struct acpicpu_softc {
149	device_t		 sc_dev;
150	struct acpi_devnode	*sc_node;
151	struct acpicpu_object	 sc_object;
152
153	struct acpicpu_cstate	 sc_cstate[ACPI_C_STATE_COUNT];
154	uint32_t		 sc_cstate_sleep;
155
156	struct acpicpu_pstate	*sc_pstate;
157	struct acpicpu_reg	 sc_pstate_control;
158	struct acpicpu_reg	 sc_pstate_status;
159	uint32_t		 sc_pstate_current;
160	uint32_t		 sc_pstate_count;
161	uint32_t		 sc_pstate_max;
162
163	kmutex_t		 sc_mtx;
164	bus_space_tag_t		 sc_iot;
165	bus_space_handle_t	 sc_ioh;
166
167	uint32_t		 sc_cap;
168	uint32_t		 sc_flags;
169	cpuid_t			 sc_cpuid;
170	bool			 sc_cold;
171	bool			 sc_mapped;
172};
173
174void		acpicpu_cstate_attach(device_t);
175int		acpicpu_cstate_detach(device_t);
176int		acpicpu_cstate_start(device_t);
177bool		acpicpu_cstate_suspend(device_t);
178bool		acpicpu_cstate_resume(device_t);
179void		acpicpu_cstate_callback(void *);
180void		acpicpu_cstate_idle(void);
181
182void		acpicpu_pstate_attach(device_t);
183int		acpicpu_pstate_detach(device_t);
184int		acpicpu_pstate_start(device_t);
185bool		acpicpu_pstate_suspend(device_t);
186bool		acpicpu_pstate_resume(device_t);
187void		acpicpu_pstate_callback(void *);
188int		acpicpu_pstate_get(struct acpicpu_softc *, uint32_t *);
189int		acpicpu_pstate_set(struct acpicpu_softc *, uint32_t);
190
191uint32_t	acpicpu_md_cap(void);
192uint32_t	acpicpu_md_quirks(void);
193uint32_t	acpicpu_md_cpus_running(void);
194int		acpicpu_md_idle_start(void);
195int		acpicpu_md_idle_stop(void);
196void		acpicpu_md_idle_enter(int, int);
197int		acpicpu_md_pstate_start(void);
198int		acpicpu_md_pstate_stop(void);
199int		acpicpu_md_pstate_get(struct acpicpu_softc *, uint32_t *);
200int		acpicpu_md_pstate_set(struct acpicpu_pstate *);
201
202#endif	/* !_SYS_DEV_ACPI_ACPI_CPU_H */
203