intrdefs.h revision 1.10 
1/*	$NetBSD: intrdefs.h,v 1.10 2007/10/17 19:58:15 garbled Exp $	*/
2
3#ifndef _X86_INTRDEFS_H_
4#define _X86_INTRDEFS_H_
5
6/*
7 * Interrupt priority levels.
8 *
9 * There are tty, network and disk drivers that use free() at interrupt
10 * time, so imp > (tty | net | bio).
11 *
12 * Since run queues may be manipulated by both the statclock and tty,
13 * network, and disk drivers, clock > imp.
14 *
15 * IPL_HIGH must block everything that can manipulate a run queue.
16 *
17 * We need serial drivers to run at the absolute highest priority to
18 * avoid overruns, so serial > high.
19 *
20 * The level numbers are picked to fit into APIC vector priorities.
21 *
22 */
23#define	IPL_NONE	0x0	/* nothing */
24#define	IPL_SOFTCLOCK	0x1	/* timeouts */
25#define	IPL_SOFTBIO	0x2	/* block I/O */
26#define	IPL_SOFTNET	0x3	/* protocol stacks */
27#define	IPL_SOFTSERIAL	0x4	/* serial */
28#define	IPL_BIO		0x5	/* block I/O */
29#define	IPL_NET		0x5	/* network */
30#define	IPL_TTY		0x5	/* terminal */
31#define	IPL_LPT		0x5
32#define	IPL_VM		0x5	/* memory allocation */
33#define	IPL_AUDIO	0x5	/* audio */
34#define	IPL_CLOCK	0x6	/* clock */
35#define	IPL_STATCLOCK	0x6
36#define IPL_SCHED	0x6
37#define	IPL_HIGH	0x7	/* everything */
38#define	IPL_SERIAL	0x7	/* serial */
39#define IPL_IPI		0x7	/* inter-processor interrupts */
40#define	NIPL		8
41
42/* Interrupt sharing types. */
43#define	IST_NONE	0	/* none */
44#define	IST_PULSE	1	/* pulsed */
45#define	IST_EDGE	2	/* edge-triggered */
46#define	IST_LEVEL	3	/* level-triggered */
47
48/*
49 * Local APIC masks and software interrupt masks, in order
50 * of priority.  Must not conflict with SIR_* below.
51 */
52#define LIR_IPI		31
53#define LIR_TIMER	30
54
55/*
56 * XXX These should be lowest numbered, but right now would
57 * conflict with the legacy IRQs.  Their current position
58 * means that soft interrupt take priority over hardware
59 * interrupts when lowering the priority level!
60 */
61#define	SIR_SERIAL	29
62#define	SIR_NET		28
63#define	SIR_BIO		27
64#define	SIR_CLOCK	26
65
66/*
67 * Maximum # of interrupt sources per CPU. 32 to fit in one word.
68 * ioapics can theoretically produce more, but it's not likely to
69 * happen. For multiple ioapics, things can be routed to different
70 * CPUs.
71 */
72#define MAX_INTR_SOURCES	32
73#define NUM_LEGACY_IRQS		16
74
75/*
76 * Low and high boundaries between which interrupt gates will
77 * be allocated in the IDT.
78 */
79#define IDT_INTR_LOW	(0x20 + NUM_LEGACY_IRQS)
80#define IDT_INTR_HIGH	0xef
81
82#define X86_IPI_HALT			0x00000001
83#define X86_IPI_MICROSET		0x00000002
84#define X86_IPI_FLUSH_FPU		0x00000004
85#define X86_IPI_SYNCH_FPU		0x00000008
86#define X86_IPI_MTRR			0x00000010
87#define X86_IPI_GDT			0x00000020
88#define X86_IPI_WRITE_MSR		0x00000040
89
90#define X86_NIPI		7
91
92#define X86_IPI_NAMES { "halt IPI", "timeset IPI", "FPU flush IPI", \
93			 "FPU synch IPI", "MTRR update IPI", \
94			 "GDT update IPI", "MSR write IPI" }
95
96#define IREENT_MAGIC	0x18041969
97
98#endif /* _X86_INTRDEFS_H_ */
99