1/* $NetBSD: dbregs.h,v 1.8 2019/01/13 10:01:07 maxv Exp $ */ 2 3/* 4 * Copyright (c) 2016 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef _X86_DBREGS_H_ 30#define _X86_DBREGS_H_ 31 32#include <sys/param.h> 33#include <sys/types.h> 34#include <machine/reg.h> 35 36/* 37 * CPU Debug Status Register (DR6) 38 * 39 * Reserved bits: 4-12 and on x86_64 32-64 40 */ 41#define X86_DR6_DR0_BREAKPOINT_CONDITION_DETECTED __BIT(0) 42#define X86_DR6_DR1_BREAKPOINT_CONDITION_DETECTED __BIT(1) 43#define X86_DR6_DR2_BREAKPOINT_CONDITION_DETECTED __BIT(2) 44#define X86_DR6_DR3_BREAKPOINT_CONDITION_DETECTED __BIT(3) 45#define X86_DR6_DEBUG_REGISTER_ACCESS_DETECTED __BIT(13) 46#define X86_DR6_SINGLE_STEP __BIT(14) 47#define X86_DR6_TASK_SWITCH __BIT(15) 48#define X86_DR6_MBZ __BITS(32, 63) 49 50/* 51 * CPU Debug Control Register (DR7) 52 * 53 * LOCAL_EXACT_BREAKPOINT and GLOBAL_EXACT_BREAKPOINT are no longer used 54 * since the P6 processor family - portable code should set these bits 55 * unconditionally in order to get exact breakpoints. 56 * 57 * Reserved bits: 10, 12, 14-15 and on x86_64 32-64. 58 */ 59#define X86_DR7_LOCAL_DR0_BREAKPOINT __BIT(0) 60#define X86_DR7_GLOBAL_DR0_BREAKPOINT __BIT(1) 61#define X86_DR7_LOCAL_DR1_BREAKPOINT __BIT(2) 62#define X86_DR7_GLOBAL_DR1_BREAKPOINT __BIT(3) 63#define X86_DR7_LOCAL_DR2_BREAKPOINT __BIT(4) 64#define X86_DR7_GLOBAL_DR2_BREAKPOINT __BIT(5) 65#define X86_DR7_LOCAL_DR3_BREAKPOINT __BIT(6) 66#define X86_DR7_GLOBAL_DR3_BREAKPOINT __BIT(7) 67#define X86_DR7_LOCAL_EXACT_BREAKPOINT __BIT(8) 68#define X86_DR7_GLOBAL_EXACT_BREAKPOINT __BIT(9) 69#define X86_DR7_RESTRICTED_TRANSACTIONAL_MEMORY __BIT(11) 70#define X86_DR7_GENERAL_DETECT_ENABLE __BIT(13) 71#define X86_DR7_DR0_CONDITION_MASK __BITS(16, 17) 72#define X86_DR7_DR0_LENGTH_MASK __BITS(18, 19) 73#define X86_DR7_DR1_CONDITION_MASK __BITS(20, 21) 74#define X86_DR7_DR1_LENGTH_MASK __BITS(22, 23) 75#define X86_DR7_DR2_CONDITION_MASK __BITS(24, 25) 76#define X86_DR7_DR2_LENGTH_MASK __BITS(26, 27) 77#define X86_DR7_DR3_CONDITION_MASK __BITS(28, 29) 78#define X86_DR7_DR3_LENGTH_MASK __BITS(30, 31) 79#define X86_DR7_MBZ __BITS(32, 63) 80 81/* 82 * X86_DR7_CONDITION_IO_READWRITE is currently unused. It requires DE 83 * (debug extension) flag in control register CR4 set, and not all CPUs 84 * support it. 85 */ 86enum x86_dr7_condition { 87 X86_DR7_CONDITION_EXECUTION = 0x0, 88 X86_DR7_CONDITION_DATA_WRITE = 0x1, 89 X86_DR7_CONDITION_IO_READWRITE = 0x2, 90 X86_DR7_CONDITION_DATA_READWRITE = 0x3 91}; 92 93/* 94 * 0x2 is currently unimplemented - it reflects 8 bytes on modern CPUs. 95 */ 96enum x86_dr7_length { 97 X86_DR7_LENGTH_BYTE = 0x0, 98 X86_DR7_LENGTH_TWOBYTES = 0x1, 99 /* 0x2 undefined */ 100 X86_DR7_LENGTH_FOURBYTES = 0x3 101}; 102 103/* 104 * The number of available watchpoint/breakpoint registers available since 105 * Intel 80386. New CPUs (x86_64) ship with up to 16 Debug Registers but they 106 * still offer the same number of watchpoints/breakpoints. 107 */ 108#define X86_DBREGS 4 109 110void x86_dbregs_init(void); 111void x86_dbregs_clear(struct lwp *); 112void x86_dbregs_abandon(struct lwp *); 113void x86_dbregs_read(struct lwp *, struct dbreg *); 114 115void x86_dbregs_save(struct lwp *); 116void x86_dbregs_restore(struct lwp *); 117 118void x86_dbregs_store_dr6(struct lwp *); 119int x86_dbregs_user_trap(void); 120int x86_dbregs_validate(const struct dbreg *); 121void x86_dbregs_write(struct lwp *, const struct dbreg *); 122void x86_dbregs_switch(struct lwp *, struct lwp *); 123 124#endif /* !_X86_DBREGS_H_ */ 125