asc_vsbus.c revision 1.9
1/*	$NetBSD: asc_vsbus.c,v 1.9 2000/04/17 20:36:23 ragge Exp $	*/
2
3/*-
4 * Copyright (c) 1998 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Charles M. Hannum.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 *    must display the following acknowledgement:
20 *	  This product includes software developed by the NetBSD
21 *	  Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 *    contributors may be used to endorse or promote products derived
24 *    from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#include "opt_vax46.h"
40
41#include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
42
43__KERNEL_RCSID(0, "$NetBSD: asc_vsbus.c,v 1.9 2000/04/17 20:36:23 ragge Exp $");
44
45#include <sys/types.h>
46#include <sys/param.h>
47#include <sys/systm.h>
48#include <sys/kernel.h>
49#include <sys/errno.h>
50#include <sys/ioctl.h>
51#include <sys/device.h>
52#include <sys/buf.h>
53#include <sys/proc.h>
54#include <sys/user.h>
55#include <sys/reboot.h>
56#include <sys/queue.h>
57
58#include <dev/scsipi/scsi_all.h>
59#include <dev/scsipi/scsipi_all.h>
60#include <dev/scsipi/scsiconf.h>
61#include <dev/scsipi/scsi_message.h>
62
63#include <machine/bus.h>
64#include <machine/vmparam.h>
65
66#include <dev/ic/ncr53c9xreg.h>
67#include <dev/ic/ncr53c9xvar.h>
68
69#include <machine/cpu.h>
70#include <machine/sid.h>
71#include <machine/rpb.h>
72#include <machine/scb.h>
73#include <machine/vsbus.h>
74#include <machine/clock.h>	/* for SCSI ctlr ID# XXX */
75
76struct asc_vsbus_softc {
77	struct ncr53c9x_softc sc_ncr53c9x;	/* Must be first */
78	bus_space_tag_t sc_bst;			/* bus space tag */
79	bus_space_handle_t sc_bsh;		/* bus space handle */
80	bus_space_handle_t sc_ncrh;		/* ncr bus space handle */
81	bus_dma_tag_t sc_dmat;			/* bus dma tag */
82	bus_dmamap_t sc_dmamap;
83	caddr_t *sc_dmaaddr;
84	size_t *sc_dmalen;
85	size_t sc_dmasize;
86	unsigned int sc_flags;
87#define	ASC_FROMMEMORY		0x0001		/* Must be 1 */
88#define	ASC_DMAACTIVE		0x0002
89#define	ASC_MAPLOADED		0x0004
90	unsigned long sc_xfers;
91};
92
93#define	ASC_REG_ADR		0x0000
94#define	ASC_REG_DIR		0x000C
95#define	ASC_REG_NCR		0x0080
96#define	ASC_REG_END		0x00B0
97
98#define	ASC_MAXXFERSIZE		65536
99#define	ASC_FREQUENCY		25000000
100
101static int asc_vsbus_match __P((struct device *, struct cfdata *, void *));
102static void asc_vsbus_attach __P((struct device *, struct device *, void *));
103
104struct cfattach asc_vsbus_ca = {
105	sizeof(struct asc_vsbus_softc), asc_vsbus_match, asc_vsbus_attach
106};
107
108static struct scsipi_device asc_vsbus_dev = {
109	NULL,			/* Use the default error handler */
110	NULL,			/* have a queue, served by this */
111	NULL,			/* have no async handler */
112	NULL,			/* use the default done handler */
113};
114
115/*
116 * Functions and the switch for the MI code
117 */
118static u_char	asc_vsbus_read_reg __P((struct ncr53c9x_softc *, int));
119static void	asc_vsbus_write_reg __P((struct ncr53c9x_softc *, int, u_char));
120static int	asc_vsbus_dma_isintr __P((struct ncr53c9x_softc *));
121static void	asc_vsbus_dma_reset __P((struct ncr53c9x_softc *));
122static int	asc_vsbus_dma_intr __P((struct ncr53c9x_softc *));
123static int	asc_vsbus_dma_setup __P((struct ncr53c9x_softc *, caddr_t *,
124		    size_t *, int, size_t *));
125static void	asc_vsbus_dma_go __P((struct ncr53c9x_softc *));
126static void	asc_vsbus_dma_stop __P((struct ncr53c9x_softc *));
127static int	asc_vsbus_dma_isactive __P((struct ncr53c9x_softc *));
128
129static struct ncr53c9x_glue asc_vsbus_glue = {
130	asc_vsbus_read_reg,
131	asc_vsbus_write_reg,
132	asc_vsbus_dma_isintr,
133	asc_vsbus_dma_reset,
134	asc_vsbus_dma_intr,
135	asc_vsbus_dma_setup,
136	asc_vsbus_dma_go,
137	asc_vsbus_dma_stop,
138	asc_vsbus_dma_isactive,
139	NULL,
140};
141
142static int
143asc_vsbus_match( struct device *parent, struct cfdata *cf, void *aux)
144{
145	struct vsbus_attach_args *va = aux;
146	int dummy;
147	volatile u_int8_t *ncr_regs;
148
149	if (vax_boardtype != VAX_BTYP_46
150	   && vax_boardtype != VAX_BTYP_48
151	   /* && vax_boardtype != VAX_BTYP_49 */)
152		return 0;
153
154	ncr_regs = (volatile u_int8_t *) va->va_addr;
155
156	/*  *** need to generate an interrupt here
157	 * From trial and error, I've determined that an INT is generated
158	 * only when the following sequence of events occurs:
159	 *   1) The interrupt status register (0x05) must be read.
160	 *   2) SCSI bus reset interrupt must be enabled
161	 *   3) SCSI bus reset command must be sent
162	 *   4) NOP command must be sent
163	 */
164
165	dummy = ncr_regs[NCR_INTR << 2] & 0xFF;
166        ncr_regs[NCR_CFG1 << 2] = 0x06; /* we're ID 6, turn on INT for SCSI reset */
167        ncr_regs[NCR_CMD << 2] = NCRCMD_RSTSCSI; /* send the reset */
168        ncr_regs[NCR_CMD << 2] = NCRCMD_NOP; /* send a NOP */
169	DELAY(10000);
170
171	dummy = ncr_regs[NCR_INTR << 2] & 0xFF;
172	return (dummy & NCRINTR_SBR) != 0;
173}
174
175
176/*
177 * Attach this instance, and then all the sub-devices
178 */
179static void
180asc_vsbus_attach(struct device *parent, struct device *self, void *aux)
181{
182	struct vsbus_attach_args *va = aux;
183	struct asc_vsbus_softc *asc = (void *)self;
184	struct ncr53c9x_softc *sc = &asc->sc_ncr53c9x;
185	int error;
186
187	/*
188	 * Set up glue for MI code early; we use some of it here.
189	 */
190	sc->sc_glue = &asc_vsbus_glue;
191
192	asc->sc_bst = va->va_iot;
193	asc->sc_dmat = va->va_dmat;
194
195	error = bus_space_map(asc->sc_bst, va->va_paddr - ASC_REG_NCR,
196	    ASC_REG_END, 0, &asc->sc_bsh);
197	if (error) {
198		printf(": failed to map registers: error=%d\n", error);
199		return;
200	}
201	error = bus_space_subregion(asc->sc_bst, asc->sc_bsh, ASC_REG_NCR,
202	    ASC_REG_END - ASC_REG_NCR, &asc->sc_ncrh);
203	if (error) {
204		printf(": failed to map ncr registers: error=%d\n", error);
205		return;
206	}
207	error = bus_dmamap_create(asc->sc_dmat, ASC_MAXXFERSIZE, 1,
208	    ASC_MAXXFERSIZE, 0, BUS_DMA_NOWAIT, &asc->sc_dmamap);
209
210	switch (vax_boardtype) {
211#if defined(VAX46)
212	case VAX_BTYP_46:
213		sc->sc_id = (clk_page[0xbc/2] >> clk_tweak) & 7;
214		break;
215#endif
216	default:
217		sc->sc_id = 6;	/* XXX need to get this from VMB */
218		break;
219	}
220printf("SCSIid: %d ", sc->sc_id);
221	sc->sc_freq = ASC_FREQUENCY;
222
223	/* gimme Mhz */
224	sc->sc_freq /= 1000000;
225
226	scb_vecalloc(va->va_cvec, (void (*)(void *)) ncr53c9x_intr,
227	    &asc->sc_ncr53c9x, SCB_ISTACK);
228
229	/*
230	 * XXX More of this should be in ncr53c9x_attach(), but
231	 * XXX should we really poke around the chip that much in
232	 * XXX the MI code?  Think about this more...
233	 */
234
235	/*
236	 * Set up static configuration info.
237	 */
238	sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
239	sc->sc_cfg2 = NCRCFG2_SCSI2;
240	sc->sc_cfg3 = 0;
241	sc->sc_rev = NCR_VARIANT_NCR53C94;
242
243	/*
244	 * XXX minsync and maxxfer _should_ be set up in MI code,
245	 * XXX but it appears to have some dependency on what sort
246	 * XXX of DMA we're hooked up to, etc.
247	 */
248
249	/*
250	 * This is the value used to start sync negotiations
251	 * Note that the NCR register "SYNCTP" is programmed
252	 * in "clocks per byte", and has a minimum value of 4.
253	 * The SCSI period used in negotiation is one-fourth
254	 * of the time (in nanoseconds) needed to transfer one byte.
255	 * Since the chip's clock is given in MHz, we have the following
256	 * formula: 4 * period = (1000 / freq) * 4
257	 */
258	sc->sc_minsync = (1000 / sc->sc_freq);
259	sc->sc_maxxfer = 63 * 1024;
260
261	printf("\n%s", self->dv_xname);	/* Pretty print */
262
263	/* Do the common parts of attachment. */
264	sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd;
265	sc->sc_adapter.scsipi_minphys = minphys;
266	ncr53c9x_attach(sc, &asc_vsbus_dev);
267
268	/*
269	 * Register this device as boot device if we booted from it.
270	 * This will fail if there are more than one le in a machine,
271	 * fortunately there may be only one.
272	 */
273	if (B_TYPE(bootdev) == BDEV_SD)
274		booted_from = self;
275}
276
277/*
278 * Glue functions.
279 */
280
281static u_char
282asc_vsbus_read_reg(struct ncr53c9x_softc *sc, int reg)
283{
284	struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc;
285
286	return bus_space_read_1(asc->sc_bst, asc->sc_ncrh,
287	    reg * sizeof(u_int32_t));
288}
289
290static void
291asc_vsbus_write_reg(sc, reg, val)
292	struct ncr53c9x_softc *sc;
293	int reg;
294	u_char val;
295{
296	struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc;
297
298	bus_space_write_1(asc->sc_bst, asc->sc_ncrh,
299	    reg * sizeof(u_int32_t), val);
300}
301
302static int
303asc_vsbus_dma_isintr(sc)
304	struct ncr53c9x_softc *sc;
305{
306	struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc;
307	return bus_space_read_1(asc->sc_bst, asc->sc_ncrh,
308	    NCR_STAT * sizeof(u_int32_t)) & NCRSTAT_INT;
309}
310
311static void
312asc_vsbus_dma_reset(sc)
313	struct ncr53c9x_softc *sc;
314{
315	struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc;
316
317	if (asc->sc_flags & ASC_MAPLOADED)
318		bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap);
319	asc->sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED);
320}
321
322static int
323asc_vsbus_dma_intr(sc)
324	struct ncr53c9x_softc *sc;
325{
326	struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc;
327	u_int tcl, tcm;
328	int trans, resid;
329
330	if ((asc->sc_flags & ASC_DMAACTIVE) == 0)
331		panic("asc_vsbus_dma_intr: DMA wasn't active");
332
333	asc->sc_flags &= ~ASC_DMAACTIVE;
334
335	if (asc->sc_dmasize == 0) {
336		/* A "Transfer Pad" operation completed */
337		tcl = NCR_READ_REG(sc, NCR_TCL);
338		tcm = NCR_READ_REG(sc, NCR_TCM);
339		NCR_DMA(("asc_vsbus_intr: discarded %d bytes (tcl=%d, tcm=%d)\n",
340		    tcl | (tcm << 8), tcl, tcm));
341		return 0;
342	}
343
344	resid = 0;
345	if ((resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) {
346		NCR_DMA(("asc_vsbus_intr: empty FIFO of %d ", resid));
347		DELAY(1);
348	}
349	if (asc->sc_flags & ASC_MAPLOADED) {
350		bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap,
351				0, asc->sc_dmasize,
352				asc->sc_flags & ASC_FROMMEMORY
353					? BUS_DMASYNC_POSTWRITE
354					: BUS_DMASYNC_POSTREAD);
355		bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap);
356	}
357	asc->sc_flags &= ~ASC_MAPLOADED;
358
359	resid += (tcl = NCR_READ_REG(sc, NCR_TCL));
360	resid += (tcm = NCR_READ_REG(sc, NCR_TCM)) << 8;
361
362	trans = asc->sc_dmasize - resid;
363	if (trans < 0) {			/* transferred < 0 ? */
364		printf("asc_vsbus_intr: xfer (%d) > req (%d)\n",
365		    trans, asc->sc_dmasize);
366		trans = asc->sc_dmasize;
367	}
368	NCR_DMA(("asc_vsbus_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n",
369	    tcl, tcm, trans, resid));
370
371	*asc->sc_dmalen -= trans;
372	*asc->sc_dmaaddr += trans;
373
374	asc->sc_xfers++;
375	return 0;
376}
377
378static int
379asc_vsbus_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len,
380		    int datain, size_t *dmasize)
381{
382	struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc;
383
384	asc->sc_dmaaddr = addr;
385	asc->sc_dmalen = len;
386	if (datain) {
387		asc->sc_flags &= ~ASC_FROMMEMORY;
388	} else {
389		asc->sc_flags |= ASC_FROMMEMORY;
390	}
391	if ((vaddr_t) *asc->sc_dmaaddr < VM_MIN_KERNEL_ADDRESS)
392		panic("asc_vsbus_dma_setup: dma address (%p) outside of kernel",
393		    *asc->sc_dmaaddr);
394
395        NCR_DMA(("%s: start %d@%p,%d\n", sc->sc_dev.dv_xname,
396                (int)*asc->sc_dmalen, *asc->sc_dmaaddr, (asc->sc_flags & ASC_FROMMEMORY)));
397	*dmasize = asc->sc_dmasize = min(*dmasize, ASC_MAXXFERSIZE);
398
399	if (asc->sc_dmasize) {
400		if (bus_dmamap_load(asc->sc_dmat, asc->sc_dmamap,
401				*asc->sc_dmaaddr, asc->sc_dmasize,
402				NULL /* kernel address */,
403				BUS_DMA_NOWAIT|VAX_BUS_DMA_SPILLPAGE))
404			panic("%s: cannot load dma map", sc->sc_dev.dv_xname);
405		bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap,
406				0, asc->sc_dmasize,
407				asc->sc_flags & ASC_FROMMEMORY
408					? BUS_DMASYNC_PREWRITE
409					: BUS_DMASYNC_PREREAD);
410		bus_space_write_4(asc->sc_bst, asc->sc_bsh, ASC_REG_ADR,
411				  asc->sc_dmamap->dm_segs[0].ds_addr);
412		bus_space_write_4(asc->sc_bst, asc->sc_bsh, ASC_REG_DIR,
413				  asc->sc_flags & ASC_FROMMEMORY);
414		asc->sc_flags |= ASC_MAPLOADED;
415	}
416
417	return 0;
418}
419
420static void
421asc_vsbus_dma_go(struct ncr53c9x_softc *sc)
422{
423	struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc;
424
425	asc->sc_flags |= ASC_DMAACTIVE;
426}
427
428static void
429asc_vsbus_dma_stop(struct ncr53c9x_softc *sc)
430{
431	struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc;
432
433	if (asc->sc_flags & ASC_MAPLOADED) {
434		bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap,
435				0, asc->sc_dmasize,
436				asc->sc_flags & ASC_FROMMEMORY
437					? BUS_DMASYNC_POSTWRITE
438					: BUS_DMASYNC_POSTREAD);
439		bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap);
440	}
441
442	asc->sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED);
443}
444
445static int
446asc_vsbus_dma_isactive(struct ncr53c9x_softc *sc)
447{
448	struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc;
449
450	return (asc->sc_flags & ASC_DMAACTIVE) != 0;
451}
452