asc_vsbus.c revision 1.38
1/* $NetBSD: asc_vsbus.c,v 1.38 2008/03/11 05:34:03 matt Exp $ */ 2 3/*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 40 41__KERNEL_RCSID(0, "$NetBSD: asc_vsbus.c,v 1.38 2008/03/11 05:34:03 matt Exp $"); 42 43#include "locators.h" 44#include "opt_cputype.h" 45 46#include <sys/types.h> 47#include <sys/param.h> 48#include <sys/systm.h> 49#include <sys/kernel.h> 50#include <sys/errno.h> 51#include <sys/ioctl.h> 52#include <sys/device.h> 53#include <sys/buf.h> 54#include <sys/proc.h> 55#include <sys/user.h> 56#include <sys/reboot.h> 57#include <sys/queue.h> 58 59#include <dev/scsipi/scsi_all.h> 60#include <dev/scsipi/scsipi_all.h> 61#include <dev/scsipi/scsiconf.h> 62#include <dev/scsipi/scsi_message.h> 63 64#include <machine/bus.h> 65#include <machine/vmparam.h> 66 67#include <dev/ic/ncr53c9xreg.h> 68#include <dev/ic/ncr53c9xvar.h> 69 70#include <machine/cpu.h> 71#include <machine/sid.h> 72#include <machine/scb.h> 73#include <machine/vsbus.h> 74#include <machine/clock.h> /* for SCSI ctlr ID# XXX */ 75 76struct asc_vsbus_softc { 77 struct ncr53c9x_softc sc_ncr53c9x; /* Must be first */ 78 struct evcnt sc_intrcnt; /* count interrupts */ 79 bus_space_tag_t sc_bst; /* bus space tag */ 80 bus_space_handle_t sc_bsh; /* bus space handle */ 81 bus_space_handle_t sc_dirh; /* scsi direction handle */ 82 bus_space_handle_t sc_adrh; /* scsi address handle */ 83 bus_space_handle_t sc_ncrh; /* ncr bus space handle */ 84 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 85 bus_dmamap_t sc_dmamap; 86 void **sc_dmaaddr; 87 size_t *sc_dmalen; 88 size_t sc_dmasize; 89 unsigned int sc_flags; 90#define ASC_FROMMEMORY 0x0001 /* Must be 1 */ 91#define ASC_DMAACTIVE 0x0002 92#define ASC_MAPLOADED 0x0004 93 unsigned long sc_xfers; 94}; 95 96#define ASC_REG_KA46_ADR 0x0000 97#define ASC_REG_KA46_DIR 0x000C 98#define ASC_REG_KA49_ADR 0x0000 99#define ASC_REG_KA49_DIR 0x0004 100#define ASC_REG_NCR 0x0080 101#define ASC_REG_END 0x00B0 102 103#define ASC_MAXXFERSIZE 65536 104#define ASC_FREQUENCY 25000000 105 106static int asc_vsbus_match(device_t, cfdata_t, void *); 107static void asc_vsbus_attach(device_t, device_t, void *); 108 109CFATTACH_DECL(asc_vsbus, sizeof(struct asc_vsbus_softc), 110 asc_vsbus_match, asc_vsbus_attach, NULL, NULL); 111 112/* 113 * Functions and the switch for the MI code 114 */ 115static u_char asc_vsbus_read_reg(struct ncr53c9x_softc *, int); 116static void asc_vsbus_write_reg(struct ncr53c9x_softc *, int, u_char); 117static int asc_vsbus_dma_isintr(struct ncr53c9x_softc *); 118static void asc_vsbus_dma_reset(struct ncr53c9x_softc *); 119static int asc_vsbus_dma_intr(struct ncr53c9x_softc *); 120static int asc_vsbus_dma_setup(struct ncr53c9x_softc *, void **, 121 size_t *, int, size_t *); 122static void asc_vsbus_dma_go(struct ncr53c9x_softc *); 123static void asc_vsbus_dma_stop(struct ncr53c9x_softc *); 124static int asc_vsbus_dma_isactive(struct ncr53c9x_softc *); 125 126static const struct ncr53c9x_glue asc_vsbus_glue = { 127 .gl_read_reg = asc_vsbus_read_reg, 128 .gl_write_reg = asc_vsbus_write_reg, 129 .gl_dma_isintr = asc_vsbus_dma_isintr, 130 .gl_dma_reset = asc_vsbus_dma_reset, 131 .gl_dma_intr = asc_vsbus_dma_intr, 132 .gl_dma_setup = asc_vsbus_dma_setup, 133 .gl_dma_go = asc_vsbus_dma_go, 134 .gl_dma_stop = asc_vsbus_dma_stop, 135 .gl_dma_isactive = asc_vsbus_dma_isactive, 136}; 137 138static uint8_t asc_attached; /* can't have more than one asc */ 139 140static int 141asc_vsbus_match( device_t parent, cfdata_t cf, void *aux) 142{ 143 struct vsbus_attach_args * const va = aux; 144 volatile uint8_t *ncr_regs; 145 int dummy; 146 147 if (asc_attached) 148 return 0; 149 150 if (vax_boardtype == VAX_BTYP_46 || vax_boardtype == VAX_BTYP_48) { 151 if (cf->cf_loc[VSBUSCF_CSR] != 0x200c0080) 152 return 0; 153 } else if (vax_boardtype == VAX_BTYP_49 || 154 vax_boardtype == VAX_BTYP_53) { 155 if (cf->cf_loc[VSBUSCF_CSR] != 0x26000080) 156 return 0; 157 } else { 158 return 0; 159 } 160 161 ncr_regs = (volatile uint8_t *) va->va_addr; 162 163 /* *** need to generate an interrupt here 164 * From trial and error, I've determined that an INT is generated 165 * only when the following sequence of events occurs: 166 * 1) The interrupt status register (0x05) must be read. 167 * 2) SCSI bus reset interrupt must be enabled 168 * 3) SCSI bus reset command must be sent 169 * 4) NOP command must be sent 170 */ 171 172 dummy = ncr_regs[NCR_INTR << 2] & 0xFF; 173 ncr_regs[NCR_CFG1 << 2] = 0x06; /* we're ID 6, turn on INT for SCSI reset */ 174 ncr_regs[NCR_CMD << 2] = NCRCMD_RSTSCSI; /* send the reset */ 175 ncr_regs[NCR_CMD << 2] = NCRCMD_NOP; /* send a NOP */ 176 DELAY(10000); 177 178 dummy = ncr_regs[NCR_INTR << 2] & 0xFF; 179 return (dummy & NCRINTR_SBR) != 0; 180} 181 182 183/* 184 * Attach this instance, and then all the sub-devices 185 */ 186static void 187asc_vsbus_attach(device_t parent, device_t self, void *aux) 188{ 189 struct vsbus_attach_args * const va = aux; 190 struct asc_vsbus_softc * const asc = device_private(self); 191 struct ncr53c9x_softc * const sc = &asc->sc_ncr53c9x; 192 int error; 193 194 asc_attached = 1; 195 /* 196 * Set up glue for MI code early; we use some of it here. 197 */ 198 sc->sc_glue = &asc_vsbus_glue; 199 200 asc->sc_bst = va->va_memt; 201 asc->sc_dmat = va->va_dmat; 202 203 error = bus_space_map(asc->sc_bst, va->va_paddr - ASC_REG_NCR, 204 ASC_REG_END, 0, &asc->sc_bsh); 205 if (error) { 206 aprint_error(": failed to map registers: error=%d\n", error); 207 return; 208 } 209 error = bus_space_subregion(asc->sc_bst, asc->sc_bsh, ASC_REG_NCR, 210 ASC_REG_END - ASC_REG_NCR, &asc->sc_ncrh); 211 if (error) { 212 aprint_error(": failed to map ncr registers: error=%d\n", error); 213 return; 214 } 215 if (vax_boardtype == VAX_BTYP_46 || vax_boardtype == VAX_BTYP_48) { 216 error = bus_space_subregion(asc->sc_bst, asc->sc_bsh, 217 ASC_REG_KA46_ADR, sizeof(uint32_t), &asc->sc_adrh); 218 if (error) { 219 aprint_error(": failed to map adr register: error=%d\n", 220 error); 221 return; 222 } 223 error = bus_space_subregion(asc->sc_bst, asc->sc_bsh, 224 ASC_REG_KA46_DIR, sizeof(uint32_t), &asc->sc_dirh); 225 if (error) { 226 aprint_error(": failed to map dir register: error=%d\n", 227 error); 228 return; 229 } 230 } else { 231 /* This is a gross and disgusting kludge but it'll 232 * save a bunch of ugly code. Unlike the VS4000/60, 233 * the SCSI Address and direction registers are not 234 * near the SCSI NCR registers and are inside the 235 * block of general VAXstation registers. So we grab 236 * them from there and knowing the internals of the 237 * bus_space implementation, we cast to bus_space_handles. 238 */ 239 struct vsbus_softc *vsc = device_private(parent); 240 asc->sc_adrh = (bus_space_handle_t) (vsc->sc_vsregs + ASC_REG_KA49_ADR); 241 asc->sc_dirh = (bus_space_handle_t) (vsc->sc_vsregs + ASC_REG_KA49_DIR); 242#if 0 243 printf("\n%s: adrh=0x%08lx dirh=0x%08lx", device_xname(self), 244 asc->sc_adrh, asc->sc_dirh); 245 ncr53c9x_debug = NCR_SHOWDMA|NCR_SHOWINTS|NCR_SHOWCMDS|NCR_SHOWPHASE|NCR_SHOWSTART|NCR_SHOWMSGS; 246#endif 247 } 248 error = bus_dmamap_create(asc->sc_dmat, ASC_MAXXFERSIZE, 1, 249 ASC_MAXXFERSIZE, 0, BUS_DMA_NOWAIT, &asc->sc_dmamap); 250 251#if defined(VAX46) || defined(VAX48) || defined(VAX49) || defined(VAXANY) 252 if(vax_boardtype != VAX_BTYP_53) 253 /* SCSI ID is store in the clock NVRAM at magic address 0xbc */ 254 sc->sc_id = (clk_page[0xbc/2] >> clk_tweak) & 7; 255 else 256#endif 257 sc->sc_id = 6; /* XXX need to get this from VMB */ 258 sc->sc_freq = ASC_FREQUENCY; 259 260 /* gimme MHz */ 261 sc->sc_freq /= 1000000; 262 263 scb_vecalloc(va->va_cvec, (void (*)(void *)) ncr53c9x_intr, 264 &asc->sc_ncr53c9x, SCB_ISTACK, &asc->sc_intrcnt); 265 evcnt_attach_dynamic(&asc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 266 device_xname(self), "intr"); 267 268 /* 269 * XXX More of this should be in ncr53c9x_attach(), but 270 * XXX should we really poke around the chip that much in 271 * XXX the MI code? Think about this more... 272 */ 273 274 /* 275 * Set up static configuration info. 276 */ 277 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 278 sc->sc_cfg2 = NCRCFG2_SCSI2; 279 sc->sc_cfg3 = 0; 280 sc->sc_rev = NCR_VARIANT_NCR53C94; 281 282 /* 283 * XXX minsync and maxxfer _should_ be set up in MI code, 284 * XXX but it appears to have some dependency on what sort 285 * XXX of DMA we're hooked up to, etc. 286 */ 287 288 /* 289 * This is the value used to start sync negotiations 290 * Note that the NCR register "SYNCTP" is programmed 291 * in "clocks per byte", and has a minimum value of 4. 292 * The SCSI period used in negotiation is one-fourth 293 * of the time (in nanoseconds) needed to transfer one byte. 294 * Since the chip's clock is given in MHz, we have the following 295 * formula: 4 * period = (1000 / freq) * 4 296 */ 297 sc->sc_minsync = (1000 / sc->sc_freq); 298 sc->sc_maxxfer = 64 * 1024; 299 300 aprint_normal("\n%s", device_xname(self)); /* Pretty print */ 301 302 /* Do the common parts of attachment. */ 303 sc->sc_adapter.adapt_minphys = minphys; 304 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 305 ncr53c9x_attach(sc); 306} 307 308/* 309 * Glue functions. 310 */ 311 312static u_char 313asc_vsbus_read_reg(struct ncr53c9x_softc *sc, int reg) 314{ 315 struct asc_vsbus_softc * const asc = (struct asc_vsbus_softc *)sc; 316 317 return bus_space_read_1(asc->sc_bst, asc->sc_ncrh, 318 reg * sizeof(uint32_t)); 319} 320 321static void 322asc_vsbus_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val) 323{ 324 struct asc_vsbus_softc * const asc = (struct asc_vsbus_softc *)sc; 325 326 bus_space_write_1(asc->sc_bst, asc->sc_ncrh, 327 reg * sizeof(uint32_t), val); 328} 329 330static int 331asc_vsbus_dma_isintr(struct ncr53c9x_softc *sc) 332{ 333 struct asc_vsbus_softc * const asc = (struct asc_vsbus_softc *)sc; 334 return bus_space_read_1(asc->sc_bst, asc->sc_ncrh, 335 NCR_STAT * sizeof(uint32_t)) & NCRSTAT_INT; 336} 337 338static void 339asc_vsbus_dma_reset(struct ncr53c9x_softc *sc) 340{ 341 struct asc_vsbus_softc * const asc = (struct asc_vsbus_softc *)sc; 342 343 if (asc->sc_flags & ASC_MAPLOADED) 344 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 345 asc->sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); 346} 347 348static int 349asc_vsbus_dma_intr(struct ncr53c9x_softc *sc) 350{ 351 struct asc_vsbus_softc * const asc = (struct asc_vsbus_softc *)sc; 352 u_int tcl, tcm; 353 int trans, resid; 354 355 if ((asc->sc_flags & ASC_DMAACTIVE) == 0) 356 panic("asc_vsbus_dma_intr: DMA wasn't active"); 357 358 asc->sc_flags &= ~ASC_DMAACTIVE; 359 360 if (asc->sc_dmasize == 0) { 361 /* A "Transfer Pad" operation completed */ 362 tcl = NCR_READ_REG(sc, NCR_TCL); 363 tcm = NCR_READ_REG(sc, NCR_TCM); 364 NCR_DMA(("asc_vsbus_intr: discarded %d bytes (tcl=%d, tcm=%d)\n", 365 tcl | (tcm << 8), tcl, tcm)); 366 return 0; 367 } 368 369 resid = 0; 370 if ((resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 371 NCR_DMA(("asc_vsbus_intr: empty FIFO of %d ", resid)); 372 DELAY(1); 373 } 374 if (asc->sc_flags & ASC_MAPLOADED) { 375 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 376 0, asc->sc_dmasize, 377 asc->sc_flags & ASC_FROMMEMORY 378 ? BUS_DMASYNC_POSTWRITE 379 : BUS_DMASYNC_POSTREAD); 380 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 381 } 382 asc->sc_flags &= ~ASC_MAPLOADED; 383 384 resid += (tcl = NCR_READ_REG(sc, NCR_TCL)); 385 resid += (tcm = NCR_READ_REG(sc, NCR_TCM)) << 8; 386 387 trans = asc->sc_dmasize - resid; 388 if (trans < 0) { /* transferred < 0 ? */ 389 printf("asc_vsbus_intr: xfer (%d) > req (%lu)\n", 390 trans, (u_long) asc->sc_dmasize); 391 trans = asc->sc_dmasize; 392 } 393 NCR_DMA(("asc_vsbus_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n", 394 tcl, tcm, trans, resid)); 395 396 *asc->sc_dmalen -= trans; 397 *asc->sc_dmaaddr = (char *)*asc->sc_dmaaddr + trans; 398 399 asc->sc_xfers++; 400 return 0; 401} 402 403static int 404asc_vsbus_dma_setup(struct ncr53c9x_softc *sc, void **addr, size_t *len, 405 int datain, size_t *dmasize) 406{ 407 struct asc_vsbus_softc * const asc = (struct asc_vsbus_softc *)sc; 408 409 asc->sc_dmaaddr = addr; 410 asc->sc_dmalen = len; 411 if (datain) { 412 asc->sc_flags &= ~ASC_FROMMEMORY; 413 } else { 414 asc->sc_flags |= ASC_FROMMEMORY; 415 } 416 if ((vaddr_t) *asc->sc_dmaaddr < VM_MIN_KERNEL_ADDRESS) 417 panic("asc_vsbus_dma_setup: DMA address (%p) outside of kernel", 418 *asc->sc_dmaaddr); 419 420 NCR_DMA(("%s: start %d@%p,%d\n", device_xname(&sc->sc_dev), 421 (int)*asc->sc_dmalen, *asc->sc_dmaaddr, 422 (asc->sc_flags & ASC_FROMMEMORY))); 423 *dmasize = asc->sc_dmasize = min(*dmasize, ASC_MAXXFERSIZE); 424 425 if (asc->sc_dmasize) { 426 if (bus_dmamap_load(asc->sc_dmat, asc->sc_dmamap, 427 *asc->sc_dmaaddr, asc->sc_dmasize, 428 NULL /* kernel address */, 429 BUS_DMA_NOWAIT|VAX_BUS_DMA_SPILLPAGE)) 430 panic("%s: cannot load DMA map", 431 device_xname(&sc->sc_dev)); 432 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 433 0, asc->sc_dmasize, 434 asc->sc_flags & ASC_FROMMEMORY 435 ? BUS_DMASYNC_PREWRITE 436 : BUS_DMASYNC_PREREAD); 437 bus_space_write_4(asc->sc_bst, asc->sc_adrh, 0, 438 asc->sc_dmamap->dm_segs[0].ds_addr); 439 bus_space_write_4(asc->sc_bst, asc->sc_dirh, 0, 440 asc->sc_flags & ASC_FROMMEMORY); 441 NCR_DMA(("%s: dma-load %lu@0x%08lx\n", 442 device_xname(&sc->sc_dev), 443 asc->sc_dmamap->dm_segs[0].ds_len, 444 asc->sc_dmamap->dm_segs[0].ds_addr)); 445 asc->sc_flags |= ASC_MAPLOADED; 446 } 447 448 return 0; 449} 450 451static void 452asc_vsbus_dma_go(struct ncr53c9x_softc *sc) 453{ 454 struct asc_vsbus_softc * const asc = (struct asc_vsbus_softc *)sc; 455 456 asc->sc_flags |= ASC_DMAACTIVE; 457} 458 459static void 460asc_vsbus_dma_stop(struct ncr53c9x_softc *sc) 461{ 462 struct asc_vsbus_softc * const asc = (struct asc_vsbus_softc *)sc; 463 464 if (asc->sc_flags & ASC_MAPLOADED) { 465 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 466 0, asc->sc_dmasize, 467 asc->sc_flags & ASC_FROMMEMORY 468 ? BUS_DMASYNC_POSTWRITE 469 : BUS_DMASYNC_POSTREAD); 470 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 471 } 472 473 asc->sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); 474} 475 476static int 477asc_vsbus_dma_isactive(struct ncr53c9x_softc *sc) 478{ 479 struct asc_vsbus_softc * const asc = (struct asc_vsbus_softc *)sc; 480 481 return (asc->sc_flags & ASC_DMAACTIVE) != 0; 482} 483