asc_vsbus.c revision 1.11
1/* $NetBSD: asc_vsbus.c,v 1.11 2000/04/23 16:38:54 matt Exp $ */ 2 3/*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39#include "opt_vax46.h" 40 41#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 42 43__KERNEL_RCSID(0, "$NetBSD: asc_vsbus.c,v 1.11 2000/04/23 16:38:54 matt Exp $"); 44 45#include <sys/types.h> 46#include <sys/param.h> 47#include <sys/systm.h> 48#include <sys/kernel.h> 49#include <sys/errno.h> 50#include <sys/ioctl.h> 51#include <sys/device.h> 52#include <sys/buf.h> 53#include <sys/proc.h> 54#include <sys/user.h> 55#include <sys/reboot.h> 56#include <sys/queue.h> 57 58#include <dev/scsipi/scsi_all.h> 59#include <dev/scsipi/scsipi_all.h> 60#include <dev/scsipi/scsiconf.h> 61#include <dev/scsipi/scsi_message.h> 62 63#include <machine/bus.h> 64#include <machine/vmparam.h> 65 66#include <dev/ic/ncr53c9xreg.h> 67#include <dev/ic/ncr53c9xvar.h> 68 69#include <machine/cpu.h> 70#include <machine/sid.h> 71#include <machine/scb.h> 72#include <machine/vsbus.h> 73#include <machine/clock.h> /* for SCSI ctlr ID# XXX */ 74 75struct asc_vsbus_softc { 76 struct ncr53c9x_softc sc_ncr53c9x; /* Must be first */ 77 bus_space_tag_t sc_bst; /* bus space tag */ 78 bus_space_handle_t sc_bsh; /* bus space handle */ 79 bus_space_handle_t sc_dirh; /* scsi direction handle */ 80 bus_space_handle_t sc_adrh; /* scsi address handle */ 81 bus_space_handle_t sc_ncrh; /* ncr bus space handle */ 82 bus_dma_tag_t sc_dmat; /* bus dma tag */ 83 bus_dmamap_t sc_dmamap; 84 caddr_t *sc_dmaaddr; 85 size_t *sc_dmalen; 86 size_t sc_dmasize; 87 unsigned int sc_flags; 88#define ASC_FROMMEMORY 0x0001 /* Must be 1 */ 89#define ASC_DMAACTIVE 0x0002 90#define ASC_MAPLOADED 0x0004 91 unsigned long sc_xfers; 92}; 93 94#define ASC_REG_KA46_ADR 0x0000 95#define ASC_REG_KA46_DIR 0x000C 96#define ASC_REG_KA49_ADR 0x0004 97#define ASC_REG_KA49_DIR 0x0008 98#define ASC_REG_NCR 0x0080 99#define ASC_REG_END 0x00B0 100 101#define ASC_MAXXFERSIZE 65536 102#define ASC_FREQUENCY 25000000 103 104static int asc_vsbus_match __P((struct device *, struct cfdata *, void *)); 105static void asc_vsbus_attach __P((struct device *, struct device *, void *)); 106 107struct cfattach asc_vsbus_ca = { 108 sizeof(struct asc_vsbus_softc), asc_vsbus_match, asc_vsbus_attach 109}; 110 111static struct scsipi_device asc_vsbus_dev = { 112 NULL, /* Use the default error handler */ 113 NULL, /* have a queue, served by this */ 114 NULL, /* have no async handler */ 115 NULL, /* use the default done handler */ 116}; 117 118/* 119 * Functions and the switch for the MI code 120 */ 121static u_char asc_vsbus_read_reg __P((struct ncr53c9x_softc *, int)); 122static void asc_vsbus_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 123static int asc_vsbus_dma_isintr __P((struct ncr53c9x_softc *)); 124static void asc_vsbus_dma_reset __P((struct ncr53c9x_softc *)); 125static int asc_vsbus_dma_intr __P((struct ncr53c9x_softc *)); 126static int asc_vsbus_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 127 size_t *, int, size_t *)); 128static void asc_vsbus_dma_go __P((struct ncr53c9x_softc *)); 129static void asc_vsbus_dma_stop __P((struct ncr53c9x_softc *)); 130static int asc_vsbus_dma_isactive __P((struct ncr53c9x_softc *)); 131 132static struct ncr53c9x_glue asc_vsbus_glue = { 133 asc_vsbus_read_reg, 134 asc_vsbus_write_reg, 135 asc_vsbus_dma_isintr, 136 asc_vsbus_dma_reset, 137 asc_vsbus_dma_intr, 138 asc_vsbus_dma_setup, 139 asc_vsbus_dma_go, 140 asc_vsbus_dma_stop, 141 asc_vsbus_dma_isactive, 142 NULL, 143}; 144 145static int 146asc_vsbus_match( struct device *parent, struct cfdata *cf, void *aux) 147{ 148 struct vsbus_attach_args *va = aux; 149 int dummy; 150 volatile u_int8_t *ncr_regs; 151 152 if (vax_boardtype != VAX_BTYP_46 153 && vax_boardtype != VAX_BTYP_48 154 && vax_boardtype != VAX_BTYP_49) 155 return 0; 156 157 ncr_regs = (volatile u_int8_t *) va->va_addr; 158 159 /* *** need to generate an interrupt here 160 * From trial and error, I've determined that an INT is generated 161 * only when the following sequence of events occurs: 162 * 1) The interrupt status register (0x05) must be read. 163 * 2) SCSI bus reset interrupt must be enabled 164 * 3) SCSI bus reset command must be sent 165 * 4) NOP command must be sent 166 */ 167 168 dummy = ncr_regs[NCR_INTR << 2] & 0xFF; 169 ncr_regs[NCR_CFG1 << 2] = 0x06; /* we're ID 6, turn on INT for SCSI reset */ 170 ncr_regs[NCR_CMD << 2] = NCRCMD_RSTSCSI; /* send the reset */ 171 ncr_regs[NCR_CMD << 2] = NCRCMD_NOP; /* send a NOP */ 172 DELAY(10000); 173 174 dummy = ncr_regs[NCR_INTR << 2] & 0xFF; 175 return (dummy & NCRINTR_SBR) != 0; 176} 177 178 179/* 180 * Attach this instance, and then all the sub-devices 181 */ 182static void 183asc_vsbus_attach(struct device *parent, struct device *self, void *aux) 184{ 185 struct vsbus_attach_args *va = aux; 186 struct asc_vsbus_softc *asc = (void *)self; 187 struct ncr53c9x_softc *sc = &asc->sc_ncr53c9x; 188 int error; 189 190 /* 191 * Set up glue for MI code early; we use some of it here. 192 */ 193 sc->sc_glue = &asc_vsbus_glue; 194 195 asc->sc_bst = va->va_iot; 196 asc->sc_dmat = va->va_dmat; 197 198 error = bus_space_map(asc->sc_bst, va->va_paddr - ASC_REG_NCR, 199 ASC_REG_END, 0, &asc->sc_bsh); 200 if (error) { 201 printf(": failed to map registers: error=%d\n", error); 202 return; 203 } 204 error = bus_space_subregion(asc->sc_bst, asc->sc_bsh, ASC_REG_NCR, 205 ASC_REG_END - ASC_REG_NCR, &asc->sc_ncrh); 206 if (error) { 207 printf(": failed to map ncr registers: error=%d\n", error); 208 return; 209 } 210 if (vax_boardtype == VAX_BTYP_46 || vax_boardtype == VAX_BTYP_48) { 211 error = bus_space_subregion(asc->sc_bst, asc->sc_bsh, 212 ASC_REG_KA46_ADR, sizeof(u_int32_t), &asc->sc_adrh); 213 if (error) { 214 printf(": failed to map adr register: error=%d\n", 215 error); 216 return; 217 } 218 error = bus_space_subregion(asc->sc_bst, asc->sc_bsh, 219 ASC_REG_KA46_DIR, sizeof(u_int32_t), &asc->sc_dirh); 220 if (error) { 221 printf(": failed to map dir register: error=%d\n", 222 error); 223 return; 224 } 225 } else { 226 /* This is a gross and disgusting kludge but it'll 227 * save a bunch of ugly code. Unlike the VS4000/60, 228 * the SCSI Address and direction registers are not 229 * near the SCSI NCR registers and are inside the 230 * block of general VAXstation registers. So we grab 231 * them from there and knowing the internals of the 232 * bus_space implementation, we cast to bus_space_handles. 233 */ 234 struct vsbus_softc *vsc = (struct vsbus_softc *) parent; 235 asc->sc_adrh = (bus_space_handle_t) (vsc->sc_vsregs + ASC_REG_KA49_ADR); 236 asc->sc_dirh = (bus_space_handle_t) (vsc->sc_vsregs + ASC_REG_KA49_DIR); 237 } 238 error = bus_dmamap_create(asc->sc_dmat, ASC_MAXXFERSIZE, 1, 239 ASC_MAXXFERSIZE, 0, BUS_DMA_NOWAIT, &asc->sc_dmamap); 240 241 switch (vax_boardtype) { 242#if defined(VAX46) 243 case VAX_BTYP_46: 244 sc->sc_id = (clk_page[0xbc/2] >> clk_tweak) & 7; 245 break; 246#endif 247 default: 248 sc->sc_id = 6; /* XXX need to get this from VMB */ 249 break; 250 } 251 252 sc->sc_freq = ASC_FREQUENCY; 253 254 /* gimme Mhz */ 255 sc->sc_freq /= 1000000; 256 257 scb_vecalloc(va->va_cvec, (void (*)(void *)) ncr53c9x_intr, 258 &asc->sc_ncr53c9x, SCB_ISTACK); 259 260 /* 261 * XXX More of this should be in ncr53c9x_attach(), but 262 * XXX should we really poke around the chip that much in 263 * XXX the MI code? Think about this more... 264 */ 265 266 /* 267 * Set up static configuration info. 268 */ 269 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 270 sc->sc_cfg2 = NCRCFG2_SCSI2; 271 sc->sc_cfg3 = 0; 272 sc->sc_rev = NCR_VARIANT_NCR53C94; 273 274 /* 275 * XXX minsync and maxxfer _should_ be set up in MI code, 276 * XXX but it appears to have some dependency on what sort 277 * XXX of DMA we're hooked up to, etc. 278 */ 279 280 /* 281 * This is the value used to start sync negotiations 282 * Note that the NCR register "SYNCTP" is programmed 283 * in "clocks per byte", and has a minimum value of 4. 284 * The SCSI period used in negotiation is one-fourth 285 * of the time (in nanoseconds) needed to transfer one byte. 286 * Since the chip's clock is given in MHz, we have the following 287 * formula: 4 * period = (1000 / freq) * 4 288 */ 289 sc->sc_minsync = (1000 / sc->sc_freq); 290 sc->sc_maxxfer = 63 * 1024; 291 292 printf("\n%s", self->dv_xname); /* Pretty print */ 293 294 /* Do the common parts of attachment. */ 295 sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd; 296 sc->sc_adapter.scsipi_minphys = minphys; 297 ncr53c9x_attach(sc, &asc_vsbus_dev); 298} 299 300/* 301 * Glue functions. 302 */ 303 304static u_char 305asc_vsbus_read_reg(struct ncr53c9x_softc *sc, int reg) 306{ 307 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 308 309 return bus_space_read_1(asc->sc_bst, asc->sc_ncrh, 310 reg * sizeof(u_int32_t)); 311} 312 313static void 314asc_vsbus_write_reg(sc, reg, val) 315 struct ncr53c9x_softc *sc; 316 int reg; 317 u_char val; 318{ 319 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 320 321 bus_space_write_1(asc->sc_bst, asc->sc_ncrh, 322 reg * sizeof(u_int32_t), val); 323} 324 325static int 326asc_vsbus_dma_isintr(sc) 327 struct ncr53c9x_softc *sc; 328{ 329 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 330 return bus_space_read_1(asc->sc_bst, asc->sc_ncrh, 331 NCR_STAT * sizeof(u_int32_t)) & NCRSTAT_INT; 332} 333 334static void 335asc_vsbus_dma_reset(sc) 336 struct ncr53c9x_softc *sc; 337{ 338 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 339 340 if (asc->sc_flags & ASC_MAPLOADED) 341 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 342 asc->sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); 343} 344 345static int 346asc_vsbus_dma_intr(sc) 347 struct ncr53c9x_softc *sc; 348{ 349 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 350 u_int tcl, tcm; 351 int trans, resid; 352 353 if ((asc->sc_flags & ASC_DMAACTIVE) == 0) 354 panic("asc_vsbus_dma_intr: DMA wasn't active"); 355 356 asc->sc_flags &= ~ASC_DMAACTIVE; 357 358 if (asc->sc_dmasize == 0) { 359 /* A "Transfer Pad" operation completed */ 360 tcl = NCR_READ_REG(sc, NCR_TCL); 361 tcm = NCR_READ_REG(sc, NCR_TCM); 362 NCR_DMA(("asc_vsbus_intr: discarded %d bytes (tcl=%d, tcm=%d)\n", 363 tcl | (tcm << 8), tcl, tcm)); 364 return 0; 365 } 366 367 resid = 0; 368 if ((resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 369 NCR_DMA(("asc_vsbus_intr: empty FIFO of %d ", resid)); 370 DELAY(1); 371 } 372 if (asc->sc_flags & ASC_MAPLOADED) { 373 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 374 0, asc->sc_dmasize, 375 asc->sc_flags & ASC_FROMMEMORY 376 ? BUS_DMASYNC_POSTWRITE 377 : BUS_DMASYNC_POSTREAD); 378 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 379 } 380 asc->sc_flags &= ~ASC_MAPLOADED; 381 382 resid += (tcl = NCR_READ_REG(sc, NCR_TCL)); 383 resid += (tcm = NCR_READ_REG(sc, NCR_TCM)) << 8; 384 385 trans = asc->sc_dmasize - resid; 386 if (trans < 0) { /* transferred < 0 ? */ 387 printf("asc_vsbus_intr: xfer (%d) > req (%d)\n", 388 trans, asc->sc_dmasize); 389 trans = asc->sc_dmasize; 390 } 391 NCR_DMA(("asc_vsbus_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n", 392 tcl, tcm, trans, resid)); 393 394 *asc->sc_dmalen -= trans; 395 *asc->sc_dmaaddr += trans; 396 397 asc->sc_xfers++; 398 return 0; 399} 400 401static int 402asc_vsbus_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 403 int datain, size_t *dmasize) 404{ 405 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 406 407 asc->sc_dmaaddr = addr; 408 asc->sc_dmalen = len; 409 if (datain) { 410 asc->sc_flags &= ~ASC_FROMMEMORY; 411 } else { 412 asc->sc_flags |= ASC_FROMMEMORY; 413 } 414 if ((vaddr_t) *asc->sc_dmaaddr < VM_MIN_KERNEL_ADDRESS) 415 panic("asc_vsbus_dma_setup: dma address (%p) outside of kernel", 416 *asc->sc_dmaaddr); 417 418 NCR_DMA(("%s: start %d@%p,%d\n", sc->sc_dev.dv_xname, 419 (int)*asc->sc_dmalen, *asc->sc_dmaaddr, (asc->sc_flags & ASC_FROMMEMORY))); 420 *dmasize = asc->sc_dmasize = min(*dmasize, ASC_MAXXFERSIZE); 421 422 if (asc->sc_dmasize) { 423 if (bus_dmamap_load(asc->sc_dmat, asc->sc_dmamap, 424 *asc->sc_dmaaddr, asc->sc_dmasize, 425 NULL /* kernel address */, 426 BUS_DMA_NOWAIT|VAX_BUS_DMA_SPILLPAGE)) 427 panic("%s: cannot load dma map", sc->sc_dev.dv_xname); 428 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 429 0, asc->sc_dmasize, 430 asc->sc_flags & ASC_FROMMEMORY 431 ? BUS_DMASYNC_PREWRITE 432 : BUS_DMASYNC_PREREAD); 433 bus_space_write_4(asc->sc_bst, asc->sc_adrh, 0, 434 asc->sc_dmamap->dm_segs[0].ds_addr); 435 bus_space_write_4(asc->sc_bst, asc->sc_dirh, 0, 436 asc->sc_flags & ASC_FROMMEMORY); 437 asc->sc_flags |= ASC_MAPLOADED; 438 } 439 440 return 0; 441} 442 443static void 444asc_vsbus_dma_go(struct ncr53c9x_softc *sc) 445{ 446 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 447 448 asc->sc_flags |= ASC_DMAACTIVE; 449} 450 451static void 452asc_vsbus_dma_stop(struct ncr53c9x_softc *sc) 453{ 454 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 455 456 if (asc->sc_flags & ASC_MAPLOADED) { 457 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 458 0, asc->sc_dmasize, 459 asc->sc_flags & ASC_FROMMEMORY 460 ? BUS_DMASYNC_POSTWRITE 461 : BUS_DMASYNC_POSTREAD); 462 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 463 } 464 465 asc->sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); 466} 467 468static int 469asc_vsbus_dma_isactive(struct ncr53c9x_softc *sc) 470{ 471 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 472 473 return (asc->sc_flags & ASC_DMAACTIVE) != 0; 474} 475