mtpr.h revision 1.7 
1/*      $NetBSD: mtpr.h,v 1.7 1996/02/02 19:08:39 mycroft Exp $     */
2
3/*
4 * Copyright (c) 1994 Ludd, University of Lule}, Sweden.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 *    must display the following acknowledgement:
17 *     This product includes software developed at Ludd, University of Lule}.
18 * 4. The name of the author may not be used to endorse or promote products
19 *    derived from this software without specific prior written permission
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /* All bugs are subject to removal without further notice */
34
35#ifndef	_VAX_MTPR_H_
36#define	_VAX_MTPR_H_
37
38#include <machine/macros.h>
39
40/******************************************************************************
41
42  Processor register numbers in the VAX		/IC
43
44******************************************************************************/
45
46
47#define PR_KSP     0 /* Kernel Stack Pointer */
48#define PR_ESP     1 /* Executive Stack Pointer */
49#define PR_SSP     2 /* Supervisor Stack Pointer */
50#define PR_USP     3 /* User Stack Pointer */
51#define PR_ISP     4 /* Interrupt Stack Pointer */
52
53#define PR_P0BR    8 /* P0 Base Register */
54#define PR_P0LR    9 /* P0 Length Register */
55#define PR_P1BR   10 /* P1 Base Register */
56#define PR_P1LR   11 /* P1 Length Register */
57#define PR_SBR    12 /* System Base Register */
58#define PR_SLR    13 /* System Limit Register */
59#define PR_PCBB   16 /* Process Control Block Base */
60#define PR_SCBB   17 /* System Control Block Base */
61#define PR_IPL    18 /* Interrupt Priority Level */
62#define PR_ASTLVL 19 /* AST Level */
63#define PR_SIRR   20 /* Software Interrupt Request */
64#define PR_SISR   21 /* Software Interrupt Summary */
65#define	PR_IPIR	  22 /* KA820 Interprocessor register */
66#define PR_MCSR   23 /* Machine Check Status Register 11/750 */
67#define PR_ICCS   24 /* Interval Clock Control */
68#define PR_NICR   25 /* Next Interval Count */
69#define PR_ICR    26 /* Interval Count */
70#define PR_TODR   27 /* Time Of Year (optional) */
71#define	PR_CSRS	  28 /* Console Storage R/S */
72#define	PR_CSRD	  29 /* Console Storage R/D */
73#define	PR_CSTS	  30 /* Console Storage T/S */
74#define	PR_CSTD	  31 /* Console Storage T/D */
75#define PR_RXCS   32 /* Console Receiver C/S */
76#define PR_RXDB   33 /* Console Receiver D/B */
77#define PR_TXCS   34 /* Console Transmit C/S */
78#define PR_TXDB   35 /* Console Transmit D/B */
79#define PR_TBDR   36 /* Translation Buffer Group Disable Register 11/750 */
80#define PR_CADR   37 /* Cache Disable Register 11/750 */
81#define PR_MCESR  38 /* Machiune Check Error Summary Register 11/750 */
82#define PR_CAER   39 /* Cache Error Register 11/750 */
83#define PR_ACCS   40 /* Accelerator control register */
84#define PR_SAVISP 41 /* Console Saved ISP */
85#define PR_SAVPC  42 /* Console Saved PC */
86#define PR_SAVPSL 43 /* Console Saved PSL */
87#define PR_WCSA   44 /* WCS Address */
88#define PR_WCSB   45 /* WCS Data */
89#define PR_SBIFS  48 /* SBI Fault/Status */
90#define PR_SBIS   49 /* SBI Silo */
91#define PR_SBISC  50 /* SBI Silo Comparator */
92#define PR_SBIMT  51 /* SBI Silo Maintenance */
93#define PR_SBIER  52 /* SBI Error Register */
94#define PR_SBITA  53 /* SBI Timeout Address Register */
95#define PR_SBIQC  54 /* SBI Quadword Clear */
96#define PR_IUR    55 /* Initialize Unibus Register 11/750 */
97#define PR_MAPEN  56 /* Memory Management Enable */
98#define PR_TBIA   57 /* Trans. Buf. Invalidate All */
99#define PR_TBIS   58 /* Trans. Buf. Invalidate Single */
100#define PR_TBDATA 59 /* Translation Buffer Data */
101#define PR_MBRK   60 /* Microprogram Break */
102#define PR_PMR    61 /* Performance Monnitor Enable */
103#define PR_SID    62 /* System ID Register */
104#define PR_TBCHK  63 /* Translation Buffer Check */
105
106/* Definitions for AST */
107#define	AST_NO	  4
108#define	AST_OK	  3
109
110#ifndef	_LOCORE
111
112#define mtpr(val,reg)                                   \
113{                                                       \
114        asm __volatile ("mtpr %0,%1"                    \
115                        : /* No output */               \
116                        : "g" (val), "g" (reg));        \
117}
118
119#define mfpr(reg)                                       \
120({                                                      \
121        register int val;                               \
122        asm __volatile ("mfpr %1,%0"                    \
123                        : "=g" (val)                    \
124                        : "g" (reg));                   \
125        val;                                            \
126})
127#endif	/* _LOCORE */
128
129#endif /* _VAX_MTPR_H_ */
130