1/* $NetBSD: am9516.h,v 1.1 1995/10/29 21:19:06 gwr Exp $ */ 2 3/* 4 * This file is derived from the file dev/devSCSI3.c from 5 * the Berkeley SPRITE distribution, which says: 6 * 7 * Copyright 1988 Regents of the University of California 8 * Permission to use, copy, modify, and distribute this 9 * software and its documentation for any purpose and without 10 * fee is hereby granted, provided that the above copyright 11 * notice appear in all copies. The University of California 12 * makes no representations about the suitability of this 13 * software for any purpose. It is provided "as is" without 14 * express or implied warranty. 15 */ 16 17/* 18 * AMD 9516 UDC (Universal DMA Controller) Registers. 19 * This is used only in the OBIO version (3/50,3/60). 20 */ 21 22/* addresses of the udc registers accessed directly by driver */ 23#define UDC_ADR_MODE 0x38 /* master mode register */ 24#define UDC_ADR_COMMAND 0x2e /* command register (write only) */ 25#define UDC_ADR_STATUS 0x2e /* status register (read only) */ 26#define UDC_ADR_CAR_HIGH 0x26 /* chain addr reg, high word */ 27#define UDC_ADR_CAR_LOW 0x22 /* chain addr reg, low word */ 28#define UDC_ADR_CARA_HIGH 0x1a /* cur addr reg A, high word */ 29#define UDC_ADR_CARA_LOW 0x0a /* cur addr reg A, low word */ 30#define UDC_ADR_CARB_HIGH 0x12 /* cur addr reg B, high word */ 31#define UDC_ADR_CARB_LOW 0x02 /* cur addr reg B, low word */ 32#define UDC_ADR_CMR_HIGH 0x56 /* channel mode reg, high word */ 33#define UDC_ADR_CMR_LOW 0x52 /* channel mode reg, low word */ 34#define UDC_ADR_COUNT 0x32 /* number of words to transfer */ 35 36/* 37 * For a DMA transfer, the appropriate udc registers are loaded from a 38 * table in memory pointed to by the chain address register. 39 */ 40struct udc_table { 41 u_short rsel; /* tells udc which regs to load */ 42 u_short addrh; /* high word of main mem DMA address */ 43 u_short addrl; /* low word of main mem DMA address */ 44 u_short count; /* num words to transfer */ 45 u_short cmrh; /* high word of channel mode reg */ 46 u_short cmrl; /* low word of channel mode reg */ 47}; 48 49/* indicates which udc registers are to be set based on info in above table */ 50#define UDC_RSEL_RECV 0x0182 51#define UDC_RSEL_SEND 0x0282 52 53/* setting of chain mode reg: selects how the DMA op is to be executed */ 54#define UDC_CMR_HIGH 0x0040 /* high word of channel mode reg */ 55#define UDC_CMR_LSEND 0x00c2 /* low word of cmr when send */ 56#define UDC_CMR_LRECV 0x00d2 /* low word of cmr when receiving */ 57 58/* setting for the master mode register */ 59#define UDC_MODE 0xd /* enables udc chip */ 60 61/* setting for the low byte in the high word of an address */ 62#define UDC_ADDR_INFO 0x40 /* inc addr after each word is DMA'd */ 63 64/* udc commands */ 65#define UDC_CMD_STRT_CHN 0xa0 /* start chaining */ 66#define UDC_CMD_CIE 0x32 /* channel 1 interrupt enable */ 67#define UDC_CMD_RESET 0x00 /* reset udc, same as hdw reset */ 68 69/* bits in the udc status register */ 70#define UDC_SR_CIE 0x8000 /* channel interrupt enable */ 71#define UDC_SR_IP 0x2000 /* interrupt pending */ 72#define UDC_SR_CA 0x1000 /* channel abort */ 73#define UDC_SR_NAC 0x0800 /* no auto reload or chaining*/ 74#define UDC_SR_WFB 0x0400 /* waiting for bus */ 75#define UDC_SR_SIP 0x0200 /* second interrupt pending */ 76#define UDC_SR_HM 0x0040 /* hardware mask */ 77#define UDC_SR_HRQ 0x0020 /* hardware request */ 78#define UDC_SR_MCH 0x0010 /* match on upper comparator byte */ 79#define UDC_SR_MCL 0x0008 /* match on lower comparator byte */ 80#define UDC_SR_MC 0x0004 /* match condition ended DMA */ 81#define UDC_SR_EOP 0x0002 /* eop condition ended DMA */ 82#define UDC_SR_TC 0x0001 /* termination of count ended DMA */ 83 84