pci_machdep.c revision 1.82
1/* $NetBSD: pci_machdep.c,v 1.82 2024/05/20 19:15:48 riastradh Exp $ */ 2 3/* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * functions expected by the MI PCI code. 31 */ 32 33#include <sys/cdefs.h> 34__KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.82 2024/05/20 19:15:48 riastradh Exp $"); 35 36#include <sys/types.h> 37#include <sys/param.h> 38#include <sys/time.h> 39#include <sys/systm.h> 40#include <sys/errno.h> 41#include <sys/device.h> 42 43#define _SPARC_BUS_DMA_PRIVATE 44#include <sys/bus.h> 45#include <machine/autoconf.h> 46#include <machine/openfirm.h> 47#include <dev/pci/pcivar.h> 48#include <dev/pci/pcireg.h> 49 50#include <dev/ofw/ofw_pci.h> 51 52#include <sparc64/dev/iommureg.h> 53#include <sparc64/sparc64/cache.h> 54 55#include "locators.h" 56 57#ifdef DEBUG 58#define SPDB_CONF 0x01 59#define SPDB_INTR 0x04 60#define SPDB_INTMAP 0x08 61#define SPDB_PROBE 0x20 62#define SPDB_TAG 0x40 63int sparc_pci_debug = 0x0; 64#define DPRINTF(l, s) do { if (sparc_pci_debug & l) printf s; } while (0) 65#else 66#define DPRINTF(l, s) 67#endif 68 69/* this is a base to be copied */ 70struct sparc_pci_chipset _sparc_pci_chipset = { 71 .cookie = NULL, 72}; 73 74static pcitag_t 75ofpci_make_tag(pci_chipset_tag_t pc, int node, int b, int d, int f) 76{ 77 pcitag_t tag; 78 pcireg_t reg; 79 80 tag = PCITAG_CREATE(node, b, d, f); 81 82 DPRINTF(SPDB_TAG, 83 ("%s: creating tag for node %x bus %d dev %d fn %d\n", 84 __func__, node, b, d, f)); 85 86 /* Enable all the different spaces for this device */ 87 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 88 reg |= PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_MASTER_ENABLE| 89 PCI_COMMAND_IO_ENABLE; 90 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 91 92 return (tag); 93} 94 95/* 96 * functions provided to the MI code. 97 */ 98 99void 100pci_attach_hook(device_t parent, device_t self, 101 struct pcibus_attach_args *pba) 102{ 103} 104 105int 106pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 107{ 108 109 return 32; 110} 111 112pcitag_t 113pci_make_tag(pci_chipset_tag_t pc, int b, int d, int f) 114{ 115 struct ofw_pci_register reg; 116 pcitag_t tag; 117 int (*valid)(void *); 118 int node, new_node, len; 119#ifdef DEBUG 120 char name[80]; 121 memset(name, 0, sizeof(name)); 122#endif 123 124 /* 125 * Refer to the PCI/CardBus bus node first. 126 * It returns a tag if node is present and bus is valid. 127 */ 128 if (0 <= b && b < 256) { 129 KASSERT(pc->spc_busnode != NULL); 130 node = (*pc->spc_busnode)[b].node; 131 valid = (*pc->spc_busnode)[b].valid; 132 if (node != 0 && d == 0 && 133 (valid == NULL || (*valid)((*pc->spc_busnode)[b].arg))) 134 return ofpci_make_tag(pc, node, b, d, f); 135 } 136 137 /* 138 * Hunt for the node that corresponds to this device 139 * 140 * We could cache this info in an array in the parent 141 * device... except then we have problems with devices 142 * attached below pci-pci bridges, and we would need to 143 * add special code to the pci-pci bridge to cache this 144 * info. 145 */ 146 147 tag = PCITAG_CREATE(-1, b, d, f); 148 node = pc->rootnode; 149 /* 150 * First make sure we're on the right bus. If our parent 151 * has a bus-range property and we're not in the range, 152 * then we're obviously on the wrong bus. So go up one 153 * level. 154 */ 155 DPRINTF(SPDB_PROBE, ("curnode %x %s\n", node, 156 prom_getpropstringA(node, "name", name, sizeof(name)))); 157#if 0 158 while ((OF_getprop(OF_parent(node), "bus-range", (void *)&busrange, 159 sizeof(busrange)) == sizeof(busrange)) && 160 (b < busrange[0] || b > busrange[1])) { 161 /* Out of range, go up one */ 162 node = OF_parent(node); 163 DPRINTF(SPDB_PROBE, printf("going up to node %x %s\n", 164 node, 165 prom_getpropstringA(node, "name", name, sizeof(name)))); 166 } 167#endif 168 node = prom_firstchild(node); 169 /* 170 * Now traverse all peers until we find the node or we find 171 * the right bridge. 172 * 173 * XXX We go up one and down one to make sure nobody's missed. 174 * but this should not be necessary. 175 */ 176 for (node = ((node)); node; node = prom_nextsibling(node)) { 177 178 DPRINTF(SPDB_PROBE, ("checking node %x %s\n", node, 179 prom_getpropstringA(node, "name", name, sizeof(name)))); 180 181#if 1 182 /* 183 * Check for PCI-PCI bridges. If the device we want is 184 * in the bus-range for that bridge, work our way down. 185 */ 186 while (1) { 187 int busrange[2], *brp; 188 len = 2; 189 brp = busrange; 190 if (prom_getprop(node, "bus-range", sizeof(*brp), 191 &len, &brp) != 0) 192 break; 193 if (len != 2 || b < busrange[0] || b > busrange[1]) 194 break; 195 /* Go down 1 level, as long as we're able */ 196 new_node = prom_firstchild(node); 197 if (new_node == 0) 198 break; 199 node = new_node; 200 DPRINTF(SPDB_PROBE, ("going down to node %x %s\n", node, 201 prom_getpropstringA(node, "name", name, 202 sizeof(name)))); 203 } 204#endif /*1*/ 205 /* 206 * We only really need the first `reg' property. 207 * 208 * For simplicity, we'll query the `reg' when we 209 * need it. Otherwise we could malloc() it, but 210 * that gets more complicated. 211 */ 212 len = prom_getproplen(node, "reg"); 213 if (len < sizeof(reg)) 214 continue; 215 if (OF_getprop(node, "reg", (void *)®, sizeof(reg)) != len) 216 panic("pci_probe_bus: OF_getprop len botch"); 217 218 if (b != OFW_PCI_PHYS_HI_BUS(reg.phys_hi)) 219 continue; 220 if (d != OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi)) 221 continue; 222 if (f != OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi)) 223 continue; 224 225 /* Got a match */ 226 tag = ofpci_make_tag(pc, node, b, d, f); 227 228 return (tag); 229 } 230 /* No device found -- return a dead tag */ 231 return (tag); 232} 233 234void 235pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, int *bp, int *dp, int *fp) 236{ 237 238 if (bp != NULL) 239 *bp = PCITAG_BUS(tag); 240 if (dp != NULL) 241 *dp = PCITAG_DEV(tag); 242 if (fp != NULL) 243 *fp = PCITAG_FUN(tag); 244} 245 246int 247sparc64_pci_enumerate_bus(struct pci_softc *sc, const int *locators, 248 int (*match)(const struct pci_attach_args *), struct pci_attach_args *pap) 249{ 250 struct ofw_pci_register reg; 251 pci_chipset_tag_t pc = sc->sc_pc; 252 pcitag_t tag; 253 pcireg_t class, csr, bhlc, ic; 254 int node, b, d, f, ret; 255 int bus_frequency, lt, cl, cacheline; 256 char name[30]; 257#if 0 258 extern int pci_config_dump; 259#endif 260 261 if (sc->sc_bridgetag) 262 node = PCITAG_NODE(*sc->sc_bridgetag); 263 else 264 node = pc->rootnode; 265 266 bus_frequency = 267 prom_getpropint(node, "clock-frequency", 33000000) / 1000000; 268 269 /* 270 * Make sure the cache line size is at least as big as the 271 * ecache line and the streaming cache (64 byte). 272 */ 273 cacheline = uimax(ecache_min_line_size, 64); 274 KASSERT((cacheline/64)*64 == cacheline && 275 (cacheline/ecache_min_line_size)*ecache_min_line_size == cacheline && 276 (cacheline/4)*4 == cacheline); 277 278#if 0 279 /* 280 * XXX this faults on Fire PCIe controllers. 281 * XXX move into the psycho and schizo driver front ends. 282 */ 283 /* Turn on parity for the bus. */ 284 tag = ofpci_make_tag(pc, node, sc->sc_bus, 0, 0); 285 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 286 csr |= PCI_COMMAND_PARITY_ENABLE; 287 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 288 289 /* 290 * Initialize the latency timer register. 291 * The value 0x40 is from Solaris. 292 */ 293 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 294 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 295 bhlc |= 0x40 << PCI_LATTIMER_SHIFT; 296 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 297 298 if (pci_config_dump) 299 pci_conf_print(pc, tag, NULL); 300#endif 301 302 for (node = prom_firstchild(node); node != 0 && node != -1; 303 node = prom_nextsibling(node)) { 304 name[0] = name[29] = 0; 305 prom_getpropstringA(node, "name", name, sizeof(name)); 306 307 if (OF_getprop(node, "class-code", &class, sizeof(class)) != 308 sizeof(class)) 309 continue; 310 if (OF_getprop(node, "reg", ®, sizeof(reg)) < sizeof(reg)) 311 panic("pci_enumerate_bus: \"%s\" regs too small", name); 312 313 b = OFW_PCI_PHYS_HI_BUS(reg.phys_hi); 314 d = OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi); 315 f = OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi); 316 317 if (sc->sc_bus != b) { 318 aprint_error_dev(sc->sc_dev, "WARNING: incorrect " 319 "bus # for \"%s\" (%d/%d/%d)\n", name, b, d, f); 320 continue; 321 } 322 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) && 323 (locators[PCICF_DEV] != d)) 324 continue; 325 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) && 326 (locators[PCICF_FUNCTION] != f)) 327 continue; 328 329 tag = ofpci_make_tag(pc, node, b, d, f); 330 331 /* 332 * Turn on parity and fast-back-to-back for the device. 333 */ 334 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 335 if (csr & PCI_STATUS_BACKTOBACK_SUPPORT) 336 csr |= PCI_COMMAND_BACKTOBACK_ENABLE; 337 csr |= PCI_COMMAND_PARITY_ENABLE; 338 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 339 340 /* 341 * Initialize the latency timer register for busmaster 342 * devices to work properly. 343 * latency-timer = min-grant * bus-freq / 4 (from FreeBSD) 344 * Also initialize the cache line size register. 345 * Solaris anytime sets this register to the value 0x10. 346 */ 347 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 348 ic = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 349 350 lt = uimin(PCI_MIN_GNT(ic) * bus_frequency / 4, 255); 351 if (lt == 0 || lt < PCI_LATTIMER(bhlc)) 352 lt = PCI_LATTIMER(bhlc); 353 354 cl = PCI_CACHELINE(bhlc); 355 if (cl == 0) 356 cl = cacheline; 357 358 bhlc &= ~((PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT) | 359 (PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT)); 360 bhlc |= (lt << PCI_LATTIMER_SHIFT) | 361 (cl << PCI_CACHELINE_SHIFT); 362 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 363 364 ret = pci_probe_device(sc, tag, match, pap); 365 if (match != NULL && ret != 0) 366 return (ret); 367 } 368 return (0); 369} 370 371const char * 372pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih, char *buf, 373 size_t len) 374{ 375 snprintf(buf, len, "ivec %x", ih); 376 DPRINTF(SPDB_INTR, ("pci_intr_string: returning %s\n", buf)); 377 378 return buf; 379} 380 381const struct evcnt * 382pci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t ih) 383{ 384 385 /* XXX for now, no evcnt parent reported */ 386 return NULL; 387} 388 389int 390pci_intr_setattr(pci_chipset_tag_t pc, pci_intr_handle_t *ih, 391 int attr, uint64_t data) 392{ 393 394 switch (attr) { 395 case PCI_INTR_MPSAFE: 396 return 0; 397 default: 398 return ENODEV; 399 } 400} 401 402/* 403 * interrupt mapping foo. 404 * XXX: how does this deal with multiple interrupts for a device? 405 */ 406int 407pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 408{ 409 pcitag_t tag = pa->pa_tag; 410 int interrupts[4], *intp, int_used; 411 int len, node = PCITAG_NODE(tag); 412 char devtype[30]; 413 414 intp = &interrupts[0]; 415 len = prom_getproplen(node, "interrupts"); 416 if (len > sizeof(interrupts)) { 417 DPRINTF(SPDB_INTMAP, 418 ("pci_intr_map: too many available interrupts\n")); 419 return (ENODEV); 420 } 421 if (prom_getprop(node, "interrupts", len, 422 &len, &intp) != 0 || len != 1) { 423 DPRINTF(SPDB_INTMAP, 424 ("pci_intr_map: could not read interrupts\n")); 425 return (ENODEV); 426 } 427 428 /* XXX We pick the first interrupt, but should do better */ 429 int_used = interrupts[0]; 430 if (OF_mapintr(node, &int_used, sizeof(int_used), 431 sizeof(int_used)) < 0) { 432 printf("OF_mapintr failed\n"); 433 if (pa->pa_pc->spc_find_ino) 434 pa->pa_pc->spc_find_ino(pa, &int_used); 435 } 436 DPRINTF(SPDB_INTMAP, ("OF_mapintr() gave %x\n", int_used)); 437 438 /* Try to find an IPL for this type of device. */ 439 prom_getpropstringA(node, "device_type", devtype, sizeof(devtype)); 440 for (len = 0; intrmap[len].in_class != NULL; len++) 441 if (strcmp(intrmap[len].in_class, devtype) == 0) { 442 int_used |= INTLEVENCODE(intrmap[len].in_lev); 443 DPRINTF(SPDB_INTMAP, ("reset to %x\n", int_used)); 444 break; 445 } 446 447 *ihp = int_used; 448 449 /* Call the sub-driver is necessary */ 450 if (pa->pa_pc->spc_intr_map) 451 (*pa->pa_pc->spc_intr_map)(pa, ihp); 452 453 return (0); 454} 455 456void 457pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie) 458{ 459 460 DPRINTF(SPDB_INTR, ("pci_intr_disestablish: cookie %p\n", cookie)); 461 462 /* XXX */ 463 /* panic("can't disestablish PCI interrupts yet"); */ 464} 465 466int 467sparc_pci_childspace(int type) 468{ 469 int ss; 470 471 switch (type) { 472 case PCI_CONFIG_BUS_SPACE: 473 ss = 0x00; 474 break; 475 case PCI_IO_BUS_SPACE: 476 ss = 0x01; 477 break; 478 case PCI_MEMORY_BUS_SPACE: 479 ss = 0x02; 480 break; 481#if 0 482 /* we don't do 64 bit memory space */ 483 case PCI_MEMORY64_BUS_SPACE: 484 ss = 0x03; 485 break; 486#endif 487 default: 488 panic("get_childspace: unknown bus type: %d", type); 489 } 490 491 return (ss); 492} 493