pci_machdep.c revision 1.20
1/* $NetBSD: pci_machdep.c,v 1.20 2001/03/06 08:09:16 mrg Exp $ */ 2 3/* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31/* 32 * functions expected by the MI PCI code. 33 */ 34 35#ifdef DEBUG 36#define SPDB_CONF 0x01 37#define SPDB_INTR 0x04 38#define SPDB_INTMAP 0x08 39#define SPDB_INTFIX 0x10 40int sparc_pci_debug = 0x0; 41#define DPRINTF(l, s) do { if (sparc_pci_debug & l) printf s; } while (0) 42#else 43#define DPRINTF(l, s) 44#endif 45 46#include <sys/types.h> 47#include <sys/param.h> 48#include <sys/time.h> 49#include <sys/systm.h> 50#include <sys/errno.h> 51#include <sys/device.h> 52#include <sys/malloc.h> 53 54#define _SPARC_BUS_DMA_PRIVATE 55#include <machine/bus.h> 56#include <machine/autoconf.h> 57 58#include <dev/pci/pcivar.h> 59#include <dev/pci/pcireg.h> 60 61#include <dev/ofw/openfirm.h> 62#include <dev/ofw/ofw_pci.h> 63 64#include <sparc64/dev/iommureg.h> 65#include <sparc64/dev/iommuvar.h> 66#include <sparc64/dev/psychoreg.h> 67#include <sparc64/dev/psychovar.h> 68 69/* this is a base to be copied */ 70struct sparc_pci_chipset _sparc_pci_chipset = { 71 NULL, 72}; 73 74/* 75 * functions provided to the MI code. 76 */ 77 78void 79pci_attach_hook(parent, self, pba) 80 struct device *parent; 81 struct device *self; 82 struct pcibus_attach_args *pba; 83{ 84 pci_chipset_tag_t pc = pba->pba_pc; 85 struct psycho_pbm *pp = pc->cookie; 86 struct psycho_registers *pr; 87 pcitag_t tag; 88 char *name, *devtype; 89 u_int32_t hi, mid, lo, intr, line; 90 u_int32_t dev, fn, bus; 91 int node, i, n, *ip, *ap; 92 93 DPRINTF((SPDB_INTFIX|SPDB_INTMAP), ("\npci_attach_hook:")); 94 95 /* 96 * ok, here we look in the OFW for each PCI device and fix it's 97 * "interrupt line" register to be useful. 98 */ 99 100 for (node = firstchild(pc->node); node; node = nextsibling(node)) { 101 pr = NULL; 102 ip = ap = NULL; 103 104 /* 105 * ok, for each child we get the "interrupts" property, 106 * which contains a value to match against later. 107 * XXX deal with multiple "interrupts" values XXX. 108 * then we get the "assigned-addresses" property which 109 * contains, in the first entry, the PCI bus, device and 110 * function associated with this node, which we use to 111 * generate a pcitag_t to use pci_conf_read() and 112 * pci_conf_write(). next, we get the 'reg" property 113 * which is structured like the following: 114 * u_int32_t phys_hi; 115 * u_int32_t phys_mid; 116 * u_int32_t phys_lo; 117 * u_int32_t size_hi; 118 * u_int32_t size_lo; 119 * we mask these values with the "interrupt-map-mask" 120 * property of our parent and them compare with each 121 * entry in the "interrupt-map" property (also of our 122 * parent) which is structred like the following: 123 * u_int32_t phys_hi; 124 * u_int32_t phys_mid; 125 * u_int32_t phys_lo; 126 * u_int32_t intr; 127 * int32_t child_node; 128 * u_int32_t child_intr; 129 * if there is an exact match with phys_hi, phys_mid, 130 * phys_lo and the interrupt, we have a match and we 131 * know that this interrupt's value is really the 132 * child_intr of the interrupt map entry. we put this 133 * into the PCI interrupt line register so that when 134 * the driver for this node wants to attach, we know 135 * it's INO already. 136 */ 137 138 name = getpropstring(node, "name"); 139 DPRINTF((SPDB_INTFIX|SPDB_INTMAP), ("\n\tnode %x name `%s'", node, name)); 140 devtype = getpropstring(node, "device_type"); 141 DPRINTF((SPDB_INTFIX|SPDB_INTMAP), (" devtype `%s':", devtype)); 142 143 /* ignore PCI bridges, we'll get them later */ 144 if (strcmp(devtype, "pci") == 0) 145 continue; 146 147 /* if there isn't any "interrupts" then we don't care to fix it */ 148 ip = NULL; 149 if (getprop(node, "interrupts", sizeof(int), &n, (void **)&ip)) 150 continue; 151 DPRINTF(SPDB_INTFIX, (" got interrupts")); 152 153 /* and if there isn't an "assigned-addresses" we can't find b/d/f */ 154 if (getprop(node, "assigned-addresses", sizeof(int), &n, 155 (void **)&ap)) 156 goto clean1; 157 DPRINTF(SPDB_INTFIX, (" got assigned-addresses")); 158 159 /* ok, and now the "reg" property, so we know what we're talking about. */ 160 if (getprop(node, "reg", sizeof(*pr), &n, 161 (void **)&pr)) 162 goto clean2; 163 DPRINTF(SPDB_INTFIX, (" got reg")); 164 165 bus = TAG2BUS(ap[0]); 166 dev = TAG2DEV(ap[0]); 167 fn = TAG2FN(ap[0]); 168 169 DPRINTF(SPDB_INTFIX, ("; bus %u dev %u fn %u", bus, dev, fn)); 170 171 tag = pci_make_tag(pc, bus, dev, fn); 172 173 DPRINTF(SPDB_INTFIX, ("; tag %08x\n\t; reg: hi %x mid %x lo %x intr %x", tag, pr->phys_hi, pr->phys_mid, pr->phys_lo, *ip)); 174 DPRINTF(SPDB_INTFIX, ("\n\t; intmapmask: hi %x mid %x lo %x intr %x", pp->pp_intmapmask.phys_hi, pp->pp_intmapmask.phys_mid, 175 pp->pp_intmapmask.phys_lo, pp->pp_intmapmask.intr)); 176 177 hi = pr->phys_hi & pp->pp_intmapmask.phys_hi; 178 mid = pr->phys_mid & pp->pp_intmapmask.phys_mid; 179 lo = pr->phys_lo & pp->pp_intmapmask.phys_lo; 180 intr = *ip & pp->pp_intmapmask.intr; 181 182 DPRINTF(SPDB_INTFIX, ("\n\t; after: hi %x mid %x lo %x intr %x", hi, mid, lo, intr)); 183 184 for (i = 0; i < pp->pp_nintmap; i++) { 185 DPRINTF(SPDB_INTFIX, ("\n\t\tmatching for: hi %x mid %x lo %x intr %x", pp->pp_intmap[i].phys_hi, pp->pp_intmap[i].phys_mid, 186 pp->pp_intmap[i].phys_lo, pp->pp_intmap[i].intr)); 187 188 if (pp->pp_intmap[i].phys_hi != hi || 189 pp->pp_intmap[i].phys_mid != mid || 190 pp->pp_intmap[i].phys_lo != lo || 191 pp->pp_intmap[i].intr != intr) 192 continue; 193 intr = pp->pp_intmap[i].child_intr; 194 DPRINTF(SPDB_INTFIX, ("... BINGO! ...")); 195 196 bingo: 197 /* 198 * OK! we found match. pull out the old interrupt 199 * register, patch in the new value, and put it back. 200 */ 201 line = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 202 DPRINTF(SPDB_INTFIX, ("\n\t ; read %x from intreg", line)); 203 204 line = PCI_INTERRUPT_CODE(PCI_INTERRUPT_LATENCY(line), 205 PCI_INTERRUPT_GRANT(line), 206 PCI_INTERRUPT_PIN(line), 207 PCI_INTERRUPT_LINE(intr)); 208 209 DPRINTF((SPDB_INTFIX|SPDB_INTMAP), ("\n\t ; gonna write %x to intreg", line)); 210 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, intr); 211 break; 212 } 213 if (i == pp->pp_nintmap) { 214 /* 215 * Not matched by parent interrupt map. If the 216 * interrupt property has the INTMAP_OBIO bit 217 * set, assume the PROM has (wrongly) supplied it 218 * in the parent's bus format, rather than as a 219 * PCI interrupt line number. 220 * 221 * This seems to be an issue only with the 222 * psycho host-to-pci bridge. 223 */ 224 if (pp->pp_sc->sc_mode == PSYCHO_MODE_PSYCHO && 225 (*ip & INTMAP_OBIO) != 0) { 226 DPRINTF((SPDB_INTFIX|SPDB_INTMAP), 227 ("\n\t; PSYCHO: no match but obio interrupt in parent format")); 228 229 intr = *ip; 230 i = -1; 231 goto bingo; /* hackish */ 232 } 233 } 234 235 /* enable mem & dma if not already */ 236 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 237 PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_MASTER_ENABLE|PCI_COMMAND_IO_ENABLE); 238 239 240 /* clean up */ 241 if (pr) 242 free(pr, M_DEVBUF); 243clean2: 244 if (ap) 245 free(ap, M_DEVBUF); 246clean1: 247 if (ip) 248 free(ip, M_DEVBUF); 249 } 250 DPRINTF(SPDB_INTFIX, ("\n")); 251} 252 253int 254pci_bus_maxdevs(pc, busno) 255 pci_chipset_tag_t pc; 256 int busno; 257{ 258 259 return 32; 260} 261 262#ifdef __PCI_BUS_DEVORDER 263int 264pci_bus_devorder(pc, busno, devs) 265 pci_chipset_tag_t pc; 266 int busno; 267 char *devs; 268{ 269 struct ofw_pci_register reg0; 270 int node, len, device, i = 0; 271 u_int32_t done = 0; 272 273 for (node = OF_child(pc->node); node; node = OF_peer(node)) { 274 len = OF_getproplen(node, "reg"); 275 if (len < sizeof(reg0)) 276 continue; 277 if (OF_getprop(node, "reg", (void *)®0, sizeof(reg0)) != len) 278 panic("pci_probe_bus: OF_getprop len botch"); 279 280 device = OFW_PCI_PHYS_HI_DEVICE(reg0.phys_hi); 281 282 if (done & (1 << device)) 283 continue; 284 285 devs[i++] = device; 286 done |= 1 << device; 287 if (i == 32) 288 break; 289 } 290 if (i < 32) 291 devs[i] = -1; 292 293 return i; 294} 295#endif 296 297#ifdef __PCI_DEV_FUNCORDER 298int 299pci_dev_funcorder(pc, busno, device, funcs) 300 pci_chipset_tag_t pc; 301 int busno; 302 int device; 303 char *funcs; 304{ 305 struct ofw_pci_register reg0; 306 int node, len, i = 0; 307 308 for (node = OF_child(pc->node); node; node = OF_peer(node)) { 309 len = OF_getproplen(node, "reg"); 310 if (len < sizeof(reg0)) 311 continue; 312 if (OF_getprop(node, "reg", (void *)®0, sizeof(reg0)) != len) 313 panic("pci_probe_bus: OF_getprop len botch"); 314 315 if (device != OFW_PCI_PHYS_HI_DEVICE(reg0.phys_hi)) 316 continue; 317 318 funcs[i++] = OFW_PCI_PHYS_HI_FUNCTION(reg0.phys_hi); 319 if (i == 8) 320 break; 321 } 322 if (i < 8) 323 funcs[i] = -1; 324 325 return i; 326} 327#endif 328 329pcitag_t 330pci_make_tag(pc, b, d, f) 331 pci_chipset_tag_t pc; 332 int b; 333 int d; 334 int f; 335{ 336 337 /* make me a useable offset */ 338 return (b << 16) | (d << 11) | (f << 8); 339} 340 341static int confaddr_ok __P((struct psycho_softc *, pcitag_t)); 342 343/* 344 * this function is a large hack. ideally, we should also trap accesses 345 * properly, but we have to avoid letting anything read various parts 346 * of bus 0 dev 0 fn 0 space or the machine may hang. so, even if we 347 * do properly implement PCI config access trap handling, this function 348 * should remain in place Just In Case. 349 */ 350static int 351confaddr_ok(sc, tag) 352 struct psycho_softc *sc; 353 pcitag_t tag; 354{ 355 int bus, dev, fn; 356 357 bus = TAG2BUS(tag); 358 dev = TAG2DEV(tag); 359 fn = TAG2FN(tag); 360 361 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 362 /* 363 * bus 0 is only ok for dev 0 fn 0, dev 1 fn 0 and dev fn 1. 364 */ 365 if (bus == 0 && 366 ((dev == 0 && fn > 0) || 367 (dev == 1 && fn > 1) || 368 (dev > 1))) { 369 DPRINTF(SPDB_CONF, (" confaddr_ok: rejecting bus %d dev %d fn %d -", bus, dev, fn)); 370 return (0); 371 } 372 } else if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 373 /* 374 * make sure we are reading our own bus 375 */ 376 /* XXX??? */ 377 paddr_t addr = sc->sc_configaddr + tag; 378 int asi = bus_type_asi[sc->sc_configtag->type]; 379 if (probeget(addr, asi, 4) == -1) { 380 DPRINTF(SPDB_CONF, (" confaddr_ok: rejecting bus %d dev %d fn %d -", bus, dev, fn)); 381 return (0); 382 } 383 } 384 return (1); 385} 386 387/* assume we are mapped little-endian/side-effect */ 388pcireg_t 389pci_conf_read(pc, tag, reg) 390 pci_chipset_tag_t pc; 391 pcitag_t tag; 392 int reg; 393{ 394 struct psycho_pbm *pp = pc->cookie; 395 struct psycho_softc *sc = pp->pp_sc; 396 pcireg_t val; 397 398 DPRINTF(SPDB_CONF, ("pci_conf_read: tag %lx; reg %x; ", (long)tag, reg)); 399 DPRINTF(SPDB_CONF, ("asi = %x; readaddr = %qx (offset = %x) ...", 400 bus_type_asi[sc->sc_configtag->type], 401 (long long)(sc->sc_configaddr + tag + reg), (int)tag + reg)); 402 403 if (confaddr_ok(sc, tag) == 0) { 404 val = (pcireg_t)~0; 405 } else { 406 membar_sync(); 407 val = bus_space_read_4(sc->sc_configtag, sc->sc_configaddr, 408 tag + reg); 409 membar_sync(); 410 } 411 DPRINTF(SPDB_CONF, (" returning %08x\n", (u_int)val)); 412 413 return (val); 414} 415 416void 417pci_conf_write(pc, tag, reg, data) 418 pci_chipset_tag_t pc; 419 pcitag_t tag; 420 int reg; 421 pcireg_t data; 422{ 423 struct psycho_pbm *pp = pc->cookie; 424 struct psycho_softc *sc = pp->pp_sc; 425 426 DPRINTF(SPDB_CONF, ("pci_conf_write: tag %lx; reg %x; data %x; ", (long)tag, reg, (int)data)); 427 DPRINTF(SPDB_CONF, ("asi = %x; readaddr = %qx (offset = %x)\n", 428 bus_type_asi[sc->sc_configtag->type], 429 (long long)(sc->sc_configaddr + tag + reg), (int)tag + reg)); 430 431 if (confaddr_ok(sc, tag) == 0) 432 panic("pci_conf_write: bad addr"); 433 434 membar_sync(); 435 bus_space_write_4(sc->sc_configtag, sc->sc_configaddr, tag + reg, data); 436 membar_sync(); 437} 438 439/* 440 * interrupt mapping foo. 441 * XXX: how does this deal with multiple interrupts for a device? 442 */ 443int 444pci_intr_map(pa, ihp) 445 struct pci_attach_args *pa; 446 pci_intr_handle_t *ihp; 447{ 448 int rv, pin, line; 449 450 pin = pa->pa_intrpin; 451 line = pa->pa_intrline; 452 453 DPRINTF(SPDB_INTMAP, ("pci_intr_map: dev %u fn %u: ", pa->pa_device, 454 pa->pa_function)); 455 /* 456 * XXX 457 * UltraSPARC PCI does not use PCI_INTERRUPT_REG, but we have 458 * used this space for our own purposes... 459 */ 460 DPRINTF(SPDB_INTR, ("pci_intr_map: tag %lx; line %d", 461 (long)pa->pa_intrtag, line)); 462 463 if (line >= 0x40) { 464 *ihp = -1; 465 rv = 1; 466 goto out; 467 } 468 if (pin > 4) 469 panic("pci_intr_map: pin > 4"); 470 471 (*ihp) = line & 0x3f; 472 rv = 0; 473out: 474 DPRINTF(SPDB_INTR, ("; handle = %x; returning %d\n", (u_int)*ihp, rv)); 475 return (rv); 476} 477 478const char * 479pci_intr_string(pc, ih) 480 pci_chipset_tag_t pc; 481 pci_intr_handle_t ih; 482{ 483 static char str[16]; 484 485 DPRINTF(SPDB_INTR, ("pci_intr_string: ih %u", ih)); 486 if (ih < 0 || ih >= 0x40) { 487 printf("\n"); /* i'm *so* beautiful */ 488 panic("pci_intr_string: bogus handle\n"); 489 } 490 sprintf(str, "ipl %u", ih); 491 DPRINTF(SPDB_INTR, ("; returning %s\n", str)); 492 493 return (str); 494} 495 496const struct evcnt * 497pci_intr_evcnt(pc, ih) 498 pci_chipset_tag_t pc; 499 pci_intr_handle_t ih; 500{ 501 502 /* XXX for now, no evcnt parent reported */ 503 return NULL; 504} 505 506void * 507pci_intr_establish(pc, ih, level, func, arg) 508 pci_chipset_tag_t pc; 509 pci_intr_handle_t ih; 510 int level; 511 int (*func) __P((void *)); 512 void *arg; 513{ 514 void *cookie; 515 struct psycho_pbm *pp = (struct psycho_pbm *)pc->cookie; 516 517 DPRINTF(SPDB_INTR, ("pci_intr_establish: ih %lu; level %d", (u_long)ih, level)); 518 cookie = bus_intr_establish(pp->pp_memt, ih, level, 0, func, arg); 519 520 DPRINTF(SPDB_INTR, ("; returning handle %p\n", cookie)); 521 return (cookie); 522} 523 524void 525pci_intr_disestablish(pc, cookie) 526 pci_chipset_tag_t pc; 527 void *cookie; 528{ 529 530 DPRINTF(SPDB_INTR, ("pci_intr_disestablish: cookie %p\n", cookie)); 531 532 /* XXX */ 533 panic("can't disestablish PCI interrupts yet"); 534} 535