pci_machdep.c revision 1.19
1/* $NetBSD: pci_machdep.c,v 1.19 2001/03/02 06:34:06 mrg Exp $ */ 2 3/* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31/* 32 * functions expected by the MI PCI code. 33 */ 34 35#ifdef DEBUG 36#define SPDB_CONF 0x01 37#define SPDB_INTR 0x04 38#define SPDB_INTMAP 0x08 39#define SPDB_INTFIX 0x10 40int sparc_pci_debug = 0x0; 41#define DPRINTF(l, s) do { if (sparc_pci_debug & l) printf s; } while (0) 42#else 43#define DPRINTF(l, s) 44#endif 45 46#include <sys/types.h> 47#include <sys/param.h> 48#include <sys/time.h> 49#include <sys/systm.h> 50#include <sys/errno.h> 51#include <sys/device.h> 52#include <sys/malloc.h> 53 54#define _SPARC_BUS_DMA_PRIVATE 55#include <machine/bus.h> 56#include <machine/autoconf.h> 57 58#include <dev/pci/pcivar.h> 59#include <dev/pci/pcireg.h> 60 61#include <dev/ofw/openfirm.h> 62#include <dev/ofw/ofw_pci.h> 63 64#include <sparc64/dev/iommureg.h> 65#include <sparc64/dev/iommuvar.h> 66#include <sparc64/dev/psychoreg.h> 67#include <sparc64/dev/psychovar.h> 68 69/* this is a base to be copied */ 70struct sparc_pci_chipset _sparc_pci_chipset = { 71 NULL, 72}; 73 74/* 75 * functions provided to the MI code. 76 */ 77 78void 79pci_attach_hook(parent, self, pba) 80 struct device *parent; 81 struct device *self; 82 struct pcibus_attach_args *pba; 83{ 84 pci_chipset_tag_t pc = pba->pba_pc; 85 struct psycho_pbm *pp = pc->cookie; 86 struct psycho_registers *pr; 87 pcitag_t tag; 88 char *name, *devtype; 89 u_int32_t hi, mid, lo, intr; 90 u_int32_t dev, fn, bus; 91 int node, i, n, *ip, *ap; 92 93 DPRINTF((SPDB_INTFIX|SPDB_INTMAP), ("\npci_attach_hook:")); 94 95 /* 96 * ok, here we look in the OFW for each PCI device and fix it's 97 * "interrupt line" register to be useful. 98 */ 99 100 for (node = firstchild(pc->node); node; node = nextsibling(node)) { 101 pr = NULL; 102 ip = ap = NULL; 103 104 /* 105 * ok, for each child we get the "interrupts" property, 106 * which contains a value to match against later. 107 * XXX deal with multiple "interrupts" values XXX. 108 * then we get the "assigned-addresses" property which 109 * contains, in the first entry, the PCI bus, device and 110 * function associated with this node, which we use to 111 * generate a pcitag_t to use pci_conf_read() and 112 * pci_conf_write(). next, we get the 'reg" property 113 * which is structured like the following: 114 * u_int32_t phys_hi; 115 * u_int32_t phys_mid; 116 * u_int32_t phys_lo; 117 * u_int32_t size_hi; 118 * u_int32_t size_lo; 119 * we mask these values with the "interrupt-map-mask" 120 * property of our parent and them compare with each 121 * entry in the "interrupt-map" property (also of our 122 * parent) which is structred like the following: 123 * u_int32_t phys_hi; 124 * u_int32_t phys_mid; 125 * u_int32_t phys_lo; 126 * u_int32_t intr; 127 * int32_t child_node; 128 * u_int32_t child_intr; 129 * if there is an exact match with phys_hi, phys_mid, 130 * phys_lo and the interrupt, we have a match and we 131 * know that this interrupt's value is really the 132 * child_intr of the interrupt map entry. we put this 133 * into the PCI interrupt line register so that when 134 * the driver for this node wants to attach, we know 135 * it's INO already. 136 */ 137 138 name = getpropstring(node, "name"); 139 DPRINTF((SPDB_INTFIX|SPDB_INTMAP), ("\n\tnode %x name `%s'", node, name)); 140 devtype = getpropstring(node, "device_type"); 141 DPRINTF((SPDB_INTFIX|SPDB_INTMAP), (" devtype `%s':", devtype)); 142 143 /* ignore PCI bridges, we'll get them later */ 144 if (strcmp(devtype, "pci") == 0) 145 continue; 146 147 /* if there isn't any "interrupts" then we don't care to fix it */ 148 ip = NULL; 149 if (getprop(node, "interrupts", sizeof(int), &n, (void **)&ip)) 150 continue; 151 DPRINTF(SPDB_INTFIX, (" got interrupts")); 152 153 /* and if there isn't an "assigned-addresses" we can't find b/d/f */ 154 if (getprop(node, "assigned-addresses", sizeof(int), &n, 155 (void **)&ap)) 156 goto clean1; 157 DPRINTF(SPDB_INTFIX, (" got assigned-addresses")); 158 159 /* ok, and now the "reg" property, so we know what we're talking about. */ 160 if (getprop(node, "reg", sizeof(*pr), &n, 161 (void **)&pr)) 162 goto clean2; 163 DPRINTF(SPDB_INTFIX, (" got reg")); 164 165 bus = TAG2BUS(ap[0]); 166 dev = TAG2DEV(ap[0]); 167 fn = TAG2FN(ap[0]); 168 169 DPRINTF(SPDB_INTFIX, ("; bus %u dev %u fn %u", bus, dev, fn)); 170 171 tag = pci_make_tag(pc, bus, dev, fn); 172 173 DPRINTF(SPDB_INTFIX, ("; tag %08x\n\t; reg: hi %x mid %x lo %x intr %x", tag, pr->phys_hi, pr->phys_mid, pr->phys_lo, *ip)); 174 DPRINTF(SPDB_INTFIX, ("\n\t; intmapmask: hi %x mid %x lo %x intr %x", pp->pp_intmapmask.phys_hi, pp->pp_intmapmask.phys_mid, 175 pp->pp_intmapmask.phys_lo, pp->pp_intmapmask.intr)); 176 177 hi = pr->phys_hi & pp->pp_intmapmask.phys_hi; 178 mid = pr->phys_mid & pp->pp_intmapmask.phys_mid; 179 lo = pr->phys_lo & pp->pp_intmapmask.phys_lo; 180 intr = *ip & pp->pp_intmapmask.intr; 181 182 DPRINTF(SPDB_INTFIX, ("\n\t; after: hi %x mid %x lo %x intr %x", hi, mid, lo, intr)); 183 184 for (i = 0; i < pp->pp_nintmap; i++) { 185 DPRINTF(SPDB_INTFIX, ("\n\t\tmatching for: hi %x mid %x lo %x intr %x", pp->pp_intmap[i].phys_hi, pp->pp_intmap[i].phys_mid, 186 pp->pp_intmap[i].phys_lo, pp->pp_intmap[i].intr)); 187 188 if (pp->pp_intmap[i].phys_hi != hi || 189 pp->pp_intmap[i].phys_mid != mid || 190 pp->pp_intmap[i].phys_lo != lo || 191 pp->pp_intmap[i].intr != intr) 192 continue; 193 DPRINTF(SPDB_INTFIX, ("... BINGO! ...")); 194 195 bingo: 196 /* 197 * OK! we found match. pull out the old interrupt 198 * register, patch in the new value, and put it back. 199 */ 200 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 201 DPRINTF(SPDB_INTFIX, ("\n\t ; read %x from intreg", intr)); 202 203 intr = (intr & ~PCI_INTERRUPT_LINE_MASK) | 204 (pp->pp_intmap[i].child_intr & PCI_INTERRUPT_LINE_MASK); 205 DPRINTF((SPDB_INTFIX|SPDB_INTMAP), ("\n\t ; gonna write %x to intreg", intr)); 206 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, intr); 207 DPRINTF((SPDB_INTFIX|SPDB_INTMAP), ("\n\t ; reread %x from intreg", intr)); 208 break; 209 } 210 if (i == pp->pp_nintmap) { 211 /* 212 * Not matched by parent interrupt map. If the 213 * interrupt property has the INTMAP_OBIO bit 214 * set, assume the PROM has (wrongly) supplied it 215 * in the parent's bus format, rather than as a 216 * PCI interrupt line number. 217 * 218 * This seems to be an issue only with the 219 * psycho host-to-pci bridge. 220 */ 221 if (pp->pp_sc->sc_mode == PSYCHO_MODE_PSYCHO && 222 (*ip & INTMAP_OBIO) != 0) { 223 DPRINTF((SPDB_INTFIX|SPDB_INTMAP), 224 ("\n\t; PSYCHO: no match but obio interrupt in parent format")); 225 226 i = -1; goto bingo; /* XXX - hackish.. */ 227 } 228 } 229 230 /* enable mem & dma if not already */ 231 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 232 PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_MASTER_ENABLE|PCI_COMMAND_IO_ENABLE); 233 234 235 /* clean up */ 236 if (pr) 237 free(pr, M_DEVBUF); 238clean2: 239 if (ap) 240 free(ap, M_DEVBUF); 241clean1: 242 if (ip) 243 free(ip, M_DEVBUF); 244 } 245 DPRINTF(SPDB_INTFIX, ("\n")); 246} 247 248int 249pci_bus_maxdevs(pc, busno) 250 pci_chipset_tag_t pc; 251 int busno; 252{ 253 254 return 32; 255} 256 257#ifdef __PCI_BUS_DEVORDER 258int 259pci_bus_devorder(pc, busno, devs) 260 pci_chipset_tag_t pc; 261 int busno; 262 char *devs; 263{ 264 struct ofw_pci_register reg0; 265 int node, len, device, i = 0; 266 u_int32_t done = 0; 267 268 for (node = OF_child(pc->node); node; node = OF_peer(node)) { 269 len = OF_getproplen(node, "reg"); 270 if (len < sizeof(reg0)) 271 continue; 272 if (OF_getprop(node, "reg", (void *)®0, sizeof(reg0)) != len) 273 panic("pci_probe_bus: OF_getprop len botch"); 274 275 device = OFW_PCI_PHYS_HI_DEVICE(reg0.phys_hi); 276 277 if (done & (1 << device)) 278 continue; 279 280 devs[i++] = device; 281 done |= 1 << device; 282 if (i == 32) 283 break; 284 } 285 if (i < 32) 286 devs[i] = -1; 287 288 return i; 289} 290#endif 291 292#ifdef __PCI_DEV_FUNCORDER 293int 294pci_dev_funcorder(pc, busno, device, funcs) 295 pci_chipset_tag_t pc; 296 int busno; 297 int device; 298 char *funcs; 299{ 300 struct ofw_pci_register reg0; 301 int node, len, i = 0; 302 303 for (node = OF_child(pc->node); node; node = OF_peer(node)) { 304 len = OF_getproplen(node, "reg"); 305 if (len < sizeof(reg0)) 306 continue; 307 if (OF_getprop(node, "reg", (void *)®0, sizeof(reg0)) != len) 308 panic("pci_probe_bus: OF_getprop len botch"); 309 310 if (device != OFW_PCI_PHYS_HI_DEVICE(reg0.phys_hi)) 311 continue; 312 313 funcs[i++] = OFW_PCI_PHYS_HI_FUNCTION(reg0.phys_hi); 314 if (i == 8) 315 break; 316 } 317 if (i < 8) 318 funcs[i] = -1; 319 320 return i; 321} 322#endif 323 324pcitag_t 325pci_make_tag(pc, b, d, f) 326 pci_chipset_tag_t pc; 327 int b; 328 int d; 329 int f; 330{ 331 332 /* make me a useable offset */ 333 return (b << 16) | (d << 11) | (f << 8); 334} 335 336static int confaddr_ok __P((struct psycho_softc *, pcitag_t)); 337 338/* 339 * this function is a large hack. ideally, we should also trap accesses 340 * properly, but we have to avoid letting anything read various parts 341 * of bus 0 dev 0 fn 0 space or the machine may hang. so, even if we 342 * do properly implement PCI config access trap handling, this function 343 * should remain in place Just In Case. 344 */ 345static int 346confaddr_ok(sc, tag) 347 struct psycho_softc *sc; 348 pcitag_t tag; 349{ 350 int bus, dev, fn; 351 352 bus = TAG2BUS(tag); 353 dev = TAG2DEV(tag); 354 fn = TAG2FN(tag); 355 356 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 357 /* 358 * bus 0 is only ok for dev 0 fn 0, dev 1 fn 0 and dev fn 1. 359 */ 360 if (bus == 0 && 361 ((dev == 0 && fn > 0) || 362 (dev == 1 && fn > 1) || 363 (dev > 1))) { 364 DPRINTF(SPDB_CONF, (" confaddr_ok: rejecting bus %d dev %d fn %d -", bus, dev, fn)); 365 return (0); 366 } 367 } else if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 368 /* 369 * make sure we are reading our own bus 370 */ 371 /* XXX??? */ 372 paddr_t addr = sc->sc_configaddr + tag; 373 int asi = bus_type_asi[sc->sc_configtag->type]; 374 if (probeget(addr, asi, 4) == -1) { 375 DPRINTF(SPDB_CONF, (" confaddr_ok: rejecting bus %d dev %d fn %d -", bus, dev, fn)); 376 return (0); 377 } 378 } 379 return (1); 380} 381 382/* assume we are mapped little-endian/side-effect */ 383pcireg_t 384pci_conf_read(pc, tag, reg) 385 pci_chipset_tag_t pc; 386 pcitag_t tag; 387 int reg; 388{ 389 struct psycho_pbm *pp = pc->cookie; 390 struct psycho_softc *sc = pp->pp_sc; 391 pcireg_t val; 392 393 DPRINTF(SPDB_CONF, ("pci_conf_read: tag %lx; reg %x; ", (long)tag, reg)); 394 DPRINTF(SPDB_CONF, ("asi = %x; readaddr = %qx (offset = %x) ...", 395 bus_type_asi[sc->sc_configtag->type], 396 (long long)(sc->sc_configaddr + tag + reg), (int)tag + reg)); 397 398 if (confaddr_ok(sc, tag) == 0) { 399 val = (pcireg_t)~0; 400 } else { 401 membar_sync(); 402 val = bus_space_read_4(sc->sc_configtag, sc->sc_configaddr, 403 tag + reg); 404 membar_sync(); 405 } 406 DPRINTF(SPDB_CONF, (" returning %08x\n", (u_int)val)); 407 408 return (val); 409} 410 411void 412pci_conf_write(pc, tag, reg, data) 413 pci_chipset_tag_t pc; 414 pcitag_t tag; 415 int reg; 416 pcireg_t data; 417{ 418 struct psycho_pbm *pp = pc->cookie; 419 struct psycho_softc *sc = pp->pp_sc; 420 421 DPRINTF(SPDB_CONF, ("pci_conf_write: tag %lx; reg %x; data %x; ", (long)tag, reg, (int)data)); 422 DPRINTF(SPDB_CONF, ("asi = %x; readaddr = %qx (offset = %x)\n", 423 bus_type_asi[sc->sc_configtag->type], 424 (long long)(sc->sc_configaddr + tag + reg), (int)tag + reg)); 425 426 if (confaddr_ok(sc, tag) == 0) 427 panic("pci_conf_write: bad addr"); 428 429 membar_sync(); 430 bus_space_write_4(sc->sc_configtag, sc->sc_configaddr, tag + reg, data); 431 membar_sync(); 432} 433 434/* 435 * interrupt mapping foo. 436 */ 437int 438pci_intr_map(pa, ihp) 439 struct pci_attach_args *pa; 440 pci_intr_handle_t *ihp; 441{ 442#if 0 443 pci_chipset_tag_t pc = pa->pa_pc; 444#endif 445 pcitag_t tag = pa->pa_intrtag; 446 int pin = pa->pa_intrpin; 447 int line = pa->pa_intrline; 448 int rv; 449 450 /* 451 * XXX 452 * UltraSPARC IIi PCI does not use PCI_INTERRUPT_REG, but we have 453 * used this space for our own purposes... 454 */ 455 DPRINTF(SPDB_INTR, ("pci_intr_map: tag %lx; pin %d; line %d", 456 (long)tag, pin, line)); 457#if 1 458 if (line == 255) { 459 *ihp = -1; 460 rv = 1; 461 goto out; 462 } 463#endif 464 if (pin > 4) 465 panic("pci_intr_map: pin > 4"); 466 467 rv = psycho_intr_map(tag, pin, line, ihp); 468 469out: 470 DPRINTF(SPDB_INTR, ("; handle = %d; returning %d\n", (int)*ihp, rv)); 471 return (rv); 472} 473 474const char * 475pci_intr_string(pc, ih) 476 pci_chipset_tag_t pc; 477 pci_intr_handle_t ih; 478{ 479 static char str[16]; 480 481 DPRINTF(SPDB_INTR, ("pci_intr_string: ih %u", ih)); 482 if (ih < 0 || ih > 0x32) { 483 printf("\n"); /* i'm *so* beautiful */ 484 panic("pci_intr_string: bogus handle\n"); 485 } 486 sprintf(str, "vector %u", ih); 487 DPRINTF(SPDB_INTR, ("; returning %s\n", str)); 488 489 return (str); 490} 491 492const struct evcnt * 493pci_intr_evcnt(pc, ih) 494 pci_chipset_tag_t pc; 495 pci_intr_handle_t ih; 496{ 497 498 /* XXX for now, no evcnt parent reported */ 499 return NULL; 500} 501 502void * 503pci_intr_establish(pc, ih, level, func, arg) 504 pci_chipset_tag_t pc; 505 pci_intr_handle_t ih; 506 int level; 507 int (*func) __P((void *)); 508 void *arg; 509{ 510 void *cookie; 511 struct psycho_pbm *pp = (struct psycho_pbm *)pc->cookie; 512 513 DPRINTF(SPDB_INTR, ("pci_intr_establish: ih %lu; level %d", (u_long)ih, level)); 514 cookie = bus_intr_establish(pp->pp_memt, ih, level, 0, func, arg); 515 516 DPRINTF(SPDB_INTR, ("; returning handle %p\n", cookie)); 517 return (cookie); 518} 519 520void 521pci_intr_disestablish(pc, cookie) 522 pci_chipset_tag_t pc; 523 void *cookie; 524{ 525 526 DPRINTF(SPDB_INTR, ("pci_intr_disestablish: cookie %p\n", cookie)); 527 528 /* XXX */ 529 panic("can't disestablish PCI interrupts yet"); 530} 531