pci_machdep.c revision 1.11
1/* $NetBSD: pci_machdep.c,v 1.11 2000/06/26 14:21:00 mrg Exp $ */ 2 3/* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31/* 32 * functions expected by the MI PCI code. 33 */ 34 35#ifdef DEBUG 36#define SPDB_CONF 0x01 37#define SPDB_INTR 0x04 38#define SPDB_INTMAP 0x08 39#define SPDB_INTFIX 0x10 40int sparc_pci_debug = 0x0; 41#define DPRINTF(l, s) do { if (sparc_pci_debug & l) printf s; } while (0) 42#else 43#define DPRINTF(l, s) 44#endif 45 46#include <sys/types.h> 47#include <sys/param.h> 48#include <sys/time.h> 49#include <sys/systm.h> 50#include <sys/errno.h> 51#include <sys/device.h> 52#include <sys/malloc.h> 53 54#include <vm/vm.h> 55 56#define _SPARC_BUS_DMA_PRIVATE 57#include <machine/bus.h> 58#include <machine/autoconf.h> 59 60#include <dev/pci/pcivar.h> 61#include <dev/pci/pcireg.h> 62 63#include <sparc64/dev/iommureg.h> 64#include <sparc64/dev/iommuvar.h> 65#include <sparc64/dev/psychoreg.h> 66#include <sparc64/dev/psychovar.h> 67 68/* this is a base to be copied */ 69struct sparc_pci_chipset _sparc_pci_chipset = { 70 NULL, 71}; 72 73/* 74 * functions provided to the MI code. 75 */ 76 77void 78pci_attach_hook(parent, self, pba) 79 struct device *parent; 80 struct device *self; 81 struct pcibus_attach_args *pba; 82{ 83 pci_chipset_tag_t pc = pba->pba_pc; 84 struct psycho_pbm *pp = pc->cookie; 85 struct psycho_registers *pr; 86 pcitag_t tag; 87 char *name, *devtype; 88 u_int32_t hi, mid, lo, intr; 89 u_int32_t dev, fn, bus; 90 int node, i, n, *ip, *ap; 91 92 DPRINTF((SPDB_INTFIX|SPDB_INTMAP), ("\npci_attach_hook:")); 93 94 /* 95 * ok, here we look in the OFW for each PCI device and fix it's 96 * "interrupt line" register to be useful. 97 */ 98 99 for (node = firstchild(pc->node); node; node = nextsibling(node)) { 100 pr = NULL; 101 ip = ap = NULL; 102 103 /* 104 * ok, for each child we get the "interrupts" property, 105 * which contains a value to match against later. 106 * XXX deal with multiple "interrupts" values XXX. 107 * then we get the "assigned-addresses" property which 108 * contains, in the first entry, the PCI bus, device and 109 * function associated with this node, which we use to 110 * generate a pcitag_t to use pci_conf_read() and 111 * pci_conf_write(). next, we get the 'reg" property 112 * which is structured like the following: 113 * u_int32_t phys_hi; 114 * u_int32_t phys_mid; 115 * u_int32_t phys_lo; 116 * u_int32_t size_hi; 117 * u_int32_t size_lo; 118 * we mask these values with the "interrupt-map-mask" 119 * property of our parent and them compare with each 120 * entry in the "interrupt-map" property (also of our 121 * parent) which is structred like the following: 122 * u_int32_t phys_hi; 123 * u_int32_t phys_mid; 124 * u_int32_t phys_lo; 125 * u_int32_t intr; 126 * int32_t child_node; 127 * u_int32_t child_intr; 128 * if there is an exact match with phys_hi, phys_mid, 129 * phys_lo and the interrupt, we have a match and we 130 * know that this interrupt's value is really the 131 * child_intr of the interrupt map entry. we put this 132 * into the PCI interrupt line register so that when 133 * the driver for this node wants to attach, we know 134 * it's INO already. 135 */ 136 137 name = getpropstring(node, "name"); 138 DPRINTF((SPDB_INTFIX|SPDB_INTMAP), ("\n\tnode %x name `%s'", node, name)); 139 devtype = getpropstring(node, "device_type"); 140 DPRINTF((SPDB_INTFIX|SPDB_INTMAP), (" devtype `%s':", devtype)); 141 142 /* ignore PCI bridges, we'll get them later */ 143 if (strcmp(devtype, "pci") == 0) 144 continue; 145 146 /* if there isn't any "interrupts" then we don't care to fix it */ 147 ip = NULL; 148 if (getprop(node, "interrupts", sizeof(int), &n, (void **)&ip)) 149 continue; 150 DPRINTF(SPDB_INTFIX, (" got interrupts")); 151 152 /* and if there isn't an "assigned-addresses" we can't find b/d/f */ 153 if (getprop(node, "assigned-addresses", sizeof(int), &n, 154 (void **)&ap)) 155 goto clean1; 156 DPRINTF(SPDB_INTFIX, (" got assigned-addresses")); 157 158 /* ok, and now the "reg" property, so we know what we're talking about. */ 159 if (getprop(node, "reg", sizeof(*pr), &n, 160 (void **)&pr)) 161 goto clean2; 162 DPRINTF(SPDB_INTFIX, (" got reg")); 163 164 bus = TAG2BUS(ap[0]); 165 dev = TAG2DEV(ap[0]); 166 fn = TAG2FN(ap[0]); 167 168 DPRINTF(SPDB_INTFIX, ("; bus %u dev %u fn %u", bus, dev, fn)); 169 170 tag = pci_make_tag(pc, bus, dev, fn); 171 172 DPRINTF(SPDB_INTFIX, ("; tag %08x\n\t; reg: hi %x mid %x lo %x intr %x", tag, pr->phys_hi, pr->phys_mid, pr->phys_lo, *ip)); 173 DPRINTF(SPDB_INTFIX, ("\n\t; intmapmask: hi %x mid %x lo %x intr %x", pp->pp_intmapmask.phys_hi, pp->pp_intmapmask.phys_mid, 174 pp->pp_intmapmask.phys_lo, pp->pp_intmapmask.intr)); 175 176 hi = pr->phys_hi & pp->pp_intmapmask.phys_hi; 177 mid = pr->phys_mid & pp->pp_intmapmask.phys_mid; 178 lo = pr->phys_lo & pp->pp_intmapmask.phys_lo; 179 intr = *ip & pp->pp_intmapmask.intr; 180 181 DPRINTF(SPDB_INTFIX, ("\n\t; after: hi %x mid %x lo %x intr %x", hi, mid, lo, intr)); 182 183 for (i = 0; i < pp->pp_nintmap; i++) { 184 DPRINTF(SPDB_INTFIX, ("\n\t\tmatching for: hi %x mid %x lo %x intr %x", pp->pp_intmap[i].phys_hi, pp->pp_intmap[i].phys_mid, 185 pp->pp_intmap[i].phys_lo, pp->pp_intmap[i].intr)); 186 187 if (pp->pp_intmap[i].phys_hi != hi || 188 pp->pp_intmap[i].phys_mid != mid || 189 pp->pp_intmap[i].phys_lo != lo || 190 pp->pp_intmap[i].intr != intr) 191 continue; 192 DPRINTF(SPDB_INTFIX, ("... BINGO! ...")); 193 194 /* 195 * OK! we found match. pull out the old interrupt 196 * register, patch in the new value, and put it back. 197 */ 198 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 199 DPRINTF(SPDB_INTFIX, ("\n\t ; read %x from intreg", intr)); 200 201 intr = (intr & ~PCI_INTERRUPT_LINE_MASK) | 202 (pp->pp_intmap[i].child_intr & PCI_INTERRUPT_LINE_MASK); 203 DPRINTF((SPDB_INTFIX|SPDB_INTMAP), ("\n\t ; gonna write %x to intreg", intr)); 204 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, intr); 205 DPRINTF((SPDB_INTFIX|SPDB_INTMAP), ("\n\t ; reread %x from intreg", intr)); 206 break; 207 } 208 209 /* enable mem & dma if not already */ 210 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 211 PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_MASTER_ENABLE); 212 213 214 /* clean up */ 215 if (pr) 216 free(pr, M_DEVBUF); 217clean2: 218 if (ap) 219 free(ap, M_DEVBUF); 220clean1: 221 if (ip) 222 free(ip, M_DEVBUF); 223 } 224 DPRINTF(SPDB_INTFIX, ("\n")); 225} 226 227int 228pci_bus_maxdevs(pc, busno) 229 pci_chipset_tag_t pc; 230 int busno; 231{ 232 233 return 32; 234} 235 236pcitag_t 237pci_make_tag(pc, b, d, f) 238 pci_chipset_tag_t pc; 239 int b; 240 int d; 241 int f; 242{ 243 244 /* make me a useable offset */ 245 return (b << 16) | (d << 11) | (f << 8); 246} 247 248static int confaddr_ok __P((struct psycho_softc *, pcitag_t)); 249 250/* 251 * this function is a large hack. ideally, we should also trap accesses 252 * properly, but we have to avoid letting anything read various parts 253 * of bus 0 dev 0 fn 0 space or the machine may hang. so, even if we 254 * do properly implement PCI config access trap handling, this function 255 * should remain in place Just In Case. 256 */ 257static int 258confaddr_ok(sc, tag) 259 struct psycho_softc *sc; 260 pcitag_t tag; 261{ 262 int bus, dev, fn; 263 264 bus = TAG2BUS(tag); 265 dev = TAG2DEV(tag); 266 fn = TAG2FN(tag); 267 268 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 269 /* 270 * bus 0 is only ok for dev 0 fn 0, dev 1 fn 0 and dev fn 1. 271 */ 272 if (bus == 0 && 273 ((dev == 0 && fn > 0) || 274 (dev == 1 && fn > 1) || 275 (dev > 1))) { 276 DPRINTF(SPDB_CONF, (" confaddr_ok: rejecting bus %d dev %d fn %d -", bus, dev, fn)); 277 return (0); 278 } 279 } else if (sc->sc_mode == PSYCHO_MODE_PSYCHO_A || 280 sc->sc_mode == PSYCHO_MODE_PSYCHO_B) { 281 /* 282 * make sure we are reading our own bus 283 */ 284 /* XXX??? */ 285 panic("confaddr_ok: can't do SUNW,psycho yet"); 286 } 287 return (1); 288} 289 290/* assume we are mapped little-endian/side-effect */ 291pcireg_t 292pci_conf_read(pc, tag, reg) 293 pci_chipset_tag_t pc; 294 pcitag_t tag; 295 int reg; 296{ 297 struct psycho_pbm *pp = pc->cookie; 298 struct psycho_softc *sc = pp->pp_sc; 299 pcireg_t val; 300 301 DPRINTF(SPDB_CONF, ("pci_conf_read: tag %lx; reg %x; ", (long)tag, reg)); 302 DPRINTF(SPDB_CONF, ("asi = %x; readaddr = %qx (offset = %x) ...", 303 bus_type_asi[sc->sc_configtag->type], 304 sc->sc_configaddr + tag + reg, (int)tag + reg)); 305 306 if (confaddr_ok(sc, tag) == 0) { 307 val = (pcireg_t)~0; 308 } else { 309 membar_sync(); 310 val = bus_space_read_4(sc->sc_configtag, sc->sc_configaddr, 311 tag + reg); 312 membar_sync(); 313 } 314 DPRINTF(SPDB_CONF, (" returning %08x\n", (u_int)val)); 315 316 return (val); 317} 318 319void 320pci_conf_write(pc, tag, reg, data) 321 pci_chipset_tag_t pc; 322 pcitag_t tag; 323 int reg; 324 pcireg_t data; 325{ 326 struct psycho_pbm *pp = pc->cookie; 327 struct psycho_softc *sc = pp->pp_sc; 328 329 DPRINTF(SPDB_CONF, ("pci_conf_write: tag %ld; reg %d; data %d; ", (long)tag, reg, (int)data)); 330 DPRINTF(SPDB_CONF, ("asi = %x; readaddr = %qx (offset = %x)\n", 331 bus_type_asi[sc->sc_configtag->type], 332 sc->sc_configaddr + tag + reg, (int)tag + reg)); 333 334 if (confaddr_ok(sc, tag) == 0) 335 panic("pci_conf_write: bad addr"); 336 337 membar_sync(); 338 bus_space_write_4(sc->sc_configtag, sc->sc_configaddr, tag + reg, data); 339 membar_sync(); 340} 341 342/* 343 * interrupt mapping foo. 344 */ 345int 346pci_intr_map(pc, tag, pin, line, ihp) 347 pci_chipset_tag_t pc; 348 pcitag_t tag; 349 int pin; 350 int line; 351 pci_intr_handle_t *ihp; 352{ 353 int rv; 354 355 /* 356 * XXX 357 * UltraSPARC IIi PCI does not use PCI_INTERRUPT_REG, but we have 358 * used this space for our own purposes... 359 */ 360 DPRINTF(SPDB_INTR, ("pci_intr_map: tag %lx; pin %d; line %d", 361 (long)tag, pin, line)); 362#if 1 363 if (line == 255) { 364 *ihp = -1; 365 rv = 1; 366 goto out; 367 } 368#endif 369 if (pin > 4) 370 panic("pci_intr_map: pin > 4"); 371 372 rv = psycho_intr_map(tag, pin, line, ihp); 373 374out: 375 DPRINTF(SPDB_INTR, ("; handle = %d; returning %d\n", (int)*ihp, rv)); 376 return (rv); 377} 378 379const char * 380pci_intr_string(pc, ih) 381 pci_chipset_tag_t pc; 382 pci_intr_handle_t ih; 383{ 384 static char str[16]; 385 386 DPRINTF(SPDB_INTR, ("pci_intr_string: ih %u", ih)); 387 if (ih < 0 || ih > 0x32) { 388 printf("\n"); /* i'm *so* beautiful */ 389 panic("pci_intr_string: bogus handle\n"); 390 } 391 sprintf(str, "vector %u", ih); 392 DPRINTF(SPDB_INTR, ("; returning %s\n", str)); 393 394 return (str); 395} 396 397const struct evcnt * 398pci_intr_evcnt(pc, ih) 399 pci_chipset_tag_t pc; 400 pci_intr_handle_t ih; 401{ 402 403 /* XXX for now, no evcnt parent reported */ 404 return NULL; 405} 406 407void * 408pci_intr_establish(pc, ih, level, func, arg) 409 pci_chipset_tag_t pc; 410 pci_intr_handle_t ih; 411 int level; 412 int (*func) __P((void *)); 413 void *arg; 414{ 415 void *cookie; 416 struct psycho_pbm *pp = (struct psycho_pbm *)pc->cookie; 417 418 DPRINTF(SPDB_INTR, ("pci_intr_establish: ih %lu; level %d", (u_long)ih, level)); 419 cookie = bus_intr_establish(pp->pp_memt, ih, 0, func, arg); 420 421 DPRINTF(SPDB_INTR, ("; returning handle %p\n", cookie)); 422 return (cookie); 423} 424 425void 426pci_intr_disestablish(pc, cookie) 427 pci_chipset_tag_t pc; 428 void *cookie; 429{ 430 431 DPRINTF(SPDB_INTR, ("pci_intr_disestablish: cookie %p\n", cookie)); 432 433 /* XXX */ 434 panic("can't disestablish PCI interrupts yet"); 435} 436