1/* $NetBSD: reg.h,v 1.11 2018/01/15 10:06:49 martin Exp $ */ 2 3/* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)reg.h 8.1 (Berkeley) 6/11/93 41 */ 42 43#ifndef _MACHINE_REG_H_ 44#define _MACHINE_REG_H_ 45 46/* 47 * Registers passed to trap/syscall/etc. 48 * This structure is known to occupy exactly 80 bytes (see locore.s). 49 * Note, tf_global[0] is not actually written (since g0 is always 0). 50 * (The slot tf_global[0] is used to send a copy of %wim to kernel gdb. 51 * This is known as `cheating'.) 52 */ 53struct trapframe { 54 int tf_psr; /* psr */ 55 int tf_pc; /* return pc */ 56 int tf_npc; /* return npc */ 57 int tf_y; /* %y register */ 58 int tf_global[8]; /* global registers in trap's caller */ 59 int tf_out[8]; /* output registers in trap's caller */ 60}; 61 62/* 63 * Register windows. Each stack pointer (%o6 aka %sp) in each window 64 * must ALWAYS point to some place at which it is safe to scribble on 65 * 64 bytes. (If not, your process gets mangled.) Furthermore, each 66 * stack pointer should be aligned on an 8-byte boundary (the kernel 67 * as currently coded allows arbitrary alignment, but with a hefty 68 * performance penalty). 69 */ 70struct rwindow { 71 int rw_local[8]; /* %l0..%l7 */ 72 int rw_in[8]; /* %i0..%i7 */ 73}; 74 75/* 76 * Clone trapframe for now; this seems to be the more useful 77 * than the old struct reg above. 78 */ 79struct reg { 80 int r_psr; /* psr */ 81 int r_pc; /* return pc */ 82 int r_npc; /* return npc */ 83 int r_y; /* %y register */ 84 int r_global[8]; /* global registers in trap's caller */ 85 int r_out[8]; /* output registers in trap's caller */ 86}; 87 88#include <machine/fsr.h> 89 90/* 91 * FP coprocessor registers. 92 * 93 * FP_QSIZE is the maximum coprocessor instruction queue depth 94 * of any implementation on which the kernel will run. David Hough: 95 * ``I'd suggest allowing 16 ... allowing an indeterminate variable 96 * size would be even better''. Of course, we cannot do that; we 97 * need to malloc these. 98 */ 99#define FP_QSIZE 16 100 101struct fp_qentry { 102 int *fq_addr; /* the instruction's address */ 103 int fq_instr; /* the instruction itself */ 104}; 105 106struct fpreg { 107 u_int fr_regs[32]; /* our view is 32 32-bit registers */ 108 int fr_fsr; /* %fsr */ 109}; 110 111struct fpstate { 112 struct fpreg fs_reg; 113#define fs_regs fs_reg.fr_regs 114#define fs_fsr fs_reg.fr_fsr 115 int fs_qsize; /* actual queue depth */ 116 struct fp_qentry fs_queue[FP_QSIZE]; /* queue contents */ 117} 118#ifdef _KERNEL 119 __aligned(8) /* asm code uses std instructions */ 120#endif 121; 122 123/* 124 * The actual FP registers are made accessible (c.f. ptrace(2)) through 125 * a `struct fpreg'; <arch/sparc/sparc/process_machdep.c> relies on the 126 * fact that `fpreg' is a prefix of `fpstate'. 127 */ 128 129#endif /* _MACHINE_REG_H_ */ 130